1 files changed, 115 insertions, 36 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 44456e163025..29475101a7b3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -34,15 +34,12 @@ config SYS_SUPPORTS_APM_EMULATION
 
 config GENERIC_GPIO
         bool
-        default n
 
 config GENERIC_TIME
         bool
-        default n
 
 config GENERIC_CLOCKEVENTS
         bool
-        default n
 
 config GENERIC_CLOCKEVENTS_BROADCAST
         bool
@@ -55,7 +52,6 @@ config MMU
 
 config NO_IOPORT
         bool
-        default n
 
 config EISA
         bool
@@ -126,11 +122,9 @@ config RWSEM_XCHGADD_ALGORITHM
 
 config ARCH_HAS_ILOG2_U32
         bool
-        default n
 
 config ARCH_HAS_ILOG2_U64
         bool
-        default n
 
 config GENERIC_HWEIGHT
         bool
@@ -281,6 +275,7 @@ config ARCH_EP93XX
         select HAVE_CLK
         select COMMON_CLKDEV
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_HOLES_MEMORYMODEL
         help
           This enables support for the Cirrus EP93xx series of CPUs.
 
@@ -299,9 +294,23 @@ config ARCH_MXC
         select ARCH_MTD_XIP
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
         help
           Support for Freescale MXC/iMX-based family of processors
 
+config ARCH_STMP3XXX
+        bool "Freescale STMP3xxx"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select USB_ARCH_HAS_EHCI
+        help
+          Support for systems based on the Freescale 3xxx CPUs.
+
 config ARCH_NETX
         bool "Hilscher NetX based"
         select CPU_ARM926T
@@ -318,15 +327,6 @@ config ARCH_H720X
         help
           This enables support for systems based on the Hynix HMS720x
 
-config ARCH_IMX
-        bool "IMX"
-        select CPU_ARM920T
-        select GENERIC_GPIO
-        select GENERIC_TIME
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Motorola's i.MX family of processors (MX1, MXL).
-
 config ARCH_IOP13XX
         bool "IOP13xx-based"
         depends on MMU
@@ -407,6 +407,7 @@ config ARCH_KIRKWOOD
         select CPU_FEROCEON
         select PCI
         select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select PLAT_ORION
@@ -428,6 +429,7 @@ config ARCH_MV78XX0
         select CPU_FEROCEON
         select PCI
         select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select PLAT_ORION
@@ -441,6 +443,7 @@ config ARCH_ORION5X
         select CPU_FEROCEON
         select PCI
         select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select PLAT_ORION
@@ -488,6 +491,9 @@ config ARCH_NS9XXX
 config ARCH_W90X900
         bool "Nuvoton W90X900 CPU"
         select CPU_ARM926T
+        select ARCH_REQUIRE_GPIOLIB
+        select GENERIC_GPIO
+        select COMMON_CLKDEV
         help
                 Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
                 can login www.mcuos.com or www.nuvoton.com to know more.
@@ -507,8 +513,6 @@ config ARCH_PXA
         select HAVE_CLK
         select COMMON_CLKDEV
         select ARCH_REQUIRE_GPIOLIB
-        select HAVE_CLK
-        select COMMON_CLKDEV
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
@@ -617,6 +621,9 @@ config ARCH_DAVINCI
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         select ZONE_DMA
+        select HAVE_IDE
+        select COMMON_CLKDEV
+        select GENERIC_ALLOCATOR
         help
           Support for TI's DaVinci platform.
 
@@ -693,9 +700,9 @@ source "arch/arm/mach-s3c6400/Kconfig"
 source "arch/arm/mach-s3c6410/Kconfig"
 endif
 
-source "arch/arm/mach-lh7a40x/Kconfig"
+source "arch/arm/plat-stmp3xxx/Kconfig"
 
-source "arch/arm/mach-imx/Kconfig"
+source "arch/arm/mach-lh7a40x/Kconfig"
 
 source "arch/arm/mach-h720x/Kconfig"
 
@@ -756,6 +763,56 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_411920
+        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
+        depends on CPU_V6 && !SMP
+        help
+          Invalidation of the Instruction Cache operation can
+          fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
+          It does not affect the MPCore. This option enables the ARM Ltd.
+          recommended workaround.
+
+config ARM_ERRATA_430973
+        bool "ARM errata: Stale prediction on replaced interworking branch"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 430973 Cortex-A8
+          (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
+          interworking branch is replaced with another code sequence at the
+          same virtual address, whether due to self-modifying code or virtual
+          to physical address re-mapping, Cortex-A8 does not recover from the
+          stale interworking branch prediction. This results in Cortex-A8
+          executing the new code sequence in the incorrect ARM or Thumb state.
+          The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
+          and also flushes the branch target cache at every context switch.
+          Note that setting specific bits in the ACTLR register may not be
+          available in non-secure mode.
+
+config ARM_ERRATA_458693
+        bool "ARM errata: Processor deadlock when a false hazard is created"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 458693 Cortex-A8 (r2p0)
+          erratum. For very specific sequences of memory operations, it is
+          possible for a hazard condition intended for a cache line to instead
+          be incorrectly associated with a different cache line. This false
+          hazard might then cause a processor deadlock. The workaround enables
+          the L1 caching of the NEON accesses and disables the PLD instruction
+          in the ACTLR register. Note that setting specific bits in the ACTLR
+          register may not be available in non-secure mode.
+
+config ARM_ERRATA_460075
+        bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 460075 Cortex-A8 (r2p0)
+          erratum. Any asynchronous access to the L2 cache may encounter a
+          situation in which recent store transactions to the L2 cache are lost
+          and overwritten with stale memory contents from external memory. The
+          workaround disables the write-allocate mode for the L2 cache via the
+          ACTLR register. Note that setting specific bits in the ACTLR register
+          may not be available in non-secure mode.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -823,8 +880,11 @@ source "kernel/time/Kconfig"
 
 config SMP
         bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP)
+        depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
+                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
+        depends on GENERIC_CLOCKEVENTS
         select USE_GENERIC_SMP_HELPERS
+        select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4)
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -842,6 +902,18 @@ config SMP
 
           If you don't know what to do here, say N.
 
+config HAVE_ARM_SCU
+        bool
+        depends on SMP
+        help
+          This option enables support for the ARM system coherency unit
+
+config HAVE_ARM_TWD
+        bool
+        depends on SMP
+        help
+          This options enables support for the ARM timer and watchdog unit
+
 choice
         prompt "Memory split"
         default VMSPLIT_3G
@@ -880,8 +952,10 @@ config HOTPLUG_CPU
 
 config LOCAL_TIMERS
         bool "Use local timer interrupts"
-        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || REALVIEW_EB_A9MP)
+        depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
+                REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4)
         default y
+        select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4)
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -941,10 +1015,8 @@ config OABI_COMPAT
           UNPREDICTABLE (in fact it can be predicted that it won't work
           at all). If in doubt say Y.
 
-config ARCH_FLATMEM_HAS_HOLES
+config ARCH_HAS_HOLES_MEMORYMODEL
         bool
-        default y
-        depends on FLATMEM
 
 # Discontigmem is deprecated
 config ARCH_DISCONTIGMEM_ENABLE
@@ -987,12 +1059,12 @@ source "mm/Kconfig"
 config LEDS
         bool "Timer and CPU usage LEDs"
         depends on ARCH_CDB89712 || ARCH_EBSA110 || \
-                   ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
+                   ARCH_EBSA285 || ARCH_INTEGRATOR || \
                    ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
                    ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
                    ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
                    ARCH_AT91 || ARCH_DAVINCI || \
-                   ARCH_KS8695 || MACH_RD88F5182
+                   ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
         help
           If you say Y here, the LEDs on your machine will be used
           to provide useful information about your current system status.
@@ -1050,6 +1122,22 @@ config ALIGNMENT_TRAP
           correct operation of some network protocols. With an IP-only
           configuration it is safe to say N, otherwise say Y.
 
+config UACCESS_WITH_MEMCPY
+        bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
+        depends on MMU && EXPERIMENTAL
+        default y if CPU_FEROCEON
+        help
+          Implement faster copy_to_user and clear_user methods for CPU
+          cores where a 8-word STM instruction give significantly higher
+          memory write throughput than a sequence of individual 32bit stores.
+
+          A possible side effect is a slight increase in scheduling latency
+          between threads sharing the same address space if they invoke
+          such copy operations with large buffers.
+
+          However, if the CPU data cache is using a write-allocate mode,
+          this option is unlikely to provide any performance gain.
+
 endmenu
 
 menu "Boot options"
@@ -1153,7 +1241,7 @@ endmenu
 
 menu "CPU Power Management"
 
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_IMX || ARCH_PXA)
+if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA)
 
 source "drivers/cpufreq/Kconfig"
 
@@ -1178,15 +1266,6 @@ config CPU_FREQ_INTEGRATOR
 
           If in doubt, say Y.
 
-config CPU_FREQ_IMX
-        tristate "CPUfreq driver for i.MX CPUs"
-        depends on ARCH_IMX && CPU_FREQ
-        default n
-        help
-          This enables the CPUfreq driver for i.MX CPUs.
-
-          If in doubt, say N.
-
 config CPU_FREQ_PXA
         bool
         depends on CPU_FREQ && ARCH_PXA && PXA25x