1 files changed, 105 insertions, 9 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dbfdf87f993f..e60ec54df334 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -241,6 +241,7 @@ config ARCH_VERSATILE
 config ARCH_AT91
         bool "Atmel AT91"
         select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         help
           This enables support for systems based on the Atmel AT91RM9200,
@@ -275,6 +276,14 @@ config ARCH_EP93XX
         help
           This enables support for the Cirrus EP93xx series of CPUs.
 
+config ARCH_GEMINI
+        bool "Cortina Systems Gemini"
+        select CPU_FA526
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Support for the Cortina Systems Gemini family SoCs
+
 config ARCH_FOOTBRIDGE
         bool "FootBridge"
         select CPU_SA110
@@ -445,6 +454,7 @@ config ARCH_MXC
         select ARCH_MTD_XIP
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
         help
           Support for Freescale MXC/iMX-based family of processors
 
@@ -480,9 +490,24 @@ config ARCH_PXA
         select GENERIC_TIME
         select GENERIC_CLOCKEVENTS
         select TICK_ONESHOT
+        select PLAT_PXA
         help
           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
+config ARCH_MMP
+        bool "Marvell PXA168/910"
+        depends on MMU
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select TICK_ONESHOT
+        select PLAT_PXA
+        help
+          Support for Marvell's PXA168/910 processor line.
+
 config ARCH_RPC
         bool "RiscPC"
         select ARCH_ACORN
@@ -559,6 +584,8 @@ config ARCH_DAVINCI
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
         select ZONE_DMA
+        select HAVE_IDE
+        select COMMON_CLKDEV
         help
           Support for TI's DaVinci platform.
 
@@ -598,6 +625,8 @@ source "arch/arm/mach-ep93xx/Kconfig"
 
 source "arch/arm/mach-footbridge/Kconfig"
 
+source "arch/arm/mach-gemini/Kconfig"
+
 source "arch/arm/mach-integrator/Kconfig"
 
 source "arch/arm/mach-iop32x/Kconfig"
@@ -617,6 +646,9 @@ source "arch/arm/mach-loki/Kconfig"
 source "arch/arm/mach-mv78xx0/Kconfig"
 
 source "arch/arm/mach-pxa/Kconfig"
+source "arch/arm/plat-pxa/Kconfig"
+
+source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-sa1100/Kconfig"
 
@@ -686,12 +718,15 @@ config PLAT_IOP
 config PLAT_ORION
         bool
 
+config PLAT_PXA
+        bool
+
 source arch/arm/mm/Kconfig
 
 config IWMMXT
         bool "Enable iWMMXt support"
-        depends on CPU_XSCALE || CPU_XSC3
-        default y if PXA27x || PXA3xx
+        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
+        default y if PXA27x || PXA3xx || ARCH_MMP
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
@@ -706,6 +741,56 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_411920
+        bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
+        depends on CPU_V6 && !SMP
+        help
+          Invalidation of the Instruction Cache operation can
+          fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
+          It does not affect the MPCore. This option enables the ARM Ltd.
+          recommended workaround.
+
+config ARM_ERRATA_430973
+        bool "ARM errata: Stale prediction on replaced interworking branch"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 430973 Cortex-A8
+          (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
+          interworking branch is replaced with another code sequence at the
+          same virtual address, whether due to self-modifying code or virtual
+          to physical address re-mapping, Cortex-A8 does not recover from the
+          stale interworking branch prediction. This results in Cortex-A8
+          executing the new code sequence in the incorrect ARM or Thumb state.
+          The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
+          and also flushes the branch target cache at every context switch.
+          Note that setting specific bits in the ACTLR register may not be
+          available in non-secure mode.
+
+config ARM_ERRATA_458693
+        bool "ARM errata: Processor deadlock when a false hazard is created"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 458693 Cortex-A8 (r2p0)
+          erratum. For very specific sequences of memory operations, it is
+          possible for a hazard condition intended for a cache line to instead
+          be incorrectly associated with a different cache line. This false
+          hazard might then cause a processor deadlock. The workaround enables
+          the L1 caching of the NEON accesses and disables the PLD instruction
+          in the ACTLR register. Note that setting specific bits in the ACTLR
+          register may not be available in non-secure mode.
+
+config ARM_ERRATA_460075
+        bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
+        depends on CPU_V7
+        help
+          This option enables the workaround for the 460075 Cortex-A8 (r2p0)
+          erratum. Any asynchronous access to the L2 cache may encounter a
+          situation in which recent store transactions to the L2 cache are lost
+          and overwritten with stale memory contents from external memory. The
+          workaround disables the write-allocate mode for the L2 cache via the
+          ACTLR register. Note that setting specific bits in the ACTLR register
+          may not be available in non-secure mode.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -915,6 +1000,23 @@ config NODES_SHIFT
         default "2"
         depends on NEED_MULTIPLE_NODES
 
+config HIGHMEM
+        bool "High Memory Support (EXPERIMENTAL)"
+        depends on MMU && EXPERIMENTAL
+        help
+          The address space of ARM processors is only 4 Gigabytes large
+          and it has to accommodate user address space, kernel address
+          space as well as some memory mapped IO. That means that, if you
+          have a large amount of physical memory and/or IO, not all of the
+          memory can be "permanently mapped" by the kernel. The physical
+          memory that is not permanently mapped is called "high memory".
+
+          Depending on the selected kernel/user memory split, minimum
+          vmalloc space and actual amount of RAM, you may not need this
+          option which should result in a slightly faster kernel.
+
+          If unsure, say n.
+
 source "mm/Kconfig"
 
 config LEDS
@@ -1092,7 +1194,7 @@ source "drivers/cpufreq/Kconfig"
 
 config CPU_FREQ_SA1100
         bool
-        depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
+        depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
         default y
 
 config CPU_FREQ_SA1110
@@ -1120,12 +1222,6 @@ config CPU_FREQ_IMX
 
           If in doubt, say N.
 
-config CPU_FREQ_PXA
-        bool
-        depends on CPU_FREQ && ARCH_PXA && PXA25x
-        default y
-        select CPU_FREQ_DEFAULT_GOV_USERSPACE
-
 endif
 
 source "drivers/cpuidle/Kconfig"