1 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 762ae536f909..0f1ad743ccdd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -924,6 +924,19 @@ config ARM_ERRATA_460075
           ACTLR register. Note that setting specific bits in the ACTLR register
           may not be available in non-secure mode.
 
+config PL310_ERRATA_588369
+        bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+        depends on CACHE_L2X0 && ARCH_OMAP4
+        help
+           The PL310 L2 cache controller implements three types of Clean &
+           Invalidate maintenance operations: by Physical Address
+           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+           They are architecturally defined to behave as the execution of a
+           clean operation followed immediately by an invalidate operation,
+           both performing to the same memory location. This functionality
+           is not correctly implemented in PL310 as clean lines are not
+           invalidated as a result of these operations. Note that this errata
+           uses Texas Instrument's secure monitor api.
 endmenu
 
 source "arch/arm/common/Kconfig"