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-rw-r--r--arch/arc/kernel/setup.c272
1 files changed, 133 insertions, 139 deletions
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 119dddb752b2..252bf603db9c 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -13,7 +13,9 @@
13#include <linux/console.h> 13#include <linux/console.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/cpu.h> 15#include <linux/cpu.h>
16#include <linux/clk-provider.h>
16#include <linux/of_fdt.h> 17#include <linux/of_fdt.h>
18#include <linux/of_platform.h>
17#include <linux/cache.h> 19#include <linux/cache.h>
18#include <asm/sections.h> 20#include <asm/sections.h>
19#include <asm/arcregs.h> 21#include <asm/arcregs.h>
@@ -24,11 +26,10 @@
24#include <asm/unwind.h> 26#include <asm/unwind.h>
25#include <asm/clk.h> 27#include <asm/clk.h>
26#include <asm/mach_desc.h> 28#include <asm/mach_desc.h>
29#include <asm/smp.h>
27 30
28#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) 31#define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
29 32
30int running_on_hw = 1; /* vs. on ISS */
31
32/* Part of U-boot ABI: see head.S */ 33/* Part of U-boot ABI: see head.S */
33int __initdata uboot_tag; 34int __initdata uboot_tag;
34char __initdata *uboot_arg; 35char __initdata *uboot_arg;
@@ -42,26 +43,26 @@ struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
42static void read_arc_build_cfg_regs(void) 43static void read_arc_build_cfg_regs(void)
43{ 44{
44 struct bcr_perip uncached_space; 45 struct bcr_perip uncached_space;
46 struct bcr_generic bcr;
45 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 47 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
46 FIX_PTR(cpu); 48 FIX_PTR(cpu);
47 49
48 READ_BCR(AUX_IDENTITY, cpu->core); 50 READ_BCR(AUX_IDENTITY, cpu->core);
51 READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
49 52
50 cpu->timers = read_aux_reg(ARC_REG_TIMERS_BCR); 53 READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
51 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); 54 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
52 55
53 READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space); 56 READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
54 cpu->uncached_base = uncached_space.start << 24; 57 cpu->uncached_base = uncached_space.start << 24;
55 58
56 cpu->extn.mul = read_aux_reg(ARC_REG_MUL_BCR); 59 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
57 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR);
58 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR);
59 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR);
60 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR);
61 READ_BCR(ARC_REG_MAC_BCR, cpu->extn_mac_mul);
62 60
63 cpu->extn.ext_arith = read_aux_reg(ARC_REG_EXTARITH_BCR); 61 cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
64 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR); 62 cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
63 cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
64 cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
65 cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
65 66
66 /* Note that we read the CCM BCRs independent of kernel config 67 /* Note that we read the CCM BCRs independent of kernel config
67 * This is to catch the cases where user doesn't know that 68 * This is to catch the cases where user doesn't know that
@@ -95,43 +96,76 @@ static void read_arc_build_cfg_regs(void)
95 read_decode_mmu_bcr(); 96 read_decode_mmu_bcr();
96 read_decode_cache_bcr(); 97 read_decode_cache_bcr();
97 98
98 READ_BCR(ARC_REG_FP_BCR, cpu->fp); 99 {
99 READ_BCR(ARC_REG_DPFP_BCR, cpu->dpfp); 100 struct bcr_fp_arcompact sp, dp;
101 struct bcr_bpu_arcompact bpu;
102
103 READ_BCR(ARC_REG_FP_BCR, sp);
104 READ_BCR(ARC_REG_DPFP_BCR, dp);
105 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
106 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
107
108 READ_BCR(ARC_REG_BPU_BCR, bpu);
109 cpu->bpu.ver = bpu.ver;
110 cpu->bpu.full = bpu.fam ? 1 : 0;
111 if (bpu.ent) {
112 cpu->bpu.num_cache = 256 << (bpu.ent - 1);
113 cpu->bpu.num_pred = 256 << (bpu.ent - 1);
114 }
115 }
116
117 READ_BCR(ARC_REG_AP_BCR, bcr);
118 cpu->extn.ap = bcr.ver ? 1 : 0;
119
120 READ_BCR(ARC_REG_SMART_BCR, bcr);
121 cpu->extn.smart = bcr.ver ? 1 : 0;
122
123 cpu->extn.debug = cpu->extn.ap | cpu->extn.smart;
100} 124}
101 125
102static const struct cpuinfo_data arc_cpu_tbl[] = { 126static const struct cpuinfo_data arc_cpu_tbl[] = {
103 { {0x10, "ARCTangent A5"}, 0x1F},
104 { {0x20, "ARC 600" }, 0x2F}, 127 { {0x20, "ARC 600" }, 0x2F},
105 { {0x30, "ARC 700" }, 0x33}, 128 { {0x30, "ARC 700" }, 0x33},
106 { {0x34, "ARC 700 R4.10"}, 0x34}, 129 { {0x34, "ARC 700 R4.10"}, 0x34},
130 { {0x35, "ARC 700 R4.11"}, 0x35},
107 { {0x00, NULL } } 131 { {0x00, NULL } }
108}; 132};
109 133
134#define IS_AVAIL1(v, str) ((v) ? str : "")
135#define IS_USED(cfg) (IS_ENABLED(cfg) ? "" : "(not used) ")
136#define IS_AVAIL2(v, str, cfg) IS_AVAIL1(v, str), IS_AVAIL1(v, IS_USED(cfg))
137
110static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) 138static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
111{ 139{
112 int n = 0;
113 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 140 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
114 struct bcr_identity *core = &cpu->core; 141 struct bcr_identity *core = &cpu->core;
115 const struct cpuinfo_data *tbl; 142 const struct cpuinfo_data *tbl;
116 int be = 0; 143 char *isa_nm;
117#ifdef CONFIG_CPU_BIG_ENDIAN 144 int i, be, atomic;
118 be = 1; 145 int n = 0;
119#endif 146
120 FIX_PTR(cpu); 147 FIX_PTR(cpu);
121 148
149 {
150 isa_nm = "ARCompact";
151 be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
152
153 atomic = cpu->isa.atomic1;
154 if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
155 atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
156 }
157
122 n += scnprintf(buf + n, len - n, 158 n += scnprintf(buf + n, len - n,
123 "\nARC IDENTITY\t: Family [%#02x]" 159 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
124 " Cpu-id [%#02x] Chip-id [%#4x]\n", 160 core->family, core->cpu_id, core->chip_id);
125 core->family, core->cpu_id,
126 core->chip_id);
127 161
128 for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { 162 for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
129 if ((core->family >= tbl->info.id) && 163 if ((core->family >= tbl->info.id) &&
130 (core->family <= tbl->up_range)) { 164 (core->family <= tbl->up_range)) {
131 n += scnprintf(buf + n, len - n, 165 n += scnprintf(buf + n, len - n,
132 "processor\t: %s %s\n", 166 "processor [%d]\t: %s (%s ISA) %s\n",
133 tbl->info.str, 167 cpu_id, tbl->info.str, isa_nm,
134 be ? "[Big Endian]" : ""); 168 IS_AVAIL1(be, "[Big-Endian]"));
135 break; 169 break;
136 } 170 }
137 } 171 }
@@ -143,34 +177,35 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
143 (unsigned int)(arc_get_core_freq() / 1000000), 177 (unsigned int)(arc_get_core_freq() / 1000000),
144 (unsigned int)(arc_get_core_freq() / 10000) % 100); 178 (unsigned int)(arc_get_core_freq() / 10000) % 100);
145 179
146 n += scnprintf(buf + n, len - n, "Timers\t\t: %s %s\n", 180 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
147 (cpu->timers & 0x200) ? "TIMER1" : "", 181 IS_AVAIL1(cpu->timers.t0, "Timer0 "),
148 (cpu->timers & 0x100) ? "TIMER0" : ""); 182 IS_AVAIL1(cpu->timers.t1, "Timer1 "),
183 IS_AVAIL2(cpu->timers.rtsc, "64-bit RTSC ", CONFIG_ARC_HAS_RTSC));
149 184
150 n += scnprintf(buf + n, len - n, "Vect Tbl Base\t: %#x\n", 185 n += i = scnprintf(buf + n, len - n, "%s%s",
151 cpu->vec_base); 186 IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC));
152 187
153 n += scnprintf(buf + n, len - n, "UNCACHED Base\t: %#x\n", 188 if (i)
154 cpu->uncached_base); 189 n += scnprintf(buf + n, len - n, "\n\t\t: ");
155 190
156 return buf; 191 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
157} 192 IS_AVAIL1(cpu->extn_mpy.ver, "mpy "),
193 IS_AVAIL1(cpu->extn.norm, "norm "),
194 IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
195 IS_AVAIL1(cpu->extn.swap, "swap "),
196 IS_AVAIL1(cpu->extn.minmax, "minmax "),
197 IS_AVAIL1(cpu->extn.crc, "crc "),
198 IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));
158 199
159static const struct id_to_str mul_type_nm[] = { 200 if (cpu->bpu.ver)
160 { 0x0, "N/A"}, 201 n += scnprintf(buf + n, len - n,
161 { 0x1, "32x32 (spl Result Reg)" }, 202 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
162 { 0x2, "32x32 (ANY Result Reg)" } 203 IS_AVAIL1(cpu->bpu.full, "full"),
163}; 204 IS_AVAIL1(!cpu->bpu.full, "partial"),
205 cpu->bpu.num_cache, cpu->bpu.num_pred);
164 206
165static const struct id_to_str mac_mul_nm[] = { 207 return buf;
166 {0x0, "N/A"}, 208}
167 {0x1, "N/A"},
168 {0x2, "Dual 16 x 16"},
169 {0x3, "N/A"},
170 {0x4, "32x16"},
171 {0x5, "N/A"},
172 {0x6, "Dual 16x16 and 32x16"}
173};
174 209
175static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) 210static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
176{ 211{
@@ -178,67 +213,46 @@ static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
178 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; 213 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
179 214
180 FIX_PTR(cpu); 215 FIX_PTR(cpu);
181#define IS_AVAIL1(var, str) ((var) ? str : "")
182#define IS_AVAIL2(var, str) ((var == 0x2) ? str : "")
183#define IS_USED(cfg) (IS_ENABLED(cfg) ? "(in-use)" : "(not used)")
184 216
185 n += scnprintf(buf + n, len - n, 217 n += scnprintf(buf + n, len - n,
186 "Extn [700-Base]\t: %s %s %s %s %s %s\n", 218 "Vector Table\t: %#x\nUncached Base\t: %#x\n",
187 IS_AVAIL2(cpu->extn.norm, "norm,"), 219 cpu->vec_base, cpu->uncached_base);
188 IS_AVAIL2(cpu->extn.barrel, "barrel-shift,"), 220
189 IS_AVAIL1(cpu->extn.swap, "swap,"), 221 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
190 IS_AVAIL2(cpu->extn.minmax, "minmax,"), 222 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
191 IS_AVAIL1(cpu->extn.crc, "crc,"), 223 IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
192 IS_AVAIL2(cpu->extn.ext_arith, "ext-arith")); 224 IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
193 225
194 n += scnprintf(buf + n, len - n, "Extn [700-MPY]\t: %s", 226 if (cpu->extn.debug)
195 mul_type_nm[cpu->extn.mul].str); 227 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
196 228 IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
197 n += scnprintf(buf + n, len - n, " MAC MPY: %s\n", 229 IS_AVAIL1(cpu->extn.smart, "smaRT "),
198 mac_mul_nm[cpu->extn_mac_mul.type].str); 230 IS_AVAIL1(cpu->extn.rtt, "RTT "));
199 231
200 if (cpu->core.family == 0x34) { 232 if (cpu->dccm.sz || cpu->iccm.sz)
201 n += scnprintf(buf + n, len - n, 233 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
202 "Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n", 234 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
203 IS_USED(CONFIG_ARC_HAS_LLSC),
204 IS_USED(CONFIG_ARC_HAS_SWAPE),
205 IS_USED(CONFIG_ARC_HAS_RTSC));
206 }
207
208 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
209 !(cpu->dccm.sz || cpu->iccm.sz) ? "N/A" : "");
210
211 if (cpu->dccm.sz)
212 n += scnprintf(buf + n, len - n, "DCCM: @ %x, %d KB ",
213 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz));
214
215 if (cpu->iccm.sz)
216 n += scnprintf(buf + n, len - n, "ICCM: @ %x, %d KB",
217 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); 235 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
218 236
219 n += scnprintf(buf + n, len - n, "\nExtn [FPU]\t: %s",
220 !(cpu->fp.ver || cpu->dpfp.ver) ? "N/A" : "");
221
222 if (cpu->fp.ver)
223 n += scnprintf(buf + n, len - n, "SP [v%d] %s",
224 cpu->fp.ver, cpu->fp.fast ? "(fast)" : "");
225
226 if (cpu->dpfp.ver)
227 n += scnprintf(buf + n, len - n, "DP [v%d] %s",
228 cpu->dpfp.ver, cpu->dpfp.fast ? "(fast)" : "");
229
230 n += scnprintf(buf + n, len - n, "\n");
231
232 n += scnprintf(buf + n, len - n, 237 n += scnprintf(buf + n, len - n,
233 "OS ABI [v3]\t: no-legacy-syscalls\n"); 238 "OS ABI [v3]\t: no-legacy-syscalls\n");
234 239
235 return buf; 240 return buf;
236} 241}
237 242
238static void arc_chk_ccms(void) 243static void arc_chk_core_config(void)
239{ 244{
240#if defined(CONFIG_ARC_HAS_DCCM) || defined(CONFIG_ARC_HAS_ICCM)
241 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; 245 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
246 int fpu_enabled;
247
248 if (!cpu->timers.t0)
249 panic("Timer0 is not present!\n");
250
251 if (!cpu->timers.t1)
252 panic("Timer1 is not present!\n");
253
254 if (IS_ENABLED(CONFIG_ARC_HAS_RTSC) && !cpu->timers.rtsc)
255 panic("RTSC is not present\n");
242 256
243#ifdef CONFIG_ARC_HAS_DCCM 257#ifdef CONFIG_ARC_HAS_DCCM
244 /* 258 /*
@@ -256,33 +270,20 @@ static void arc_chk_ccms(void)
256 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) 270 if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
257 panic("Linux built with incorrect ICCM Size\n"); 271 panic("Linux built with incorrect ICCM Size\n");
258#endif 272#endif
259#endif
260}
261 273
262/* 274 /*
263 * Ensure that FP hardware and kernel config match 275 * FP hardware/software config sanity
264 * -If hardware contains DPFP, kernel needs to save/restore FPU state 276 * -If hardware contains DPFP, kernel needs to save/restore FPU state
265 * across context switches 277 * -If not, it will crash trying to save/restore the non-existant regs
266 * -If hardware lacks DPFP, but kernel configured to save FPU state then 278 *
267 * kernel trying to access non-existant DPFP regs will crash 279 * (only DPDP checked since SP has no arch visible regs)
268 * 280 */
269 * We only check for Dbl precision Floating Point, because only DPFP 281 fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
270 * hardware has dedicated regs which need to be saved/restored on ctx-sw
271 * (Single Precision uses core regs), thus kernel is kind of oblivious to it
272 */
273static void arc_chk_fpu(void)
274{
275 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
276 282
277 if (cpu->dpfp.ver) { 283 if (cpu->extn.fpu_dp && !fpu_enabled)
278#ifndef CONFIG_ARC_FPU_SAVE_RESTORE 284 pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
279 pr_warn("DPFP support broken in this kernel...\n"); 285 else if (!cpu->extn.fpu_dp && fpu_enabled)
280#endif 286 panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
281 } else {
282#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
283 panic("H/w lacks DPFP support, apps won't work\n");
284#endif
285 }
286} 287}
287 288
288/* 289/*
@@ -303,15 +304,11 @@ void setup_processor(void)
303 304
304 arc_mmu_init(); 305 arc_mmu_init();
305 arc_cache_init(); 306 arc_cache_init();
306 arc_chk_ccms();
307 307
308 printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); 308 printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
309
310#ifdef CONFIG_SMP
311 printk(arc_platform_smp_cpuinfo()); 309 printk(arc_platform_smp_cpuinfo());
312#endif
313 310
314 arc_chk_fpu(); 311 arc_chk_core_config();
315} 312}
316 313
317static inline int is_kernel(unsigned long addr) 314static inline int is_kernel(unsigned long addr)
@@ -360,11 +357,7 @@ void __init setup_arch(char **cmdline_p)
360 machine_desc->init_early(); 357 machine_desc->init_early();
361 358
362 setup_processor(); 359 setup_processor();
363
364#ifdef CONFIG_SMP
365 smp_init_cpus(); 360 smp_init_cpus();
366#endif
367
368 setup_arch_memory(); 361 setup_arch_memory();
369 362
370 /* copy flat DT out of .init and then unflatten it */ 363 /* copy flat DT out of .init and then unflatten it */
@@ -385,7 +378,13 @@ void __init setup_arch(char **cmdline_p)
385 378
386static int __init customize_machine(void) 379static int __init customize_machine(void)
387{ 380{
388 /* Add platform devices */ 381 of_clk_init(NULL);
382 /*
383 * Traverses flattened DeviceTree - registering platform devices
384 * (if any) complete with their resources
385 */
386 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
387
389 if (machine_desc->init_machine) 388 if (machine_desc->init_machine)
390 machine_desc->init_machine(); 389 machine_desc->init_machine();
391 390
@@ -419,19 +418,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
419 418
420 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 419 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
421 420
422 seq_printf(m, "Bogo MIPS : \t%lu.%02lu\n", 421 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
423 loops_per_jiffy / (500000 / HZ), 422 loops_per_jiffy / (500000 / HZ),
424 (loops_per_jiffy / (5000 / HZ)) % 100); 423 (loops_per_jiffy / (5000 / HZ)) % 100);
425 424
426 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); 425 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
427
428 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); 426 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
429
430 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); 427 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
431
432#ifdef CONFIG_SMP
433 seq_printf(m, arc_platform_smp_cpuinfo()); 428 seq_printf(m, arc_platform_smp_cpuinfo());
434#endif
435 429
436 free_page((unsigned long)str); 430 free_page((unsigned long)str);
437done: 431done: