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-rw-r--r--arch/alpha/kernel/sys_dp264.c689
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diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
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1/*
2 * linux/arch/alpha/kernel/sys_dp264.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996, 1999 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Modified by Christopher C. Chimelis, 2001 to
9 * add support for the addition of Shark to the
10 * Tsunami family.
11 *
12 * Code supporting the DP264 (EV6+TSUNAMI).
13 */
14
15#include <linux/config.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/bitops.h>
23
24#include <asm/ptrace.h>
25#include <asm/system.h>
26#include <asm/dma.h>
27#include <asm/irq.h>
28#include <asm/mmu_context.h>
29#include <asm/io.h>
30#include <asm/pgtable.h>
31#include <asm/core_tsunami.h>
32#include <asm/hwrpb.h>
33#include <asm/tlbflush.h>
34
35#include "proto.h"
36#include "irq_impl.h"
37#include "pci_impl.h"
38#include "machvec_impl.h"
39
40
41/* Note mask bit is true for ENABLED irqs. */
42static unsigned long cached_irq_mask;
43/* dp264 boards handle at max four CPUs */
44static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL };
45
46DEFINE_SPINLOCK(dp264_irq_lock);
47
48static void
49tsunami_update_irq_hw(unsigned long mask)
50{
51 register tsunami_cchip *cchip = TSUNAMI_cchip;
52 unsigned long isa_enable = 1UL << 55;
53 register int bcpu = boot_cpuid;
54
55#ifdef CONFIG_SMP
56 volatile unsigned long *dim0, *dim1, *dim2, *dim3;
57 unsigned long mask0, mask1, mask2, mask3, dummy;
58
59 mask &= ~isa_enable;
60 mask0 = mask & cpu_irq_affinity[0];
61 mask1 = mask & cpu_irq_affinity[1];
62 mask2 = mask & cpu_irq_affinity[2];
63 mask3 = mask & cpu_irq_affinity[3];
64
65 if (bcpu == 0) mask0 |= isa_enable;
66 else if (bcpu == 1) mask1 |= isa_enable;
67 else if (bcpu == 2) mask2 |= isa_enable;
68 else mask3 |= isa_enable;
69
70 dim0 = &cchip->dim0.csr;
71 dim1 = &cchip->dim1.csr;
72 dim2 = &cchip->dim2.csr;
73 dim3 = &cchip->dim3.csr;
74 if (!cpu_possible(0)) dim0 = &dummy;
75 if (!cpu_possible(1)) dim1 = &dummy;
76 if (!cpu_possible(2)) dim2 = &dummy;
77 if (!cpu_possible(3)) dim3 = &dummy;
78
79 *dim0 = mask0;
80 *dim1 = mask1;
81 *dim2 = mask2;
82 *dim3 = mask3;
83 mb();
84 *dim0;
85 *dim1;
86 *dim2;
87 *dim3;
88#else
89 volatile unsigned long *dimB;
90 if (bcpu == 0) dimB = &cchip->dim0.csr;
91 else if (bcpu == 1) dimB = &cchip->dim1.csr;
92 else if (bcpu == 2) dimB = &cchip->dim2.csr;
93 else dimB = &cchip->dim3.csr;
94
95 *dimB = mask | isa_enable;
96 mb();
97 *dimB;
98#endif
99}
100
101static void
102dp264_enable_irq(unsigned int irq)
103{
104 spin_lock(&dp264_irq_lock);
105 cached_irq_mask |= 1UL << irq;
106 tsunami_update_irq_hw(cached_irq_mask);
107 spin_unlock(&dp264_irq_lock);
108}
109
110static void
111dp264_disable_irq(unsigned int irq)
112{
113 spin_lock(&dp264_irq_lock);
114 cached_irq_mask &= ~(1UL << irq);
115 tsunami_update_irq_hw(cached_irq_mask);
116 spin_unlock(&dp264_irq_lock);
117}
118
119static unsigned int
120dp264_startup_irq(unsigned int irq)
121{
122 dp264_enable_irq(irq);
123 return 0; /* never anything pending */
124}
125
126static void
127dp264_end_irq(unsigned int irq)
128{
129 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
130 dp264_enable_irq(irq);
131}
132
133static void
134clipper_enable_irq(unsigned int irq)
135{
136 spin_lock(&dp264_irq_lock);
137 cached_irq_mask |= 1UL << (irq - 16);
138 tsunami_update_irq_hw(cached_irq_mask);
139 spin_unlock(&dp264_irq_lock);
140}
141
142static void
143clipper_disable_irq(unsigned int irq)
144{
145 spin_lock(&dp264_irq_lock);
146 cached_irq_mask &= ~(1UL << (irq - 16));
147 tsunami_update_irq_hw(cached_irq_mask);
148 spin_unlock(&dp264_irq_lock);
149}
150
151static unsigned int
152clipper_startup_irq(unsigned int irq)
153{
154 clipper_enable_irq(irq);
155 return 0; /* never anything pending */
156}
157
158static void
159clipper_end_irq(unsigned int irq)
160{
161 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
162 clipper_enable_irq(irq);
163}
164
165static void
166cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
167{
168 int cpu;
169
170 for (cpu = 0; cpu < 4; cpu++) {
171 unsigned long aff = cpu_irq_affinity[cpu];
172 if (cpu_isset(cpu, affinity))
173 aff |= 1UL << irq;
174 else
175 aff &= ~(1UL << irq);
176 cpu_irq_affinity[cpu] = aff;
177 }
178}
179
180static void
181dp264_set_affinity(unsigned int irq, cpumask_t affinity)
182{
183 spin_lock(&dp264_irq_lock);
184 cpu_set_irq_affinity(irq, affinity);
185 tsunami_update_irq_hw(cached_irq_mask);
186 spin_unlock(&dp264_irq_lock);
187}
188
189static void
190clipper_set_affinity(unsigned int irq, cpumask_t affinity)
191{
192 spin_lock(&dp264_irq_lock);
193 cpu_set_irq_affinity(irq - 16, affinity);
194 tsunami_update_irq_hw(cached_irq_mask);
195 spin_unlock(&dp264_irq_lock);
196}
197
198static struct hw_interrupt_type dp264_irq_type = {
199 .typename = "DP264",
200 .startup = dp264_startup_irq,
201 .shutdown = dp264_disable_irq,
202 .enable = dp264_enable_irq,
203 .disable = dp264_disable_irq,
204 .ack = dp264_disable_irq,
205 .end = dp264_end_irq,
206 .set_affinity = dp264_set_affinity,
207};
208
209static struct hw_interrupt_type clipper_irq_type = {
210 .typename = "CLIPPER",
211 .startup = clipper_startup_irq,
212 .shutdown = clipper_disable_irq,
213 .enable = clipper_enable_irq,
214 .disable = clipper_disable_irq,
215 .ack = clipper_disable_irq,
216 .end = clipper_end_irq,
217 .set_affinity = clipper_set_affinity,
218};
219
220static void
221dp264_device_interrupt(unsigned long vector, struct pt_regs * regs)
222{
223#if 1
224 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!! \n");
225#else
226 unsigned long pld;
227 unsigned int i;
228
229 /* Read the interrupt summary register of TSUNAMI */
230 pld = TSUNAMI_cchip->dir0.csr;
231
232 /*
233 * Now for every possible bit set, work through them and call
234 * the appropriate interrupt handler.
235 */
236 while (pld) {
237 i = ffz(~pld);
238 pld &= pld - 1; /* clear least bit set */
239 if (i == 55)
240 isa_device_interrupt(vector, regs);
241 else
242 handle_irq(16 + i, 16 + i, regs);
243#if 0
244 TSUNAMI_cchip->dir0.csr = 1UL << i; mb();
245 tmp = TSUNAMI_cchip->dir0.csr;
246#endif
247 }
248#endif
249}
250
251static void
252dp264_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
253{
254 int irq;
255
256 irq = (vector - 0x800) >> 4;
257
258 /*
259 * The SRM console reports PCI interrupts with a vector calculated by:
260 *
261 * 0x900 + (0x10 * DRIR-bit)
262 *
263 * So bit 16 shows up as IRQ 32, etc.
264 *
265 * On DP264/BRICK/MONET, we adjust it down by 16 because at least
266 * that many of the low order bits of the DRIR are not used, and
267 * so we don't count them.
268 */
269 if (irq >= 32)
270 irq -= 16;
271
272 handle_irq(irq, regs);
273}
274
275static void
276clipper_srm_device_interrupt(unsigned long vector, struct pt_regs * regs)
277{
278 int irq;
279
280 irq = (vector - 0x800) >> 4;
281
282/*
283 * The SRM console reports PCI interrupts with a vector calculated by:
284 *
285 * 0x900 + (0x10 * DRIR-bit)
286 *
287 * So bit 16 shows up as IRQ 32, etc.
288 *
289 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need
290 * to scale down the vector reported, we just use it.
291 *
292 * Eg IRQ 24 is DRIR bit 8, etc, etc
293 */
294 handle_irq(irq, regs);
295}
296
297static void __init
298init_tsunami_irqs(struct hw_interrupt_type * ops, int imin, int imax)
299{
300 long i;
301 for (i = imin; i <= imax; ++i) {
302 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
303 irq_desc[i].handler = ops;
304 }
305}
306
307static void __init
308dp264_init_irq(void)
309{
310 outb(0, DMA1_RESET_REG);
311 outb(0, DMA2_RESET_REG);
312 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
313 outb(0, DMA2_MASK_REG);
314
315 if (alpha_using_srm)
316 alpha_mv.device_interrupt = dp264_srm_device_interrupt;
317
318 tsunami_update_irq_hw(0);
319
320 init_i8259a_irqs();
321 init_tsunami_irqs(&dp264_irq_type, 16, 47);
322}
323
324static void __init
325clipper_init_irq(void)
326{
327 outb(0, DMA1_RESET_REG);
328 outb(0, DMA2_RESET_REG);
329 outb(DMA_MODE_CASCADE, DMA2_MODE_REG);
330 outb(0, DMA2_MASK_REG);
331
332 if (alpha_using_srm)
333 alpha_mv.device_interrupt = clipper_srm_device_interrupt;
334
335 tsunami_update_irq_hw(0);
336
337 init_i8259a_irqs();
338 init_tsunami_irqs(&clipper_irq_type, 24, 63);
339}
340
341
342/*
343 * PCI Fixup configuration.
344 *
345 * Summary @ TSUNAMI_CSR_DIM0:
346 * Bit Meaning
347 * 0-17 Unused
348 *18 Interrupt SCSI B (Adaptec 7895 builtin)
349 *19 Interrupt SCSI A (Adaptec 7895 builtin)
350 *20 Interrupt Line D from slot 2 PCI0
351 *21 Interrupt Line C from slot 2 PCI0
352 *22 Interrupt Line B from slot 2 PCI0
353 *23 Interrupt Line A from slot 2 PCI0
354 *24 Interrupt Line D from slot 1 PCI0
355 *25 Interrupt Line C from slot 1 PCI0
356 *26 Interrupt Line B from slot 1 PCI0
357 *27 Interrupt Line A from slot 1 PCI0
358 *28 Interrupt Line D from slot 0 PCI0
359 *29 Interrupt Line C from slot 0 PCI0
360 *30 Interrupt Line B from slot 0 PCI0
361 *31 Interrupt Line A from slot 0 PCI0
362 *
363 *32 Interrupt Line D from slot 3 PCI1
364 *33 Interrupt Line C from slot 3 PCI1
365 *34 Interrupt Line B from slot 3 PCI1
366 *35 Interrupt Line A from slot 3 PCI1
367 *36 Interrupt Line D from slot 2 PCI1
368 *37 Interrupt Line C from slot 2 PCI1
369 *38 Interrupt Line B from slot 2 PCI1
370 *39 Interrupt Line A from slot 2 PCI1
371 *40 Interrupt Line D from slot 1 PCI1
372 *41 Interrupt Line C from slot 1 PCI1
373 *42 Interrupt Line B from slot 1 PCI1
374 *43 Interrupt Line A from slot 1 PCI1
375 *44 Interrupt Line D from slot 0 PCI1
376 *45 Interrupt Line C from slot 0 PCI1
377 *46 Interrupt Line B from slot 0 PCI1
378 *47 Interrupt Line A from slot 0 PCI1
379 *48-52 Unused
380 *53 PCI0 NMI (from Cypress)
381 *54 PCI0 SMI INT (from Cypress)
382 *55 PCI0 ISA Interrupt (from Cypress)
383 *56-60 Unused
384 *61 PCI1 Bus Error
385 *62 PCI0 Bus Error
386 *63 Reserved
387 *
388 * IdSel
389 * 5 Cypress Bridge I/O
390 * 6 SCSI Adaptec builtin
391 * 7 64 bit PCI option slot 0 (all busses)
392 * 8 64 bit PCI option slot 1 (all busses)
393 * 9 64 bit PCI option slot 2 (all busses)
394 * 10 64 bit PCI option slot 3 (not bus 0)
395 */
396
397static int __init
398dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
399{
400 static char irq_tab[6][5] __initdata = {
401 /*INT INTA INTB INTC INTD */
402 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */
403 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/
404 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */
405 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */
406 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */
407 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */
408 };
409 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5;
410
411 struct pci_controller *hose = dev->sysdata;
412 int irq = COMMON_TABLE_LOOKUP;
413
414 if (irq > 0) {
415 irq += 16 * hose->index;
416 } else {
417 /* ??? The Contaq IDE controller on the ISA bridge uses
418 "legacy" interrupts 14 and 15. I don't know if anything
419 can wind up at the same slot+pin on hose1, so we'll
420 just have to trust whatever value the console might
421 have assigned. */
422
423 u8 irq8;
424 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8);
425 irq = irq8;
426 }
427
428 return irq;
429}
430
431static int __init
432monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
433{
434 static char irq_tab[13][5] __initdata = {
435 /*INT INTA INTB INTC INTD */
436 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */
437 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */
438 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */
439 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */
440 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
441 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */
442#if 1
443 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
444 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/
445#else
446 { -1, -1, -1, -1, -1}, /* IdSel 9 unused */
447 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
448#endif
449 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/
450 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/
451 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/
452 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/
453 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/
454 };
455 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5;
456 return COMMON_TABLE_LOOKUP;
457}
458
459static u8 __init
460monet_swizzle(struct pci_dev *dev, u8 *pinp)
461{
462 struct pci_controller *hose = dev->sysdata;
463 int slot, pin = *pinp;
464
465 if (!dev->bus->parent) {
466 slot = PCI_SLOT(dev->devfn);
467 }
468 /* Check for the built-in bridge on hose 1. */
469 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) {
470 slot = PCI_SLOT(dev->devfn);
471 } else {
472 /* Must be a card-based bridge. */
473 do {
474 /* Check for built-in bridge on hose 1. */
475 if (hose->index == 1 &&
476 PCI_SLOT(dev->bus->self->devfn) == 8) {
477 slot = PCI_SLOT(dev->devfn);
478 break;
479 }
480 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)) ;
481
482 /* Move up the chain of bridges. */
483 dev = dev->bus->self;
484 /* Slot of the next bridge. */
485 slot = PCI_SLOT(dev->devfn);
486 } while (dev->bus->self);
487 }
488 *pinp = pin;
489 return slot;
490}
491
492static int __init
493webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
494{
495 static char irq_tab[13][5] __initdata = {
496 /*INT INTA INTB INTC INTD */
497 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */
498 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */
499 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */
500 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */
501 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */
502 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */
503 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */
504 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */
505 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */
506 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */
507 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */
508 };
509 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5;
510 return COMMON_TABLE_LOOKUP;
511}
512
513static int __init
514clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
515{
516 static char irq_tab[7][5] __initdata = {
517 /*INT INTA INTB INTC INTD */
518 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */
519 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */
520 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */
521 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */
522 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */
523 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */
524 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */
525 };
526 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5;
527
528 struct pci_controller *hose = dev->sysdata;
529 int irq = COMMON_TABLE_LOOKUP;
530
531 if (irq > 0)
532 irq += 16 * hose->index;
533
534 return irq;
535}
536
537static void __init
538dp264_init_pci(void)
539{
540 common_init_pci();
541 SMC669_Init(0);
542}
543
544static void __init
545monet_init_pci(void)
546{
547 common_init_pci();
548 SMC669_Init(1);
549 es1888_init();
550}
551
552static void __init
553webbrick_init_arch(void)
554{
555 tsunami_init_arch();
556
557 /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */
558 hose_head->sg_isa->align_entry = 4;
559 hose_head->sg_pci->align_entry = 4;
560}
561
562
563/*
564 * The System Vectors
565 */
566
567struct alpha_machine_vector dp264_mv __initmv = {
568 .vector_name = "DP264",
569 DO_EV6_MMU,
570 DO_DEFAULT_RTC,
571 DO_TSUNAMI_IO,
572 .machine_check = tsunami_machine_check,
573 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
574 .min_io_address = DEFAULT_IO_BASE,
575 .min_mem_address = DEFAULT_MEM_BASE,
576 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
577
578 .nr_irqs = 64,
579 .device_interrupt = dp264_device_interrupt,
580
581 .init_arch = tsunami_init_arch,
582 .init_irq = dp264_init_irq,
583 .init_rtc = common_init_rtc,
584 .init_pci = dp264_init_pci,
585 .kill_arch = tsunami_kill_arch,
586 .pci_map_irq = dp264_map_irq,
587 .pci_swizzle = common_swizzle,
588};
589ALIAS_MV(dp264)
590
591struct alpha_machine_vector monet_mv __initmv = {
592 .vector_name = "Monet",
593 DO_EV6_MMU,
594 DO_DEFAULT_RTC,
595 DO_TSUNAMI_IO,
596 .machine_check = tsunami_machine_check,
597 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
598 .min_io_address = DEFAULT_IO_BASE,
599 .min_mem_address = DEFAULT_MEM_BASE,
600 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
601
602 .nr_irqs = 64,
603 .device_interrupt = dp264_device_interrupt,
604
605 .init_arch = tsunami_init_arch,
606 .init_irq = dp264_init_irq,
607 .init_rtc = common_init_rtc,
608 .init_pci = monet_init_pci,
609 .kill_arch = tsunami_kill_arch,
610 .pci_map_irq = monet_map_irq,
611 .pci_swizzle = monet_swizzle,
612};
613
614struct alpha_machine_vector webbrick_mv __initmv = {
615 .vector_name = "Webbrick",
616 DO_EV6_MMU,
617 DO_DEFAULT_RTC,
618 DO_TSUNAMI_IO,
619 .machine_check = tsunami_machine_check,
620 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
621 .min_io_address = DEFAULT_IO_BASE,
622 .min_mem_address = DEFAULT_MEM_BASE,
623 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
624
625 .nr_irqs = 64,
626 .device_interrupt = dp264_device_interrupt,
627
628 .init_arch = webbrick_init_arch,
629 .init_irq = dp264_init_irq,
630 .init_rtc = common_init_rtc,
631 .init_pci = common_init_pci,
632 .kill_arch = tsunami_kill_arch,
633 .pci_map_irq = webbrick_map_irq,
634 .pci_swizzle = common_swizzle,
635};
636
637struct alpha_machine_vector clipper_mv __initmv = {
638 .vector_name = "Clipper",
639 DO_EV6_MMU,
640 DO_DEFAULT_RTC,
641 DO_TSUNAMI_IO,
642 .machine_check = tsunami_machine_check,
643 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
644 .min_io_address = DEFAULT_IO_BASE,
645 .min_mem_address = DEFAULT_MEM_BASE,
646 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
647
648 .nr_irqs = 64,
649 .device_interrupt = dp264_device_interrupt,
650
651 .init_arch = tsunami_init_arch,
652 .init_irq = clipper_init_irq,
653 .init_rtc = common_init_rtc,
654 .init_pci = common_init_pci,
655 .kill_arch = tsunami_kill_arch,
656 .pci_map_irq = clipper_map_irq,
657 .pci_swizzle = common_swizzle,
658};
659
660/* Sharks strongly resemble Clipper, at least as far
661 * as interrupt routing, etc, so we're using the
662 * same functions as Clipper does
663 */
664
665struct alpha_machine_vector shark_mv __initmv = {
666 .vector_name = "Shark",
667 DO_EV6_MMU,
668 DO_DEFAULT_RTC,
669 DO_TSUNAMI_IO,
670 .machine_check = tsunami_machine_check,
671 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
672 .min_io_address = DEFAULT_IO_BASE,
673 .min_mem_address = DEFAULT_MEM_BASE,
674 .pci_dac_offset = TSUNAMI_DAC_OFFSET,
675
676 .nr_irqs = 64,
677 .device_interrupt = dp264_device_interrupt,
678
679 .init_arch = tsunami_init_arch,
680 .init_irq = clipper_init_irq,
681 .init_rtc = common_init_rtc,
682 .init_pci = common_init_pci,
683 .kill_arch = tsunami_kill_arch,
684 .pci_map_irq = clipper_map_irq,
685 .pci_swizzle = common_swizzle,
686};
687
688/* No alpha_mv alias for webbrick/monet/clipper, since we compile them
689 in unconditionally with DP264; setup_arch knows how to cope. */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 10:34:04 -0500