5 files changed, 141 insertions, 29 deletions

diff --git a/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
new file mode 100644
index 000000000000..d3058768b23d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/apm-xgene-dma.txt
@@ -0,0 +1,47 @@
+Applied Micro X-Gene SoC DMA nodes
+
+DMA nodes are defined to describe on-chip DMA interfaces in
+APM X-Gene SoC.
+
+Required properties for DMA interfaces:
+- compatible: Should be "apm,xgene-dma".
+- device_type: set to "dma".
+- reg: Address and length of the register set for the device.
+  It contains the information of registers in the following order:
+  1st - DMA control and status register address space.
+  2nd - Descriptor ring control and status register address space.
+  3rd - Descriptor ring command register address space.
+  4th - Soc efuse register address space.
+- interrupts: DMA has 5 interrupts sources. 1st interrupt is
+  DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
+  are completion interrupts for each DMA channels.
+- clocks: Reference to the clock entry.
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+
+Example:
+        dmaclk: dmaclk@1f27c000 {
+                compatible = "apm,xgene-device-clock";
+                #clock-cells = <1>;
+                clocks = <&socplldiv2 0>;
+                reg = <0x0 0x1f27c000 0x0 0x1000>;
+                reg-names = "csr-reg";
+                clock-output-names = "dmaclk";
+        };
+
+        dma: dma@1f270000 {
+                        compatible = "apm,xgene-storm-dma";
+                        device_type = "dma";
+                        reg = <0x0 0x1f270000 0x0 0x10000>,
+                              <0x0 0x1f200000 0x0 0x10000>,
+                              <0x0 0x1b008000 0x0 0x2000>,
+                              <0x0 0x1054a000 0x0 0x100>;
+                        interrupts = <0x0 0x82 0x4>,
+                                     <0x0 0xb8 0x4>,
+                                     <0x0 0xb9 0x4>,
+                                     <0x0 0xba 0x4>,
+                                     <0x0 0xbb 0x4>;
+                        dma-coherent;
+                        clocks = <&dmaclk 0>;
+        };
diff --git a/Documentation/devicetree/bindings/dma/jz4780-dma.txt b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
new file mode 100644
index 000000000000..f25feee62b15
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/jz4780-dma.txt
@@ -0,0 +1,56 @@
+* Ingenic JZ4780 DMA Controller
+
+Required properties:
+
+- compatible: Should be "ingenic,jz4780-dma"
+- reg: Should contain the DMA controller registers location and length.
+- interrupts: Should contain the interrupt specifier of the DMA controller.
+- interrupt-parent: Should be the phandle of the interrupt controller that
+- clocks: Should contain a clock specifier for the JZ4780 PDMA clock.
+- #dma-cells: Must be <2>. Number of integer cells in the dmas property of
+  DMA clients (see below).
+
+Optional properties:
+
+- ingenic,reserved-channels: Bitmask of channels to reserve for devices that
+  need a specific channel. These channels will only be assigned when explicitly
+  requested by a client. The primary use for this is channels 0 and 1, which
+  can be configured to have special behaviour for NAND/BCH when using
+  programmable firmware.
+
+Example:
+
+dma: dma@13420000 {
+        compatible = "ingenic,jz4780-dma";
+        reg = <0x13420000 0x10000>;
+
+        interrupt-parent = <&intc>;
+        interrupts = <10>;
+
+        clocks = <&cgu JZ4780_CLK_PDMA>;
+
+        #dma-cells = <2>;
+
+        ingenic,reserved-channels = <0x3>;
+};
+
+DMA clients must use the format described in dma.txt, giving a phandle to the
+DMA controller plus the following 2 integer cells:
+
+1. Request type: The DMA request type for transfers to/from the device on
+   the allocated channel, as defined in the SoC documentation.
+
+2. Channel: If set to 0xffffffff, any available channel will be allocated for
+   the client. Otherwise, the exact channel specified will be used. The channel
+   should be reserved on the DMA controller using the ingenic,reserved-channels
+   property.
+
+Example:
+
+uart0: serial@10030000 {
+        ...
+        dmas = <&dma 0x14 0xffffffff
+                &dma 0x15 0xffffffff>;
+        dma-names = "tx", "rx";
+        ...
+};
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
index f8c3311b7153..1c9d48ea4914 100644
--- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible: must be one of the following:
  * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084
  * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960
+ * "qcom,bam-v1.7.0" for MSM8916
 - reg: Address range for DMA registers
 - interrupts: Should contain the one interrupt shared by all channels
 - #dma-cells: must be <1>, the cell in the dmas property of the client device
diff --git a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt b/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
deleted file mode 100644
index 61bca509d7b9..000000000000
--- a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* R-Car Audio DMAC peri peri Device Tree bindings
-
-Required properties:
-- compatible:   should be "renesas,rcar-audmapp"
-- #dma-cells:   should be <1>, see "dmas" property below
-
-Example:
-        audmapp: audio-dma-pp@0xec740000 {
-                compatible = "renesas,rcar-audmapp";
-                #dma-cells = <1>;
-
-                reg = <0 0xec740000 0 0x200>;
-        };
-
-
-* DMA client
-
-Required properties:
-- dmas:         a list of <[DMA multiplexer phandle] [SRS << 8 | DRS]> pairs.
-                where SRS/DRS are specified in the SoC manual.
-                It will be written into PDMACHCR as high 16-bit parts.
-- dma-names:    a list of DMA channel names, one per "dmas" entry
-
-Example:
-
-        dmas = <&audmapp 0x2d00
-                &audmapp 0x3700>;
-        dma-names =  "src0_ssiu0",
-                     "dvc0_ssiu0";
diff --git a/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
new file mode 100644
index 000000000000..040f365954cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/renesas,usb-dmac.txt
@@ -0,0 +1,37 @@
+* Renesas USB DMA Controller Device Tree bindings
+
+Required Properties:
+- compatible: must contain "renesas,usb-dmac"
+- reg: base address and length of the registers block for the DMAC
+- interrupts: interrupt specifiers for the DMAC, one for each entry in
+  interrupt-names.
+- interrupt-names: one entry per channel, named "ch%u", where %u is the
+  channel number ranging from zero to the number of channels minus one.
+- clocks: a list of phandle + clock-specifier pairs.
+- #dma-cells: must be <1>, the cell specifies the channel number of the DMAC
+  port connected to the DMA client.
+- dma-channels: number of DMA channels
+
+Example: R8A7790 (R-Car H2) USB-DMACs
+
+        usb_dmac0: dma-controller@e65a0000 {
+                compatible = "renesas,usb-dmac";
+                reg = <0 0xe65a0000 0 0x100>;
+                interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH
+                              0 109 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "ch0", "ch1";
+                clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
+                #dma-cells = <1>;
+                dma-channels = <2>;
+        };
+
+        usb_dmac1: dma-controller@e65b0000 {
+                compatible = "renesas,usb-dmac";
+                reg = <0 0xe65b0000 0 0x100>;
+                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH
+                              0 110 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "ch0", "ch1";
+                clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
+                #dma-cells = <1>;
+                dma-channels = <2>;
+        };