5 files changed, 122 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
index 64fc82bc8928..0df6acacfaea 100644
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ b/Documentation/devicetree/bindings/arm/primecell.txt
@@ -16,14 +16,31 @@ Optional properties:
 - clocks : From common clock binding. First clock is phandle to clock for apb
         pclk. Additional clocks are optional and specific to those peripherals.
 - clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
+- dmas : From common DMA binding. If present, refers to one or more dma channels.
+- dma-names : From common DMA binding, needs to match the 'dmas' property.
+              Devices with exactly one receive and transmit channel shall name
+              these "rx" and "tx", respectively.
+- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
+- pinctrl-names : Names corresponding to the numbered pinctrl states
+- interrupts : one or more interrupt specifiers
+- interrupt-names : names corresponding to the interrupts properties
 
 Example:
 
 serial@fff36000 {
         compatible = "arm,pl011", "arm,primecell";
         arm,primecell-periphid = <0x00341011>;
+
         clocks = <&pclk>;
         clock-names = "apb_pclk";
-        
+
+        dmas = <&dma-controller 4>, <&dma-controller 5>;
+        dma-names = "rx", "tx"; 
+
+        pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
+        pinctrl-1 = <&uart0_sleep_mode>;
+        pinctrl-names = "default","sleep";
+
+        interrupts = <0 11 0x4>;
 };
 
diff --git a/Documentation/devicetree/bindings/ata/pata-arasan.txt b/Documentation/devicetree/bindings/ata/pata-arasan.txt
index 95ec7f825ede..2aff154be84e 100644
--- a/Documentation/devicetree/bindings/ata/pata-arasan.txt
+++ b/Documentation/devicetree/bindings/ata/pata-arasan.txt
@@ -6,6 +6,26 @@ Required properties:
 - interrupt-parent: Should be the phandle for the interrupt controller
   that services interrupts for this device
 - interrupt: Should contain the CF interrupt number
+- clock-frequency: Interface clock rate, in Hz, one of
+       25000000
+       33000000
+       40000000
+       50000000
+       66000000
+       75000000
+      100000000
+      125000000
+      150000000
+      166000000
+      200000000
+
+Optional properties:
+- arasan,broken-udma: if present, UDMA mode is unusable
+- arasan,broken-mwdma: if present, MWDMA mode is unusable
+- arasan,broken-pio: if present, PIO mode is unusable
+- dmas: one DMA channel, as described in bindings/dma/dma.txt
+  required unless both UDMA and MWDMA mode are broken
+- dma-names: the corresponding channel name, must be "data"
 
 Example:
 
@@ -14,4 +34,6 @@ Example:
                 reg = <0xfc000000 0x1000>;
                 interrupt-parent = <&vic1>;
                 interrupts = <12>;
+                dmas = <&dma-controller 23>;
+                dma-names = "data";
         };
diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt
new file mode 100644
index 000000000000..5d2e840ae65c
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/pl011.txt
@@ -0,0 +1,17 @@
+* ARM AMBA Primecell PL011 serial UART
+
+Required properties:
+- compatible: must be "arm,primecell", "arm,pl011"
+- reg: exactly one register range with length 0x1000
+- interrupts: exactly one interrupt specifier
+
+Optional properties:
+- pinctrl: When present, must have one state named "sleep"
+           and one state named "default"
+- clocks:  When present, must refer to exactly one clock named
+           "apb_pclk"
+- dmas:    When present, may have one or two dma channels.
+           The first one must be named "rx", the second one
+           must be named "tx".
+
+See also bindings/arm/primecell.txt
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt
index f158fd31cfda..22ed6797216d 100644
--- a/Documentation/devicetree/bindings/spi/spi_pl022.txt
+++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt
@@ -16,6 +16,11 @@ Optional properties:
                             device will be suspended immediately
 - pl022,rt : indicates the controller should run the message pump with realtime
              priority to minimise the transfer latency on the bus (boolean)
+- dmas : Two or more DMA channel specifiers following the convention outlined
+         in bindings/dma/dma.txt
+- dma-names: Names for the dma channels, if present. There must be at
+             least one channel named "tx" for transmit and named "rx" for
+             receive.
 
 
 SPI slave nodes must be children of the SPI master node and can
@@ -32,3 +37,34 @@ contain the following properties.
 - pl022,wait-state : Microwire interface: Wait state
 - pl022,duplex : Microwire interface: Full/Half duplex
 
+
+Example:
+
+        spi@e0100000 {
+                compatible = "arm,pl022", "arm,primecell";
+                reg = <0xe0100000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <0 31 0x4>;
+                dmas = <&dma-controller 23 1>,
+                        <&dma-controller 24 0>;
+                dma-names = "rx", "tx";
+
+                m25p80@1 {
+                        compatible = "st,m25p80";
+                        reg = <1>;
+                        spi-max-frequency = <12000000>;
+                        spi-cpol;
+                        spi-cpha;
+                        pl022,hierarchy = <0>;
+                        pl022,interface = <0>;
+                        pl022,slave-tx-disable;
+                        pl022,com-mode = <0x2>;
+                        pl022,rx-level-trig = <0>;
+                        pl022,tx-level-trig = <0>;
+                        pl022,ctrl-len = <0x11>;
+                        pl022,wait-state = <0>;
+                        pl022,duplex = <0>;
+                };
+        };
+        
diff --git a/Documentation/devicetree/bindings/timer/arm,sp804.txt b/Documentation/devicetree/bindings/timer/arm,sp804.txt
new file mode 100644
index 000000000000..5cd8eee74af1
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,sp804.txt
@@ -0,0 +1,29 @@
+ARM sp804 Dual Timers
+---------------------------------------
+
+Required properties:
+- compatible: Should be "arm,sp804" & "arm,primecell"
+- interrupts: Should contain the list of Dual Timer interrupts. This is the
+        interrupt for timer 1 and timer 2. In the case of a single entry, it is
+        the combined interrupt or if "arm,sp804-has-irq" is present that
+        specifies which timer interrupt is connected.
+- reg: Should contain location and length for dual timer register.
+- clocks: clocks driving the dual timer hardware. This list should be 1 or 3
+        clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
+        apb_pclk. A single clock can also be specified if the same clock is
+        used for all clock inputs.
+
+Optional properties:
+- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
+        specifies if the irq connection is for timer 1 or timer 2. A value of 1
+        or 2 should be used.
+
+Example:
+
+        timer0: timer@fc800000 {
+                compatible = "arm,sp804", "arm,primecell";
+                reg = <0xfc800000 0x1000>;
+                interrupts = <0 0 4>, <0 1 4>;
+                clocks = <&timclk1 &timclk2 &pclk>;
+                clock-names = "timer1", "timer2", "apb_pclk";
+        };