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-rw-r--r--Documentation/kprobes.txt1
-rw-r--r--Documentation/powerpc/booting-without-of.txt1082
-rw-r--r--Documentation/powerpc/bootwrapper.txt141
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/board.txt29
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt67
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt21
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt41
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt18
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt15
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt45
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt58
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt24
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt51
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt60
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt70
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt22
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt21
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/diu.txt18
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/dma.txt127
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/gtm.txt31
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/guts.txt25
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/i2c.txt32
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/lbc.txt35
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/msi-pic.txt36
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/sata.txt29
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/sec.txt68
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/spi.txt24
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/ssi.txt38
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/tsec.txt69
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/usb.txt59
30 files changed, 1287 insertions, 1070 deletions
diff --git a/Documentation/kprobes.txt b/Documentation/kprobes.txt
index 6877e7187113..a79633d702bf 100644
--- a/Documentation/kprobes.txt
+++ b/Documentation/kprobes.txt
@@ -172,6 +172,7 @@ architectures:
172- ia64 (Does not support probes on instruction slot1.) 172- ia64 (Does not support probes on instruction slot1.)
173- sparc64 (Return probes not yet implemented.) 173- sparc64 (Return probes not yet implemented.)
174- arm 174- arm
175- ppc
175 176
1763. Configuring Kprobes 1773. Configuring Kprobes
177 178
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 1d2a772506cf..de2e5c05d6e7 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -41,23 +41,12 @@ Table of Contents
41 VI - System-on-a-chip devices and nodes 41 VI - System-on-a-chip devices and nodes
42 1) Defining child nodes of an SOC 42 1) Defining child nodes of an SOC
43 2) Representing devices without a current OF specification 43 2) Representing devices without a current OF specification
44 a) MDIO IO device 44 a) PHY nodes
45 b) Gianfar-compatible ethernet nodes 45 b) Interrupt controllers
46 c) PHY nodes 46 c) CFI or JEDEC memory-mapped NOR flash
47 d) Interrupt controllers 47 d) 4xx/Axon EMAC ethernet nodes
48 e) I2C 48 e) Xilinx IP cores
49 f) Freescale SOC USB controllers 49 f) USB EHCI controllers
50 g) Freescale SOC SEC Security Engines
51 h) Board Control and Status (BCSR)
52 i) Freescale QUICC Engine module (QE)
53 j) CFI or JEDEC memory-mapped NOR flash
54 k) Global Utilities Block
55 l) Freescale Communications Processor Module
56 m) Chipselect/Local Bus
57 n) 4xx/Axon EMAC ethernet nodes
58 o) Xilinx IP cores
59 p) Freescale Synchronous Serial Interface
60 q) USB EHCI controllers
61 50
62 VII - Marvell Discovery mv64[345]6x System Controller chips 51 VII - Marvell Discovery mv64[345]6x System Controller chips
63 1) The /system-controller node 52 1) The /system-controller node
@@ -1246,80 +1235,7 @@ descriptions for the SOC devices for which new nodes have been
1246defined; this list will expand as more and more SOC-containing 1235defined; this list will expand as more and more SOC-containing
1247platforms are moved over to use the flattened-device-tree model. 1236platforms are moved over to use the flattened-device-tree model.
1248 1237
1249 a) MDIO IO device 1238 a) PHY nodes
1250
1251 The MDIO is a bus to which the PHY devices are connected. For each
1252 device that exists on this bus, a child node should be created. See
1253 the definition of the PHY node below for an example of how to define
1254 a PHY.
1255
1256 Required properties:
1257 - reg : Offset and length of the register set for the device
1258 - compatible : Should define the compatible device type for the
1259 mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
1260
1261 Example:
1262
1263 mdio@24520 {
1264 reg = <24520 20>;
1265 compatible = "fsl,gianfar-mdio";
1266
1267 ethernet-phy@0 {
1268 ......
1269 };
1270 };
1271
1272
1273 b) Gianfar-compatible ethernet nodes
1274
1275 Required properties:
1276
1277 - device_type : Should be "network"
1278 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
1279 - compatible : Should be "gianfar"
1280 - reg : Offset and length of the register set for the device
1281 - mac-address : List of bytes representing the ethernet address of
1282 this controller
1283 - interrupts : <a b> where a is the interrupt number and b is a
1284 field that represents an encoding of the sense and level
1285 information for the interrupt. This should be encoded based on
1286 the information in section 2) depending on the type of interrupt
1287 controller you have.
1288 - interrupt-parent : the phandle for the interrupt controller that
1289 services interrupts for this device.
1290 - phy-handle : The phandle for the PHY connected to this ethernet
1291 controller.
1292 - fixed-link : <a b c d e> where a is emulated phy id - choose any,
1293 but unique to the all specified fixed-links, b is duplex - 0 half,
1294 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
1295 pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
1296
1297 Recommended properties:
1298
1299 - phy-connection-type : a string naming the controller/PHY interface type,
1300 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
1301 "tbi", or "rtbi". This property is only really needed if the connection
1302 is of type "rgmii-id", as all other connection types are detected by
1303 hardware.
1304
1305
1306 Example:
1307
1308 ethernet@24000 {
1309 #size-cells = <0>;
1310 device_type = "network";
1311 model = "TSEC";
1312 compatible = "gianfar";
1313 reg = <24000 1000>;
1314 mac-address = [ 00 E0 0C 00 73 00 ];
1315 interrupts = <d 3 e 3 12 3>;
1316 interrupt-parent = <40000>;
1317 phy-handle = <2452000>
1318 };
1319
1320
1321
1322 c) PHY nodes
1323 1239
1324 Required properties: 1240 Required properties:
1325 1241
@@ -1347,7 +1263,7 @@ platforms are moved over to use the flattened-device-tree model.
1347 }; 1263 };
1348 1264
1349 1265
1350 d) Interrupt controllers 1266 b) Interrupt controllers
1351 1267
1352 Some SOC devices contain interrupt controllers that are different 1268 Some SOC devices contain interrupt controllers that are different
1353 from the standard Open PIC specification. The SOC device nodes for 1269 from the standard Open PIC specification. The SOC device nodes for
@@ -1360,491 +1276,14 @@ platforms are moved over to use the flattened-device-tree model.
1360 1276
1361 pic@40000 { 1277 pic@40000 {
1362 linux,phandle = <40000>; 1278 linux,phandle = <40000>;
1363 clock-frequency = <0>;
1364 interrupt-controller; 1279 interrupt-controller;
1365 #address-cells = <0>; 1280 #address-cells = <0>;
1366 reg = <40000 40000>; 1281 reg = <40000 40000>;
1367 built-in;
1368 compatible = "chrp,open-pic"; 1282 compatible = "chrp,open-pic";
1369 device_type = "open-pic"; 1283 device_type = "open-pic";
1370 big-endian;
1371 };
1372
1373
1374 e) I2C
1375
1376 Required properties :
1377
1378 - device_type : Should be "i2c"
1379 - reg : Offset and length of the register set for the device
1380
1381 Recommended properties :
1382
1383 - compatible : Should be "fsl-i2c" for parts compatible with
1384 Freescale I2C specifications.
1385 - interrupts : <a b> where a is the interrupt number and b is a
1386 field that represents an encoding of the sense and level
1387 information for the interrupt. This should be encoded based on
1388 the information in section 2) depending on the type of interrupt
1389 controller you have.
1390 - interrupt-parent : the phandle for the interrupt controller that
1391 services interrupts for this device.
1392 - dfsrr : boolean; if defined, indicates that this I2C device has
1393 a digital filter sampling rate register
1394 - fsl5200-clocking : boolean; if defined, indicated that this device
1395 uses the FSL 5200 clocking mechanism.
1396
1397 Example :
1398
1399 i2c@3000 {
1400 interrupt-parent = <40000>;
1401 interrupts = <1b 3>;
1402 reg = <3000 18>;
1403 device_type = "i2c";
1404 compatible = "fsl-i2c";
1405 dfsrr;
1406 };
1407
1408
1409 f) Freescale SOC USB controllers
1410
1411 The device node for a USB controller that is part of a Freescale
1412 SOC is as described in the document "Open Firmware Recommended
1413 Practice : Universal Serial Bus" with the following modifications
1414 and additions :
1415
1416 Required properties :
1417 - compatible : Should be "fsl-usb2-mph" for multi port host USB
1418 controllers, or "fsl-usb2-dr" for dual role USB controllers
1419 - phy_type : For multi port host USB controllers, should be one of
1420 "ulpi", or "serial". For dual role USB controllers, should be
1421 one of "ulpi", "utmi", "utmi_wide", or "serial".
1422 - reg : Offset and length of the register set for the device
1423 - port0 : boolean; if defined, indicates port0 is connected for
1424 fsl-usb2-mph compatible controllers. Either this property or
1425 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
1426 controllers.
1427 - port1 : boolean; if defined, indicates port1 is connected for
1428 fsl-usb2-mph compatible controllers. Either this property or
1429 "port0" (or both) must be defined for "fsl-usb2-mph" compatible
1430 controllers.
1431 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
1432 controllers. Can be "host", "peripheral", or "otg". Default to
1433 "host" if not defined for backward compatibility.
1434
1435 Recommended properties :
1436 - interrupts : <a b> where a is the interrupt number and b is a
1437 field that represents an encoding of the sense and level
1438 information for the interrupt. This should be encoded based on
1439 the information in section 2) depending on the type of interrupt
1440 controller you have.
1441 - interrupt-parent : the phandle for the interrupt controller that
1442 services interrupts for this device.
1443
1444 Example multi port host USB controller device node :
1445 usb@22000 {
1446 compatible = "fsl-usb2-mph";
1447 reg = <22000 1000>;
1448 #address-cells = <1>;
1449 #size-cells = <0>;
1450 interrupt-parent = <700>;
1451 interrupts = <27 1>;
1452 phy_type = "ulpi";
1453 port0;
1454 port1;
1455 };
1456
1457 Example dual role USB controller device node :
1458 usb@23000 {
1459 compatible = "fsl-usb2-dr";
1460 reg = <23000 1000>;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 interrupt-parent = <700>;
1464 interrupts = <26 1>;
1465 dr_mode = "otg";
1466 phy = "ulpi";
1467 };
1468
1469
1470 g) Freescale SOC SEC Security Engines
1471
1472 Required properties:
1473
1474 - device_type : Should be "crypto"
1475 - model : Model of the device. Should be "SEC1" or "SEC2"
1476 - compatible : Should be "talitos"
1477 - reg : Offset and length of the register set for the device
1478 - interrupts : <a b> where a is the interrupt number and b is a
1479 field that represents an encoding of the sense and level
1480 information for the interrupt. This should be encoded based on
1481 the information in section 2) depending on the type of interrupt
1482 controller you have.
1483 - interrupt-parent : the phandle for the interrupt controller that
1484 services interrupts for this device.
1485 - num-channels : An integer representing the number of channels
1486 available.
1487 - channel-fifo-len : An integer representing the number of
1488 descriptor pointers each channel fetch fifo can hold.
1489 - exec-units-mask : The bitmask representing what execution units
1490 (EUs) are available. It's a single 32-bit cell. EU information
1491 should be encoded following the SEC's Descriptor Header Dword
1492 EU_SEL0 field documentation, i.e. as follows:
1493
1494 bit 0 = reserved - should be 0
1495 bit 1 = set if SEC has the ARC4 EU (AFEU)
1496 bit 2 = set if SEC has the DES/3DES EU (DEU)
1497 bit 3 = set if SEC has the message digest EU (MDEU)
1498 bit 4 = set if SEC has the random number generator EU (RNG)
1499 bit 5 = set if SEC has the public key EU (PKEU)
1500 bit 6 = set if SEC has the AES EU (AESU)
1501 bit 7 = set if SEC has the Kasumi EU (KEU)
1502
1503 bits 8 through 31 are reserved for future SEC EUs.
1504
1505 - descriptor-types-mask : The bitmask representing what descriptors
1506 are available. It's a single 32-bit cell. Descriptor type
1507 information should be encoded following the SEC's Descriptor
1508 Header Dword DESC_TYPE field documentation, i.e. as follows:
1509
1510 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
1511 bit 1 = set if SEC supports the ipsec_esp descriptor type
1512 bit 2 = set if SEC supports the common_nonsnoop desc. type
1513 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
1514 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
1515 bit 5 = set if SEC supports the srtp descriptor type
1516 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
1517 bit 7 = set if SEC supports the pkeu_assemble descriptor type
1518 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
1519 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
1520 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
1521 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
1522
1523 ..and so on and so forth.
1524
1525 Example:
1526
1527 /* MPC8548E */
1528 crypto@30000 {
1529 device_type = "crypto";
1530 model = "SEC2";
1531 compatible = "talitos";
1532 reg = <30000 10000>;
1533 interrupts = <1d 3>;
1534 interrupt-parent = <40000>;
1535 num-channels = <4>;
1536 channel-fifo-len = <18>;
1537 exec-units-mask = <000000fe>;
1538 descriptor-types-mask = <012b0ebf>;
1539 };
1540
1541 h) Board Control and Status (BCSR)
1542
1543 Required properties:
1544
1545 - device_type : Should be "board-control"
1546 - reg : Offset and length of the register set for the device
1547
1548 Example:
1549
1550 bcsr@f8000000 {
1551 device_type = "board-control";
1552 reg = <f8000000 8000>;
1553 };
1554
1555 i) Freescale QUICC Engine module (QE)
1556 This represents qe module that is installed on PowerQUICC II Pro.
1557
1558 NOTE: This is an interim binding; it should be updated to fit
1559 in with the CPM binding later in this document.
1560
1561 Basically, it is a bus of devices, that could act more or less
1562 as a complete entity (UCC, USB etc ). All of them should be siblings on
1563 the "root" qe node, using the common properties from there.
1564 The description below applies to the qe of MPC8360 and
1565 more nodes and properties would be extended in the future.
1566
1567 i) Root QE device
1568
1569 Required properties:
1570 - compatible : should be "fsl,qe";
1571 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
1572 - reg : offset and length of the device registers.
1573 - bus-frequency : the clock frequency for QUICC Engine.
1574
1575 Recommended properties
1576 - brg-frequency : the internal clock source frequency for baud-rate
1577 generators in Hz.
1578
1579 Example:
1580 qe@e0100000 {
1581 #address-cells = <1>;
1582 #size-cells = <1>;
1583 #interrupt-cells = <2>;
1584 compatible = "fsl,qe";
1585 ranges = <0 e0100000 00100000>;
1586 reg = <e0100000 480>;
1587 brg-frequency = <0>;
1588 bus-frequency = <179A7B00>;
1589 }
1590
1591
1592 ii) SPI (Serial Peripheral Interface)
1593
1594 Required properties:
1595 - cell-index : SPI controller index.
1596 - compatible : should be "fsl,spi".
1597 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
1598 - reg : Offset and length of the register set for the device
1599 - interrupts : <a b> where a is the interrupt number and b is a
1600 field that represents an encoding of the sense and level
1601 information for the interrupt. This should be encoded based on
1602 the information in section 2) depending on the type of interrupt
1603 controller you have.
1604 - interrupt-parent : the phandle for the interrupt controller that
1605 services interrupts for this device.
1606
1607 Example:
1608 spi@4c0 {
1609 cell-index = <0>;
1610 compatible = "fsl,spi";
1611 reg = <4c0 40>;
1612 interrupts = <82 0>;
1613 interrupt-parent = <700>;
1614 mode = "cpu";
1615 };
1616
1617
1618 iii) USB (Universal Serial Bus Controller)
1619
1620 Required properties:
1621 - compatible : could be "qe_udc" or "fhci-hcd".
1622 - mode : the could be "host" or "slave".
1623 - reg : Offset and length of the register set for the device
1624 - interrupts : <a b> where a is the interrupt number and b is a
1625 field that represents an encoding of the sense and level
1626 information for the interrupt. This should be encoded based on
1627 the information in section 2) depending on the type of interrupt
1628 controller you have.
1629 - interrupt-parent : the phandle for the interrupt controller that
1630 services interrupts for this device.
1631
1632 Example(slave):
1633 usb@6c0 {
1634 compatible = "qe_udc";
1635 reg = <6c0 40>;
1636 interrupts = <8b 0>;
1637 interrupt-parent = <700>;
1638 mode = "slave";
1639 }; 1284 };
1640 1285
1641 1286 c) CFI or JEDEC memory-mapped NOR flash
1642 iv) UCC (Unified Communications Controllers)
1643
1644 Required properties:
1645 - device_type : should be "network", "hldc", "uart", "transparent"
1646 "bisync", "atm", or "serial".
1647 - compatible : could be "ucc_geth" or "fsl_atm" and so on.
1648 - cell-index : the ucc number(1-8), corresponding to UCCx in UM.
1649 - reg : Offset and length of the register set for the device
1650 - interrupts : <a b> where a is the interrupt number and b is a
1651 field that represents an encoding of the sense and level
1652 information for the interrupt. This should be encoded based on
1653 the information in section 2) depending on the type of interrupt
1654 controller you have.
1655 - interrupt-parent : the phandle for the interrupt controller that
1656 services interrupts for this device.
1657 - pio-handle : The phandle for the Parallel I/O port configuration.
1658 - port-number : for UART drivers, the port number to use, between 0 and 3.
1659 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
1660 The port number is added to the minor number of the device. Unlike the
1661 CPM UART driver, the port-number is required for the QE UART driver.
1662 - soft-uart : for UART drivers, if specified this means the QE UART device
1663 driver should use "Soft-UART" mode, which is needed on some SOCs that have
1664 broken UART hardware. Soft-UART is provided via a microcode upload.
1665 - rx-clock-name: the UCC receive clock source
1666 "none": clock source is disabled
1667 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1668 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1669 - tx-clock-name: the UCC transmit clock source
1670 "none": clock source is disabled
1671 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
1672 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
1673 The following two properties are deprecated. rx-clock has been replaced
1674 with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
1675 Drivers that currently use the deprecated properties should continue to
1676 do so, in order to support older device trees, but they should be updated
1677 to check for the new properties first.
1678 - rx-clock : represents the UCC receive clock source.
1679 0x00 : clock source is disabled;
1680 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1681 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1682 - tx-clock: represents the UCC transmit clock source;
1683 0x00 : clock source is disabled;
1684 0x1~0x10 : clock source is BRG1~BRG16 respectively;
1685 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
1686
1687 Required properties for network device_type:
1688 - mac-address : list of bytes representing the ethernet address.
1689 - phy-handle : The phandle for the PHY connected to this controller.
1690
1691 Recommended properties:
1692 - phy-connection-type : a string naming the controller/PHY interface type,
1693 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
1694 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
1695 "tbi", or "rtbi".
1696
1697 Example:
1698 ucc@2000 {
1699 device_type = "network";
1700 compatible = "ucc_geth";
1701 cell-index = <1>;
1702 reg = <2000 200>;
1703 interrupts = <a0 0>;
1704 interrupt-parent = <700>;
1705 mac-address = [ 00 04 9f 00 23 23 ];
1706 rx-clock = "none";
1707 tx-clock = "clk9";
1708 phy-handle = <212000>;
1709 phy-connection-type = "gmii";
1710 pio-handle = <140001>;
1711 };
1712
1713
1714 v) Parallel I/O Ports
1715
1716 This node configures Parallel I/O ports for CPUs with QE support.
1717 The node should reside in the "soc" node of the tree. For each
1718 device that using parallel I/O ports, a child node should be created.
1719 See the definition of the Pin configuration nodes below for more
1720 information.
1721
1722 Required properties:
1723 - device_type : should be "par_io".
1724 - reg : offset to the register set and its length.
1725 - num-ports : number of Parallel I/O ports
1726
1727 Example:
1728 par_io@1400 {
1729 reg = <1400 100>;
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1732 device_type = "par_io";
1733 num-ports = <7>;
1734 ucc_pin@01 {
1735 ......
1736 };
1737
1738
1739 vi) Pin configuration nodes
1740
1741 Required properties:
1742 - linux,phandle : phandle of this node; likely referenced by a QE
1743 device.
1744 - pio-map : array of pin configurations. Each pin is defined by 6
1745 integers. The six numbers are respectively: port, pin, dir,
1746 open_drain, assignment, has_irq.
1747 - port : port number of the pin; 0-6 represent port A-G in UM.
1748 - pin : pin number in the port.
1749 - dir : direction of the pin, should encode as follows:
1750
1751 0 = The pin is disabled
1752 1 = The pin is an output
1753 2 = The pin is an input
1754 3 = The pin is I/O
1755
1756 - open_drain : indicates the pin is normal or wired-OR:
1757
1758 0 = The pin is actively driven as an output
1759 1 = The pin is an open-drain driver. As an output, the pin is
1760 driven active-low, otherwise it is three-stated.
1761
1762 - assignment : function number of the pin according to the Pin Assignment
1763 tables in User Manual. Each pin can have up to 4 possible functions in
1764 QE and two options for CPM.
1765 - has_irq : indicates if the pin is used as source of external
1766 interrupts.
1767
1768 Example:
1769 ucc_pin@01 {
1770 linux,phandle = <140001>;
1771 pio-map = <
1772 /* port pin dir open_drain assignment has_irq */
1773 0 3 1 0 1 0 /* TxD0 */
1774 0 4 1 0 1 0 /* TxD1 */
1775 0 5 1 0 1 0 /* TxD2 */
1776 0 6 1 0 1 0 /* TxD3 */
1777 1 6 1 0 3 0 /* TxD4 */
1778 1 7 1 0 1 0 /* TxD5 */
1779 1 9 1 0 2 0 /* TxD6 */
1780 1 a 1 0 2 0 /* TxD7 */
1781 0 9 2 0 1 0 /* RxD0 */
1782 0 a 2 0 1 0 /* RxD1 */
1783 0 b 2 0 1 0 /* RxD2 */
1784 0 c 2 0 1 0 /* RxD3 */
1785 0 d 2 0 1 0 /* RxD4 */
1786 1 1 2 0 2 0 /* RxD5 */
1787 1 0 2 0 2 0 /* RxD6 */
1788 1 4 2 0 2 0 /* RxD7 */
1789 0 7 1 0 1 0 /* TX_EN */
1790 0 8 1 0 1 0 /* TX_ER */
1791 0 f 2 0 1 0 /* RX_DV */
1792 0 10 2 0 1 0 /* RX_ER */
1793 0 0 2 0 1 0 /* RX_CLK */
1794 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
1795 2 8 2 0 1 0>; /* GTX125 - CLK9 */
1796 };
1797
1798 vii) Multi-User RAM (MURAM)
1799
1800 Required properties:
1801 - compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
1802 - mode : the could be "host" or "slave".
1803 - ranges : Should be defined as specified in 1) to describe the
1804 translation of MURAM addresses.
1805 - data-only : sub-node which defines the address area under MURAM
1806 bus that can be allocated as data/parameter
1807
1808 Example:
1809
1810 muram@10000 {
1811 compatible = "fsl,qe-muram", "fsl,cpm-muram";
1812 ranges = <0 00010000 0000c000>;
1813
1814 data-only@0{
1815 compatible = "fsl,qe-muram-data",
1816 "fsl,cpm-muram-data";
1817 reg = <0 c000>;
1818 };
1819 };
1820
1821 viii) Uploaded QE firmware
1822
1823 If a new firwmare has been uploaded to the QE (usually by the
1824 boot loader), then a 'firmware' child node should be added to the QE
1825 node. This node provides information on the uploaded firmware that
1826 device drivers may need.
1827
1828 Required properties:
1829 - id: The string name of the firmware. This is taken from the 'id'
1830 member of the qe_firmware structure of the uploaded firmware.
1831 Device drivers can search this string to determine if the
1832 firmware they want is already present.
1833 - extended-modes: The Extended Modes bitfield, taken from the
1834 firmware binary. It is a 64-bit number represented
1835 as an array of two 32-bit numbers.
1836 - virtual-traps: The virtual traps, taken from the firmware binary.
1837 It is an array of 8 32-bit numbers.
1838
1839 Example:
1840
1841 firmware {
1842 id = "Soft-UART";
1843 extended-modes = <0 0>;
1844 virtual-traps = <0 0 0 0 0 0 0 0>;
1845 }
1846
1847 j) CFI or JEDEC memory-mapped NOR flash
1848 1287
1849 Flash chips (Memory Technology Devices) are often used for solid state 1288 Flash chips (Memory Technology Devices) are often used for solid state
1850 file systems on embedded devices. 1289 file systems on embedded devices.
@@ -1908,268 +1347,7 @@ platforms are moved over to use the flattened-device-tree model.
1908 }; 1347 };
1909 }; 1348 };
1910 1349
1911 k) Global Utilities Block 1350 d) 4xx/Axon EMAC ethernet nodes
1912
1913 The global utilities block controls power management, I/O device
1914 enabling, power-on-reset configuration monitoring, general-purpose
1915 I/O signal configuration, alternate function selection for multiplexed
1916 signals, and clock control.
1917
1918 Required properties:
1919
1920 - compatible : Should define the compatible device type for
1921 global-utilities.
1922 - reg : Offset and length of the register set for the device.
1923
1924 Recommended properties:
1925
1926 - fsl,has-rstcr : Indicates that the global utilities register set
1927 contains a functioning "reset control register" (i.e. the board
1928 is wired to reset upon setting the HRESET_REQ bit in this register).
1929
1930 Example:
1931
1932 global-utilities@e0000 { /* global utilities block */
1933 compatible = "fsl,mpc8548-guts";
1934 reg = <e0000 1000>;
1935 fsl,has-rstcr;
1936 };
1937
1938 l) Freescale Communications Processor Module
1939
1940 NOTE: This is an interim binding, and will likely change slightly,
1941 as more devices are supported. The QE bindings especially are
1942 incomplete.
1943
1944 i) Root CPM node
1945
1946 Properties:
1947 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
1948 - reg : A 48-byte region beginning with CPCR.
1949
1950 Example:
1951 cpm@119c0 {
1952 #address-cells = <1>;
1953 #size-cells = <1>;
1954 #interrupt-cells = <2>;
1955 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
1956 reg = <119c0 30>;
1957 }
1958
1959 ii) Properties common to mulitple CPM/QE devices
1960
1961 - fsl,cpm-command : This value is ORed with the opcode and command flag
1962 to specify the device on which a CPM command operates.
1963
1964 - fsl,cpm-brg : Indicates which baud rate generator the device
1965 is associated with. If absent, an unused BRG
1966 should be dynamically allocated. If zero, the
1967 device uses an external clock rather than a BRG.
1968
1969 - reg : Unless otherwise specified, the first resource represents the
1970 scc/fcc/ucc registers, and the second represents the device's
1971 parameter RAM region (if it has one).
1972
1973 iii) Serial
1974
1975 Currently defined compatibles:
1976 - fsl,cpm1-smc-uart
1977 - fsl,cpm2-smc-uart
1978 - fsl,cpm1-scc-uart
1979 - fsl,cpm2-scc-uart
1980 - fsl,qe-uart
1981
1982 Example:
1983
1984 serial@11a00 {
1985 device_type = "serial";
1986 compatible = "fsl,mpc8272-scc-uart",
1987 "fsl,cpm2-scc-uart";
1988 reg = <11a00 20 8000 100>;
1989 interrupts = <28 8>;
1990 interrupt-parent = <&PIC>;
1991 fsl,cpm-brg = <1>;
1992 fsl,cpm-command = <00800000>;
1993 };
1994
1995 iii) Network
1996
1997 Currently defined compatibles:
1998 - fsl,cpm1-scc-enet
1999 - fsl,cpm2-scc-enet
2000 - fsl,cpm1-fec-enet
2001 - fsl,cpm2-fcc-enet (third resource is GFEMR)
2002 - fsl,qe-enet
2003
2004 Example:
2005
2006 ethernet@11300 {
2007 device_type = "network";
2008 compatible = "fsl,mpc8272-fcc-enet",
2009 "fsl,cpm2-fcc-enet";
2010 reg = <11300 20 8400 100 11390 1>;
2011 local-mac-address = [ 00 00 00 00 00 00 ];
2012 interrupts = <20 8>;
2013 interrupt-parent = <&PIC>;
2014 phy-handle = <&PHY0>;
2015 fsl,cpm-command = <12000300>;
2016 };
2017
2018 iv) MDIO
2019
2020 Currently defined compatibles:
2021 fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
2022 fsl,cpm2-mdio-bitbang (reg is port C registers)
2023
2024 Properties for fsl,cpm2-mdio-bitbang:
2025 fsl,mdio-pin : pin of port C controlling mdio data
2026 fsl,mdc-pin : pin of port C controlling mdio clock
2027
2028 Example:
2029
2030 mdio@10d40 {
2031 device_type = "mdio";
2032 compatible = "fsl,mpc8272ads-mdio-bitbang",
2033 "fsl,mpc8272-mdio-bitbang",
2034 "fsl,cpm2-mdio-bitbang";
2035 reg = <10d40 14>;
2036 #address-cells = <1>;
2037 #size-cells = <0>;
2038 fsl,mdio-pin = <12>;
2039 fsl,mdc-pin = <13>;
2040 };
2041
2042 v) Baud Rate Generators
2043
2044 Currently defined compatibles:
2045 fsl,cpm-brg
2046 fsl,cpm1-brg
2047 fsl,cpm2-brg
2048
2049 Properties:
2050 - reg : There may be an arbitrary number of reg resources; BRG
2051 numbers are assigned to these in order.
2052 - clock-frequency : Specifies the base frequency driving
2053 the BRG.
2054
2055 Example:
2056
2057 brg@119f0 {
2058 compatible = "fsl,mpc8272-brg",
2059 "fsl,cpm2-brg",
2060 "fsl,cpm-brg";
2061 reg = <119f0 10 115f0 10>;
2062 clock-frequency = <d#25000000>;
2063 };
2064
2065 vi) Interrupt Controllers
2066
2067 Currently defined compatibles:
2068 - fsl,cpm1-pic
2069 - only one interrupt cell
2070 - fsl,pq1-pic
2071 - fsl,cpm2-pic
2072 - second interrupt cell is level/sense:
2073 - 2 is falling edge
2074 - 8 is active low
2075
2076 Example:
2077
2078 interrupt-controller@10c00 {
2079 #interrupt-cells = <2>;
2080 interrupt-controller;
2081 reg = <10c00 80>;
2082 compatible = "mpc8272-pic", "fsl,cpm2-pic";
2083 };
2084
2085 vii) USB (Universal Serial Bus Controller)
2086
2087 Properties:
2088 - compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
2089
2090 Example:
2091 usb@11bc0 {
2092 #address-cells = <1>;
2093 #size-cells = <0>;
2094 compatible = "fsl,cpm2-usb";
2095 reg = <11b60 18 8b00 100>;
2096 interrupts = <b 8>;
2097 interrupt-parent = <&PIC>;
2098 fsl,cpm-command = <2e600000>;
2099 };
2100
2101 viii) Multi-User RAM (MURAM)
2102
2103 The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
2104
2105 Ranges must be set up subject to the following restrictions:
2106
2107 - Children's reg nodes must be offsets from the start of all muram, even
2108 if the user-data area does not begin at zero.
2109 - If multiple range entries are used, the difference between the parent
2110 address and the child address must be the same in all, so that a single
2111 mapping can cover them all while maintaining the ability to determine
2112 CPM-side offsets with pointer subtraction. It is recommended that
2113 multiple range entries not be used.
2114 - A child address of zero must be translatable, even if no reg resources
2115 contain it.
2116
2117 A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
2118 indicate the portion of muram that is usable by the OS for arbitrary
2119 purposes. The data node may have an arbitrary number of reg resources,
2120 all of which contribute to the allocatable muram pool.
2121
2122 Example, based on mpc8272:
2123
2124 muram@0 {
2125 #address-cells = <1>;
2126 #size-cells = <1>;
2127 ranges = <0 0 10000>;
2128
2129 data@0 {
2130 compatible = "fsl,cpm-muram-data";
2131 reg = <0 2000 9800 800>;
2132 };
2133 };
2134
2135 m) Chipselect/Local Bus
2136
2137 Properties:
2138 - name : Should be localbus
2139 - #address-cells : Should be either two or three. The first cell is the
2140 chipselect number, and the remaining cells are the
2141 offset into the chipselect.
2142 - #size-cells : Either one or two, depending on how large each chipselect
2143 can be.
2144 - ranges : Each range corresponds to a single chipselect, and cover
2145 the entire access window as configured.
2146
2147 Example:
2148 localbus@f0010100 {
2149 compatible = "fsl,mpc8272-localbus",
2150 "fsl,pq2-localbus";
2151 #address-cells = <2>;
2152 #size-cells = <1>;
2153 reg = <f0010100 40>;
2154
2155 ranges = <0 0 fe000000 02000000
2156 1 0 f4500000 00008000>;
2157
2158 flash@0,0 {
2159 compatible = "jedec-flash";
2160 reg = <0 0 2000000>;
2161 bank-width = <4>;
2162 device-width = <1>;
2163 };
2164
2165 board-control@1,0 {
2166 reg = <1 0 20>;
2167 compatible = "fsl,mpc8272ads-bcsr";
2168 };
2169 };
2170
2171
2172 n) 4xx/Axon EMAC ethernet nodes
2173 1351
2174 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also 1352 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
2175 the Axon bridge. To operate this needs to interact with a ths 1353 the Axon bridge. To operate this needs to interact with a ths
@@ -2317,7 +1495,7 @@ platforms are moved over to use the flattened-device-tree model.
2317 available. 1495 available.
2318 For Axon: 0x0000012a 1496 For Axon: 0x0000012a
2319 1497
2320 o) Xilinx IP cores 1498 e) Xilinx IP cores
2321 1499
2322 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use 1500 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
2323 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range 1501 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
@@ -2611,206 +1789,7 @@ platforms are moved over to use the flattened-device-tree model.
2611 - reg-offset : A value of 3 is required 1789 - reg-offset : A value of 3 is required
2612 - reg-shift : A value of 2 is required 1790 - reg-shift : A value of 2 is required
2613 1791
2614 1792 f) USB EHCI controllers
2615 p) Freescale Synchronous Serial Interface
2616
2617 The SSI is a serial device that communicates with audio codecs. It can
2618 be programmed in AC97, I2S, left-justified, or right-justified modes.
2619
2620 Required properties:
2621 - compatible : compatible list, containing "fsl,ssi"
2622 - cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
2623 - reg : offset and length of the register set for the device
2624 - interrupts : <a b> where a is the interrupt number and b is a
2625 field that represents an encoding of the sense and
2626 level information for the interrupt. This should be
2627 encoded based on the information in section 2)
2628 depending on the type of interrupt controller you
2629 have.
2630 - interrupt-parent : the phandle for the interrupt controller that
2631 services interrupts for this device.
2632 - fsl,mode : the operating mode for the SSI interface
2633 "i2s-slave" - I2S mode, SSI is clock slave
2634 "i2s-master" - I2S mode, SSI is clock master
2635 "lj-slave" - left-justified mode, SSI is clock slave
2636 "lj-master" - l.j. mode, SSI is clock master
2637 "rj-slave" - right-justified mode, SSI is clock slave
2638 "rj-master" - r.j., SSI is clock master
2639 "ac97-slave" - AC97 mode, SSI is clock slave
2640 "ac97-master" - AC97 mode, SSI is clock master
2641
2642 Optional properties:
2643 - codec-handle : phandle to a 'codec' node that defines an audio
2644 codec connected to this SSI. This node is typically
2645 a child of an I2C or other control node.
2646
2647 Child 'codec' node required properties:
2648 - compatible : compatible list, contains the name of the codec
2649
2650 Child 'codec' node optional properties:
2651 - clock-frequency : The frequency of the input clock, which typically
2652 comes from an on-board dedicated oscillator.
2653
2654 * Freescale 83xx DMA Controller
2655
2656 Freescale PowerPC 83xx have on chip general purpose DMA controllers.
2657
2658 Required properties:
2659
2660 - compatible : compatible list, contains 2 entries, first is
2661 "fsl,CHIP-dma", where CHIP is the processor
2662 (mpc8349, mpc8360, etc.) and the second is
2663 "fsl,elo-dma"
2664 - reg : <registers mapping for DMA general status reg>
2665 - ranges : Should be defined as specified in 1) to describe the
2666 DMA controller channels.
2667 - cell-index : controller index. 0 for controller @ 0x8100
2668 - interrupts : <interrupt mapping for DMA IRQ>
2669 - interrupt-parent : optional, if needed for interrupt mapping
2670
2671
2672 - DMA channel nodes:
2673 - compatible : compatible list, contains 2 entries, first is
2674 "fsl,CHIP-dma-channel", where CHIP is the processor
2675 (mpc8349, mpc8350, etc.) and the second is
2676 "fsl,elo-dma-channel"
2677 - reg : <registers mapping for channel>
2678 - cell-index : dma channel index starts at 0.
2679
2680 Optional properties:
2681 - interrupts : <interrupt mapping for DMA channel IRQ>
2682 (on 83xx this is expected to be identical to
2683 the interrupts property of the parent node)
2684 - interrupt-parent : optional, if needed for interrupt mapping
2685
2686 Example:
2687 dma@82a8 {
2688 #address-cells = <1>;
2689 #size-cells = <1>;
2690 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
2691 reg = <82a8 4>;
2692 ranges = <0 8100 1a4>;
2693 interrupt-parent = <&ipic>;
2694 interrupts = <47 8>;
2695 cell-index = <0>;
2696 dma-channel@0 {
2697 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2698 cell-index = <0>;
2699 reg = <0 80>;
2700 };
2701 dma-channel@80 {
2702 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2703 cell-index = <1>;
2704 reg = <80 80>;
2705 };
2706 dma-channel@100 {
2707 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2708 cell-index = <2>;
2709 reg = <100 80>;
2710 };
2711 dma-channel@180 {
2712 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
2713 cell-index = <3>;
2714 reg = <180 80>;
2715 };
2716 };
2717
2718 * Freescale 85xx/86xx DMA Controller
2719
2720 Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
2721
2722 Required properties:
2723
2724 - compatible : compatible list, contains 2 entries, first is
2725 "fsl,CHIP-dma", where CHIP is the processor
2726 (mpc8540, mpc8540, etc.) and the second is
2727 "fsl,eloplus-dma"
2728 - reg : <registers mapping for DMA general status reg>
2729 - cell-index : controller index. 0 for controller @ 0x21000,
2730 1 for controller @ 0xc000
2731 - ranges : Should be defined as specified in 1) to describe the
2732 DMA controller channels.
2733
2734 - DMA channel nodes:
2735 - compatible : compatible list, contains 2 entries, first is
2736 "fsl,CHIP-dma-channel", where CHIP is the processor
2737 (mpc8540, mpc8560, etc.) and the second is
2738 "fsl,eloplus-dma-channel"
2739 - cell-index : dma channel index starts at 0.
2740 - reg : <registers mapping for channel>
2741 - interrupts : <interrupt mapping for DMA channel IRQ>
2742 - interrupt-parent : optional, if needed for interrupt mapping
2743
2744 Example:
2745 dma@21300 {
2746 #address-cells = <1>;
2747 #size-cells = <1>;
2748 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
2749 reg = <21300 4>;
2750 ranges = <0 21100 200>;
2751 cell-index = <0>;
2752 dma-channel@0 {
2753 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2754 reg = <0 80>;
2755 cell-index = <0>;
2756 interrupt-parent = <&mpic>;
2757 interrupts = <14 2>;
2758 };
2759 dma-channel@80 {
2760 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2761 reg = <80 80>;
2762 cell-index = <1>;
2763 interrupt-parent = <&mpic>;
2764 interrupts = <15 2>;
2765 };
2766 dma-channel@100 {
2767 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2768 reg = <100 80>;
2769 cell-index = <2>;
2770 interrupt-parent = <&mpic>;
2771 interrupts = <16 2>;
2772 };
2773 dma-channel@180 {
2774 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
2775 reg = <180 80>;
2776 cell-index = <3>;
2777 interrupt-parent = <&mpic>;
2778 interrupts = <17 2>;
2779 };
2780 };
2781
2782 * Freescale 8xxx/3.0 Gb/s SATA nodes
2783
2784 SATA nodes are defined to describe on-chip Serial ATA controllers.
2785 Each SATA port should have its own node.
2786
2787 Required properties:
2788 - compatible : compatible list, contains 2 entries, first is
2789 "fsl,CHIP-sata", where CHIP is the processor
2790 (mpc8315, mpc8379, etc.) and the second is
2791 "fsl,pq-sata"
2792 - interrupts : <interrupt mapping for SATA IRQ>
2793 - cell-index : controller index.
2794 1 for controller @ 0x18000
2795 2 for controller @ 0x19000
2796 3 for controller @ 0x1a000
2797 4 for controller @ 0x1b000
2798
2799 Optional properties:
2800 - interrupt-parent : optional, if needed for interrupt mapping
2801 - reg : <registers mapping>
2802
2803 Example:
2804
2805 sata@18000 {
2806 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
2807 reg = <0x18000 0x1000>;
2808 cell-index = <1>;
2809 interrupts = <2c 8>;
2810 interrupt-parent = < &ipic >;
2811 };
2812
2813 q) USB EHCI controllers
2814 1793
2815 Required properties: 1794 Required properties:
2816 - compatible : should be "usb-ehci". 1795 - compatible : should be "usb-ehci".
@@ -2836,40 +1815,6 @@ platforms are moved over to use the flattened-device-tree model.
2836 big-endian; 1815 big-endian;
2837 }; 1816 };
2838 1817
2839 r) Freescale Display Interface Unit
2840
2841 The Freescale DIU is a LCD controller, with proper hardware, it can also
2842 drive DVI monitors.
2843
2844 Required properties:
2845 - compatible : should be "fsl-diu".
2846 - reg : should contain at least address and length of the DIU register
2847 set.
2848 - Interrupts : one DIU interrupt should be describe here.
2849
2850 Example (MPC8610HPCD)
2851 display@2c000 {
2852 compatible = "fsl,diu";
2853 reg = <0x2c000 100>;
2854 interrupts = <72 2>;
2855 interrupt-parent = <&mpic>;
2856 };
2857
2858 s) Freescale on board FPGA
2859
2860 This is the memory-mapped registers for on board FPGA.
2861
2862 Required properities:
2863 - compatible : should be "fsl,fpga-pixis".
2864 - reg : should contain the address and the lenght of the FPPGA register
2865 set.
2866
2867 Example (MPC8610HPCD)
2868 board-control@e8000000 {
2869 compatible = "fsl,fpga-pixis";
2870 reg = <0xe8000000 32>;
2871 };
2872
2873VII - Marvell Discovery mv64[345]6x System Controller chips 1818VII - Marvell Discovery mv64[345]6x System Controller chips
2874=========================================================== 1819===========================================================
2875 1820
@@ -3622,14 +2567,11 @@ not necessary as they are usually the same as the root node.
3622 2567
3623 pic@40000 { 2568 pic@40000 {
3624 linux,phandle = <40000>; 2569 linux,phandle = <40000>;
3625 clock-frequency = <0>;
3626 interrupt-controller; 2570 interrupt-controller;
3627 #address-cells = <0>; 2571 #address-cells = <0>;
3628 reg = <40000 40000>; 2572 reg = <40000 40000>;
3629 built-in;
3630 compatible = "chrp,open-pic"; 2573 compatible = "chrp,open-pic";
3631 device_type = "open-pic"; 2574 device_type = "open-pic";
3632 big-endian;
3633 }; 2575 };
3634 2576
3635 i2c@3000 { 2577 i2c@3000 {
diff --git a/Documentation/powerpc/bootwrapper.txt b/Documentation/powerpc/bootwrapper.txt
new file mode 100644
index 000000000000..d60fced5e1cc
--- /dev/null
+++ b/Documentation/powerpc/bootwrapper.txt
@@ -0,0 +1,141 @@
1The PowerPC boot wrapper
2------------------------
3Copyright (C) Secret Lab Technologies Ltd.
4
5PowerPC image targets compresses and wraps the kernel image (vmlinux) with
6a boot wrapper to make it usable by the system firmware. There is no
7standard PowerPC firmware interface, so the boot wrapper is designed to
8be adaptable for each kind of image that needs to be built.
9
10The boot wrapper can be found in the arch/powerpc/boot/ directory. The
11Makefile in that directory has targets for all the available image types.
12The different image types are used to support all of the various firmware
13interfaces found on PowerPC platforms. OpenFirmware is the most commonly
14used firmware type on general purpose PowerPC systems from Apple, IBM and
15others. U-Boot is typically found on embedded PowerPC hardware, but there
16are a handful of other firmware implementations which are also popular. Each
17firmware interface requires a different image format.
18
19The boot wrapper is built from the makefile in arch/powerpc/boot/Makefile and
20it uses the wrapper script (arch/powerpc/boot/wrapper) to generate target
21image. The details of the build system is discussed in the next section.
22Currently, the following image format targets exist:
23
24 cuImage.%: Backwards compatible uImage for older version of
25 U-Boot (for versions that don't understand the device
26 tree). This image embeds a device tree blob inside
27 the image. The boot wrapper, kernel and device tree
28 are all embedded inside the U-Boot uImage file format
29 with boot wrapper code that extracts data from the old
30 bd_info structure and loads the data into the device
31 tree before jumping into the kernel.
32 Because of the series of #ifdefs found in the
33 bd_info structure used in the old U-Boot interfaces,
34 cuImages are platform specific. Each specific
35 U-Boot platform has a different platform init file
36 which populates the embedded device tree with data
37 from the platform specific bd_info file. The platform
38 specific cuImage platform init code can be found in
39 arch/powerpc/boot/cuboot.*.c. Selection of the correct
40 cuImage init code for a specific board can be found in
41 the wrapper structure.
42 dtbImage.%: Similar to zImage, except device tree blob is embedded
43 inside the image instead of provided by firmware. The
44 output image file can be either an elf file or a flat
45 binary depending on the platform.
46 dtbImages are used on systems which do not have an
47 interface for passing a device tree directly.
48 dtbImages are similar to simpleImages except that
49 dtbImages have platform specific code for extracting
50 data from the board firmware, but simpleImages do not
51 talk to the firmware at all.
52 PlayStation 3 support uses dtbImage. So do Embedded
53 Planet boards using the PlanetCore firmware. Board
54 specific initialization code is typically found in a
55 file named arch/powerpc/boot/<platform>.c; but this
56 can be overridden by the wrapper script.
57 simpleImage.%: Firmware independent compressed image that does not
58 depend on any particular firmware interface and embeds
59 a device tree blob. This image is a flat binary that
60 can be loaded to any location in RAM and jumped to.
61 Firmware cannot pass any configuration data to the
62 kernel with this image type and it depends entirely on
63 the embedded device tree for all information.
64 The simpleImage is useful for booting systems with
65 an unknown firmware interface or for booting from
66 a debugger when no firmware is present (such as on
67 the Xilinx Virtex platform). The only assumption that
68 simpleImage makes is that RAM is correctly initialized
69 and that the MMU is either off or has RAM mapped to
70 base address 0.
71 simpleImage also supports inserting special platform
72 specific initialization code to the start of the bootup
73 sequence. The virtex405 platform uses this feature to
74 ensure that the cache is invalidated before caching
75 is enabled. Platform specific initialization code is
76 added as part of the wrapper script and is keyed on
77 the image target name. For example, all
78 simpleImage.virtex405-* targets will add the
79 virtex405-head.S initialization code (This also means
80 that the dts file for virtex405 targets should be
81 named (virtex405-<board>.dts). Search the wrapper
82 script for 'virtex405' and see the file
83 arch/powerpc/boot/virtex405-head.S for details.
84 treeImage.%; Image format for used with OpenBIOS firmware found
85 on some ppc4xx hardware. This image embeds a device
86 tree blob inside the image.
87 uImage: Native image format used by U-Boot. The uImage target
88 does not add any boot code. It just wraps a compressed
89 vmlinux in the uImage data structure. This image
90 requires a version of U-Boot that is able to pass
91 a device tree to the kernel at boot. If using an older
92 version of U-Boot, then you need to use a cuImage
93 instead.
94 zImage.%: Image format which does not embed a device tree.
95 Used by OpenFirmware and other firmware interfaces
96 which are able to supply a device tree. This image
97 expects firmware to provide the device tree at boot.
98 Typically, if you have general purpose PowerPC
99 hardware then you want this image format.
100
101Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
102and cuImage) all generate the device tree blob from a file in the
103arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
104tree source based on the name of the target. Therefore, if the kernel is
105built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
106build system will use arch/powerpc/boot/dts/walnut.dts to build
107treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
108the simpleImage.virtex405-ml403.
109
110Two special targets called 'zImage' and 'zImage.initrd' also exist. These
111targets build all the default images as selected by the kernel configuration.
112Default images are selected by the boot wrapper Makefile
113(arch/powerpc/boot/Makefile) by adding targets to the $image-y variable. Look
114at the Makefile to see which default image targets are available.
115
116How it is built
117---------------
118arch/powerpc is designed to support multiplatform kernels, which means
119that a single vmlinux image can be booted on many different target boards.
120It also means that the boot wrapper must be able to wrap for many kinds of
121images on a single build. The design decision was made to not use any
122conditional compilation code (#ifdef, etc) in the boot wrapper source code.
123All of the boot wrapper pieces are buildable at any time regardless of the
124kernel configuration. Building all the wrapper bits on every kernel build
125also ensures that obscure parts of the wrapper are at the very least compile
126tested in a large variety of environments.
127
128The wrapper is adapted for different image types at link time by linking in
129just the wrapper bits that are appropriate for the image type. The 'wrapper
130script' (found in arch/powerpc/boot/wrapper) is called by the Makefile and
131is responsible for selecting the correct wrapper bits for the image type.
132The arguments are well documented in the script's comment block, so they
133are not repeated here. However, it is worth mentioning that the script
134uses the -p (platform) argument as the main method of deciding which wrapper
135bits to compile in. Look for the large 'case "$platform" in' block in the
136middle of the script. This is also the place where platform specific fixups
137can be selected by changing the link order.
138
139In particular, care should be taken when working with cuImages. cuImage
140wrapper bits are very board specific and care should be taken to make sure
141the target you are trying to build is supported by the wrapper bits.
diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
new file mode 100644
index 000000000000..74ae6f1cd2d6
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -0,0 +1,29 @@
1* Board Control and Status (BCSR)
2
3Required properties:
4
5 - device_type : Should be "board-control"
6 - reg : Offset and length of the register set for the device
7
8Example:
9
10 bcsr@f8000000 {
11 device_type = "board-control";
12 reg = <f8000000 8000>;
13 };
14
15* Freescale on board FPGA
16
17This is the memory-mapped registers for on board FPGA.
18
19Required properities:
20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the lenght of the FPPGA register
22 set.
23
24Example (MPC8610HPCD):
25
26 board-control@e8000000 {
27 compatible = "fsl,fpga-pixis";
28 reg = <0xe8000000 32>;
29 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
new file mode 100644
index 000000000000..088fc471e03a
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm.txt
@@ -0,0 +1,67 @@
1* Freescale Communications Processor Module
2
3NOTE: This is an interim binding, and will likely change slightly,
4as more devices are supported. The QE bindings especially are
5incomplete.
6
7* Root CPM node
8
9Properties:
10- compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11- reg : A 48-byte region beginning with CPCR.
12
13Example:
14 cpm@119c0 {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
19 reg = <119c0 30>;
20 }
21
22* Properties common to mulitple CPM/QE devices
23
24- fsl,cpm-command : This value is ORed with the opcode and command flag
25 to specify the device on which a CPM command operates.
26
27- fsl,cpm-brg : Indicates which baud rate generator the device
28 is associated with. If absent, an unused BRG
29 should be dynamically allocated. If zero, the
30 device uses an external clock rather than a BRG.
31
32- reg : Unless otherwise specified, the first resource represents the
33 scc/fcc/ucc registers, and the second represents the device's
34 parameter RAM region (if it has one).
35
36* Multi-User RAM (MURAM)
37
38The multi-user/dual-ported RAM is expressed as a bus under the CPM node.
39
40Ranges must be set up subject to the following restrictions:
41
42- Children's reg nodes must be offsets from the start of all muram, even
43 if the user-data area does not begin at zero.
44- If multiple range entries are used, the difference between the parent
45 address and the child address must be the same in all, so that a single
46 mapping can cover them all while maintaining the ability to determine
47 CPM-side offsets with pointer subtraction. It is recommended that
48 multiple range entries not be used.
49- A child address of zero must be translatable, even if no reg resources
50 contain it.
51
52A child "data" node must exist, compatible with "fsl,cpm-muram-data", to
53indicate the portion of muram that is usable by the OS for arbitrary
54purposes. The data node may have an arbitrary number of reg resources,
55all of which contribute to the allocatable muram pool.
56
57Example, based on mpc8272:
58 muram@0 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges = <0 0 10000>;
62
63 data@0 {
64 compatible = "fsl,cpm-muram-data";
65 reg = <0 2000 9800 800>;
66 };
67 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
new file mode 100644
index 000000000000..4c7d45eaf025
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/brg.txt
@@ -0,0 +1,21 @@
1* Baud Rate Generators
2
3Currently defined compatibles:
4fsl,cpm-brg
5fsl,cpm1-brg
6fsl,cpm2-brg
7
8Properties:
9- reg : There may be an arbitrary number of reg resources; BRG
10 numbers are assigned to these in order.
11- clock-frequency : Specifies the base frequency driving
12 the BRG.
13
14Example:
15 brg@119f0 {
16 compatible = "fsl,mpc8272-brg",
17 "fsl,cpm2-brg",
18 "fsl,cpm-brg";
19 reg = <119f0 10 115f0 10>;
20 clock-frequency = <d#25000000>;
21 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
new file mode 100644
index 000000000000..87bc6048667e
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/i2c.txt
@@ -0,0 +1,41 @@
1* I2C
2
3The I2C controller is expressed as a bus under the CPM node.
4
5Properties:
6- compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7- reg : On CPM2 devices, the second resource doesn't specify the I2C
8 Parameter RAM itself, but the I2C_BASE field of the CPM2 Parameter RAM
9 (typically 0x8afc 0x2).
10- #address-cells : Should be one. The cell is the i2c device address with
11 the r/w bit set to zero.
12- #size-cells : Should be zero.
13- clock-frequency : Can be used to set the i2c clock frequency. If
14 unspecified, a default frequency of 60kHz is being used.
15The following two properties are deprecated. They are only used by legacy
16i2c drivers to find the bus to probe:
17- linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
19- linux,i2c-class : Can be used to override the i2c class. The class is used
20 by legacy i2c device drivers to find a bus in a specific context like
21 system management, video or sound. By default, I2C_CLASS_HWMON (1) is
22 being used. The definition of the classes can be found in
23 include/i2c/i2c.h
24
25Example, based on mpc823:
26
27 i2c@860 {
28 compatible = "fsl,mpc823-i2c",
29 "fsl,cpm1-i2c";
30 reg = <0x860 0x20 0x3c80 0x30>;
31 interrupts = <16>;
32 interrupt-parent = <&CPM_PIC>;
33 fsl,cpm-command = <0x10>;
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 rtc@68 {
38 compatible = "dallas,ds1307";
39 reg = <0x68>;
40 };
41 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
new file mode 100644
index 000000000000..8e3ee1681618
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/pic.txt
@@ -0,0 +1,18 @@
1* Interrupt Controllers
2
3Currently defined compatibles:
4- fsl,cpm1-pic
5 - only one interrupt cell
6- fsl,pq1-pic
7- fsl,cpm2-pic
8 - second interrupt cell is level/sense:
9 - 2 is falling edge
10 - 8 is active low
11
12Example:
13 interrupt-controller@10c00 {
14 #interrupt-cells = <2>;
15 interrupt-controller;
16 reg = <10c00 80>;
17 compatible = "mpc8272-pic", "fsl,cpm2-pic";
18 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
new file mode 100644
index 000000000000..74bfda4bb824
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/cpm/usb.txt
@@ -0,0 +1,15 @@
1* USB (Universal Serial Bus Controller)
2
3Properties:
4- compatible : "fsl,cpm1-usb", "fsl,cpm2-usb", "fsl,qe-usb"
5
6Example:
7 usb@11bc0 {
8 #address-cells = <1>;
9 #size-cells = <0>;
10 compatible = "fsl,cpm2-usb";
11 reg = <11b60 18 8b00 100>;
12 interrupts = <b 8>;
13 interrupt-parent = <&PIC>;
14 fsl,cpm-command = <2e600000>;
15 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
new file mode 100644
index 000000000000..0e4269446580
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/network.txt
@@ -0,0 +1,45 @@
1* Network
2
3Currently defined compatibles:
4- fsl,cpm1-scc-enet
5- fsl,cpm2-scc-enet
6- fsl,cpm1-fec-enet
7- fsl,cpm2-fcc-enet (third resource is GFEMR)
8- fsl,qe-enet
9
10Example:
11
12 ethernet@11300 {
13 device_type = "network";
14 compatible = "fsl,mpc8272-fcc-enet",
15 "fsl,cpm2-fcc-enet";
16 reg = <11300 20 8400 100 11390 1>;
17 local-mac-address = [ 00 00 00 00 00 00 ];
18 interrupts = <20 8>;
19 interrupt-parent = <&PIC>;
20 phy-handle = <&PHY0>;
21 fsl,cpm-command = <12000300>;
22 };
23
24* MDIO
25
26Currently defined compatibles:
27fsl,pq1-fec-mdio (reg is same as first resource of FEC device)
28fsl,cpm2-mdio-bitbang (reg is port C registers)
29
30Properties for fsl,cpm2-mdio-bitbang:
31fsl,mdio-pin : pin of port C controlling mdio data
32fsl,mdc-pin : pin of port C controlling mdio clock
33
34Example:
35 mdio@10d40 {
36 device_type = "mdio";
37 compatible = "fsl,mpc8272ads-mdio-bitbang",
38 "fsl,mpc8272-mdio-bitbang",
39 "fsl,cpm2-mdio-bitbang";
40 reg = <10d40 14>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43 fsl,mdio-pin = <12>;
44 fsl,mdc-pin = <13>;
45 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
new file mode 100644
index 000000000000..78790d58dc2c
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -0,0 +1,58 @@
1* Freescale QUICC Engine module (QE)
2This represents qe module that is installed on PowerQUICC II Pro.
3
4NOTE: This is an interim binding; it should be updated to fit
5in with the CPM binding later in this document.
6
7Basically, it is a bus of devices, that could act more or less
8as a complete entity (UCC, USB etc ). All of them should be siblings on
9the "root" qe node, using the common properties from there.
10The description below applies to the qe of MPC8360 and
11more nodes and properties would be extended in the future.
12
13i) Root QE device
14
15Required properties:
16- compatible : should be "fsl,qe";
17- model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18- reg : offset and length of the device registers.
19- bus-frequency : the clock frequency for QUICC Engine.
20
21Recommended properties
22- brg-frequency : the internal clock source frequency for baud-rate
23 generators in Hz.
24
25Example:
26 qe@e0100000 {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 #interrupt-cells = <2>;
30 compatible = "fsl,qe";
31 ranges = <0 e0100000 00100000>;
32 reg = <e0100000 480>;
33 brg-frequency = <0>;
34 bus-frequency = <179A7B00>;
35 }
36
37* Multi-User RAM (MURAM)
38
39Required properties:
40- compatible : should be "fsl,qe-muram", "fsl,cpm-muram".
41- mode : the could be "host" or "slave".
42- ranges : Should be defined as specified in 1) to describe the
43 translation of MURAM addresses.
44- data-only : sub-node which defines the address area under MURAM
45 bus that can be allocated as data/parameter
46
47Example:
48
49 muram@10000 {
50 compatible = "fsl,qe-muram", "fsl,cpm-muram";
51 ranges = <0 00010000 0000c000>;
52
53 data-only@0{
54 compatible = "fsl,qe-muram-data",
55 "fsl,cpm-muram-data";
56 reg = <0 c000>;
57 };
58 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
new file mode 100644
index 000000000000..6c238f59b2a9
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/firmware.txt
@@ -0,0 +1,24 @@
1* Uploaded QE firmware
2
3 If a new firwmare has been uploaded to the QE (usually by the
4 boot loader), then a 'firmware' child node should be added to the QE
5 node. This node provides information on the uploaded firmware that
6 device drivers may need.
7
8 Required properties:
9 - id: The string name of the firmware. This is taken from the 'id'
10 member of the qe_firmware structure of the uploaded firmware.
11 Device drivers can search this string to determine if the
12 firmware they want is already present.
13 - extended-modes: The Extended Modes bitfield, taken from the
14 firmware binary. It is a 64-bit number represented
15 as an array of two 32-bit numbers.
16 - virtual-traps: The virtual traps, taken from the firmware binary.
17 It is an array of 8 32-bit numbers.
18
19Example:
20 firmware {
21 id = "Soft-UART";
22 extended-modes = <0 0>;
23 virtual-traps = <0 0 0 0 0 0 0 0>;
24 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
new file mode 100644
index 000000000000..60984260207b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/par_io.txt
@@ -0,0 +1,51 @@
1* Parallel I/O Ports
2
3This node configures Parallel I/O ports for CPUs with QE support.
4The node should reside in the "soc" node of the tree. For each
5device that using parallel I/O ports, a child node should be created.
6See the definition of the Pin configuration nodes below for more
7information.
8
9Required properties:
10- device_type : should be "par_io".
11- reg : offset to the register set and its length.
12- num-ports : number of Parallel I/O ports
13
14Example:
15par_io@1400 {
16 reg = <1400 100>;
17 #address-cells = <1>;
18 #size-cells = <0>;
19 device_type = "par_io";
20 num-ports = <7>;
21 ucc_pin@01 {
22 ......
23 };
24
25Note that "par_io" nodes are obsolete, and should not be used for
26the new device trees. Instead, each Par I/O bank should be represented
27via its own gpio-controller node:
28
29Required properties:
30- #gpio-cells : should be "2".
31- compatible : should be "fsl,<chip>-qe-pario-bank",
32 "fsl,mpc8323-qe-pario-bank".
33- reg : offset to the register set and its length.
34- gpio-controller : node to identify gpio controllers.
35
36Example:
37 qe_pio_a: gpio-controller@1400 {
38 #gpio-cells = <2>;
39 compatible = "fsl,mpc8360-qe-pario-bank",
40 "fsl,mpc8323-qe-pario-bank";
41 reg = <0x1400 0x18>;
42 gpio-controller;
43 };
44
45 qe_pio_e: gpio-controller@1460 {
46 #gpio-cells = <2>;
47 compatible = "fsl,mpc8360-qe-pario-bank",
48 "fsl,mpc8323-qe-pario-bank";
49 reg = <0x1460 0x18>;
50 gpio-controller;
51 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
new file mode 100644
index 000000000000..c5b43061db3a
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/pincfg.txt
@@ -0,0 +1,60 @@
1* Pin configuration nodes
2
3Required properties:
4- linux,phandle : phandle of this node; likely referenced by a QE
5 device.
6- pio-map : array of pin configurations. Each pin is defined by 6
7 integers. The six numbers are respectively: port, pin, dir,
8 open_drain, assignment, has_irq.
9 - port : port number of the pin; 0-6 represent port A-G in UM.
10 - pin : pin number in the port.
11 - dir : direction of the pin, should encode as follows:
12
13 0 = The pin is disabled
14 1 = The pin is an output
15 2 = The pin is an input
16 3 = The pin is I/O
17
18 - open_drain : indicates the pin is normal or wired-OR:
19
20 0 = The pin is actively driven as an output
21 1 = The pin is an open-drain driver. As an output, the pin is
22 driven active-low, otherwise it is three-stated.
23
24 - assignment : function number of the pin according to the Pin Assignment
25 tables in User Manual. Each pin can have up to 4 possible functions in
26 QE and two options for CPM.
27 - has_irq : indicates if the pin is used as source of external
28 interrupts.
29
30Example:
31 ucc_pin@01 {
32 linux,phandle = <140001>;
33 pio-map = <
34 /* port pin dir open_drain assignment has_irq */
35 0 3 1 0 1 0 /* TxD0 */
36 0 4 1 0 1 0 /* TxD1 */
37 0 5 1 0 1 0 /* TxD2 */
38 0 6 1 0 1 0 /* TxD3 */
39 1 6 1 0 3 0 /* TxD4 */
40 1 7 1 0 1 0 /* TxD5 */
41 1 9 1 0 2 0 /* TxD6 */
42 1 a 1 0 2 0 /* TxD7 */
43 0 9 2 0 1 0 /* RxD0 */
44 0 a 2 0 1 0 /* RxD1 */
45 0 b 2 0 1 0 /* RxD2 */
46 0 c 2 0 1 0 /* RxD3 */
47 0 d 2 0 1 0 /* RxD4 */
48 1 1 2 0 2 0 /* RxD5 */
49 1 0 2 0 2 0 /* RxD6 */
50 1 4 2 0 2 0 /* RxD7 */
51 0 7 1 0 1 0 /* TX_EN */
52 0 8 1 0 1 0 /* TX_ER */
53 0 f 2 0 1 0 /* RX_DV */
54 0 10 2 0 1 0 /* RX_ER */
55 0 0 2 0 1 0 /* RX_CLK */
56 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
57 2 8 2 0 1 0>; /* GTX125 - CLK9 */
58 };
59
60
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
new file mode 100644
index 000000000000..e47734bee3f0
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/ucc.txt
@@ -0,0 +1,70 @@
1* UCC (Unified Communications Controllers)
2
3Required properties:
4- device_type : should be "network", "hldc", "uart", "transparent"
5 "bisync", "atm", or "serial".
6- compatible : could be "ucc_geth" or "fsl_atm" and so on.
7- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
8- reg : Offset and length of the register set for the device
9- interrupts : <a b> where a is the interrupt number and b is a
10 field that represents an encoding of the sense and level
11 information for the interrupt. This should be encoded based on
12 the information in section 2) depending on the type of interrupt
13 controller you have.
14- interrupt-parent : the phandle for the interrupt controller that
15 services interrupts for this device.
16- pio-handle : The phandle for the Parallel I/O port configuration.
17- port-number : for UART drivers, the port number to use, between 0 and 3.
18 This usually corresponds to the /dev/ttyQE device, e.g. <0> = /dev/ttyQE0.
19 The port number is added to the minor number of the device. Unlike the
20 CPM UART driver, the port-number is required for the QE UART driver.
21- soft-uart : for UART drivers, if specified this means the QE UART device
22 driver should use "Soft-UART" mode, which is needed on some SOCs that have
23 broken UART hardware. Soft-UART is provided via a microcode upload.
24- rx-clock-name: the UCC receive clock source
25 "none": clock source is disabled
26 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
27 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
28- tx-clock-name: the UCC transmit clock source
29 "none": clock source is disabled
30 "brg1" through "brg16": clock source is BRG1-BRG16, respectively
31 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
32The following two properties are deprecated. rx-clock has been replaced
33with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
34Drivers that currently use the deprecated properties should continue to
35do so, in order to support older device trees, but they should be updated
36to check for the new properties first.
37- rx-clock : represents the UCC receive clock source.
38 0x00 : clock source is disabled;
39 0x1~0x10 : clock source is BRG1~BRG16 respectively;
40 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
41- tx-clock: represents the UCC transmit clock source;
42 0x00 : clock source is disabled;
43 0x1~0x10 : clock source is BRG1~BRG16 respectively;
44 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
45
46Required properties for network device_type:
47- mac-address : list of bytes representing the ethernet address.
48- phy-handle : The phandle for the PHY connected to this controller.
49
50Recommended properties:
51- phy-connection-type : a string naming the controller/PHY interface type,
52 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
53 Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
54 "tbi", or "rtbi".
55
56Example:
57 ucc@2000 {
58 device_type = "network";
59 compatible = "ucc_geth";
60 cell-index = <1>;
61 reg = <2000 200>;
62 interrupts = <a0 0>;
63 interrupt-parent = <700>;
64 mac-address = [ 00 04 9f 00 23 23 ];
65 rx-clock = "none";
66 tx-clock = "clk9";
67 phy-handle = <212000>;
68 phy-connection-type = "gmii";
69 pio-handle = <140001>;
70 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
new file mode 100644
index 000000000000..c8f44d6bcbcf
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe/usb.txt
@@ -0,0 +1,22 @@
1* USB (Universal Serial Bus Controller)
2
3Required properties:
4- compatible : could be "qe_udc" or "fhci-hcd".
5- mode : the could be "host" or "slave".
6- reg : Offset and length of the register set for the device
7- interrupts : <a b> where a is the interrupt number and b is a
8 field that represents an encoding of the sense and level
9 information for the interrupt. This should be encoded based on
10 the information in section 2) depending on the type of interrupt
11 controller you have.
12- interrupt-parent : the phandle for the interrupt controller that
13 services interrupts for this device.
14
15Example(slave):
16 usb@6c0 {
17 compatible = "qe_udc";
18 reg = <6c0 40>;
19 interrupts = <8b 0>;
20 interrupt-parent = <700>;
21 mode = "slave";
22 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
new file mode 100644
index 000000000000..b35f3482e3e4
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt
@@ -0,0 +1,21 @@
1* Serial
2
3Currently defined compatibles:
4- fsl,cpm1-smc-uart
5- fsl,cpm2-smc-uart
6- fsl,cpm1-scc-uart
7- fsl,cpm2-scc-uart
8- fsl,qe-uart
9
10Example:
11
12 serial@11a00 {
13 device_type = "serial";
14 compatible = "fsl,mpc8272-scc-uart",
15 "fsl,cpm2-scc-uart";
16 reg = <11a00 20 8000 100>;
17 interrupts = <28 8>;
18 interrupt-parent = <&PIC>;
19 fsl,cpm-brg = <1>;
20 fsl,cpm-command = <00800000>;
21 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/diu.txt b/Documentation/powerpc/dts-bindings/fsl/diu.txt
new file mode 100644
index 000000000000..deb35de70988
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/diu.txt
@@ -0,0 +1,18 @@
1* Freescale Display Interface Unit
2
3The Freescale DIU is a LCD controller, with proper hardware, it can also
4drive DVI monitors.
5
6Required properties:
7- compatible : should be "fsl-diu".
8- reg : should contain at least address and length of the DIU register
9 set.
10- Interrupts : one DIU interrupt should be describe here.
11
12Example (MPC8610HPCD):
13 display@2c000 {
14 compatible = "fsl,diu";
15 reg = <0x2c000 100>;
16 interrupts = <72 2>;
17 interrupt-parent = <&mpic>;
18 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
new file mode 100644
index 000000000000..86826df00e64
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -0,0 +1,127 @@
1* Freescale 83xx DMA Controller
2
3Freescale PowerPC 83xx have on chip general purpose DMA controllers.
4
5Required properties:
6
7- compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-dma", where CHIP is the processor
9 (mpc8349, mpc8360, etc.) and the second is
10 "fsl,elo-dma"
11- reg : <registers mapping for DMA general status reg>
12- ranges : Should be defined as specified in 1) to describe the
13 DMA controller channels.
14- cell-index : controller index. 0 for controller @ 0x8100
15- interrupts : <interrupt mapping for DMA IRQ>
16- interrupt-parent : optional, if needed for interrupt mapping
17
18
19- DMA channel nodes:
20 - compatible : compatible list, contains 2 entries, first is
21 "fsl,CHIP-dma-channel", where CHIP is the processor
22 (mpc8349, mpc8350, etc.) and the second is
23 "fsl,elo-dma-channel"
24 - reg : <registers mapping for channel>
25 - cell-index : dma channel index starts at 0.
26
27Optional properties:
28 - interrupts : <interrupt mapping for DMA channel IRQ>
29 (on 83xx this is expected to be identical to
30 the interrupts property of the parent node)
31 - interrupt-parent : optional, if needed for interrupt mapping
32
33Example:
34 dma@82a8 {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
38 reg = <82a8 4>;
39 ranges = <0 8100 1a4>;
40 interrupt-parent = <&ipic>;
41 interrupts = <47 8>;
42 cell-index = <0>;
43 dma-channel@0 {
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 cell-index = <0>;
46 reg = <0 80>;
47 };
48 dma-channel@80 {
49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
50 cell-index = <1>;
51 reg = <80 80>;
52 };
53 dma-channel@100 {
54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
55 cell-index = <2>;
56 reg = <100 80>;
57 };
58 dma-channel@180 {
59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
60 cell-index = <3>;
61 reg = <180 80>;
62 };
63 };
64
65* Freescale 85xx/86xx DMA Controller
66
67Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.
68
69Required properties:
70
71- compatible : compatible list, contains 2 entries, first is
72 "fsl,CHIP-dma", where CHIP is the processor
73 (mpc8540, mpc8540, etc.) and the second is
74 "fsl,eloplus-dma"
75- reg : <registers mapping for DMA general status reg>
76- cell-index : controller index. 0 for controller @ 0x21000,
77 1 for controller @ 0xc000
78- ranges : Should be defined as specified in 1) to describe the
79 DMA controller channels.
80
81- DMA channel nodes:
82 - compatible : compatible list, contains 2 entries, first is
83 "fsl,CHIP-dma-channel", where CHIP is the processor
84 (mpc8540, mpc8560, etc.) and the second is
85 "fsl,eloplus-dma-channel"
86 - cell-index : dma channel index starts at 0.
87 - reg : <registers mapping for channel>
88 - interrupts : <interrupt mapping for DMA channel IRQ>
89 - interrupt-parent : optional, if needed for interrupt mapping
90
91Example:
92 dma@21300 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
96 reg = <21300 4>;
97 ranges = <0 21100 200>;
98 cell-index = <0>;
99 dma-channel@0 {
100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
101 reg = <0 80>;
102 cell-index = <0>;
103 interrupt-parent = <&mpic>;
104 interrupts = <14 2>;
105 };
106 dma-channel@80 {
107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
108 reg = <80 80>;
109 cell-index = <1>;
110 interrupt-parent = <&mpic>;
111 interrupts = <15 2>;
112 };
113 dma-channel@100 {
114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
115 reg = <100 80>;
116 cell-index = <2>;
117 interrupt-parent = <&mpic>;
118 interrupts = <16 2>;
119 };
120 dma-channel@180 {
121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
122 reg = <180 80>;
123 cell-index = <3>;
124 interrupt-parent = <&mpic>;
125 interrupts = <17 2>;
126 };
127 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/gtm.txt b/Documentation/powerpc/dts-bindings/fsl/gtm.txt
new file mode 100644
index 000000000000..9a33efded4bc
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/gtm.txt
@@ -0,0 +1,31 @@
1* Freescale General-purpose Timers Module
2
3Required properties:
4 - compatible : should be
5 "fsl,<chip>-gtm", "fsl,gtm" for SOC GTMs
6 "fsl,<chip>-qe-gtm", "fsl,qe-gtm", "fsl,gtm" for QE GTMs
7 "fsl,<chip>-cpm2-gtm", "fsl,cpm2-gtm", "fsl,gtm" for CPM2 GTMs
8 - reg : should contain gtm registers location and length (0x40).
9 - interrupts : should contain four interrupts.
10 - interrupt-parent : interrupt source phandle.
11 - clock-frequency : specifies the frequency driving the timer.
12
13Example:
14
15timer@500 {
16 compatible = "fsl,mpc8360-gtm", "fsl,gtm";
17 reg = <0x500 0x40>;
18 interrupts = <90 8 78 8 84 8 72 8>;
19 interrupt-parent = <&ipic>;
20 /* filled by u-boot */
21 clock-frequency = <0>;
22};
23
24timer@440 {
25 compatible = "fsl,mpc8360-qe-gtm", "fsl,qe-gtm", "fsl,gtm";
26 reg = <0x440 0x40>;
27 interrupts = <12 13 14 15>;
28 interrupt-parent = <&qeic>;
29 /* filled by u-boot */
30 clock-frequency = <0>;
31};
diff --git a/Documentation/powerpc/dts-bindings/fsl/guts.txt b/Documentation/powerpc/dts-bindings/fsl/guts.txt
new file mode 100644
index 000000000000..9e7a2417dac5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/guts.txt
@@ -0,0 +1,25 @@
1* Global Utilities Block
2
3The global utilities block controls power management, I/O device
4enabling, power-on-reset configuration monitoring, general-purpose
5I/O signal configuration, alternate function selection for multiplexed
6signals, and clock control.
7
8Required properties:
9
10 - compatible : Should define the compatible device type for
11 global-utilities.
12 - reg : Offset and length of the register set for the device.
13
14Recommended properties:
15
16 - fsl,has-rstcr : Indicates that the global utilities register set
17 contains a functioning "reset control register" (i.e. the board
18 is wired to reset upon setting the HRESET_REQ bit in this register).
19
20Example:
21 global-utilities@e0000 { /* global utilities block */
22 compatible = "fsl,mpc8548-guts";
23 reg = <e0000 1000>;
24 fsl,has-rstcr;
25 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
new file mode 100644
index 000000000000..d0ab33e21fe6
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -0,0 +1,32 @@
1* I2C
2
3Required properties :
4
5 - device_type : Should be "i2c"
6 - reg : Offset and length of the register set for the device
7
8Recommended properties :
9
10 - compatible : Should be "fsl-i2c" for parts compatible with
11 Freescale I2C specifications.
12 - interrupts : <a b> where a is the interrupt number and b is a
13 field that represents an encoding of the sense and level
14 information for the interrupt. This should be encoded based on
15 the information in section 2) depending on the type of interrupt
16 controller you have.
17 - interrupt-parent : the phandle for the interrupt controller that
18 services interrupts for this device.
19 - dfsrr : boolean; if defined, indicates that this I2C device has
20 a digital filter sampling rate register
21 - fsl5200-clocking : boolean; if defined, indicated that this device
22 uses the FSL 5200 clocking mechanism.
23
24Example :
25 i2c@3000 {
26 interrupt-parent = <40000>;
27 interrupts = <1b 3>;
28 reg = <3000 18>;
29 device_type = "i2c";
30 compatible = "fsl-i2c";
31 dfsrr;
32 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/lbc.txt b/Documentation/powerpc/dts-bindings/fsl/lbc.txt
new file mode 100644
index 000000000000..3300fec501c5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/lbc.txt
@@ -0,0 +1,35 @@
1* Chipselect/Local Bus
2
3Properties:
4- name : Should be localbus
5- #address-cells : Should be either two or three. The first cell is the
6 chipselect number, and the remaining cells are the
7 offset into the chipselect.
8- #size-cells : Either one or two, depending on how large each chipselect
9 can be.
10- ranges : Each range corresponds to a single chipselect, and cover
11 the entire access window as configured.
12
13Example:
14 localbus@f0010100 {
15 compatible = "fsl,mpc8272-localbus",
16 "fsl,pq2-localbus";
17 #address-cells = <2>;
18 #size-cells = <1>;
19 reg = <f0010100 40>;
20
21 ranges = <0 0 fe000000 02000000
22 1 0 f4500000 00008000>;
23
24 flash@0,0 {
25 compatible = "jedec-flash";
26 reg = <0 0 2000000>;
27 bank-width = <4>;
28 device-width = <1>;
29 };
30
31 board-control@1,0 {
32 reg = <1 0 20>;
33 compatible = "fsl,mpc8272ads-bcsr";
34 };
35 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
new file mode 100644
index 000000000000..b26b91992c55
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/msi-pic.txt
@@ -0,0 +1,36 @@
1* Freescale MSI interrupt controller
2
3Reguired properities:
4- compatible : compatible list, contains 2 entries,
5 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
7 the parent type.
8- reg : should contain the address and the length of the shared message
9 interrupt register set.
10- msi-available-ranges: use <start count> style section to define which
11 msi interrupt can be used in the 256 msi interrupts. This property is
12 optional, without this, all the 256 MSI interrupts can be used.
13- interrupts : each one of the interrupts here is one entry per 32 MSIs,
14 and routed to the host interrupt controller. the interrupts should
15 be set as edge sensitive.
16- interrupt-parent: the phandle for the interrupt controller
17 that services interrupts for this device. for 83xx cpu, the interrupts
18 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
19 to MPIC.
20
21Example:
22 msi@41600 {
23 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
24 reg = <0x41600 0x80>;
25 msi-available-ranges = <0 0x100>;
26 interrupts = <
27 0xe0 0
28 0xe1 0
29 0xe2 0
30 0xe3 0
31 0xe4 0
32 0xe5 0
33 0xe6 0
34 0xe7 0>;
35 interrupt-parent = <&mpic>;
36 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/sata.txt b/Documentation/powerpc/dts-bindings/fsl/sata.txt
new file mode 100644
index 000000000000..b46bcf46c3d8
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/sata.txt
@@ -0,0 +1,29 @@
1* Freescale 8xxx/3.0 Gb/s SATA nodes
2
3SATA nodes are defined to describe on-chip Serial ATA controllers.
4Each SATA port should have its own node.
5
6Required properties:
7- compatible : compatible list, contains 2 entries, first is
8 "fsl,CHIP-sata", where CHIP is the processor
9 (mpc8315, mpc8379, etc.) and the second is
10 "fsl,pq-sata"
11- interrupts : <interrupt mapping for SATA IRQ>
12- cell-index : controller index.
13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
15 3 for controller @ 0x1a000
16 4 for controller @ 0x1b000
17
18Optional properties:
19- interrupt-parent : optional, if needed for interrupt mapping
20- reg : <registers mapping>
21
22Example:
23 sata@18000 {
24 compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
25 reg = <0x18000 0x1000>;
26 cell-index = <1>;
27 interrupts = <2c 8>;
28 interrupt-parent = < &ipic >;
29 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/sec.txt b/Documentation/powerpc/dts-bindings/fsl/sec.txt
new file mode 100644
index 000000000000..2b6f2d45c45a
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/sec.txt
@@ -0,0 +1,68 @@
1Freescale SoC SEC Security Engines
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0"
7- reg : Offset and length of the register set for the device
8- interrupts : the SEC's interrupt number
9- fsl,num-channels : An integer representing the number of channels
10 available.
11- fsl,channel-fifo-len : An integer representing the number of
12 descriptor pointers each channel fetch fifo can hold.
13- fsl,exec-units-mask : The bitmask representing what execution units
14 (EUs) are available. It's a single 32-bit cell. EU information
15 should be encoded following the SEC's Descriptor Header Dword
16 EU_SEL0 field documentation, i.e. as follows:
17
18 bit 0 = reserved - should be 0
19 bit 1 = set if SEC has the ARC4 EU (AFEU)
20 bit 2 = set if SEC has the DES/3DES EU (DEU)
21 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
22 bit 4 = set if SEC has the random number generator EU (RNG)
23 bit 5 = set if SEC has the public key EU (PKEU)
24 bit 6 = set if SEC has the AES EU (AESU)
25 bit 7 = set if SEC has the Kasumi EU (KEU)
26 bit 8 = set if SEC has the CRC EU (CRCU)
27 bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B)
28
29remaining bits are reserved for future SEC EUs.
30
31- fsl,descriptor-types-mask : The bitmask representing what descriptors
32 are available. It's a single 32-bit cell. Descriptor type information
33 should be encoded following the SEC's Descriptor Header Dword DESC_TYPE
34 field documentation, i.e. as follows:
35
36 bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type
37 bit 1 = set if SEC supports the ipsec_esp descriptor type
38 bit 2 = set if SEC supports the common_nonsnoop desc. type
39 bit 3 = set if SEC supports the 802.11i AES ccmp desc. type
40 bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type
41 bit 5 = set if SEC supports the srtp descriptor type
42 bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type
43 bit 7 = set if SEC supports the pkeu_assemble descriptor type
44 bit 8 = set if SEC supports the aesu_key_expand_output desc.type
45 bit 9 = set if SEC supports the pkeu_ptmul descriptor type
46 bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type
47 bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type
48
49 ..and so on and so forth.
50
51Optional properties:
52
53- interrupt-parent : the phandle for the interrupt controller that
54 services interrupts for this device.
55
56Example:
57
58 /* MPC8548E */
59 crypto@30000 {
60 compatible = "fsl,sec2.1", "fsl,sec2.0";
61 reg = <0x30000 0x10000>;
62 interrupts = <29 2>;
63 interrupt-parent = <&mpic>;
64 fsl,num-channels = <4>;
65 fsl,channel-fifo-len = <24>;
66 fsl,exec-units-mask = <0xfe>;
67 fsl,descriptor-types-mask = <0x12b0ebf>;
68 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt
new file mode 100644
index 000000000000..e7d9a344c4f4
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -0,0 +1,24 @@
1* SPI (Serial Peripheral Interface)
2
3Required properties:
4- cell-index : SPI controller index.
5- compatible : should be "fsl,spi".
6- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
7- reg : Offset and length of the register set for the device
8- interrupts : <a b> where a is the interrupt number and b is a
9 field that represents an encoding of the sense and level
10 information for the interrupt. This should be encoded based on
11 the information in section 2) depending on the type of interrupt
12 controller you have.
13- interrupt-parent : the phandle for the interrupt controller that
14 services interrupts for this device.
15
16Example:
17 spi@4c0 {
18 cell-index = <0>;
19 compatible = "fsl,spi";
20 reg = <4c0 40>;
21 interrupts = <82 0>;
22 interrupt-parent = <700>;
23 mode = "cpu";
24 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/ssi.txt b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
new file mode 100644
index 000000000000..d100555d488a
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
@@ -0,0 +1,38 @@
1Freescale Synchronous Serial Interface
2
3The SSI is a serial device that communicates with audio codecs. It can
4be programmed in AC97, I2S, left-justified, or right-justified modes.
5
6Required properties:
7- compatible : compatible list, containing "fsl,ssi"
8- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on
9- reg : offset and length of the register set for the device
10- interrupts : <a b> where a is the interrupt number and b is a
11 field that represents an encoding of the sense and
12 level information for the interrupt. This should be
13 encoded based on the information in section 2)
14 depending on the type of interrupt controller you
15 have.
16- interrupt-parent : the phandle for the interrupt controller that
17 services interrupts for this device.
18- fsl,mode : the operating mode for the SSI interface
19 "i2s-slave" - I2S mode, SSI is clock slave
20 "i2s-master" - I2S mode, SSI is clock master
21 "lj-slave" - left-justified mode, SSI is clock slave
22 "lj-master" - l.j. mode, SSI is clock master
23 "rj-slave" - right-justified mode, SSI is clock slave
24 "rj-master" - r.j., SSI is clock master
25 "ac97-slave" - AC97 mode, SSI is clock slave
26 "ac97-master" - AC97 mode, SSI is clock master
27
28Optional properties:
29- codec-handle : phandle to a 'codec' node that defines an audio
30 codec connected to this SSI. This node is typically
31 a child of an I2C or other control node.
32
33Child 'codec' node required properties:
34- compatible : compatible list, contains the name of the codec
35
36Child 'codec' node optional properties:
37- clock-frequency : The frequency of the input clock, which typically
38 comes from an on-board dedicated oscillator.
diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
new file mode 100644
index 000000000000..583ef6b56c43
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
@@ -0,0 +1,69 @@
1* MDIO IO device
2
3The MDIO is a bus to which the PHY devices are connected. For each
4device that exists on this bus, a child node should be created. See
5the definition of the PHY node below for an example of how to define
6a PHY.
7
8Required properties:
9 - reg : Offset and length of the register set for the device
10 - compatible : Should define the compatible device type for the
11 mdio. Currently, this is most likely to be "fsl,gianfar-mdio"
12
13Example:
14
15 mdio@24520 {
16 reg = <24520 20>;
17 compatible = "fsl,gianfar-mdio";
18
19 ethernet-phy@0 {
20 ......
21 };
22 };
23
24
25* Gianfar-compatible ethernet nodes
26
27Required properties:
28
29 - device_type : Should be "network"
30 - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC"
31 - compatible : Should be "gianfar"
32 - reg : Offset and length of the register set for the device
33 - mac-address : List of bytes representing the ethernet address of
34 this controller
35 - interrupts : <a b> where a is the interrupt number and b is a
36 field that represents an encoding of the sense and level
37 information for the interrupt. This should be encoded based on
38 the information in section 2) depending on the type of interrupt
39 controller you have.
40 - interrupt-parent : the phandle for the interrupt controller that
41 services interrupts for this device.
42 - phy-handle : The phandle for the PHY connected to this ethernet
43 controller.
44 - fixed-link : <a b c d e> where a is emulated phy id - choose any,
45 but unique to the all specified fixed-links, b is duplex - 0 half,
46 1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
47 pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
48
49Recommended properties:
50
51 - phy-connection-type : a string naming the controller/PHY interface type,
52 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
53 "tbi", or "rtbi". This property is only really needed if the connection
54 is of type "rgmii-id", as all other connection types are detected by
55 hardware.
56
57
58Example:
59 ethernet@24000 {
60 #size-cells = <0>;
61 device_type = "network";
62 model = "TSEC";
63 compatible = "gianfar";
64 reg = <24000 1000>;
65 mac-address = [ 00 E0 0C 00 73 00 ];
66 interrupts = <d 3 e 3 12 3>;
67 interrupt-parent = <40000>;
68 phy-handle = <2452000>
69 };
diff --git a/Documentation/powerpc/dts-bindings/fsl/usb.txt b/Documentation/powerpc/dts-bindings/fsl/usb.txt
new file mode 100644
index 000000000000..b00152402694
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/usb.txt
@@ -0,0 +1,59 @@
1Freescale SOC USB controllers
2
3The device node for a USB controller that is part of a Freescale
4SOC is as described in the document "Open Firmware Recommended
5Practice : Universal Serial Bus" with the following modifications
6and additions :
7
8Required properties :
9 - compatible : Should be "fsl-usb2-mph" for multi port host USB
10 controllers, or "fsl-usb2-dr" for dual role USB controllers
11 - phy_type : For multi port host USB controllers, should be one of
12 "ulpi", or "serial". For dual role USB controllers, should be
13 one of "ulpi", "utmi", "utmi_wide", or "serial".
14 - reg : Offset and length of the register set for the device
15 - port0 : boolean; if defined, indicates port0 is connected for
16 fsl-usb2-mph compatible controllers. Either this property or
17 "port1" (or both) must be defined for "fsl-usb2-mph" compatible
18 controllers.
19 - port1 : boolean; if defined, indicates port1 is connected for
20 fsl-usb2-mph compatible controllers. Either this property or
21 "port0" (or both) must be defined for "fsl-usb2-mph" compatible
22 controllers.
23 - dr_mode : indicates the working mode for "fsl-usb2-dr" compatible
24 controllers. Can be "host", "peripheral", or "otg". Default to
25 "host" if not defined for backward compatibility.
26
27Recommended properties :
28 - interrupts : <a b> where a is the interrupt number and b is a
29 field that represents an encoding of the sense and level
30 information for the interrupt. This should be encoded based on
31 the information in section 2) depending on the type of interrupt
32 controller you have.
33 - interrupt-parent : the phandle for the interrupt controller that
34 services interrupts for this device.
35
36Example multi port host USB controller device node :
37 usb@22000 {
38 compatible = "fsl-usb2-mph";
39 reg = <22000 1000>;
40 #address-cells = <1>;
41 #size-cells = <0>;
42 interrupt-parent = <700>;
43 interrupts = <27 1>;
44 phy_type = "ulpi";
45 port0;
46 port1;
47 };
48
49Example dual role USB controller device node :
50 usb@23000 {
51 compatible = "fsl-usb2-dr";
52 reg = <23000 1000>;
53 #address-cells = <1>;
54 #size-cells = <0>;
55 interrupt-parent = <700>;
56 interrupts = <26 1>;
57 dr_mode = "otg";
58 phy = "ulpi";
59 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 02:18:34 -0400