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-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index e2371f5cdebe..eabcb4b5db6e 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -18,6 +18,7 @@ Required properties:
18- interrupt-map-mask and interrupt-map: standard PCI properties 18- interrupt-map-mask and interrupt-map: standard PCI properties
19 to define the mapping of the PCIe interface to interrupt 19 to define the mapping of the PCIe interface to interrupt
20 numbers. 20 numbers.
21- num-lanes: number of lanes to use
21- reset-gpio: gpio pin number of power good signal 22- reset-gpio: gpio pin number of power good signal
22 23
23Example: 24Example:
@@ -41,6 +42,7 @@ SoC specific DT Entry:
41 #interrupt-cells = <1>; 42 #interrupt-cells = <1>;
42 interrupt-map-mask = <0 0 0 0>; 43 interrupt-map-mask = <0 0 0 0>;
43 interrupt-map = <0x0 0 &gic 53>; 44 interrupt-map = <0x0 0 &gic 53>;
45 num-lanes = <4>;
44 }; 46 };
45 47
46 pcie@2a0000 { 48 pcie@2a0000 {
@@ -60,6 +62,7 @@ SoC specific DT Entry:
60 #interrupt-cells = <1>; 62 #interrupt-cells = <1>;
61 interrupt-map-mask = <0 0 0 0>; 63 interrupt-map-mask = <0 0 0 0>;
62 interrupt-map = <0x0 0 &gic 56>; 64 interrupt-map = <0x0 0 &gic 56>;
65 num-lanes = <4>;
63 }; 66 };
64 67
65Board specific DT Entry: 68Board specific DT Entry: