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-rw-r--r--Documentation/spi/spi-summary53
1 files changed, 48 insertions, 5 deletions
diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary
index 795fbb48ffa7..76ea6c837be5 100644
--- a/Documentation/spi/spi-summary
+++ b/Documentation/spi/spi-summary
@@ -1,26 +1,30 @@
1Overview of Linux kernel SPI support 1Overview of Linux kernel SPI support
2==================================== 2====================================
3 3
402-Dec-2005 421-May-2007
5 5
6What is SPI? 6What is SPI?
7------------ 7------------
8The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial 8The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial
9link used to connect microcontrollers to sensors, memory, and peripherals. 9link used to connect microcontrollers to sensors, memory, and peripherals.
10It's a simple "de facto" standard, not complicated enough to acquire a
11standardization body. SPI uses a master/slave configuration.
10 12
11The three signal wires hold a clock (SCK, often on the order of 10 MHz), 13The three signal wires hold a clock (SCK, often on the order of 10 MHz),
12and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In, 14and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
13Slave Out" (MISO) signals. (Other names are also used.) There are four 15Slave Out" (MISO) signals. (Other names are also used.) There are four
14clocking modes through which data is exchanged; mode-0 and mode-3 are most 16clocking modes through which data is exchanged; mode-0 and mode-3 are most
15commonly used. Each clock cycle shifts data out and data in; the clock 17commonly used. Each clock cycle shifts data out and data in; the clock
16doesn't cycle except when there is data to shift. 18doesn't cycle except when there is a data bit to shift. Not all data bits
19are used though; not every protocol uses those full duplex capabilities.
17 20
18SPI masters may use a "chip select" line to activate a given SPI slave 21SPI masters use a fourth "chip select" line to activate a given SPI slave
19device, so those three signal wires may be connected to several chips 22device, so those three signal wires may be connected to several chips
20in parallel. All SPI slaves support chipselects. Some devices have 23in parallel. All SPI slaves support chipselects; they are usually active
24low signals, labeled nCSx for slave 'x' (e.g. nCS0). Some devices have
21other signals, often including an interrupt to the master. 25other signals, often including an interrupt to the master.
22 26
23Unlike serial busses like USB or SMBUS, even low level protocols for 27Unlike serial busses like USB or SMBus, even low level protocols for
24SPI slave functions are usually not interoperable between vendors 28SPI slave functions are usually not interoperable between vendors
25(except for commodities like SPI memory chips). 29(except for commodities like SPI memory chips).
26 30
@@ -33,6 +37,11 @@ SPI slave functions are usually not interoperable between vendors
33 - Some devices may use eight bit words. Others may different word 37 - Some devices may use eight bit words. Others may different word
34 lengths, such as streams of 12-bit or 20-bit digital samples. 38 lengths, such as streams of 12-bit or 20-bit digital samples.
35 39
40 - Words are usually sent with their most significant bit (MSB) first,
41 but sometimes the least significant bit (LSB) goes first instead.
42
43 - Sometimes SPI is used to daisy-chain devices, like shift registers.
44
36In the same way, SPI slaves will only rarely support any kind of automatic 45In the same way, SPI slaves will only rarely support any kind of automatic
37discovery/enumeration protocol. The tree of slave devices accessible from 46discovery/enumeration protocol. The tree of slave devices accessible from
38a given SPI master will normally be set up manually, with configuration 47a given SPI master will normally be set up manually, with configuration
@@ -44,6 +53,14 @@ half-duplex SPI, for request/response protocols), SSP ("Synchronous
44Serial Protocol"), PSP ("Programmable Serial Protocol"), and other 53Serial Protocol"), PSP ("Programmable Serial Protocol"), and other
45related protocols. 54related protocols.
46 55
56Some chips eliminate a signal line by combining MOSI and MISO, and
57limiting themselves to half-duplex at the hardware level. In fact
58some SPI chips have this signal mode as a strapping option. These
59can be accessed using the same programming interface as SPI, but of
60course they won't handle full duplex transfers. You may find such
61chips described as using "three wire" signaling: SCK, data, nCSx.
62(That data line is sometimes called MOMI or SISO.)
63
47Microcontrollers often support both master and slave sides of the SPI 64Microcontrollers often support both master and slave sides of the SPI
48protocol. This document (and Linux) currently only supports the master 65protocol. This document (and Linux) currently only supports the master
49side of SPI interactions. 66side of SPI interactions.
@@ -74,6 +91,32 @@ interfaces with SPI modes. Given SPI support, they could use MMC or SD
74cards without needing a special purpose MMC/SD/SDIO controller. 91cards without needing a special purpose MMC/SD/SDIO controller.
75 92
76 93
94I'm confused. What are these four SPI "clock modes"?
95-----------------------------------------------------
96It's easy to be confused here, and the vendor documentation you'll
97find isn't necessarily helpful. The four modes combine two mode bits:
98
99 - CPOL indicates the initial clock polarity. CPOL=0 means the
100 clock starts low, so the first (leading) edge is rising, and
101 the second (trailing) edge is falling. CPOL=1 means the clock
102 starts high, so the first (leading) edge is falling.
103
104 - CPHA indicates the clock phase used to sample data; CPHA=0 says
105 sample on the leading edge, CPHA=1 means the trailing edge.
106
107 Since the signal needs to stablize before it's sampled, CPHA=0
108 implies that its data is written half a clock before the first
109 clock edge. The chipselect may have made it become available.
110
111Chip specs won't always say "uses SPI mode X" in as many words,
112but their timing diagrams will make the CPOL and CPHA modes clear.
113
114In the SPI mode number, CPOL is the high order bit and CPHA is the
115low order bit. So when a chip's timing diagram shows the clock
116starting low (CPOL=0) and data stabilized for sampling during the
117trailing clock edge (CPHA=1), that's SPI mode 1.
118
119
77How do these driver programming interfaces work? 120How do these driver programming interfaces work?
78------------------------------------------------ 121------------------------------------------------
79The <linux/spi/spi.h> header file includes kerneldoc, as does the 122The <linux/spi/spi.h> header file includes kerneldoc, as does the