diff options
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/spi/spi-summary | 53 |
1 files changed, 48 insertions, 5 deletions
diff --git a/Documentation/spi/spi-summary b/Documentation/spi/spi-summary index 795fbb48ffa7..76ea6c837be5 100644 --- a/Documentation/spi/spi-summary +++ b/Documentation/spi/spi-summary | |||
@@ -1,26 +1,30 @@ | |||
1 | Overview of Linux kernel SPI support | 1 | Overview of Linux kernel SPI support |
2 | ==================================== | 2 | ==================================== |
3 | 3 | ||
4 | 02-Dec-2005 | 4 | 21-May-2007 |
5 | 5 | ||
6 | What is SPI? | 6 | What is SPI? |
7 | ------------ | 7 | ------------ |
8 | The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial | 8 | The "Serial Peripheral Interface" (SPI) is a synchronous four wire serial |
9 | link used to connect microcontrollers to sensors, memory, and peripherals. | 9 | link used to connect microcontrollers to sensors, memory, and peripherals. |
10 | It's a simple "de facto" standard, not complicated enough to acquire a | ||
11 | standardization body. SPI uses a master/slave configuration. | ||
10 | 12 | ||
11 | The three signal wires hold a clock (SCK, often on the order of 10 MHz), | 13 | The three signal wires hold a clock (SCK, often on the order of 10 MHz), |
12 | and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In, | 14 | and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In, |
13 | Slave Out" (MISO) signals. (Other names are also used.) There are four | 15 | Slave Out" (MISO) signals. (Other names are also used.) There are four |
14 | clocking modes through which data is exchanged; mode-0 and mode-3 are most | 16 | clocking modes through which data is exchanged; mode-0 and mode-3 are most |
15 | commonly used. Each clock cycle shifts data out and data in; the clock | 17 | commonly used. Each clock cycle shifts data out and data in; the clock |
16 | doesn't cycle except when there is data to shift. | 18 | doesn't cycle except when there is a data bit to shift. Not all data bits |
19 | are used though; not every protocol uses those full duplex capabilities. | ||
17 | 20 | ||
18 | SPI masters may use a "chip select" line to activate a given SPI slave | 21 | SPI masters use a fourth "chip select" line to activate a given SPI slave |
19 | device, so those three signal wires may be connected to several chips | 22 | device, so those three signal wires may be connected to several chips |
20 | in parallel. All SPI slaves support chipselects. Some devices have | 23 | in parallel. All SPI slaves support chipselects; they are usually active |
24 | low signals, labeled nCSx for slave 'x' (e.g. nCS0). Some devices have | ||
21 | other signals, often including an interrupt to the master. | 25 | other signals, often including an interrupt to the master. |
22 | 26 | ||
23 | Unlike serial busses like USB or SMBUS, even low level protocols for | 27 | Unlike serial busses like USB or SMBus, even low level protocols for |
24 | SPI slave functions are usually not interoperable between vendors | 28 | SPI slave functions are usually not interoperable between vendors |
25 | (except for commodities like SPI memory chips). | 29 | (except for commodities like SPI memory chips). |
26 | 30 | ||
@@ -33,6 +37,11 @@ SPI slave functions are usually not interoperable between vendors | |||
33 | - Some devices may use eight bit words. Others may different word | 37 | - Some devices may use eight bit words. Others may different word |
34 | lengths, such as streams of 12-bit or 20-bit digital samples. | 38 | lengths, such as streams of 12-bit or 20-bit digital samples. |
35 | 39 | ||
40 | - Words are usually sent with their most significant bit (MSB) first, | ||
41 | but sometimes the least significant bit (LSB) goes first instead. | ||
42 | |||
43 | - Sometimes SPI is used to daisy-chain devices, like shift registers. | ||
44 | |||
36 | In the same way, SPI slaves will only rarely support any kind of automatic | 45 | In the same way, SPI slaves will only rarely support any kind of automatic |
37 | discovery/enumeration protocol. The tree of slave devices accessible from | 46 | discovery/enumeration protocol. The tree of slave devices accessible from |
38 | a given SPI master will normally be set up manually, with configuration | 47 | a given SPI master will normally be set up manually, with configuration |
@@ -44,6 +53,14 @@ half-duplex SPI, for request/response protocols), SSP ("Synchronous | |||
44 | Serial Protocol"), PSP ("Programmable Serial Protocol"), and other | 53 | Serial Protocol"), PSP ("Programmable Serial Protocol"), and other |
45 | related protocols. | 54 | related protocols. |
46 | 55 | ||
56 | Some chips eliminate a signal line by combining MOSI and MISO, and | ||
57 | limiting themselves to half-duplex at the hardware level. In fact | ||
58 | some SPI chips have this signal mode as a strapping option. These | ||
59 | can be accessed using the same programming interface as SPI, but of | ||
60 | course they won't handle full duplex transfers. You may find such | ||
61 | chips described as using "three wire" signaling: SCK, data, nCSx. | ||
62 | (That data line is sometimes called MOMI or SISO.) | ||
63 | |||
47 | Microcontrollers often support both master and slave sides of the SPI | 64 | Microcontrollers often support both master and slave sides of the SPI |
48 | protocol. This document (and Linux) currently only supports the master | 65 | protocol. This document (and Linux) currently only supports the master |
49 | side of SPI interactions. | 66 | side of SPI interactions. |
@@ -74,6 +91,32 @@ interfaces with SPI modes. Given SPI support, they could use MMC or SD | |||
74 | cards without needing a special purpose MMC/SD/SDIO controller. | 91 | cards without needing a special purpose MMC/SD/SDIO controller. |
75 | 92 | ||
76 | 93 | ||
94 | I'm confused. What are these four SPI "clock modes"? | ||
95 | ----------------------------------------------------- | ||
96 | It's easy to be confused here, and the vendor documentation you'll | ||
97 | find isn't necessarily helpful. The four modes combine two mode bits: | ||
98 | |||
99 | - CPOL indicates the initial clock polarity. CPOL=0 means the | ||
100 | clock starts low, so the first (leading) edge is rising, and | ||
101 | the second (trailing) edge is falling. CPOL=1 means the clock | ||
102 | starts high, so the first (leading) edge is falling. | ||
103 | |||
104 | - CPHA indicates the clock phase used to sample data; CPHA=0 says | ||
105 | sample on the leading edge, CPHA=1 means the trailing edge. | ||
106 | |||
107 | Since the signal needs to stablize before it's sampled, CPHA=0 | ||
108 | implies that its data is written half a clock before the first | ||
109 | clock edge. The chipselect may have made it become available. | ||
110 | |||
111 | Chip specs won't always say "uses SPI mode X" in as many words, | ||
112 | but their timing diagrams will make the CPOL and CPHA modes clear. | ||
113 | |||
114 | In the SPI mode number, CPOL is the high order bit and CPHA is the | ||
115 | low order bit. So when a chip's timing diagram shows the clock | ||
116 | starting low (CPOL=0) and data stabilized for sampling during the | ||
117 | trailing clock edge (CPHA=1), that's SPI mode 1. | ||
118 | |||
119 | |||
77 | How do these driver programming interfaces work? | 120 | How do these driver programming interfaces work? |
78 | ------------------------------------------------ | 121 | ------------------------------------------------ |
79 | The <linux/spi/spi.h> header file includes kerneldoc, as does the | 122 | The <linux/spi/spi.h> header file includes kerneldoc, as does the |