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-rw-r--r--Documentation/powerpc/dts-bindings/fsl/dma.txt34
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/esdhc.txt24
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/ssi.txt68
3 files changed, 81 insertions, 45 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
index cc453110fc46..0732cdd05ba1 100644
--- a/Documentation/powerpc/dts-bindings/fsl/dma.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -35,30 +35,30 @@ Example:
35 #address-cells = <1>; 35 #address-cells = <1>;
36 #size-cells = <1>; 36 #size-cells = <1>;
37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; 37 compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
38 reg = <82a8 4>; 38 reg = <0x82a8 4>;
39 ranges = <0 8100 1a4>; 39 ranges = <0 0x8100 0x1a4>;
40 interrupt-parent = <&ipic>; 40 interrupt-parent = <&ipic>;
41 interrupts = <47 8>; 41 interrupts = <71 8>;
42 cell-index = <0>; 42 cell-index = <0>;
43 dma-channel@0 { 43 dma-channel@0 {
44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 44 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 cell-index = <0>; 45 cell-index = <0>;
46 reg = <0 80>; 46 reg = <0 0x80>;
47 }; 47 };
48 dma-channel@80 { 48 dma-channel@80 {
49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 49 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
50 cell-index = <1>; 50 cell-index = <1>;
51 reg = <80 80>; 51 reg = <0x80 0x80>;
52 }; 52 };
53 dma-channel@100 { 53 dma-channel@100 {
54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 54 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
55 cell-index = <2>; 55 cell-index = <2>;
56 reg = <100 80>; 56 reg = <0x100 0x80>;
57 }; 57 };
58 dma-channel@180 { 58 dma-channel@180 {
59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; 59 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
60 cell-index = <3>; 60 cell-index = <3>;
61 reg = <180 80>; 61 reg = <0x180 0x80>;
62 }; 62 };
63 }; 63 };
64 64
@@ -93,36 +93,36 @@ Example:
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <1>; 94 #size-cells = <1>;
95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 95 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
96 reg = <21300 4>; 96 reg = <0x21300 4>;
97 ranges = <0 21100 200>; 97 ranges = <0 0x21100 0x200>;
98 cell-index = <0>; 98 cell-index = <0>;
99 dma-channel@0 { 99 dma-channel@0 {
100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 100 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
101 reg = <0 80>; 101 reg = <0 0x80>;
102 cell-index = <0>; 102 cell-index = <0>;
103 interrupt-parent = <&mpic>; 103 interrupt-parent = <&mpic>;
104 interrupts = <14 2>; 104 interrupts = <20 2>;
105 }; 105 };
106 dma-channel@80 { 106 dma-channel@80 {
107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 107 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
108 reg = <80 80>; 108 reg = <0x80 0x80>;
109 cell-index = <1>; 109 cell-index = <1>;
110 interrupt-parent = <&mpic>; 110 interrupt-parent = <&mpic>;
111 interrupts = <15 2>; 111 interrupts = <21 2>;
112 }; 112 };
113 dma-channel@100 { 113 dma-channel@100 {
114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 114 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
115 reg = <100 80>; 115 reg = <0x100 0x80>;
116 cell-index = <2>; 116 cell-index = <2>;
117 interrupt-parent = <&mpic>; 117 interrupt-parent = <&mpic>;
118 interrupts = <16 2>; 118 interrupts = <22 2>;
119 }; 119 };
120 dma-channel@180 { 120 dma-channel@180 {
121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; 121 compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
122 reg = <180 80>; 122 reg = <0x180 0x80>;
123 cell-index = <3>; 123 cell-index = <3>;
124 interrupt-parent = <&mpic>; 124 interrupt-parent = <&mpic>;
125 interrupts = <17 2>; 125 interrupts = <23 2>;
126 }; 126 };
127 }; 127 };
128 128
diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
new file mode 100644
index 000000000000..600846557763
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
@@ -0,0 +1,24 @@
1* Freescale Enhanced Secure Digital Host Controller (eSDHC)
2
3The Enhanced Secure Digital Host Controller provides an interface
4for MMC, SD, and SDIO types of memory cards.
5
6Required properties:
7 - compatible : should be
8 "fsl,<chip>-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors.
9 "fsl,<chip>-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors.
10 - reg : should contain eSDHC registers location and length.
11 - interrupts : should contain eSDHC interrupt.
12 - interrupt-parent : interrupt source phandle.
13 - clock-frequency : specifies eSDHC base clock frequency.
14
15Example:
16
17sdhci@2e000 {
18 compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc";
19 reg = <0x2e000 0x1000>;
20 interrupts = <42 0x8>;
21 interrupt-parent = <&ipic>;
22 /* Filled in by U-Boot */
23 clock-frequency = <0>;
24};
diff --git a/Documentation/powerpc/dts-bindings/fsl/ssi.txt b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
index a2d963998a65..5ff76c9c57d2 100644
--- a/Documentation/powerpc/dts-bindings/fsl/ssi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/ssi.txt
@@ -4,44 +4,56 @@ The SSI is a serial device that communicates with audio codecs. It can
4be programmed in AC97, I2S, left-justified, or right-justified modes. 4be programmed in AC97, I2S, left-justified, or right-justified modes.
5 5
6Required properties: 6Required properties:
7- compatible : compatible list, containing "fsl,ssi" 7- compatible: Compatible list, contains "fsl,ssi".
8- cell-index : the SSI, <0> = SSI1, <1> = SSI2, and so on 8- cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
9- reg : offset and length of the register set for the device 9- reg: Offset and length of the register set for the device.
10- interrupts : <a b> where a is the interrupt number and b is a 10- interrupts: <a b> where a is the interrupt number and b is a
11 field that represents an encoding of the sense and 11 field that represents an encoding of the sense and
12 level information for the interrupt. This should be 12 level information for the interrupt. This should be
13 encoded based on the information in section 2) 13 encoded based on the information in section 2)
14 depending on the type of interrupt controller you 14 depending on the type of interrupt controller you
15 have. 15 have.
16- interrupt-parent : the phandle for the interrupt controller that 16- interrupt-parent: The phandle for the interrupt controller that
17 services interrupts for this device. 17 services interrupts for this device.
18- fsl,mode : the operating mode for the SSI interface 18- fsl,mode: The operating mode for the SSI interface.
19 "i2s-slave" - I2S mode, SSI is clock slave 19 "i2s-slave" - I2S mode, SSI is clock slave
20 "i2s-master" - I2S mode, SSI is clock master 20 "i2s-master" - I2S mode, SSI is clock master
21 "lj-slave" - left-justified mode, SSI is clock slave 21 "lj-slave" - left-justified mode, SSI is clock slave
22 "lj-master" - l.j. mode, SSI is clock master 22 "lj-master" - l.j. mode, SSI is clock master
23 "rj-slave" - right-justified mode, SSI is clock slave 23 "rj-slave" - right-justified mode, SSI is clock slave
24 "rj-master" - r.j., SSI is clock master 24 "rj-master" - r.j., SSI is clock master
25 "ac97-slave" - AC97 mode, SSI is clock slave 25 "ac97-slave" - AC97 mode, SSI is clock slave
26 "ac97-master" - AC97 mode, SSI is clock master 26 "ac97-master" - AC97 mode, SSI is clock master
27- fsl,playback-dma: phandle to a node for the DMA channel to use for 27- fsl,playback-dma: Phandle to a node for the DMA channel to use for
28 playback of audio. This is typically dictated by SOC 28 playback of audio. This is typically dictated by SOC
29 design. See the notes below. 29 design. See the notes below.
30- fsl,capture-dma: phandle to a node for the DMA channel to use for 30- fsl,capture-dma: Phandle to a node for the DMA channel to use for
31 capture (recording) of audio. This is typically dictated 31 capture (recording) of audio. This is typically dictated
32 by SOC design. See the notes below. 32 by SOC design. See the notes below.
33- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
34 This number is the maximum allowed value for SFCSR[TFWM0].
35- fsl,ssi-asynchronous:
36 If specified, the SSI is to be programmed in asynchronous
37 mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
38 all be connected to valid signals. In synchronous mode,
39 SRCK and SRFS are ignored. Asynchronous mode allows
40 playback and capture to use different sample sizes and
41 sample rates. Some drivers may require that SRCK and STCK
42 be connected together, and SRFS and STFS be connected
43 together. This would still allow different sample sizes,
44 but not different sample rates.
33 45
34Optional properties: 46Optional properties:
35- codec-handle : phandle to a 'codec' node that defines an audio 47- codec-handle: Phandle to a 'codec' node that defines an audio
36 codec connected to this SSI. This node is typically 48 codec connected to this SSI. This node is typically
37 a child of an I2C or other control node. 49 a child of an I2C or other control node.
38 50
39Child 'codec' node required properties: 51Child 'codec' node required properties:
40- compatible : compatible list, contains the name of the codec 52- compatible: Compatible list, contains the name of the codec
41 53
42Child 'codec' node optional properties: 54Child 'codec' node optional properties:
43- clock-frequency : The frequency of the input clock, which typically 55- clock-frequency: The frequency of the input clock, which typically comes
44 comes from an on-board dedicated oscillator. 56 from an on-board dedicated oscillator.
45 57
46Notes on fsl,playback-dma and fsl,capture-dma: 58Notes on fsl,playback-dma and fsl,capture-dma:
47 59
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-24 23:29:44 -0400