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1 | ===================================================================== | ||
2 | SEC 4 Device Tree Binding | ||
3 | Copyright (C) 2008-2011 Freescale Semiconductor Inc. | ||
4 | |||
5 | CONTENTS | ||
6 | -Overview | ||
7 | -SEC 4 Node | ||
8 | -Job Ring Node | ||
9 | -Run Time Integrity Check (RTIC) Node | ||
10 | -Run Time Integrity Check (RTIC) Memory Node | ||
11 | -Secure Non-Volatile Storage (SNVS) Node | ||
12 | -Full Example | ||
13 | |||
14 | NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator | ||
15 | Accelerator and Assurance Module (CAAM). | ||
16 | |||
17 | ===================================================================== | ||
18 | Overview | ||
19 | |||
20 | DESCRIPTION | ||
21 | |||
22 | SEC 4 h/w can process requests from 2 types of sources. | ||
23 | 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4). | ||
24 | 2. Job Rings (HW interface between cores & SEC 4 registers). | ||
25 | |||
26 | High Speed Data Path Configuration: | ||
27 | |||
28 | HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts | ||
29 | such as the P4080. The number of simultaneous dequeues the QI can make is | ||
30 | equal to the number of Descriptor Controller (DECO) engines in a particular | ||
31 | SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus | ||
32 | dequeue from 5 subportals simultaneously. | ||
33 | |||
34 | Job Ring Data Path Configuration: | ||
35 | |||
36 | Each JR is located on a separate 4k page, they may (or may not) be made visible | ||
37 | in the memory partition devoted to a particular core. The P4080 has 4 JRs, so | ||
38 | up to 4 JRs can be configured; and all 4 JRs process requests in parallel. | ||
39 | |||
40 | ===================================================================== | ||
41 | P4080 SEC 4 Node | ||
42 | |||
43 | Description | ||
44 | |||
45 | Node defines the base address of the SEC 4 block. | ||
46 | This block specifies the address range of all global | ||
47 | configuration registers for the SEC 4 block. It | ||
48 | also receives interrupts from the Run Time Integrity Check | ||
49 | (RTIC) function within the SEC 4 block. | ||
50 | |||
51 | PROPERTIES | ||
52 | |||
53 | - compatible | ||
54 | Usage: required | ||
55 | Value type: <string> | ||
56 | Definition: Must include "fsl,p4080-sec4.0","fsl,sec-4.0" | ||
57 | |||
58 | - #address-cells | ||
59 | Usage: required | ||
60 | Value type: <u32> | ||
61 | Definition: A standard property. Defines the number of cells | ||
62 | for representing physical addresses in child nodes. | ||
63 | |||
64 | - #size-cells | ||
65 | Usage: required | ||
66 | Value type: <u32> | ||
67 | Definition: A standard property. Defines the number of cells | ||
68 | for representing the size of physical addresses in | ||
69 | child nodes. | ||
70 | |||
71 | - reg | ||
72 | Usage: required | ||
73 | Value type: <prop-encoded-array> | ||
74 | Definition: A standard property. Specifies the physical | ||
75 | address and length of the SEC4.0 configuration registers. | ||
76 | registers | ||
77 | |||
78 | - ranges | ||
79 | Usage: required | ||
80 | Value type: <prop-encoded-array> | ||
81 | Definition: A standard property. Specifies the physical address | ||
82 | range of the SEC 4.0 register space (-SNVS not included). A | ||
83 | triplet that includes the child address, parent address, & | ||
84 | length. | ||
85 | |||
86 | - interrupts | ||
87 | Usage: required | ||
88 | Value type: <prop_encoded-array> | ||
89 | Definition: Specifies the interrupts generated by this | ||
90 | device. The value of the interrupts property | ||
91 | consists of one interrupt specifier. The format | ||
92 | of the specifier is defined by the binding document | ||
93 | describing the node's interrupt parent. | ||
94 | |||
95 | - interrupt-parent | ||
96 | Usage: (required if interrupt property is defined) | ||
97 | Value type: <phandle> | ||
98 | Definition: A single <phandle> value that points | ||
99 | to the interrupt parent to which the child domain | ||
100 | is being mapped. | ||
101 | |||
102 | Note: All other standard properties (see the ePAPR) are allowed | ||
103 | but are optional. | ||
104 | |||
105 | |||
106 | EXAMPLE | ||
107 | crypto@300000 { | ||
108 | compatible = "fsl,p4080-sec4.0", "fsl,sec4.0"; | ||
109 | #address-cells = <1>; | ||
110 | #size-cells = <1>; | ||
111 | reg = <0x300000 0x10000>; | ||
112 | ranges = <0 0x300000 0x10000>; | ||
113 | interrupt-parent = <&mpic>; | ||
114 | interrupts = <92 2>; | ||
115 | }; | ||
116 | |||
117 | ===================================================================== | ||
118 | P4080 Job Ring (JR) Node | ||
119 | |||
120 | Child of the crypto node defines data processing interface to SEC 4 | ||
121 | across the peripheral bus for purposes of processing | ||
122 | cryptographic descriptors. The specified address | ||
123 | range can be made visible to one (or more) cores. | ||
124 | The interrupt defined for this node is controlled within | ||
125 | the address range of this node. | ||
126 | |||
127 | - compatible | ||
128 | Usage: required | ||
129 | Value type: <string> | ||
130 | Definition: Must include "fsl,p4080-sec4.0-job-ring","fsl,sec4.0-job-ring" | ||
131 | |||
132 | - reg | ||
133 | Usage: required | ||
134 | Value type: <prop-encoded-array> | ||
135 | Definition: Specifies a two JR parameters: an offset from | ||
136 | the parent physical address and the length the JR registers. | ||
137 | |||
138 | - fsl,liodn | ||
139 | Usage: optional-but-recommended | ||
140 | Value type: <prop-encoded-array> | ||
141 | Definition: | ||
142 | Specifies the LIODN to be used in conjunction with | ||
143 | the ppid-to-liodn table that specifies the PPID to LIODN mapping. | ||
144 | Needed if the PAMU is used. Value is a 12 bit value | ||
145 | where value is a LIODN ID for this JR. This property is | ||
146 | normally set by boot firmware. | ||
147 | |||
148 | - interrupts | ||
149 | Usage: required | ||
150 | Value type: <prop_encoded-array> | ||
151 | Definition: Specifies the interrupts generated by this | ||
152 | device. The value of the interrupts property | ||
153 | consists of one interrupt specifier. The format | ||
154 | of the specifier is defined by the binding document | ||
155 | describing the node's interrupt parent. | ||
156 | |||
157 | - interrupt-parent | ||
158 | Usage: (required if interrupt property is defined) | ||
159 | Value type: <phandle> | ||
160 | Definition: A single <phandle> value that points | ||
161 | to the interrupt parent to which the child domain | ||
162 | is being mapped. | ||
163 | |||
164 | EXAMPLE | ||
165 | jr@1000 { | ||
166 | compatible = "fsl,p4080-sec4.0-job-ring", | ||
167 | "fsl,sec4.0-job-ring"; | ||
168 | reg = <0x1000 0x1000>; | ||
169 | fsl,liodn = <0x081>; | ||
170 | interrupt-parent = <&mpic>; | ||
171 | interrupts = <88 2>; | ||
172 | }; | ||
173 | |||
174 | |||
175 | ===================================================================== | ||
176 | P4080 Run Time Integrity Check (RTIC) Node | ||
177 | |||
178 | Child node of the crypto node. Defines a register space that | ||
179 | contains up to 5 sets of addresses and their lengths (sizes) that | ||
180 | will be checked at run time. After an initial hash result is | ||
181 | calculated, these addresses are checked by HW to monitor any | ||
182 | change. If any memory is modified, a Security Violation is | ||
183 | triggered (see SNVS definition). | ||
184 | |||
185 | |||
186 | - compatible | ||
187 | Usage: required | ||
188 | Value type: <string> | ||
189 | Definition: Must include "fsl,p4080-sec4.0-rtic","fsl,sec4.0-rtic". | ||
190 | |||
191 | - #address-cells | ||
192 | Usage: required | ||
193 | Value type: <u32> | ||
194 | Definition: A standard property. Defines the number of cells | ||
195 | for representing physical addresses in child nodes. Must | ||
196 | have a value of 1. | ||
197 | |||
198 | - #size-cells | ||
199 | Usage: required | ||
200 | Value type: <u32> | ||
201 | Definition: A standard property. Defines the number of cells | ||
202 | for representing the size of physical addresses in | ||
203 | child nodes. Must have a value of 1. | ||
204 | |||
205 | - reg | ||
206 | Usage: required | ||
207 | Value type: <prop-encoded-array> | ||
208 | Definition: A standard property. Specifies a two parameters: | ||
209 | an offset from the parent physical address and the length | ||
210 | the SEC4 registers. | ||
211 | |||
212 | - ranges | ||
213 | Usage: required | ||
214 | Value type: <prop-encoded-array> | ||
215 | Definition: A standard property. Specifies the physical address | ||
216 | range of the SEC 4 register space (-SNVS not included). A | ||
217 | triplet that includes the child address, parent address, & | ||
218 | length. | ||
219 | |||
220 | EXAMPLE | ||
221 | rtic@6000 { | ||
222 | compatible = "fsl,p4080-sec4.0-rtic", | ||
223 | "fsl,sec4.0-rtic"; | ||
224 | #address-cells = <1>; | ||
225 | #size-cells = <1>; | ||
226 | reg = <0x6000 0x100>; | ||
227 | ranges = <0x0 0x6100 0xe00>; | ||
228 | }; | ||
229 | |||
230 | ===================================================================== | ||
231 | P4080 Run Time Integrity Check (RTIC) Memory Node | ||
232 | A child node that defines individual RTIC memory regions that are used to | ||
233 | perform run-time integrity check of memory areas that should not modified. | ||
234 | The node defines a register that contains the memory address & | ||
235 | length (combined) and a second register that contains the hash result | ||
236 | in big endian format. | ||
237 | |||
238 | - compatible | ||
239 | Usage: required | ||
240 | Value type: <string> | ||
241 | Definition: Must include "fsl,p4080-sec4.0-rtic-memory","fsl,sec4.0-rtic-memory". | ||
242 | |||
243 | - reg | ||
244 | Usage: required | ||
245 | Value type: <prop-encoded-array> | ||
246 | Definition: A standard property. Specifies two parameters: | ||
247 | an offset from the parent physical address and the length: | ||
248 | |||
249 | 1. The location of the RTIC memory address & length registers. | ||
250 | 2. The location RTIC hash result. | ||
251 | |||
252 | - fsl,rtic-region | ||
253 | Usage: optional-but-recommended | ||
254 | Value type: <prop-encoded-array> | ||
255 | Definition: | ||
256 | Specifies the HW address (36 bit address) for this region | ||
257 | followed by the length of the HW partition to be checked; | ||
258 | the address is represented as a 64 bit quantity followed | ||
259 | by a 32 bit length. | ||
260 | |||
261 | - fsl,liodn | ||
262 | Usage: optional-but-recommended | ||
263 | Value type: <prop-encoded-array> | ||
264 | Definition: | ||
265 | Specifies the LIODN to be used in conjunction with | ||
266 | the ppid-to-liodn table that specifies the PPID to LIODN | ||
267 | mapping. Needed if the PAMU is used. Value is a 12 bit value | ||
268 | where value is a LIODN ID for this RTIC memory region. This | ||
269 | property is normally set by boot firmware. | ||
270 | |||
271 | EXAMPLE | ||
272 | rtic-a@0 { | ||
273 | compatible = "fsl,p4080-sec4.0-rtic-memory", | ||
274 | "fsl,sec4.0-rtic-memory"; | ||
275 | reg = <0x00 0x20 0x100 0x80>; | ||
276 | fsl,liodn = <0x03c>; | ||
277 | fsl,rtic-region = <0x12345678 0x12345678 0x12345678>; | ||
278 | }; | ||
279 | |||
280 | ===================================================================== | ||
281 | P4080 Secure Non-Volatile Storage (SNVS) Node | ||
282 | |||
283 | Node defines address range and the associated | ||
284 | interrupt for the SNVS function. This function | ||
285 | monitors security state information & reports | ||
286 | security violations. | ||
287 | |||
288 | - compatible | ||
289 | Usage: required | ||
290 | Value type: <string> | ||
291 | Definition: Must include "fsl,p4080-sec4.0-mon", "fsl,sec4.0-mon". | ||
292 | |||
293 | - reg | ||
294 | Usage: required | ||
295 | Value type: <prop-encoded-array> | ||
296 | Definition: A standard property. Specifies the physical | ||
297 | address and length of the SEC4 configuration | ||
298 | registers. | ||
299 | |||
300 | - interrupts | ||
301 | Usage: required | ||
302 | Value type: <prop_encoded-array> | ||
303 | Definition: Specifies the interrupts generated by this | ||
304 | device. The value of the interrupts property | ||
305 | consists of one interrupt specifier. The format | ||
306 | of the specifier is defined by the binding document | ||
307 | describing the node's interrupt parent. | ||
308 | |||
309 | - interrupt-parent | ||
310 | Usage: (required if interrupt property is defined) | ||
311 | Value type: <phandle> | ||
312 | Definition: A single <phandle> value that points | ||
313 | to the interrupt parent to which the child domain | ||
314 | is being mapped. | ||
315 | |||
316 | EXAMPLE | ||
317 | sec_mon@314000 { | ||
318 | compatible = "fsl,p4080-sec4.0-mon", "fsl,sec4.0-mon"; | ||
319 | reg = <0x314000 0x1000>; | ||
320 | interrupt-parent = <&mpic>; | ||
321 | interrupts = <93 2>; | ||
322 | }; | ||
323 | |||
324 | ===================================================================== | ||
325 | FULL EXAMPLE | ||
326 | |||
327 | crypto: crypto@300000 { | ||
328 | compatible = "fsl,p4080-sec4.0", "fsl,sec4.0"; | ||
329 | #address-cells = <1>; | ||
330 | #size-cells = <1>; | ||
331 | reg = <0x300000 0x10000>; | ||
332 | ranges = <0 0x300000 0x10000>; | ||
333 | interrupt-parent = <&mpic>; | ||
334 | interrupts = <92 2>; | ||
335 | |||
336 | sec_jr0: jr@1000 { | ||
337 | compatible = "fsl,p4080-sec4.0-job-ring", | ||
338 | "fsl,sec4.0-job-ring"; | ||
339 | reg = <0x1000 0x1000>; | ||
340 | interrupt-parent = <&mpic>; | ||
341 | interrupts = <88 2>; | ||
342 | }; | ||
343 | |||
344 | sec_jr1: jr@2000 { | ||
345 | compatible = "fsl,p4080-sec4.0-job-ring", | ||
346 | "fsl,sec4.0-job-ring"; | ||
347 | reg = <0x2000 0x1000>; | ||
348 | interrupt-parent = <&mpic>; | ||
349 | interrupts = <89 2>; | ||
350 | }; | ||
351 | |||
352 | sec_jr2: jr@3000 { | ||
353 | compatible = "fsl,p4080-sec4.0-job-ring", | ||
354 | "fsl,sec4.0-job-ring"; | ||
355 | reg = <0x3000 0x1000>; | ||
356 | interrupt-parent = <&mpic>; | ||
357 | interrupts = <90 2>; | ||
358 | }; | ||
359 | |||
360 | sec_jr3: jr@4000 { | ||
361 | compatible = "fsl,p4080-sec4.0-job-ring", | ||
362 | "fsl,sec4.0-job-ring"; | ||
363 | reg = <0x4000 0x1000>; | ||
364 | interrupt-parent = <&mpic>; | ||
365 | interrupts = <91 2>; | ||
366 | }; | ||
367 | |||
368 | rtic@6000 { | ||
369 | compatible = "fsl,p4080-sec4.0-rtic", | ||
370 | "fsl,sec4.0-rtic"; | ||
371 | #address-cells = <1>; | ||
372 | #size-cells = <1>; | ||
373 | reg = <0x6000 0x100>; | ||
374 | ranges = <0x0 0x6100 0xe00>; | ||
375 | |||
376 | rtic_a: rtic-a@0 { | ||
377 | compatible = "fsl,p4080-sec4.0-rtic-memory", | ||
378 | "fsl,sec4.0-rtic-memory"; | ||
379 | reg = <0x00 0x20 0x100 0x80>; | ||
380 | }; | ||
381 | |||
382 | rtic_b: rtic-b@20 { | ||
383 | compatible = "fsl,p4080-sec4.0-rtic-memory", | ||
384 | "fsl,sec4.0-rtic-memory"; | ||
385 | reg = <0x20 0x20 0x200 0x80>; | ||
386 | }; | ||
387 | |||
388 | rtic_c: rtic-c@40 { | ||
389 | compatible = "fsl,p4080-sec4.0-rtic-memory", | ||
390 | "fsl,sec4.0-rtic-memory"; | ||
391 | reg = <0x40 0x20 0x300 0x80>; | ||
392 | }; | ||
393 | |||
394 | rtic_d: rtic-d@60 { | ||
395 | compatible = "fsl,p4080-sec4.0-rtic-memory", | ||
396 | "fsl,sec4.0-rtic-memory"; | ||
397 | reg = <0x60 0x20 0x500 0x80>; | ||
398 | }; | ||
399 | }; | ||
400 | }; | ||
401 | |||
402 | sec_mon: sec_mon@314000 { | ||
403 | compatible = "fsl,p4080-sec4.0-mon", "fsl,sec4.0-mon"; | ||
404 | reg = <0x314000 0x1000>; | ||
405 | interrupt-parent = <&mpic>; | ||
406 | interrupts = <93 2>; | ||
407 | }; | ||
408 | |||
409 | ===================================================================== | ||