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-rw-r--r--Documentation/devicetree/bindings/arm/mrvl/intc.txt20
-rw-r--r--Documentation/devicetree/bindings/gpio/mrvl-gpio.txt23
2 files changed, 43 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mrvl/intc.txt b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
index 80b9a94d9a23..8b53273cb22f 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/intc.txt
+++ b/Documentation/devicetree/bindings/arm/mrvl/intc.txt
@@ -38,3 +38,23 @@ Example:
38 reg-names = "mux status", "mux mask"; 38 reg-names = "mux status", "mux mask";
39 mrvl,intc-nr-irqs = <2>; 39 mrvl,intc-nr-irqs = <2>;
40 }; 40 };
41
42* Marvell Orion Interrupt controller
43
44Required properties
45- compatible : Should be "marvell,orion-intc".
46- #interrupt-cells: Specifies the number of cells needed to encode an
47 interrupt source. Supported value is <1>.
48- interrupt-controller : Declare this node to be an interrupt controller.
49- reg : Interrupt mask address. A list of 4 byte ranges, one per controller.
50 One entry in the list represents 32 interrupts.
51
52Example:
53
54 intc: interrupt-controller {
55 compatible = "marvell,orion-intc", "marvell,intc";
56 interrupt-controller;
57 #interrupt-cells = <1>;
58 reg = <0xfed20204 0x04>,
59 <0xfed20214 0x04>;
60 };
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 05428f39d9ac..e13787498bcf 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -27,3 +27,26 @@ Example:
27 interrupt-controller; 27 interrupt-controller;
28 #interrupt-cells = <1>; 28 #interrupt-cells = <1>;
29 }; 29 };
30
31* Marvell Orion GPIO Controller
32
33Required properties:
34- compatible : Should be "marvell,orion-gpio"
35- reg : Address and length of the register set for controller.
36- gpio-controller : So we know this is a gpio controller.
37- ngpio : How many gpios this controller has.
38- interrupts : Up to 4 Interrupts for the controller.
39
40Optional properties:
41- mask-offset : For SMP Orions, offset for Nth CPU
42
43Example:
44
45 gpio0: gpio@10100 {
46 compatible = "marvell,orion-gpio";
47 #gpio-cells = <2>;
48 gpio-controller;
49 reg = <0x10100 0x40>;
50 ngpio = <32>;
51 interrupts = <35>, <36>, <37>, <38>;
52 };