aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/powerpc/dts-bindings
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation/powerpc/dts-bindings')
-rw-r--r--Documentation/powerpc/dts-bindings/4xx/emac.txt148
-rw-r--r--Documentation/powerpc/dts-bindings/gpio/gpio.txt50
-rw-r--r--Documentation/powerpc/dts-bindings/gpio/mdio.txt19
-rw-r--r--Documentation/powerpc/dts-bindings/marvell.txt521
-rw-r--r--Documentation/powerpc/dts-bindings/phy.txt25
-rw-r--r--Documentation/powerpc/dts-bindings/spi-bus.txt57
-rw-r--r--Documentation/powerpc/dts-bindings/usb-ehci.txt25
-rw-r--r--Documentation/powerpc/dts-bindings/xilinx.txt295
8 files changed, 1140 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/4xx/emac.txt b/Documentation/powerpc/dts-bindings/4xx/emac.txt
new file mode 100644
index 000000000000..2161334a7ca5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/4xx/emac.txt
@@ -0,0 +1,148 @@
1 4xx/Axon EMAC ethernet nodes
2
3 The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
4 the Axon bridge. To operate this needs to interact with a ths
5 special McMAL DMA controller, and sometimes an RGMII or ZMII
6 interface. In addition to the nodes and properties described
7 below, the node for the OPB bus on which the EMAC sits must have a
8 correct clock-frequency property.
9
10 i) The EMAC node itself
11
12 Required properties:
13 - device_type : "network"
14
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
17 405gp, Axon) and second is either "ibm,emac" or
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
19 "ibm,emac4"
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - interrupt-parent : optional, if needed for interrupt mapping
22 - reg : <registers mapping>
23 - local-mac-address : 6 bytes, MAC address
24 - mal-device : phandle of the associated McMAL node
25 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
26 with this EMAC
27 - mal-rx-channel : 1 cell, index of the rx channel on McMAL associated
28 with this EMAC
29 - cell-index : 1 cell, hardware index of the EMAC cell on a given
30 ASIC (typically 0x0 and 0x1 for EMAC0 and EMAC1 on
31 each Axon chip)
32 - max-frame-size : 1 cell, maximum frame size supported in bytes
33 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
34 operations.
35 For Axon, 2048
36 - tx-fifo-size : 1 cell, Tx fifo size in bytes for 10 and 100 Mb/sec
37 operations.
38 For Axon, 2048.
39 - fifo-entry-size : 1 cell, size of a fifo entry (used to calculate
40 thresholds).
41 For Axon, 0x00000010
42 - mal-burst-size : 1 cell, MAL burst size (used to calculate thresholds)
43 in bytes.
44 For Axon, 0x00000100 (I think ...)
45 - phy-mode : string, mode of operations of the PHY interface.
46 Supported values are: "mii", "rmii", "smii", "rgmii",
47 "tbi", "gmii", rtbi", "sgmii".
48 For Axon on CAB, it is "rgmii"
49 - mdio-device : 1 cell, required iff using shared MDIO registers
50 (440EP). phandle of the EMAC to use to drive the
51 MDIO lines for the PHY used by this EMAC.
52 - zmii-device : 1 cell, required iff connected to a ZMII. phandle of
53 the ZMII device node
54 - zmii-channel : 1 cell, required iff connected to a ZMII. Which ZMII
55 channel or 0xffffffff if ZMII is only used for MDIO.
56 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
57 of the RGMII device node.
58 For Axon: phandle of plb5/plb4/opb/rgmii
59 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
60 RGMII channel is used by this EMAC.
61 Fox Axon: present, whatever value is appropriate for each
62 EMAC, that is the content of the current (bogus) "phy-port"
63 property.
64
65 Optional properties:
66 - phy-address : 1 cell, optional, MDIO address of the PHY. If absent,
67 a search is performed.
68 - phy-map : 1 cell, optional, bitmap of addresses to probe the PHY
69 for, used if phy-address is absent. bit 0x00000001 is
70 MDIO address 0.
71 For Axon it can be absent, though my current driver
72 doesn't handle phy-address yet so for now, keep
73 0x00ffffff in it.
74 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
75 operations (if absent the value is the same as
76 rx-fifo-size). For Axon, either absent or 2048.
77 - tx-fifo-size-gige : 1 cell, Tx fifo size in bytes for 1000 Mb/sec
78 operations (if absent the value is the same as
79 tx-fifo-size). For Axon, either absent or 2048.
80 - tah-device : 1 cell, optional. If connected to a TAH engine for
81 offload, phandle of the TAH device node.
82 - tah-channel : 1 cell, optional. If appropriate, channel used on the
83 TAH engine.
84
85 Example:
86
87 EMAC0: ethernet@40000800 {
88 device_type = "network";
89 compatible = "ibm,emac-440gp", "ibm,emac";
90 interrupt-parent = <&UIC1>;
91 interrupts = <1c 4 1d 4>;
92 reg = <40000800 70>;
93 local-mac-address = [00 04 AC E3 1B 1E];
94 mal-device = <&MAL0>;
95 mal-tx-channel = <0 1>;
96 mal-rx-channel = <0>;
97 cell-index = <0>;
98 max-frame-size = <5dc>;
99 rx-fifo-size = <1000>;
100 tx-fifo-size = <800>;
101 phy-mode = "rmii";
102 phy-map = <00000001>;
103 zmii-device = <&ZMII0>;
104 zmii-channel = <0>;
105 };
106
107 ii) McMAL node
108
109 Required properties:
110 - device_type : "dma-controller"
111 - compatible : compatible list, containing 2 entries, first is
112 "ibm,mcmal-CHIP" where CHIP is the host ASIC (like
113 emac) and the second is either "ibm,mcmal" or
114 "ibm,mcmal2".
115 For Axon, "ibm,mcmal-axon","ibm,mcmal2"
116 - interrupts : <interrupt mapping for the MAL interrupts sources:
117 5 sources: tx_eob, rx_eob, serr, txde, rxde>.
118 For Axon: This is _different_ from the current
119 firmware. We use the "delayed" interrupts for txeob
120 and rxeob. Thus we end up with mapping those 5 MPIC
121 interrupts, all level positive sensitive: 10, 11, 32,
122 33, 34 (in decimal)
123 - dcr-reg : < DCR registers range >
124 - dcr-parent : if needed for dcr-reg
125 - num-tx-chans : 1 cell, number of Tx channels
126 - num-rx-chans : 1 cell, number of Rx channels
127
128 iii) ZMII node
129
130 Required properties:
131 - compatible : compatible list, containing 2 entries, first is
132 "ibm,zmii-CHIP" where CHIP is the host ASIC (like
133 EMAC) and the second is "ibm,zmii".
134 For Axon, there is no ZMII node.
135 - reg : <registers mapping>
136
137 iv) RGMII node
138
139 Required properties:
140 - compatible : compatible list, containing 2 entries, first is
141 "ibm,rgmii-CHIP" where CHIP is the host ASIC (like
142 EMAC) and the second is "ibm,rgmii".
143 For Axon, "ibm,rgmii-axon","ibm,rgmii"
144 - reg : <registers mapping>
145 - revision : as provided by the RGMII new version register if
146 available.
147 For Axon: 0x0000012a
148
diff --git a/Documentation/powerpc/dts-bindings/gpio/gpio.txt b/Documentation/powerpc/dts-bindings/gpio/gpio.txt
new file mode 100644
index 000000000000..edaa84d288a1
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/gpio/gpio.txt
@@ -0,0 +1,50 @@
1Specifying GPIO information for devices
2============================================
3
41) gpios property
5-----------------
6
7Nodes that makes use of GPIOs should define them using `gpios' property,
8format of which is: <&gpio-controller1-phandle gpio1-specifier
9 &gpio-controller2-phandle gpio2-specifier
10 0 /* holes are permitted, means no GPIO 3 */
11 &gpio-controller4-phandle gpio4-specifier
12 ...>;
13
14Note that gpio-specifier length is controller dependent.
15
16gpio-specifier may encode: bank, pin position inside the bank,
17whether pin is open-drain and whether pin is logically inverted.
18
19Example of the node using GPIOs:
20
21 node {
22 gpios = <&qe_pio_e 18 0>;
23 };
24
25In this example gpio-specifier is "18 0" and encodes GPIO pin number,
26and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
27
282) gpio-controller nodes
29------------------------
30
31Every GPIO controller node must have #gpio-cells property defined,
32this information will be used to translate gpio-specifiers.
33
34Example of two SOC GPIO banks defined as gpio-controller nodes:
35
36 qe_pio_a: gpio-controller@1400 {
37 #gpio-cells = <2>;
38 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
39 reg = <0x1400 0x18>;
40 gpio-controller;
41 };
42
43 qe_pio_e: gpio-controller@1460 {
44 #gpio-cells = <2>;
45 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
46 reg = <0x1460 0x18>;
47 gpio-controller;
48 };
49
50
diff --git a/Documentation/powerpc/dts-bindings/gpio/mdio.txt b/Documentation/powerpc/dts-bindings/gpio/mdio.txt
new file mode 100644
index 000000000000..bc9549529014
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/gpio/mdio.txt
@@ -0,0 +1,19 @@
1MDIO on GPIOs
2
3Currently defined compatibles:
4- virtual,gpio-mdio
5
6MDC and MDIO lines connected to GPIO controllers are listed in the
7gpios property as described in section VIII.1 in the following order:
8
9MDC, MDIO.
10
11Example:
12
13mdio {
14 compatible = "virtual,mdio-gpio";
15 #address-cells = <1>;
16 #size-cells = <0>;
17 gpios = <&qe_pio_a 11
18 &qe_pio_c 6>;
19};
diff --git a/Documentation/powerpc/dts-bindings/marvell.txt b/Documentation/powerpc/dts-bindings/marvell.txt
new file mode 100644
index 000000000000..3708a2fd4747
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/marvell.txt
@@ -0,0 +1,521 @@
1Marvell Discovery mv64[345]6x System Controller chips
2===========================================================
3
4The Marvell mv64[345]60 series of system controller chips contain
5many of the peripherals needed to implement a complete computer
6system. In this section, we define device tree nodes to describe
7the system controller chip itself and each of the peripherals
8which it contains. Compatible string values for each node are
9prefixed with the string "marvell,", for Marvell Technology Group Ltd.
10
111) The /system-controller node
12
13 This node is used to represent the system-controller and must be
14 present when the system uses a system controller chip. The top-level
15 system-controller node contains information that is global to all
16 devices within the system controller chip. The node name begins
17 with "system-controller" followed by the unit address, which is
18 the base address of the memory-mapped register set for the system
19 controller chip.
20
21 Required properties:
22
23 - ranges : Describes the translation of system controller addresses
24 for memory mapped registers.
25 - clock-frequency: Contains the main clock frequency for the system
26 controller chip.
27 - reg : This property defines the address and size of the
28 memory-mapped registers contained within the system controller
29 chip. The address specified in the "reg" property should match
30 the unit address of the system-controller node.
31 - #address-cells : Address representation for system controller
32 devices. This field represents the number of cells needed to
33 represent the address of the memory-mapped registers of devices
34 within the system controller chip.
35 - #size-cells : Size representation for for the memory-mapped
36 registers within the system controller chip.
37 - #interrupt-cells : Defines the width of cells used to represent
38 interrupts.
39
40 Optional properties:
41
42 - model : The specific model of the system controller chip. Such
43 as, "mv64360", "mv64460", or "mv64560".
44 - compatible : A string identifying the compatibility identifiers
45 of the system controller chip.
46
47 The system-controller node contains child nodes for each system
48 controller device that the platform uses. Nodes should not be created
49 for devices which exist on the system controller chip but are not used
50
51 Example Marvell Discovery mv64360 system-controller node:
52
53 system-controller@f1000000 { /* Marvell Discovery mv64360 */
54 #address-cells = <1>;
55 #size-cells = <1>;
56 model = "mv64360"; /* Default */
57 compatible = "marvell,mv64360";
58 clock-frequency = <133333333>;
59 reg = <0xf1000000 0x10000>;
60 virtual-reg = <0xf1000000>;
61 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */
62 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */
63 0xa0000000 0xa0000000 0x4000000 /* User FLASH */
64 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */
65 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */
66
67 [ child node definitions... ]
68 }
69
702) Child nodes of /system-controller
71
72 a) Marvell Discovery MDIO bus
73
74 The MDIO is a bus to which the PHY devices are connected. For each
75 device that exists on this bus, a child node should be created. See
76 the definition of the PHY node below for an example of how to define
77 a PHY.
78
79 Required properties:
80 - #address-cells : Should be <1>
81 - #size-cells : Should be <0>
82 - device_type : Should be "mdio"
83 - compatible : Should be "marvell,mv64360-mdio"
84
85 Example:
86
87 mdio {
88 #address-cells = <1>;
89 #size-cells = <0>;
90 device_type = "mdio";
91 compatible = "marvell,mv64360-mdio";
92
93 ethernet-phy@0 {
94 ......
95 };
96 };
97
98
99 b) Marvell Discovery ethernet controller
100
101 The Discover ethernet controller is described with two levels
102 of nodes. The first level describes an ethernet silicon block
103 and the second level describes up to 3 ethernet nodes within
104 that block. The reason for the multiple levels is that the
105 registers for the node are interleaved within a single set
106 of registers. The "ethernet-block" level describes the
107 shared register set, and the "ethernet" nodes describe ethernet
108 port-specific properties.
109
110 Ethernet block node
111
112 Required properties:
113 - #address-cells : <1>
114 - #size-cells : <0>
115 - compatible : "marvell,mv64360-eth-block"
116 - reg : Offset and length of the register set for this block
117
118 Example Discovery Ethernet block node:
119 ethernet-block@2000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "marvell,mv64360-eth-block";
123 reg = <0x2000 0x2000>;
124 ethernet@0 {
125 .......
126 };
127 };
128
129 Ethernet port node
130
131 Required properties:
132 - device_type : Should be "network".
133 - compatible : Should be "marvell,mv64360-eth".
134 - reg : Should be <0>, <1>, or <2>, according to which registers
135 within the silicon block the device uses.
136 - interrupts : <a> where a is the interrupt number for the port.
137 - interrupt-parent : the phandle for the interrupt controller
138 that services interrupts for this device.
139 - phy : the phandle for the PHY connected to this ethernet
140 controller.
141 - local-mac-address : 6 bytes, MAC address
142
143 Example Discovery Ethernet port node:
144 ethernet@0 {
145 device_type = "network";
146 compatible = "marvell,mv64360-eth";
147 reg = <0>;
148 interrupts = <32>;
149 interrupt-parent = <&PIC>;
150 phy = <&PHY0>;
151 local-mac-address = [ 00 00 00 00 00 00 ];
152 };
153
154
155
156 c) Marvell Discovery PHY nodes
157
158 Required properties:
159 - device_type : Should be "ethernet-phy"
160 - interrupts : <a> where a is the interrupt number for this phy.
161 - interrupt-parent : the phandle for the interrupt controller that
162 services interrupts for this device.
163 - reg : The ID number for the phy, usually a small integer
164
165 Example Discovery PHY node:
166 ethernet-phy@1 {
167 device_type = "ethernet-phy";
168 compatible = "broadcom,bcm5421";
169 interrupts = <76>; /* GPP 12 */
170 interrupt-parent = <&PIC>;
171 reg = <1>;
172 };
173
174
175 d) Marvell Discovery SDMA nodes
176
177 Represent DMA hardware associated with the MPSC (multiprotocol
178 serial controllers).
179
180 Required properties:
181 - compatible : "marvell,mv64360-sdma"
182 - reg : Offset and length of the register set for this device
183 - interrupts : <a> where a is the interrupt number for the DMA
184 device.
185 - interrupt-parent : the phandle for the interrupt controller
186 that services interrupts for this device.
187
188 Example Discovery SDMA node:
189 sdma@4000 {
190 compatible = "marvell,mv64360-sdma";
191 reg = <0x4000 0xc18>;
192 virtual-reg = <0xf1004000>;
193 interrupts = <36>;
194 interrupt-parent = <&PIC>;
195 };
196
197
198 e) Marvell Discovery BRG nodes
199
200 Represent baud rate generator hardware associated with the MPSC
201 (multiprotocol serial controllers).
202
203 Required properties:
204 - compatible : "marvell,mv64360-brg"
205 - reg : Offset and length of the register set for this device
206 - clock-src : A value from 0 to 15 which selects the clock
207 source for the baud rate generator. This value corresponds
208 to the CLKS value in the BRGx configuration register. See
209 the mv64x60 User's Manual.
210 - clock-frequence : The frequency (in Hz) of the baud rate
211 generator's input clock.
212 - current-speed : The current speed setting (presumably by
213 firmware) of the baud rate generator.
214
215 Example Discovery BRG node:
216 brg@b200 {
217 compatible = "marvell,mv64360-brg";
218 reg = <0xb200 0x8>;
219 clock-src = <8>;
220 clock-frequency = <133333333>;
221 current-speed = <9600>;
222 };
223
224
225 f) Marvell Discovery CUNIT nodes
226
227 Represent the Serial Communications Unit device hardware.
228
229 Required properties:
230 - reg : Offset and length of the register set for this device
231
232 Example Discovery CUNIT node:
233 cunit@f200 {
234 reg = <0xf200 0x200>;
235 };
236
237
238 g) Marvell Discovery MPSCROUTING nodes
239
240 Represent the Discovery's MPSC routing hardware
241
242 Required properties:
243 - reg : Offset and length of the register set for this device
244
245 Example Discovery CUNIT node:
246 mpscrouting@b500 {
247 reg = <0xb400 0xc>;
248 };
249
250
251 h) Marvell Discovery MPSCINTR nodes
252
253 Represent the Discovery's MPSC DMA interrupt hardware registers
254 (SDMA cause and mask registers).
255
256 Required properties:
257 - reg : Offset and length of the register set for this device
258
259 Example Discovery MPSCINTR node:
260 mpsintr@b800 {
261 reg = <0xb800 0x100>;
262 };
263
264
265 i) Marvell Discovery MPSC nodes
266
267 Represent the Discovery's MPSC (Multiprotocol Serial Controller)
268 serial port.
269
270 Required properties:
271 - device_type : "serial"
272 - compatible : "marvell,mv64360-mpsc"
273 - reg : Offset and length of the register set for this device
274 - sdma : the phandle for the SDMA node used by this port
275 - brg : the phandle for the BRG node used by this port
276 - cunit : the phandle for the CUNIT node used by this port
277 - mpscrouting : the phandle for the MPSCROUTING node used by this port
278 - mpscintr : the phandle for the MPSCINTR node used by this port
279 - cell-index : the hardware index of this cell in the MPSC core
280 - max_idle : value needed for MPSC CHR3 (Maximum Frame Length)
281 register
282 - interrupts : <a> where a is the interrupt number for the MPSC.
283 - interrupt-parent : the phandle for the interrupt controller
284 that services interrupts for this device.
285
286 Example Discovery MPSCINTR node:
287 mpsc@8000 {
288 device_type = "serial";
289 compatible = "marvell,mv64360-mpsc";
290 reg = <0x8000 0x38>;
291 virtual-reg = <0xf1008000>;
292 sdma = <&SDMA0>;
293 brg = <&BRG0>;
294 cunit = <&CUNIT>;
295 mpscrouting = <&MPSCROUTING>;
296 mpscintr = <&MPSCINTR>;
297 cell-index = <0>;
298 max_idle = <40>;
299 interrupts = <40>;
300 interrupt-parent = <&PIC>;
301 };
302
303
304 j) Marvell Discovery Watch Dog Timer nodes
305
306 Represent the Discovery's watchdog timer hardware
307
308 Required properties:
309 - compatible : "marvell,mv64360-wdt"
310 - reg : Offset and length of the register set for this device
311
312 Example Discovery Watch Dog Timer node:
313 wdt@b410 {
314 compatible = "marvell,mv64360-wdt";
315 reg = <0xb410 0x8>;
316 };
317
318
319 k) Marvell Discovery I2C nodes
320
321 Represent the Discovery's I2C hardware
322
323 Required properties:
324 - device_type : "i2c"
325 - compatible : "marvell,mv64360-i2c"
326 - reg : Offset and length of the register set for this device
327 - interrupts : <a> where a is the interrupt number for the I2C.
328 - interrupt-parent : the phandle for the interrupt controller
329 that services interrupts for this device.
330
331 Example Discovery I2C node:
332 compatible = "marvell,mv64360-i2c";
333 reg = <0xc000 0x20>;
334 virtual-reg = <0xf100c000>;
335 interrupts = <37>;
336 interrupt-parent = <&PIC>;
337 };
338
339
340 l) Marvell Discovery PIC (Programmable Interrupt Controller) nodes
341
342 Represent the Discovery's PIC hardware
343
344 Required properties:
345 - #interrupt-cells : <1>
346 - #address-cells : <0>
347 - compatible : "marvell,mv64360-pic"
348 - reg : Offset and length of the register set for this device
349 - interrupt-controller
350
351 Example Discovery PIC node:
352 pic {
353 #interrupt-cells = <1>;
354 #address-cells = <0>;
355 compatible = "marvell,mv64360-pic";
356 reg = <0x0 0x88>;
357 interrupt-controller;
358 };
359
360
361 m) Marvell Discovery MPP (Multipurpose Pins) multiplexing nodes
362
363 Represent the Discovery's MPP hardware
364
365 Required properties:
366 - compatible : "marvell,mv64360-mpp"
367 - reg : Offset and length of the register set for this device
368
369 Example Discovery MPP node:
370 mpp@f000 {
371 compatible = "marvell,mv64360-mpp";
372 reg = <0xf000 0x10>;
373 };
374
375
376 n) Marvell Discovery GPP (General Purpose Pins) nodes
377
378 Represent the Discovery's GPP hardware
379
380 Required properties:
381 - compatible : "marvell,mv64360-gpp"
382 - reg : Offset and length of the register set for this device
383
384 Example Discovery GPP node:
385 gpp@f000 {
386 compatible = "marvell,mv64360-gpp";
387 reg = <0xf100 0x20>;
388 };
389
390
391 o) Marvell Discovery PCI host bridge node
392
393 Represents the Discovery's PCI host bridge device. The properties
394 for this node conform to Rev 2.1 of the PCI Bus Binding to IEEE
395 1275-1994. A typical value for the compatible property is
396 "marvell,mv64360-pci".
397
398 Example Discovery PCI host bridge node
399 pci@80000000 {
400 #address-cells = <3>;
401 #size-cells = <2>;
402 #interrupt-cells = <1>;
403 device_type = "pci";
404 compatible = "marvell,mv64360-pci";
405 reg = <0xcf8 0x8>;
406 ranges = <0x01000000 0x0 0x0
407 0x88000000 0x0 0x01000000
408 0x02000000 0x0 0x80000000
409 0x80000000 0x0 0x08000000>;
410 bus-range = <0 255>;
411 clock-frequency = <66000000>;
412 interrupt-parent = <&PIC>;
413 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
414 interrupt-map = <
415 /* IDSEL 0x0a */
416 0x5000 0 0 1 &PIC 80
417 0x5000 0 0 2 &PIC 81
418 0x5000 0 0 3 &PIC 91
419 0x5000 0 0 4 &PIC 93
420
421 /* IDSEL 0x0b */
422 0x5800 0 0 1 &PIC 91
423 0x5800 0 0 2 &PIC 93
424 0x5800 0 0 3 &PIC 80
425 0x5800 0 0 4 &PIC 81
426
427 /* IDSEL 0x0c */
428 0x6000 0 0 1 &PIC 91
429 0x6000 0 0 2 &PIC 93
430 0x6000 0 0 3 &PIC 80
431 0x6000 0 0 4 &PIC 81
432
433 /* IDSEL 0x0d */
434 0x6800 0 0 1 &PIC 93
435 0x6800 0 0 2 &PIC 80
436 0x6800 0 0 3 &PIC 81
437 0x6800 0 0 4 &PIC 91
438 >;
439 };
440
441
442 p) Marvell Discovery CPU Error nodes
443
444 Represent the Discovery's CPU error handler device.
445
446 Required properties:
447 - compatible : "marvell,mv64360-cpu-error"
448 - reg : Offset and length of the register set for this device
449 - interrupts : the interrupt number for this device
450 - interrupt-parent : the phandle for the interrupt controller
451 that services interrupts for this device.
452
453 Example Discovery CPU Error node:
454 cpu-error@0070 {
455 compatible = "marvell,mv64360-cpu-error";
456 reg = <0x70 0x10 0x128 0x28>;
457 interrupts = <3>;
458 interrupt-parent = <&PIC>;
459 };
460
461
462 q) Marvell Discovery SRAM Controller nodes
463
464 Represent the Discovery's SRAM controller device.
465
466 Required properties:
467 - compatible : "marvell,mv64360-sram-ctrl"
468 - reg : Offset and length of the register set for this device
469 - interrupts : the interrupt number for this device
470 - interrupt-parent : the phandle for the interrupt controller
471 that services interrupts for this device.
472
473 Example Discovery SRAM Controller node:
474 sram-ctrl@0380 {
475 compatible = "marvell,mv64360-sram-ctrl";
476 reg = <0x380 0x80>;
477 interrupts = <13>;
478 interrupt-parent = <&PIC>;
479 };
480
481
482 r) Marvell Discovery PCI Error Handler nodes
483
484 Represent the Discovery's PCI error handler device.
485
486 Required properties:
487 - compatible : "marvell,mv64360-pci-error"
488 - reg : Offset and length of the register set for this device
489 - interrupts : the interrupt number for this device
490 - interrupt-parent : the phandle for the interrupt controller
491 that services interrupts for this device.
492
493 Example Discovery PCI Error Handler node:
494 pci-error@1d40 {
495 compatible = "marvell,mv64360-pci-error";
496 reg = <0x1d40 0x40 0xc28 0x4>;
497 interrupts = <12>;
498 interrupt-parent = <&PIC>;
499 };
500
501
502 s) Marvell Discovery Memory Controller nodes
503
504 Represent the Discovery's memory controller device.
505
506 Required properties:
507 - compatible : "marvell,mv64360-mem-ctrl"
508 - reg : Offset and length of the register set for this device
509 - interrupts : the interrupt number for this device
510 - interrupt-parent : the phandle for the interrupt controller
511 that services interrupts for this device.
512
513 Example Discovery Memory Controller node:
514 mem-ctrl@1400 {
515 compatible = "marvell,mv64360-mem-ctrl";
516 reg = <0x1400 0x60>;
517 interrupts = <17>;
518 interrupt-parent = <&PIC>;
519 };
520
521
diff --git a/Documentation/powerpc/dts-bindings/phy.txt b/Documentation/powerpc/dts-bindings/phy.txt
new file mode 100644
index 000000000000..bb8c742eb8c5
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/phy.txt
@@ -0,0 +1,25 @@
1PHY nodes
2
3Required properties:
4
5 - device_type : Should be "ethernet-phy"
6 - interrupts : <a b> where a is the interrupt number and b is a
7 field that represents an encoding of the sense and level
8 information for the interrupt. This should be encoded based on
9 the information in section 2) depending on the type of interrupt
10 controller you have.
11 - interrupt-parent : the phandle for the interrupt controller that
12 services interrupts for this device.
13 - reg : The ID number for the phy, usually a small integer
14 - linux,phandle : phandle for this node; likely referenced by an
15 ethernet controller node.
16
17Example:
18
19ethernet-phy@0 {
20 linux,phandle = <2452000>
21 interrupt-parent = <40000>;
22 interrupts = <35 1>;
23 reg = <0>;
24 device_type = "ethernet-phy";
25};
diff --git a/Documentation/powerpc/dts-bindings/spi-bus.txt b/Documentation/powerpc/dts-bindings/spi-bus.txt
new file mode 100644
index 000000000000..e782add2e457
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/spi-bus.txt
@@ -0,0 +1,57 @@
1SPI (Serial Peripheral Interface) busses
2
3SPI busses can be described with a node for the SPI master device
4and a set of child nodes for each SPI slave on the bus. For this
5discussion, it is assumed that the system's SPI controller is in
6SPI master mode. This binding does not describe SPI controllers
7in slave mode.
8
9The SPI master node requires the following properties:
10- #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12- #size-cells - should be zero.
13- compatible - name of SPI bus controller following generic names
14 recommended practice.
15No other properties are required in the SPI bus node. It is assumed
16that a driver for an SPI bus device will understand that it is an SPI bus.
17However, the binding does not attempt to define the specific method for
18assigning chip select numbers. Since SPI chip select configuration is
19flexible and non-standardized, it is left out of this binding with the
20assumption that board specific platform code will be used to manage
21chip selects. Individual drivers can define additional properties to
22support describing the chip select layout.
23
24SPI slave nodes must be children of the SPI master node and can
25contain the following properties.
26- reg - (required) chip select address of device.
27- compatible - (required) name of SPI device following generic names
28 recommended practice
29- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
30- spi-cpol - (optional) Empty property indicating device requires
31 inverse clock polarity (CPOL) mode
32- spi-cpha - (optional) Empty property indicating device requires
33 shifted clock phase (CPHA) mode
34- spi-cs-high - (optional) Empty property indicating device requires
35 chip select active high
36
37SPI example for an MPC5200 SPI bus:
38 spi@f00 {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
42 reg = <0xf00 0x20>;
43 interrupts = <2 13 0 2 14 0>;
44 interrupt-parent = <&mpc5200_pic>;
45
46 ethernet-switch@0 {
47 compatible = "micrel,ks8995m";
48 spi-max-frequency = <1000000>;
49 reg = <0>;
50 };
51
52 codec@1 {
53 compatible = "ti,tlv320aic26";
54 spi-max-frequency = <100000>;
55 reg = <1>;
56 };
57 };
diff --git a/Documentation/powerpc/dts-bindings/usb-ehci.txt b/Documentation/powerpc/dts-bindings/usb-ehci.txt
new file mode 100644
index 000000000000..fa18612f757b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/usb-ehci.txt
@@ -0,0 +1,25 @@
1USB EHCI controllers
2
3Required properties:
4 - compatible : should be "usb-ehci".
5 - reg : should contain at least address and length of the standard EHCI
6 register set for the device. Optional platform-dependent registers
7 (debug-port or other) can be also specified here, but only after
8 definition of standard EHCI registers.
9 - interrupts : one EHCI interrupt should be described here.
10If device registers are implemented in big endian mode, the device
11node should have "big-endian-regs" property.
12If controller implementation operates with big endian descriptors,
13"big-endian-desc" property should be specified.
14If both big endian registers and descriptors are used by the controller
15implementation, "big-endian" property can be specified instead of having
16both "big-endian-regs" and "big-endian-desc".
17
18Example (Sequoia 440EPx):
19 ehci@e0000300 {
20 compatible = "ibm,usb-ehci-440epx", "usb-ehci";
21 interrupt-parent = <&UIC0>;
22 interrupts = <1a 4>;
23 reg = <0 e0000300 90 0 e0000390 70>;
24 big-endian;
25 };
diff --git a/Documentation/powerpc/dts-bindings/xilinx.txt b/Documentation/powerpc/dts-bindings/xilinx.txt
new file mode 100644
index 000000000000..80339fe4300b
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/xilinx.txt
@@ -0,0 +1,295 @@
1 d) Xilinx IP cores
2
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
5 of standard device types (network, serial, etc.) and miscellaneous
6 devices (gpio, LCD, spi, etc). Also, since these devices are
7 implemented within the fpga fabric every instance of the device can be
8 synthesised with different options that change the behaviour.
9
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
12 extract the device parameters relevant to device drivers and copy them
13 into an 'xparameters.h' in the form of #define symbols. This tells the
14 device drivers how the IP cores are configured, but it requres the kernel
15 to be recompiled every time the FPGA bitstream is resynthesized.
16
17 The new approach is to export the parameters into the device tree and
18 generate a new device tree each time the FPGA bitstream changes. The
19 parameters which used to be exported as #defines will now become
20 properties of the device node. In general, device nodes for IP-cores
21 will take the following form:
22
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
25 [, (list of compatible devices), ...];
26 reg = <(baseaddr) (size)>;
27 interrupt-parent = <&interrupt-controller-phandle>;
28 interrupts = < ... >;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
31 };
32
33 (generic-name): an open firmware-style name that describes the
34 generic class of device. Preferably, this is one word, such
35 as 'serial' or 'ethernet'.
36 (ip-core-name): the name of the ip block (given after the BEGIN
37 directive in system.mhs). Should be in lowercase
38 and all underscores '_' converted to dashes '-'.
39 (name): is derived from the "PARAMETER INSTANCE" value.
40 (parameter#): C_* parameters from system.mhs. The C_ prefix is
41 dropped from the parameter name, the name is converted
42 to lowercase and all underscore '_' characters are
43 converted to dashes '-'.
44 (baseaddr): the baseaddr parameter value (often named C_BASEADDR).
45 (HW_VER): from the HW_VER parameter.
46 (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
47
48 Typically, the compatible list will include the exact IP core version
49 followed by an older IP core version which implements the same
50 interface or any other device with the same interface.
51
52 'reg', 'interrupt-parent' and 'interrupts' are all optional properties.
53
54 For example, the following block from system.mhs:
55
56 BEGIN opb_uartlite
57 PARAMETER INSTANCE = opb_uartlite_0
58 PARAMETER HW_VER = 1.00.b
59 PARAMETER C_BAUDRATE = 115200
60 PARAMETER C_DATA_BITS = 8
61 PARAMETER C_ODD_PARITY = 0
62 PARAMETER C_USE_PARITY = 0
63 PARAMETER C_CLK_FREQ = 50000000
64 PARAMETER C_BASEADDR = 0xEC100000
65 PARAMETER C_HIGHADDR = 0xEC10FFFF
66 BUS_INTERFACE SOPB = opb_7
67 PORT OPB_Clk = CLK_50MHz
68 PORT Interrupt = opb_uartlite_0_Interrupt
69 PORT RX = opb_uartlite_0_RX
70 PORT TX = opb_uartlite_0_TX
71 PORT OPB_Rst = sys_bus_reset_0
72 END
73
74 becomes the following device tree node:
75
76 opb_uartlite_0: serial@ec100000 {
77 device_type = "serial";
78 compatible = "xlnx,opb-uartlite-1.00.b";
79 reg = <ec100000 10000>;
80 interrupt-parent = <&opb_intc_0>;
81 interrupts = <1 0>; // got this from the opb_intc parameters
82 current-speed = <d#115200>; // standard serial device prop
83 clock-frequency = <d#50000000>; // standard serial device prop
84 xlnx,data-bits = <8>;
85 xlnx,odd-parity = <0>;
86 xlnx,use-parity = <0>;
87 };
88
89 Some IP cores actually implement 2 or more logical devices. In
90 this case, the device should still describe the whole IP core with
91 a single node and add a child node for each logical device. The
92 ranges property can be used to translate from parent IP-core to the
93 registers of each device. In addition, the parent node should be
94 compatible with the bus type 'xlnx,compound', and should contain
95 #address-cells and #size-cells, as with any other bus. (Note: this
96 makes the assumption that both logical devices have the same bus
97 binding. If this is not true, then separate nodes should be used
98 for each logical device). The 'cell-index' property can be used to
99 enumerate logical devices within an IP core. For example, the
100 following is the system.mhs entry for the dual ps2 controller found
101 on the ml403 reference design.
102
103 BEGIN opb_ps2_dual_ref
104 PARAMETER INSTANCE = opb_ps2_dual_ref_0
105 PARAMETER HW_VER = 1.00.a
106 PARAMETER C_BASEADDR = 0xA9000000
107 PARAMETER C_HIGHADDR = 0xA9001FFF
108 BUS_INTERFACE SOPB = opb_v20_0
109 PORT Sys_Intr1 = ps2_1_intr
110 PORT Sys_Intr2 = ps2_2_intr
111 PORT Clkin1 = ps2_clk_rx_1
112 PORT Clkin2 = ps2_clk_rx_2
113 PORT Clkpd1 = ps2_clk_tx_1
114 PORT Clkpd2 = ps2_clk_tx_2
115 PORT Rx1 = ps2_d_rx_1
116 PORT Rx2 = ps2_d_rx_2
117 PORT Txpd1 = ps2_d_tx_1
118 PORT Txpd2 = ps2_d_tx_2
119 END
120
121 It would result in the following device tree nodes:
122
123 opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "xlnx,compound";
127 ranges = <0 a9000000 2000>;
128 // If this device had extra parameters, then they would
129 // go here.
130 ps2@0 {
131 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
132 reg = <0 40>;
133 interrupt-parent = <&opb_intc_0>;
134 interrupts = <3 0>;
135 cell-index = <0>;
136 };
137 ps2@1000 {
138 compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
139 reg = <1000 40>;
140 interrupt-parent = <&opb_intc_0>;
141 interrupts = <3 0>;
142 cell-index = <0>;
143 };
144 };
145
146 Also, the system.mhs file defines bus attachments from the processor
147 to the devices. The device tree structure should reflect the bus
148 attachments. Again an example; this system.mhs fragment:
149
150 BEGIN ppc405_virtex4
151 PARAMETER INSTANCE = ppc405_0
152 PARAMETER HW_VER = 1.01.a
153 BUS_INTERFACE DPLB = plb_v34_0
154 BUS_INTERFACE IPLB = plb_v34_0
155 END
156
157 BEGIN opb_intc
158 PARAMETER INSTANCE = opb_intc_0
159 PARAMETER HW_VER = 1.00.c
160 PARAMETER C_BASEADDR = 0xD1000FC0
161 PARAMETER C_HIGHADDR = 0xD1000FDF
162 BUS_INTERFACE SOPB = opb_v20_0
163 END
164
165 BEGIN opb_uart16550
166 PARAMETER INSTANCE = opb_uart16550_0
167 PARAMETER HW_VER = 1.00.d
168 PARAMETER C_BASEADDR = 0xa0000000
169 PARAMETER C_HIGHADDR = 0xa0001FFF
170 BUS_INTERFACE SOPB = opb_v20_0
171 END
172
173 BEGIN plb_v34
174 PARAMETER INSTANCE = plb_v34_0
175 PARAMETER HW_VER = 1.02.a
176 END
177
178 BEGIN plb_bram_if_cntlr
179 PARAMETER INSTANCE = plb_bram_if_cntlr_0
180 PARAMETER HW_VER = 1.00.b
181 PARAMETER C_BASEADDR = 0xFFFF0000
182 PARAMETER C_HIGHADDR = 0xFFFFFFFF
183 BUS_INTERFACE SPLB = plb_v34_0
184 END
185
186 BEGIN plb2opb_bridge
187 PARAMETER INSTANCE = plb2opb_bridge_0
188 PARAMETER HW_VER = 1.01.a
189 PARAMETER C_RNG0_BASEADDR = 0x20000000
190 PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
191 PARAMETER C_RNG1_BASEADDR = 0x60000000
192 PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
193 PARAMETER C_RNG2_BASEADDR = 0x80000000
194 PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
195 PARAMETER C_RNG3_BASEADDR = 0xC0000000
196 PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
197 BUS_INTERFACE SPLB = plb_v34_0
198 BUS_INTERFACE MOPB = opb_v20_0
199 END
200
201 Gives this device tree (some properties removed for clarity):
202
203 plb@0 {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 compatible = "xlnx,plb-v34-1.02.a";
207 device_type = "ibm,plb";
208 ranges; // 1:1 translation
209
210 plb_bram_if_cntrl_0: bram@ffff0000 {
211 reg = <ffff0000 10000>;
212 }
213
214 opb@20000000 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 ranges = <20000000 20000000 20000000
218 60000000 60000000 20000000
219 80000000 80000000 40000000
220 c0000000 c0000000 20000000>;
221
222 opb_uart16550_0: serial@a0000000 {
223 reg = <a00000000 2000>;
224 };
225
226 opb_intc_0: interrupt-controller@d1000fc0 {
227 reg = <d1000fc0 20>;
228 };
229 };
230 };
231
232 That covers the general approach to binding xilinx IP cores into the
233 device tree. The following are bindings for specific devices:
234
235 i) Xilinx ML300 Framebuffer
236
237 Simple framebuffer device from the ML300 reference design (also on the
238 ML403 reference design as well as others).
239
240 Optional properties:
241 - resolution = <xres yres> : pixel resolution of framebuffer. Some
242 implementations use a different resolution.
243 Default is <d#640 d#480>
244 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
245 Default is <d#1024 d#480>.
246 - rotate-display (empty) : rotate display 180 degrees.
247
248 ii) Xilinx SystemACE
249
250 The Xilinx SystemACE device is used to program FPGAs from an FPGA
251 bitstream stored on a CF card. It can also be used as a generic CF
252 interface device.
253
254 Optional properties:
255 - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
256
257 iii) Xilinx EMAC and Xilinx TEMAC
258
259 Xilinx Ethernet devices. In addition to general xilinx properties
260 listed above, nodes for these devices should include a phy-handle
261 property, and may include other common network device properties
262 like local-mac-address.
263
264 iv) Xilinx Uartlite
265
266 Xilinx uartlite devices are simple fixed speed serial ports.
267
268 Required properties:
269 - current-speed : Baud rate of uartlite
270
271 v) Xilinx hwicap
272
273 Xilinx hwicap devices provide access to the configuration logic
274 of the FPGA through the Internal Configuration Access Port
275 (ICAP). The ICAP enables partial reconfiguration of the FPGA,
276 readback of the configuration information, and some control over
277 'warm boots' of the FPGA fabric.
278
279 Required properties:
280 - xlnx,family : The family of the FPGA, necessary since the
281 capabilities of the underlying ICAP hardware
282 differ between different families. May be
283 'virtex2p', 'virtex4', or 'virtex5'.
284
285 vi) Xilinx Uart 16550
286
287 Xilinx UART 16550 devices are very similar to the NS16550 but with
288 different register spacing and an offset from the base address.
289
290 Required properties:
291 - clock-frequency : Frequency of the clock input
292 - reg-offset : A value of 3 is required
293 - reg-shift : A value of 2 is required
294
295
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 17:00:13 -0500