8 files changed, 236 insertions, 17 deletions

diff --git a/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt b/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt
index d015dcec4011..b0019eb5330e 100644
--- a/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt
@@ -11,7 +11,7 @@ Required properties:
   83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
 - #gpio-cells : Should be two. The first cell is the pin number and the
   second cell is used to specify optional parameters (currently unused).
- - interrupts : Interrupt mapping for GPIO IRQ (currently unused).
+ - interrupts : Interrupt mapping for GPIO IRQ.
  - interrupt-parent : Phandle for the interrupt controller that
    services interrupts for this device.
 - gpio-controller : Marks the port as GPIO controller.
@@ -38,3 +38,23 @@ Example of gpio-controller nodes for a MPC8347 SoC:
 
 See booting-without-of.txt for details of how to specify GPIO
 information for devices.
+
+To use GPIO pins as interrupt sources for peripherals, specify the
+GPIO controller as the interrupt parent and define GPIO number +
+trigger mode using the interrupts property, which is defined like
+this:
+
+interrupts = <number trigger>, where:
+ - number: GPIO pin (0..31)
+ - trigger: trigger mode:
+        2 = trigger on falling edge
+        3 = trigger on both edges
+
+Example of device using this is:
+
+        funkyfpga@0 {
+                compatible = "funky-fpga";
+                ...
+                interrupts = <4 3>;
+                interrupt-parent = <&gpio1>;
+        };
diff --git a/Documentation/powerpc/dts-bindings/fsl/can.txt b/Documentation/powerpc/dts-bindings/fsl/can.txt
new file mode 100644
index 000000000000..2fa4fcd38fd6
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/can.txt
@@ -0,0 +1,53 @@
+CAN Device Tree Bindings
+------------------------
+
+(c) 2006-2009 Secret Lab Technologies Ltd
+Grant Likely <grant.likely@secretlab.ca>
+
+fsl,mpc5200-mscan nodes
+-----------------------
+In addition to the required compatible-, reg- and interrupt-properties, you can
+also specify which clock source shall be used for the controller:
+
+- fsl,mscan-clock-source : a string describing the clock source. Valid values
+                           are: "ip" for ip bus clock
+                                 "ref" for reference clock (XTAL)
+                           "ref" is default in case this property is not
+                           present.
+
+fsl,mpc5121-mscan nodes
+-----------------------
+In addition to the required compatible-, reg- and interrupt-properties, you can
+also specify which clock source and divider shall be used for the controller:
+
+- fsl,mscan-clock-source : a string describing the clock source. Valid values
+                           are: "ip" for ip bus clock
+                                "ref" for reference clock
+                                "sys" for system clock
+                           If this property is not present, an optimal CAN
+                           clock source and frequency based on the system
+                           clock will be selected. If this is not possible,
+                           the reference clock will be used.
+
+- fsl,mscan-clock-divider: for the reference and system clock, an additional
+                           clock divider can be specified. By default, a
+                           value of 1 is used.
+
+Note that the MPC5121 Rev. 1 processor is not supported.
+
+Examples:
+        can@1300 {
+                compatible = "fsl,mpc5121-mscan";
+                interrupts = <12 0x8>;
+                interrupt-parent = <&ipic>;
+                reg = <0x1300 0x80>;
+        };
+
+        can@1380 {
+                compatible = "fsl,mpc5121-mscan";
+                interrupts = <13 0x8>;
+                interrupt-parent = <&ipic>;
+                reg = <0x1380 0x80>;
+                fsl,mscan-clock-source = "ref";
+                fsl,mscan-clock-divider = <3>;
+        };
diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
index 6e37be1eeb2d..4f8930263dd9 100644
--- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt
@@ -21,6 +21,15 @@ Required properties:
 - fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the
   threads.
 
+Optional properties:
+- fsl,firmware-phandle:
+    Usage: required only if there is no fsl,qe-firmware child node
+    Value type: <phandle>
+    Definition: Points to a firmware node (see "QE Firmware Node" below)
+        that contains the firmware that should be uploaded for this QE.
+        The compatible property for the firmware node should say,
+        "fsl,qe-firmware".
+
 Recommended properties
 - brg-frequency : the internal clock source frequency for baud-rate
   generators in Hz.
@@ -59,3 +68,48 @@ Example:
                 reg = <0 c000>;
         };
      };
+
+* QE Firmware Node
+
+This node defines a firmware binary that is embedded in the device tree, for
+the purpose of passing the firmware from bootloader to the kernel, or from
+the hypervisor to the guest.
+
+The firmware node itself contains the firmware binary contents, a compatible
+property, and any firmware-specific properties.  The node should be placed
+inside a QE node that needs it.  Doing so eliminates the need for a
+fsl,firmware-phandle property.  Other QE nodes that need the same firmware
+should define an fsl,firmware-phandle property that points to the firmware node
+in the first QE node.
+
+The fsl,firmware property can be specified in the DTS (possibly using incbin)
+or can be inserted by the boot loader at boot time.
+
+Required properties:
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: A standard property.  Specify a string that indicates what
+          kind of firmware it is.  For QE, this should be "fsl,qe-firmware".
+
+   - fsl,firmware
+      Usage: required
+      Value type: <prop-encoded-array>, encoded as an array of bytes
+      Definition: A standard property.  This property contains the firmware
+          binary "blob".
+
+Example:
+        qe1@e0080000 {
+                compatible = "fsl,qe";
+                qe_firmware:qe-firmware {
+                        compatible = "fsl,qe-firmware";
+                        fsl,firmware = [0x70 0xcd 0x00 0x00 0x01 0x46 0x45 ...];
+                };
+                ...
+        };
+
+        qe2@e0090000 {
+                compatible = "fsl,qe";
+                fsl,firmware-phandle = <&qe_firmware>;
+                ...
+        };
diff --git a/Documentation/powerpc/dts-bindings/fsl/dma.txt b/Documentation/powerpc/dts-bindings/fsl/dma.txt
index 0732cdd05ba1..2a4b4bce6110 100644
--- a/Documentation/powerpc/dts-bindings/fsl/dma.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/dma.txt
@@ -44,21 +44,29 @@ Example:
                         compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
                         cell-index = <0>;
                         reg = <0 0x80>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <71 8>;
                 };
                 dma-channel@80 {
                         compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
                         cell-index = <1>;
                         reg = <0x80 0x80>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <71 8>;
                 };
                 dma-channel@100 {
                         compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
                         cell-index = <2>;
                         reg = <0x100 0x80>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <71 8>;
                 };
                 dma-channel@180 {
                         compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
                         cell-index = <3>;
                         reg = <0x180 0x80>;
+                        interrupt-parent = <&ipic>;
+                        interrupts = <71 8>;
                 };
         };
 
diff --git a/Documentation/powerpc/dts-bindings/fsl/i2c.txt b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
index b6d2e21474f9..50da20310585 100644
--- a/Documentation/powerpc/dts-bindings/fsl/i2c.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/i2c.txt
@@ -2,15 +2,14 @@
 
 Required properties :
 
- - device_type : Should be "i2c"
  - reg : Offset and length of the register set for the device
+ - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
+   compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
+   mpc5200 or mpc5200b. For the mpc5121, an additional node
+   "fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
 
 Recommended properties :
 
- - compatible : compatibility list with 2 entries, the first should
-   be "fsl,CHIP-i2c" where CHIP is the name of a compatible processor,
-   e.g. mpc8313, mpc8543, mpc8544, mpc5200 or mpc5200b. The second one
-   should be "fsl-i2c".
  - interrupts : <a b> where a is the interrupt number and b is a
    field that represents an encoding of the sense and level
    information for the interrupt.  This should be encoded based on
@@ -24,25 +23,40 @@ Recommended properties :
 
 Examples :
 
+        /* MPC5121 based board */
+        i2c@1740 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mpc5121-i2c", "fsl-i2c";
+                reg = <0x1740 0x20>;
+                interrupts = <11 0x8>;
+                interrupt-parent = <&ipic>;
+                clock-frequency = <100000>;
+        };
+
+        i2ccontrol@1760 {
+                compatible = "fsl,mpc5121-i2c-ctrl";
+                reg = <0x1760 0x8>;
+        };
+
+        /* MPC5200B based board */
         i2c@3d00 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
-                cell-index = <0>;
                 reg = <0x3d00 0x40>;
                 interrupts = <2 15 0>;
                 interrupt-parent = <&mpc5200_pic>;
                 fsl,preserve-clocking;
         };
 
+        /* MPC8544 base board */
         i2c@3100 {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                cell-index = <1>;
                 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
                 reg = <0x3100 0x100>;
                 interrupts = <43 2>;
                 interrupt-parent = <&mpic>;
                 clock-frequency = <400000>;
         };
-
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
new file mode 100644
index 000000000000..8832e8798912
--- /dev/null
+++ b/Documentation/powerpc/dts-bindings/fsl/mpc5121-psc.txt
@@ -0,0 +1,70 @@
+MPC5121 PSC Device Tree Bindings
+
+PSC in UART mode
+----------------
+
+For PSC in UART mode the needed PSC serial devices
+are specified by fsl,mpc5121-psc-uart nodes in the
+fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
+Controller node fsl,mpc5121-psc-fifo is requered there:
+
+fsl,mpc5121-psc-uart nodes
+--------------------------
+
+Required properties :
+ - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
+ - cell-index : Index of the PSC in hardware
+ - reg : Offset and length of the register set for the PSC device
+ - interrupts : <a b> where a is the interrupt number of the
+   PSC FIFO Controller and b is a field that represents an
+   encoding of the sense and level information for the interrupt.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+
+Recommended properties :
+ - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
+ - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
+
+
+fsl,mpc5121-psc-fifo node
+-------------------------
+
+Required properties :
+ - compatible : Should be "fsl,mpc5121-psc-fifo"
+ - reg : Offset and length of the register set for the PSC
+         FIFO Controller
+ - interrupts : <a b> where a is the interrupt number of the
+   PSC FIFO Controller and b is a field that represents an
+   encoding of the sense and level information for the interrupt.
+ - interrupt-parent : the phandle for the interrupt controller that
+   services interrupts for this device.
+
+
+Example for a board using PSC0 and PSC1 devices in serial mode:
+
+serial@11000 {
+        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+        cell-index = <0>;
+        reg = <0x11000 0x100>;
+        interrupts = <40 0x8>;
+        interrupt-parent = < &ipic >;
+        fsl,rx-fifo-size = <16>;
+        fsl,tx-fifo-size = <16>;
+};
+
+serial@11100 {
+        compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+        cell-index = <1>;
+        reg = <0x11100 0x100>;
+        interrupts = <40 0x8>;
+        interrupt-parent = < &ipic >;
+        fsl,rx-fifo-size = <16>;
+        fsl,tx-fifo-size = <16>;
+};
+
+pscfifo@11f00 {
+        compatible = "fsl,mpc5121-psc-fifo";
+        reg = <0x11f00 0x100>;
+        interrupts = <40 0x8>;
+        interrupt-parent = < &ipic >;
+};
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
index 5c6602dbfdc2..4ccb2cd5df94 100644
--- a/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
@@ -195,11 +195,4 @@ External interrupts:
 
 fsl,mpc5200-mscan nodes
 -----------------------
-In addition to the required compatible-, reg- and interrupt-properites, you can
-also specify which clock source shall be used for the controller:
-
-- fsl,mscan-clock-source- a string describing the clock source. Valid values
-                          are:  "ip" for ip bus clock
-                                "ref" for reference clock (XTAL)
-                          "ref" is default in case this property is not
-                          present.
+See file can.txt in this directory.
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index e7d9a344c4f4..80510c018eea 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -13,6 +13,11 @@ Required properties:
 - interrupt-parent : the phandle for the interrupt controller that
   services interrupts for this device.
 
+Optional properties:
+- gpios : specifies the gpio pins to be used for chipselects.
+  The gpios will be referred to as reg = <index> in the SPI child nodes.
+  If unspecified, a single SPI device without a chip select can be used.
+
 Example:
         spi@4c0 {
                 cell-index = <0>;
@@ -21,4 +26,6 @@ Example:
                 interrupts = <82 0>;
                 interrupt-parent = <700>;
                 mode = "cpu";
+                gpios = <&gpio 18 1     // device reg=<0>
+                         &gpio 19 1>;   // device reg=<1>
         };