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-rw-r--r--Documentation/powerpc/dts-bindings/fsl/mpc5200.txt27
1 files changed, 26 insertions, 1 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt b/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
index 8447fd7090d0..5c6602dbfdc2 100644
--- a/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/mpc5200.txt
@@ -103,7 +103,22 @@ fsl,mpc5200-gpt nodes
103--------------------- 103---------------------
104On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board 104On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
105design supports the internal wdt, then the device node for GPT0 should 105design supports the internal wdt, then the device node for GPT0 should
106include the empty property 'fsl,has-wdt'. 106include the empty property 'fsl,has-wdt'. Note that this does not activate
107the watchdog. The timer will function as a GPT if the timer api is used, and
108it will function as watchdog if the watchdog device is used. The watchdog
109mode has priority over the gpt mode, i.e. if the watchdog is activated, any
110gpt api call to this timer will fail with -EBUSY.
111
112If you add the property
113 fsl,wdt-on-boot = <n>;
114GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
115If n>0, the watchdog is started with a timeout of n seconds. If n=0, the
116configuration of the watchdog is not touched. This is useful in two cases:
117- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
118- do not touch a configuration assigned by the boot loader which supervises
119 the boot process itself.
120
121The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option.
107 122
108An mpc5200-gpt can be used as a single line GPIO controller. To do so, 123An mpc5200-gpt can be used as a single line GPIO controller. To do so,
109add the following properties to the gpt node: 124add the following properties to the gpt node:
@@ -178,3 +193,13 @@ External interrupts:
178 external irq3: interrupts = <1 3 n>; 193 external irq3: interrupts = <1 3 n>;
179'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low) 194'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low)
180 195
196fsl,mpc5200-mscan nodes
197-----------------------
198In addition to the required compatible-, reg- and interrupt-properites, you can
199also specify which clock source shall be used for the controller:
200
201- fsl,mscan-clock-source- a string describing the clock source. Valid values
202 are: "ip" for ip bus clock
203 "ref" for reference clock (XTAL)
204 "ref" is default in case this property is not
205 present.