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1* Board Control and Status (BCSR)
2
3Required properties:
4
5 - compatible : Should be "fsl,<board>-bcsr"
6 - reg : Offset and length of the register set for the device
7
8Example:
9
10 bcsr@f8000000 {
11 compatible = "fsl,mpc8360mds-bcsr";
12 reg = <f8000000 8000>;
13 };
14
15* Freescale on board FPGA
16
17This is the memory-mapped registers for on board FPGA.
18
19Required properities:
20- compatible : should be "fsl,fpga-pixis".
21- reg : should contain the address and the length of the FPPGA register
22 set.
23- interrupt-parent: should specify phandle for the interrupt controller.
24- interrupts : should specify event (wakeup) IRQ.
25
26Example (MPC8610HPCD):
27
28 board-control@e8000000 {
29 compatible = "fsl,fpga-pixis";
30 reg = <0xe8000000 32>;
31 interrupt-parent = <&mpic>;
32 interrupts = <8 8>;
33 };
34
35* Freescale BCSR GPIO banks
36
37Some BCSR registers act as simple GPIO controllers, each such
38register can be represented by the gpio-controller node.
39
40Required properities:
41- compatible : Should be "fsl,<board>-bcsr-gpio".
42- reg : Should contain the address and the length of the GPIO bank
43 register.
44- #gpio-cells : Should be two. The first cell is the pin number and the
45 second cell is used to specify optional parameters (currently unused).
46- gpio-controller : Marks the port as GPIO controller.
47
48Example:
49
50 bcsr@1,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "fsl,mpc8360mds-bcsr";
54 reg = <1 0 0x8000>;
55 ranges = <0 1 0 0x8000>;
56
57 bcsr13: gpio-controller@d {
58 #gpio-cells = <2>;
59 compatible = "fsl,mpc8360mds-bcsr-gpio";
60 reg = <0xd 1>;
61 gpio-controller;
62 };
63 };