diff options
Diffstat (limited to 'Documentation/powerpc/booting-without-of.txt')
-rw-r--r-- | Documentation/powerpc/booting-without-of.txt | 67 |
1 files changed, 12 insertions, 55 deletions
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index de4063cb4fdc..0ab0230cbcb0 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt | |||
@@ -41,25 +41,14 @@ Table of Contents | |||
41 | VI - System-on-a-chip devices and nodes | 41 | VI - System-on-a-chip devices and nodes |
42 | 1) Defining child nodes of an SOC | 42 | 1) Defining child nodes of an SOC |
43 | 2) Representing devices without a current OF specification | 43 | 2) Representing devices without a current OF specification |
44 | a) MDIO IO device | 44 | a) PHY nodes |
45 | b) Gianfar-compatible ethernet nodes | 45 | b) Interrupt controllers |
46 | c) PHY nodes | 46 | c) CFI or JEDEC memory-mapped NOR flash |
47 | d) Interrupt controllers | 47 | d) 4xx/Axon EMAC ethernet nodes |
48 | e) I2C | 48 | e) Xilinx IP cores |
49 | f) Freescale SOC USB controllers | 49 | f) USB EHCI controllers |
50 | g) Freescale SOC SEC Security Engines | 50 | g) MDIO on GPIOs |
51 | h) Board Control and Status (BCSR) | 51 | h) SPI busses |
52 | i) Freescale QUICC Engine module (QE) | ||
53 | j) CFI or JEDEC memory-mapped NOR flash | ||
54 | k) Global Utilities Block | ||
55 | l) Freescale Communications Processor Module | ||
56 | m) Chipselect/Local Bus | ||
57 | n) 4xx/Axon EMAC ethernet nodes | ||
58 | o) Xilinx IP cores | ||
59 | p) Freescale Synchronous Serial Interface | ||
60 | q) USB EHCI controllers | ||
61 | r) MDIO on GPIOs | ||
62 | s) SPI busses | ||
63 | 52 | ||
64 | VII - Marvell Discovery mv64[345]6x System Controller chips | 53 | VII - Marvell Discovery mv64[345]6x System Controller chips |
65 | 1) The /system-controller node | 54 | 1) The /system-controller node |
@@ -1830,41 +1819,7 @@ platforms are moved over to use the flattened-device-tree model. | |||
1830 | big-endian; | 1819 | big-endian; |
1831 | }; | 1820 | }; |
1832 | 1821 | ||
1833 | r) Freescale Display Interface Unit | 1822 | g) MDIO on GPIOs |
1834 | |||
1835 | The Freescale DIU is a LCD controller, with proper hardware, it can also | ||
1836 | drive DVI monitors. | ||
1837 | |||
1838 | Required properties: | ||
1839 | - compatible : should be "fsl-diu". | ||
1840 | - reg : should contain at least address and length of the DIU register | ||
1841 | set. | ||
1842 | - Interrupts : one DIU interrupt should be describe here. | ||
1843 | |||
1844 | Example (MPC8610HPCD) | ||
1845 | display@2c000 { | ||
1846 | compatible = "fsl,diu"; | ||
1847 | reg = <0x2c000 100>; | ||
1848 | interrupts = <72 2>; | ||
1849 | interrupt-parent = <&mpic>; | ||
1850 | }; | ||
1851 | |||
1852 | s) Freescale on board FPGA | ||
1853 | |||
1854 | This is the memory-mapped registers for on board FPGA. | ||
1855 | |||
1856 | Required properities: | ||
1857 | - compatible : should be "fsl,fpga-pixis". | ||
1858 | - reg : should contain the address and the lenght of the FPPGA register | ||
1859 | set. | ||
1860 | |||
1861 | Example (MPC8610HPCD) | ||
1862 | board-control@e8000000 { | ||
1863 | compatible = "fsl,fpga-pixis"; | ||
1864 | reg = <0xe8000000 32>; | ||
1865 | }; | ||
1866 | |||
1867 | r) MDIO on GPIOs | ||
1868 | 1823 | ||
1869 | Currently defined compatibles: | 1824 | Currently defined compatibles: |
1870 | - virtual,gpio-mdio | 1825 | - virtual,gpio-mdio |
@@ -1884,7 +1839,7 @@ platforms are moved over to use the flattened-device-tree model. | |||
1884 | &qe_pio_c 6>; | 1839 | &qe_pio_c 6>; |
1885 | }; | 1840 | }; |
1886 | 1841 | ||
1887 | s) SPI (Serial Peripheral Interface) busses | 1842 | h) SPI (Serial Peripheral Interface) busses |
1888 | 1843 | ||
1889 | SPI busses can be described with a node for the SPI master device | 1844 | SPI busses can be described with a node for the SPI master device |
1890 | and a set of child nodes for each SPI slave on the bus. For this | 1845 | and a set of child nodes for each SPI slave on the bus. For this |
@@ -1917,6 +1872,8 @@ platforms are moved over to use the flattened-device-tree model. | |||
1917 | inverse clock polarity (CPOL) mode | 1872 | inverse clock polarity (CPOL) mode |
1918 | - spi-cpha - (optional) Empty property indicating device requires | 1873 | - spi-cpha - (optional) Empty property indicating device requires |
1919 | shifted clock phase (CPHA) mode | 1874 | shifted clock phase (CPHA) mode |
1875 | - spi-cs-high - (optional) Empty property indicating device requires | ||
1876 | chip select active high | ||
1920 | 1877 | ||
1921 | SPI example for an MPC5200 SPI bus: | 1878 | SPI example for an MPC5200 SPI bus: |
1922 | spi@f00 { | 1879 | spi@f00 { |