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-rw-r--r--Documentation/memory-barriers.txt14
1 files changed, 12 insertions, 2 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 650657c54733..4e17beba2379 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -1479,7 +1479,8 @@ kernel.
1479 1479
1480Any atomic operation that modifies some state in memory and returns information 1480Any atomic operation that modifies some state in memory and returns information
1481about the state (old or new) implies an SMP-conditional general memory barrier 1481about the state (old or new) implies an SMP-conditional general memory barrier
1482(smp_mb()) on each side of the actual operation. These include: 1482(smp_mb()) on each side of the actual operation (with the exception of
1483explicit lock operations, described later). These include:
1483 1484
1484 xchg(); 1485 xchg();
1485 cmpxchg(); 1486 cmpxchg();
@@ -1536,10 +1537,19 @@ If they're used for constructing a lock of some description, then they probably
1536do need memory barriers as a lock primitive generally has to do things in a 1537do need memory barriers as a lock primitive generally has to do things in a
1537specific order. 1538specific order.
1538 1539
1539
1540Basically, each usage case has to be carefully considered as to whether memory 1540Basically, each usage case has to be carefully considered as to whether memory
1541barriers are needed or not. 1541barriers are needed or not.
1542 1542
1543The following operations are special locking primitives:
1544
1545 test_and_set_bit_lock();
1546 clear_bit_unlock();
1547 __clear_bit_unlock();
1548
1549These implement LOCK-class and UNLOCK-class operations. These should be used in
1550preference to other operations when implementing locking primitives, because
1551their implementations can be optimised on many architectures.
1552
1543[!] Note that special memory barrier primitives are available for these 1553[!] Note that special memory barrier primitives are available for these
1544situations because on some CPUs the atomic instructions used imply full memory 1554situations because on some CPUs the atomic instructions used imply full memory
1545barriers, and so barrier instructions are superfluous in conjunction with them, 1555barriers, and so barrier instructions are superfluous in conjunction with them,