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Diffstat (limited to 'Documentation/memory-barriers.txt')
| -rw-r--r-- | Documentation/memory-barriers.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 46b9b389df35..994355b0cd19 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt | |||
| @@ -670,7 +670,7 @@ effectively random order, despite the write barrier issued by CPU 1: | |||
| 670 | 670 | ||
| 671 | 671 | ||
| 672 | In the above example, CPU 2 perceives that B is 7, despite the load of *C | 672 | In the above example, CPU 2 perceives that B is 7, despite the load of *C |
| 673 | (which would be B) coming after the the LOAD of C. | 673 | (which would be B) coming after the LOAD of C. |
| 674 | 674 | ||
| 675 | If, however, a data dependency barrier were to be placed between the load of C | 675 | If, however, a data dependency barrier were to be placed between the load of C |
| 676 | and the load of *C (ie: B) on CPU 2: | 676 | and the load of *C (ie: B) on CPU 2: |
| @@ -1915,7 +1915,7 @@ Whilst most CPUs do imply a data dependency barrier on the read when a memory | |||
| 1915 | access depends on a read, not all do, so it may not be relied on. | 1915 | access depends on a read, not all do, so it may not be relied on. |
| 1916 | 1916 | ||
| 1917 | Other CPUs may also have split caches, but must coordinate between the various | 1917 | Other CPUs may also have split caches, but must coordinate between the various |
| 1918 | cachelets for normal memory accesss. The semantics of the Alpha removes the | 1918 | cachelets for normal memory accesses. The semantics of the Alpha removes the |
| 1919 | need for coordination in absence of memory barriers. | 1919 | need for coordination in absence of memory barriers. |
| 1920 | 1920 | ||
| 1921 | 1921 | ||