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-rw-r--r--Documentation/i2c/busses/i2c-ali15354
-rw-r--r--Documentation/i2c/busses/i2c-ali15632
-rw-r--r--Documentation/i2c/busses/i2c-ali15x316
-rw-r--r--Documentation/i2c/busses/i2c-pca-isa14
-rw-r--r--Documentation/i2c/busses/i2c-sis559558
-rw-r--r--Documentation/i2c/busses/i2c-sis6308
-rw-r--r--Documentation/i2c/ten-bit-addresses6
7 files changed, 54 insertions, 54 deletions
diff --git a/Documentation/i2c/busses/i2c-ali1535 b/Documentation/i2c/busses/i2c-ali1535
index 0db3b4c74ad1..acbc65a08097 100644
--- a/Documentation/i2c/busses/i2c-ali1535
+++ b/Documentation/i2c/busses/i2c-ali1535
@@ -6,12 +6,12 @@ Supported adapters:
6 http://www.ali.com.tw/eng/support/datasheet_request.php 6 http://www.ali.com.tw/eng/support/datasheet_request.php
7 7
8Authors: 8Authors:
9 Frodo Looijaard <frodol@dds.nl>, 9 Frodo Looijaard <frodol@dds.nl>,
10 Philip Edelbrock <phil@netroedge.com>, 10 Philip Edelbrock <phil@netroedge.com>,
11 Mark D. Studebaker <mdsxyz123@yahoo.com>, 11 Mark D. Studebaker <mdsxyz123@yahoo.com>,
12 Dan Eaton <dan.eaton@rocketlogix.com>, 12 Dan Eaton <dan.eaton@rocketlogix.com>,
13 Stephen Rousset<stephen.rousset@rocketlogix.com> 13 Stephen Rousset<stephen.rousset@rocketlogix.com>
14 14
15Description 15Description
16----------- 16-----------
17 17
diff --git a/Documentation/i2c/busses/i2c-ali1563 b/Documentation/i2c/busses/i2c-ali1563
index 99ad4b9bcc32..54691698d2dd 100644
--- a/Documentation/i2c/busses/i2c-ali1563
+++ b/Documentation/i2c/busses/i2c-ali1563
@@ -18,7 +18,7 @@ For an overview of these chips see http://www.acerlabs.com
18The M1563 southbridge is deceptively similar to the M1533, with a few 18The M1563 southbridge is deceptively similar to the M1533, with a few
19notable exceptions. One of those happens to be the fact they upgraded the 19notable exceptions. One of those happens to be the fact they upgraded the
20i2c core to be SMBus 2.0 compliant, and happens to be almost identical to 20i2c core to be SMBus 2.0 compliant, and happens to be almost identical to
21the i2c controller found in the Intel 801 south bridges. 21the i2c controller found in the Intel 801 south bridges.
22 22
23Features 23Features
24-------- 24--------
diff --git a/Documentation/i2c/busses/i2c-ali15x3 b/Documentation/i2c/busses/i2c-ali15x3
index ff28d381bebe..600da90b8f12 100644
--- a/Documentation/i2c/busses/i2c-ali15x3
+++ b/Documentation/i2c/busses/i2c-ali15x3
@@ -6,8 +6,8 @@ Supported adapters:
6 http://www.ali.com.tw/eng/support/datasheet_request.php 6 http://www.ali.com.tw/eng/support/datasheet_request.php
7 7
8Authors: 8Authors:
9 Frodo Looijaard <frodol@dds.nl>, 9 Frodo Looijaard <frodol@dds.nl>,
10 Philip Edelbrock <phil@netroedge.com>, 10 Philip Edelbrock <phil@netroedge.com>,
11 Mark D. Studebaker <mdsxyz123@yahoo.com> 11 Mark D. Studebaker <mdsxyz123@yahoo.com>
12 12
13Module Parameters 13Module Parameters
@@ -40,10 +40,10 @@ M1541 and M1543C South Bridges.
40The M1543C is a South bridge for desktop systems. 40The M1543C is a South bridge for desktop systems.
41The M1541 is a South bridge for portable systems. 41The M1541 is a South bridge for portable systems.
42They are part of the following ALI chipsets: 42They are part of the following ALI chipsets:
43 43
44 * "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and 44 * "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and
45 100MHz CPU Front Side bus 45 100MHz CPU Front Side bus
46 * "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz 46 * "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
47 CPU Front Side bus 47 CPU Front Side bus
48 Some Aladdin V motherboards: 48 Some Aladdin V motherboards:
49 Asus P5A 49 Asus P5A
@@ -77,7 +77,7 @@ output of lspci will show something similar to the following:
77** then run lspci. 77** then run lspci.
78** If you see the 1533 and 5229 devices but NOT the 7101 device, 78** If you see the 1533 and 5229 devices but NOT the 7101 device,
79** then you must enable ACPI, the PMU, SMB, or something similar 79** then you must enable ACPI, the PMU, SMB, or something similar
80** in the BIOS. 80** in the BIOS.
81** The driver won't work if it can't find the M7101 device. 81** The driver won't work if it can't find the M7101 device.
82 82
83The SMB controller is part of the M7101 device, which is an ACPI-compliant 83The SMB controller is part of the M7101 device, which is an ACPI-compliant
@@ -87,8 +87,8 @@ The whole M7101 device has to be enabled for the SMB to work. You can't
87just enable the SMB alone. The SMB and the ACPI have separate I/O spaces. 87just enable the SMB alone. The SMB and the ACPI have separate I/O spaces.
88We make sure that the SMB is enabled. We leave the ACPI alone. 88We make sure that the SMB is enabled. We leave the ACPI alone.
89 89
90Features 90Features
91-------- 91--------
92 92
93This driver controls the SMB Host only. The SMB Slave 93This driver controls the SMB Host only. The SMB Slave
94controller on the M15X3 is not enabled. This driver does not use 94controller on the M15X3 is not enabled. This driver does not use
diff --git a/Documentation/i2c/busses/i2c-pca-isa b/Documentation/i2c/busses/i2c-pca-isa
index 6fc8f4c27c3c..b044e5265488 100644
--- a/Documentation/i2c/busses/i2c-pca-isa
+++ b/Documentation/i2c/busses/i2c-pca-isa
@@ -1,10 +1,10 @@
1Kernel driver i2c-pca-isa 1Kernel driver i2c-pca-isa
2 2
3Supported adapters: 3Supported adapters:
4This driver supports ISA boards using the Philips PCA 9564 4This driver supports ISA boards using the Philips PCA 9564
5Parallel bus to I2C bus controller 5Parallel bus to I2C bus controller
6 6
7Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems 7Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems
8 8
9Module Parameters 9Module Parameters
10----------------- 10-----------------
@@ -12,12 +12,12 @@ Module Parameters
12* base int 12* base int
13 I/O base address 13 I/O base address
14* irq int 14* irq int
15 IRQ interrupt 15 IRQ interrupt
16* clock int 16* clock int
17 Clock rate as described in table 1 of PCA9564 datasheet 17 Clock rate as described in table 1 of PCA9564 datasheet
18 18
19Description 19Description
20----------- 20-----------
21 21
22This driver supports ISA boards using the Philips PCA 9564 22This driver supports ISA boards using the Philips PCA 9564
23Parallel bus to I2C bus controller 23Parallel bus to I2C bus controller
diff --git a/Documentation/i2c/busses/i2c-sis5595 b/Documentation/i2c/busses/i2c-sis5595
index cc47db7d00a9..ecd21fb49a8f 100644
--- a/Documentation/i2c/busses/i2c-sis5595
+++ b/Documentation/i2c/busses/i2c-sis5595
@@ -1,41 +1,41 @@
1Kernel driver i2c-sis5595 1Kernel driver i2c-sis5595
2 2
3Authors: 3Authors:
4 Frodo Looijaard <frodol@dds.nl>, 4 Frodo Looijaard <frodol@dds.nl>,
5 Mark D. Studebaker <mdsxyz123@yahoo.com>, 5 Mark D. Studebaker <mdsxyz123@yahoo.com>,
6 Philip Edelbrock <phil@netroedge.com> 6 Philip Edelbrock <phil@netroedge.com>
7 7
8Supported adapters: 8Supported adapters:
9 * Silicon Integrated Systems Corp. SiS5595 Southbridge 9 * Silicon Integrated Systems Corp. SiS5595 Southbridge
10 Datasheet: Publicly available at the Silicon Integrated Systems Corp. site. 10 Datasheet: Publicly available at the Silicon Integrated Systems Corp. site.
11 11
12Note: all have mfr. ID 0x1039. 12Note: all have mfr. ID 0x1039.
13 13
14 SUPPORTED PCI ID 14 SUPPORTED PCI ID
15 5595 0008 15 5595 0008
16 16
17 Note: these chips contain a 0008 device which is incompatible with the 17 Note: these chips contain a 0008 device which is incompatible with the
18 5595. We recognize these by the presence of the listed 18 5595. We recognize these by the presence of the listed
19 "blacklist" PCI ID and refuse to load. 19 "blacklist" PCI ID and refuse to load.
20 20
21 NOT SUPPORTED PCI ID BLACKLIST PCI ID 21 NOT SUPPORTED PCI ID BLACKLIST PCI ID
22 540 0008 0540 22 540 0008 0540
23 550 0008 0550 23 550 0008 0550
24 5513 0008 5511 24 5513 0008 5511
25 5581 0008 5597 25 5581 0008 5597
26 5582 0008 5597 26 5582 0008 5597
27 5597 0008 5597 27 5597 0008 5597
28 5598 0008 5597/5598 28 5598 0008 5597/5598
29 630 0008 0630 29 630 0008 0630
30 645 0008 0645 30 645 0008 0645
31 646 0008 0646 31 646 0008 0646
32 648 0008 0648 32 648 0008 0648
33 650 0008 0650 33 650 0008 0650
34 651 0008 0651 34 651 0008 0651
35 730 0008 0730 35 730 0008 0730
36 735 0008 0735 36 735 0008 0735
37 745 0008 0745 37 745 0008 0745
38 746 0008 0746 38 746 0008 0746
39 39
40Module Parameters 40Module Parameters
41----------------- 41-----------------
diff --git a/Documentation/i2c/busses/i2c-sis630 b/Documentation/i2c/busses/i2c-sis630
index 9aca6889f748..629ea2c356fd 100644
--- a/Documentation/i2c/busses/i2c-sis630
+++ b/Documentation/i2c/busses/i2c-sis630
@@ -14,9 +14,9 @@ Module Parameters
14* force = [1|0] Forcibly enable the SIS630. DANGEROUS! 14* force = [1|0] Forcibly enable the SIS630. DANGEROUS!
15 This can be interesting for chipsets not named 15 This can be interesting for chipsets not named
16 above to check if it works for you chipset, but DANGEROUS! 16 above to check if it works for you chipset, but DANGEROUS!
17 17
18* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default, 18* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
19 what your BIOS use). DANGEROUS! This should be a bit 19 what your BIOS use). DANGEROUS! This should be a bit
20 faster, but freeze some systems (i.e. my Laptop). 20 faster, but freeze some systems (i.e. my Laptop).
21 21
22 22
@@ -44,6 +44,6 @@ Philip Edelbrock <phil@netroedge.com>
44- testing SiS730 support 44- testing SiS730 support
45Mark M. Hoffman <mhoffman@lightlink.com> 45Mark M. Hoffman <mhoffman@lightlink.com>
46- bug fixes 46- bug fixes
47 47
48To anyone else which I forgot here ;), thanks! 48To anyone else which I forgot here ;), thanks!
49 49
diff --git a/Documentation/i2c/ten-bit-addresses b/Documentation/i2c/ten-bit-addresses
index 200074f81360..e9890709c508 100644
--- a/Documentation/i2c/ten-bit-addresses
+++ b/Documentation/i2c/ten-bit-addresses
@@ -1,17 +1,17 @@
1The I2C protocol knows about two kinds of device addresses: normal 7 bit 1The I2C protocol knows about two kinds of device addresses: normal 7 bit
2addresses, and an extended set of 10 bit addresses. The sets of addresses 2addresses, and an extended set of 10 bit addresses. The sets of addresses
3do not intersect: the 7 bit address 0x10 is not the same as the 10 bit 3do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
4address 0x10 (though a single device could respond to both of them). You 4address 0x10 (though a single device could respond to both of them). You
5select a 10 bit address by adding an extra byte after the address 5select a 10 bit address by adding an extra byte after the address
6byte: 6byte:
7 S Addr7 Rd/Wr .... 7 S Addr7 Rd/Wr ....
8becomes 8becomes
9 S 11110 Addr10 Rd/Wr 9 S 11110 Addr10 Rd/Wr
10S is the start bit, Rd/Wr the read/write bit, and if you count the number 10S is the start bit, Rd/Wr the read/write bit, and if you count the number
11of bits, you will see the there are 8 after the S bit for 7 bit addresses, 11of bits, you will see the there are 8 after the S bit for 7 bit addresses,
12and 16 after the S bit for 10 bit addresses. 12and 16 after the S bit for 10 bit addresses.
13 13
14WARNING! The current 10 bit address support is EXPERIMENTAL. There are 14WARNING! The current 10 bit address support is EXPERIMENTAL. There are
15several places in the code that will cause SEVERE PROBLEMS with 10 bit 15several places in the code that will cause SEVERE PROBLEMS with 10 bit
16addresses, even though there is some basic handling and hooks. Also, 16addresses, even though there is some basic handling and hooks. Also,
17almost no supported adapter handles the 10 bit addresses correctly. 17almost no supported adapter handles the 10 bit addresses correctly.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 14:21:20 -0500