diff options
Diffstat (limited to 'Documentation/devicetree')
378 files changed, 11394 insertions, 631 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt new file mode 100644 index 000000000000..d0ce01da5c59 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] | ||
2 | The EDAC accesses a range of registers in the SDRAM controller. | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : should contain "altr,sdram-edac"; | ||
6 | - altr,sdr-syscon : phandle of the sdr module | ||
7 | - interrupts : Should contain the SDRAM ECC IRQ in the | ||
8 | appropriate format for the IRQ controller. | ||
9 | |||
10 | Example: | ||
11 | sdramedac { | ||
12 | compatible = "altr,sdram-edac"; | ||
13 | altr,sdr-syscon = <&sdr>; | ||
14 | interrupts = <0 39 4>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt new file mode 100644 index 000000000000..8fe815046140 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amlogic.txt | |||
@@ -0,0 +1,10 @@ | |||
1 | Amlogic MesonX device tree bindings | ||
2 | ------------------------------------------- | ||
3 | |||
4 | Boards with the Amlogic Meson6 SoC shall have the following properties: | ||
5 | Required root node property: | ||
6 | compatible: "amlogic,meson6" | ||
7 | |||
8 | Boards with the Amlogic Meson8 SoC shall have the following properties: | ||
9 | Required root node property: | ||
10 | compatible: "amlogic,meson8"; | ||
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index 37b2cafa4e52..256b4d8bab7b 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt | |||
@@ -22,6 +22,14 @@ to deliver its interrupts via SPIs. | |||
22 | - always-on : a boolean property. If present, the timer is powered through an | 22 | - always-on : a boolean property. If present, the timer is powered through an |
23 | always-on power domain, therefore it never loses context. | 23 | always-on power domain, therefore it never loses context. |
24 | 24 | ||
25 | ** Optional properties: | ||
26 | |||
27 | - arm,cpu-registers-not-fw-configured : Firmware does not initialize | ||
28 | any of the generic timer CPU registers, which contain their | ||
29 | architecturally-defined reset values. Only supported for 32-bit | ||
30 | systems which follow the ARMv7 architected reset values. | ||
31 | |||
32 | |||
25 | Example: | 33 | Example: |
26 | 34 | ||
27 | timer { | 35 | timer { |
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index c554ed3d44fb..556c8665fdbf 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards | |||
@@ -92,3 +92,68 @@ Required nodes: | |||
92 | - core-module: the root node to the Versatile platforms must have | 92 | - core-module: the root node to the Versatile platforms must have |
93 | a core-module with regs and the compatible strings | 93 | a core-module with regs and the compatible strings |
94 | "arm,core-module-versatile", "syscon" | 94 | "arm,core-module-versatile", "syscon" |
95 | |||
96 | ARM RealView Boards | ||
97 | ------------------- | ||
98 | The RealView boards cover tailored evaluation boards that are used to explore | ||
99 | the ARM11 and Cortex A-8 and Cortex A-9 processors. | ||
100 | |||
101 | Required properties (in root node): | ||
102 | /* RealView Emulation Baseboard */ | ||
103 | compatible = "arm,realview-eb"; | ||
104 | /* RealView Platform Baseboard for ARM1176JZF-S */ | ||
105 | compatible = "arm,realview-pb1176"; | ||
106 | /* RealView Platform Baseboard for ARM11 MPCore */ | ||
107 | compatible = "arm,realview-pb11mp"; | ||
108 | /* RealView Platform Baseboard for Cortex A-8 */ | ||
109 | compatible = "arm,realview-pba8"; | ||
110 | /* RealView Platform Baseboard Explore for Cortex A-9 */ | ||
111 | compatible = "arm,realview-pbx"; | ||
112 | |||
113 | Required nodes: | ||
114 | |||
115 | - soc: some node of the RealView platforms must be the SoC | ||
116 | node that contain the SoC-specific devices, withe the compatible | ||
117 | string set to one of these tuples: | ||
118 | "arm,realview-eb-soc", "simple-bus" | ||
119 | "arm,realview-pb1176-soc", "simple-bus" | ||
120 | "arm,realview-pb11mp-soc", "simple-bus" | ||
121 | "arm,realview-pba8-soc", "simple-bus" | ||
122 | "arm,realview-pbx-soc", "simple-bus" | ||
123 | |||
124 | - syscon: some subnode of the RealView SoC node must be a | ||
125 | system controller node pointing to the control registers, | ||
126 | with the compatible string set to one of these tuples: | ||
127 | "arm,realview-eb-syscon", "syscon" | ||
128 | "arm,realview-pb1176-syscon", "syscon" | ||
129 | "arm,realview-pb11mp-syscon", "syscon" | ||
130 | "arm,realview-pba8-syscon", "syscon" | ||
131 | "arm,realview-pbx-syscon", "syscon" | ||
132 | |||
133 | Required properties for the system controller: | ||
134 | - regs: the location and size of the system controller registers, | ||
135 | one range of 0x1000 bytes. | ||
136 | |||
137 | Example: | ||
138 | |||
139 | /dts-v1/; | ||
140 | #include <dt-bindings/interrupt-controller/irq.h> | ||
141 | #include "skeleton.dtsi" | ||
142 | |||
143 | / { | ||
144 | model = "ARM RealView PB1176 with device tree"; | ||
145 | compatible = "arm,realview-pb1176"; | ||
146 | |||
147 | soc { | ||
148 | #address-cells = <1>; | ||
149 | #size-cells = <1>; | ||
150 | compatible = "arm,realview-pb1176-soc", "simple-bus"; | ||
151 | ranges; | ||
152 | |||
153 | syscon: syscon@10000000 { | ||
154 | compatible = "arm,realview-syscon", "syscon"; | ||
155 | reg = <0x10000000 0x1000>; | ||
156 | }; | ||
157 | |||
158 | }; | ||
159 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 16f60b41c147..562cda9d86d9 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt | |||
@@ -1,6 +1,43 @@ | |||
1 | Atmel AT91 device tree bindings. | 1 | Atmel AT91 device tree bindings. |
2 | ================================ | 2 | ================================ |
3 | 3 | ||
4 | Boards with a SoC of the Atmel AT91 or SMART family shall have the following | ||
5 | properties: | ||
6 | |||
7 | Required root node properties: | ||
8 | compatible: must be one of: | ||
9 | * "atmel,at91rm9200" | ||
10 | |||
11 | * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with | ||
12 | the specific SoC family or compatible: | ||
13 | o "atmel,at91sam9260" | ||
14 | o "atmel,at91sam9261" | ||
15 | o "atmel,at91sam9263" | ||
16 | o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific | ||
17 | SoC compatible: | ||
18 | - "atmel,at91sam9g15" | ||
19 | - "atmel,at91sam9g25" | ||
20 | - "atmel,at91sam9g35" | ||
21 | - "atmel,at91sam9x25" | ||
22 | - "atmel,at91sam9x35" | ||
23 | o "atmel,at91sam9g20" | ||
24 | o "atmel,at91sam9g45" | ||
25 | o "atmel,at91sam9n12" | ||
26 | o "atmel,at91sam9rl" | ||
27 | * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific | ||
28 | SoC family: | ||
29 | o "atmel,sama5d3" shall be extended with the specific SoC compatible: | ||
30 | - "atmel,sama5d31" | ||
31 | - "atmel,sama5d33" | ||
32 | - "atmel,sama5d34" | ||
33 | - "atmel,sama5d35" | ||
34 | - "atmel,sama5d36" | ||
35 | o "atmel,sama5d4" shall be extended with the specific SoC compatible: | ||
36 | - "atmel,sama5d41" | ||
37 | - "atmel,sama5d42" | ||
38 | - "atmel,sama5d43" | ||
39 | - "atmel,sama5d44" | ||
40 | |||
4 | PIT Timer required properties: | 41 | PIT Timer required properties: |
5 | - compatible: Should be "atmel,at91sam9260-pit" | 42 | - compatible: Should be "atmel,at91sam9260-pit" |
6 | - reg: Should contain registers location and length | 43 | - reg: Should contain registers location and length |
@@ -61,8 +98,8 @@ RAMC SDRAM/DDR Controller required properties: | |||
61 | - compatible: Should be "atmel,at91rm9200-sdramc", | 98 | - compatible: Should be "atmel,at91rm9200-sdramc", |
62 | "atmel,at91sam9260-sdramc", | 99 | "atmel,at91sam9260-sdramc", |
63 | "atmel,at91sam9g45-ddramc", | 100 | "atmel,at91sam9g45-ddramc", |
101 | "atmel,sama5d3-ddramc", | ||
64 | - reg: Should contain registers location and length | 102 | - reg: Should contain registers location and length |
65 | For at91sam9263 and at91sam9g45 you must specify 2 entries. | ||
66 | 103 | ||
67 | Examples: | 104 | Examples: |
68 | 105 | ||
@@ -71,12 +108,6 @@ Examples: | |||
71 | reg = <0xffffe800 0x200>; | 108 | reg = <0xffffe800 0x200>; |
72 | }; | 109 | }; |
73 | 110 | ||
74 | ramc0: ramc@ffffe400 { | ||
75 | compatible = "atmel,at91sam9g45-ddramc"; | ||
76 | reg = <0xffffe400 0x200 | ||
77 | 0xffffe600 0x200>; | ||
78 | }; | ||
79 | |||
80 | SHDWC Shutdown Controller | 111 | SHDWC Shutdown Controller |
81 | 112 | ||
82 | required properties: | 113 | required properties: |
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt new file mode 100644 index 000000000000..bd49987a8812 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt | |||
@@ -0,0 +1,9 @@ | |||
1 | Broadcom BCM63138 DSL System-on-a-Chip device tree bindings | ||
2 | ----------------------------------------------------------- | ||
3 | |||
4 | Boards compatible with the BCM63138 DSL System-on-a-Chip should have the | ||
5 | following properties: | ||
6 | |||
7 | Required root node property: | ||
8 | |||
9 | compatible: should be "brcm,bcm63138" | ||
diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt new file mode 100644 index 000000000000..4c77169bb534 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt | |||
@@ -0,0 +1,31 @@ | |||
1 | Broadcom Cygnus device tree bindings | ||
2 | ------------------------------------ | ||
3 | |||
4 | |||
5 | Boards with Cygnus SoCs shall have the following properties: | ||
6 | |||
7 | Required root node property: | ||
8 | |||
9 | BCM11300 | ||
10 | compatible = "brcm,bcm11300", "brcm,cygnus"; | ||
11 | |||
12 | BCM11320 | ||
13 | compatible = "brcm,bcm11320", "brcm,cygnus"; | ||
14 | |||
15 | BCM11350 | ||
16 | compatible = "brcm,bcm11350", "brcm,cygnus"; | ||
17 | |||
18 | BCM11360 | ||
19 | compatible = "brcm,bcm11360", "brcm,cygnus"; | ||
20 | |||
21 | BCM58300 | ||
22 | compatible = "brcm,bcm58300", "brcm,cygnus"; | ||
23 | |||
24 | BCM58302 | ||
25 | compatible = "brcm,bcm58302", "brcm,cygnus"; | ||
26 | |||
27 | BCM58303 | ||
28 | compatible = "brcm,bcm58303", "brcm,cygnus"; | ||
29 | |||
30 | BCM58305 | ||
31 | compatible = "brcm,bcm58305", "brcm,cygnus"; | ||
diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt new file mode 100644 index 000000000000..6f63a5866902 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt | |||
@@ -0,0 +1,10 @@ | |||
1 | Cavium Thunder platform device tree bindings | ||
2 | -------------------------------------------- | ||
3 | |||
4 | Boards with Cavium's Thunder SoC shall have following properties. | ||
5 | |||
6 | Root Node | ||
7 | --------- | ||
8 | Required root node properties: | ||
9 | |||
10 | - compatible = "cavium,thunder-88xx"; | ||
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt new file mode 100644 index 000000000000..d790f49066f3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight.txt | |||
@@ -0,0 +1,204 @@ | |||
1 | * CoreSight Components: | ||
2 | |||
3 | CoreSight components are compliant with the ARM CoreSight architecture | ||
4 | specification and can be connected in various topologies to suit a particular | ||
5 | SoCs tracing needs. These trace components can generally be classified as | ||
6 | sinks, links and sources. Trace data produced by one or more sources flows | ||
7 | through the intermediate links connecting the source to the currently selected | ||
8 | sink. Each CoreSight component device should use these properties to describe | ||
9 | its hardware characteristcs. | ||
10 | |||
11 | * Required properties for all components *except* non-configurable replicators: | ||
12 | |||
13 | * compatible: These have to be supplemented with "arm,primecell" as | ||
14 | drivers are using the AMBA bus interface. Possible values include: | ||
15 | - "arm,coresight-etb10", "arm,primecell"; | ||
16 | - "arm,coresight-tpiu", "arm,primecell"; | ||
17 | - "arm,coresight-tmc", "arm,primecell"; | ||
18 | - "arm,coresight-funnel", "arm,primecell"; | ||
19 | - "arm,coresight-etm3x", "arm,primecell"; | ||
20 | |||
21 | * reg: physical base address and length of the register | ||
22 | set(s) of the component. | ||
23 | |||
24 | * clocks: the clock associated to this component. | ||
25 | |||
26 | * clock-names: the name of the clock as referenced by the code. | ||
27 | Since we are using the AMBA framework, the name should be | ||
28 | "apb_pclk". | ||
29 | |||
30 | * port or ports: The representation of the component's port | ||
31 | layout using the generic DT graph presentation found in | ||
32 | "bindings/graph.txt". | ||
33 | |||
34 | * Required properties for devices that don't show up on the AMBA bus, such as | ||
35 | non-configurable replicators: | ||
36 | |||
37 | * compatible: Currently supported value is (note the absence of the | ||
38 | AMBA markee): | ||
39 | - "arm,coresight-replicator" | ||
40 | |||
41 | * id: a unique number that will identify this replicator. | ||
42 | |||
43 | * port or ports: same as above. | ||
44 | |||
45 | * Optional properties for ETM/PTMs: | ||
46 | |||
47 | * arm,cp14: must be present if the system accesses ETM/PTM management | ||
48 | registers via co-processor 14. | ||
49 | |||
50 | * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the | ||
51 | source is considered to belong to CPU0. | ||
52 | |||
53 | * Optional property for TMC: | ||
54 | |||
55 | * arm,buffer-size: size of contiguous buffer space for TMC ETR | ||
56 | (embedded trace router) | ||
57 | |||
58 | |||
59 | Example: | ||
60 | |||
61 | 1. Sinks | ||
62 | etb@20010000 { | ||
63 | compatible = "arm,coresight-etb10", "arm,primecell"; | ||
64 | reg = <0 0x20010000 0 0x1000>; | ||
65 | |||
66 | coresight-default-sink; | ||
67 | clocks = <&oscclk6a>; | ||
68 | clock-names = "apb_pclk"; | ||
69 | port { | ||
70 | etb_in_port: endpoint@0 { | ||
71 | slave-mode; | ||
72 | remote-endpoint = <&replicator_out_port0>; | ||
73 | }; | ||
74 | }; | ||
75 | }; | ||
76 | |||
77 | tpiu@20030000 { | ||
78 | compatible = "arm,coresight-tpiu", "arm,primecell"; | ||
79 | reg = <0 0x20030000 0 0x1000>; | ||
80 | |||
81 | clocks = <&oscclk6a>; | ||
82 | clock-names = "apb_pclk"; | ||
83 | port { | ||
84 | tpiu_in_port: endpoint@0 { | ||
85 | slave-mode; | ||
86 | remote-endpoint = <&replicator_out_port1>; | ||
87 | }; | ||
88 | }; | ||
89 | }; | ||
90 | |||
91 | 2. Links | ||
92 | replicator { | ||
93 | /* non-configurable replicators don't show up on the | ||
94 | * AMBA bus. As such no need to add "arm,primecell". | ||
95 | */ | ||
96 | compatible = "arm,coresight-replicator"; | ||
97 | /* this will show up in debugfs as "0.replicator" */ | ||
98 | id = <0>; | ||
99 | |||
100 | ports { | ||
101 | #address-cells = <1>; | ||
102 | #size-cells = <0>; | ||
103 | |||
104 | /* replicator output ports */ | ||
105 | port@0 { | ||
106 | reg = <0>; | ||
107 | replicator_out_port0: endpoint { | ||
108 | remote-endpoint = <&etb_in_port>; | ||
109 | }; | ||
110 | }; | ||
111 | |||
112 | port@1 { | ||
113 | reg = <1>; | ||
114 | replicator_out_port1: endpoint { | ||
115 | remote-endpoint = <&tpiu_in_port>; | ||
116 | }; | ||
117 | }; | ||
118 | |||
119 | /* replicator input port */ | ||
120 | port@2 { | ||
121 | reg = <0>; | ||
122 | replicator_in_port0: endpoint { | ||
123 | slave-mode; | ||
124 | remote-endpoint = <&funnel_out_port0>; | ||
125 | }; | ||
126 | }; | ||
127 | }; | ||
128 | }; | ||
129 | |||
130 | funnel@20040000 { | ||
131 | compatible = "arm,coresight-funnel", "arm,primecell"; | ||
132 | reg = <0 0x20040000 0 0x1000>; | ||
133 | |||
134 | clocks = <&oscclk6a>; | ||
135 | clock-names = "apb_pclk"; | ||
136 | ports { | ||
137 | #address-cells = <1>; | ||
138 | #size-cells = <0>; | ||
139 | |||
140 | /* funnel output port */ | ||
141 | port@0 { | ||
142 | reg = <0>; | ||
143 | funnel_out_port0: endpoint { | ||
144 | remote-endpoint = | ||
145 | <&replicator_in_port0>; | ||
146 | }; | ||
147 | }; | ||
148 | |||
149 | /* funnel input ports */ | ||
150 | port@1 { | ||
151 | reg = <0>; | ||
152 | funnel_in_port0: endpoint { | ||
153 | slave-mode; | ||
154 | remote-endpoint = <&ptm0_out_port>; | ||
155 | }; | ||
156 | }; | ||
157 | |||
158 | port@2 { | ||
159 | reg = <1>; | ||
160 | funnel_in_port1: endpoint { | ||
161 | slave-mode; | ||
162 | remote-endpoint = <&ptm1_out_port>; | ||
163 | }; | ||
164 | }; | ||
165 | |||
166 | port@3 { | ||
167 | reg = <2>; | ||
168 | funnel_in_port2: endpoint { | ||
169 | slave-mode; | ||
170 | remote-endpoint = <&etm0_out_port>; | ||
171 | }; | ||
172 | }; | ||
173 | |||
174 | }; | ||
175 | }; | ||
176 | |||
177 | 3. Sources | ||
178 | ptm@2201c000 { | ||
179 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
180 | reg = <0 0x2201c000 0 0x1000>; | ||
181 | |||
182 | cpu = <&cpu0>; | ||
183 | clocks = <&oscclk6a>; | ||
184 | clock-names = "apb_pclk"; | ||
185 | port { | ||
186 | ptm0_out_port: endpoint { | ||
187 | remote-endpoint = <&funnel_in_port0>; | ||
188 | }; | ||
189 | }; | ||
190 | }; | ||
191 | |||
192 | ptm@2201d000 { | ||
193 | compatible = "arm,coresight-etm3x", "arm,primecell"; | ||
194 | reg = <0 0x2201d000 0 0x1000>; | ||
195 | |||
196 | cpu = <&cpu1>; | ||
197 | clocks = <&oscclk6a>; | ||
198 | clock-names = "apb_pclk"; | ||
199 | port { | ||
200 | ptm1_out_port: endpoint { | ||
201 | remote-endpoint = <&funnel_in_port1>; | ||
202 | }; | ||
203 | }; | ||
204 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index 298e2f6b33c6..b2aacbe16ed9 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt | |||
@@ -166,6 +166,7 @@ nodes to be present and contain the properties described below. | |||
166 | "arm,cortex-r5" | 166 | "arm,cortex-r5" |
167 | "arm,cortex-r7" | 167 | "arm,cortex-r7" |
168 | "brcm,brahma-b15" | 168 | "brcm,brahma-b15" |
169 | "cavium,thunder" | ||
169 | "faraday,fa526" | 170 | "faraday,fa526" |
170 | "intel,sa110" | 171 | "intel,sa110" |
171 | "intel,sa1100" | 172 | "intel,sa1100" |
@@ -219,6 +220,21 @@ nodes to be present and contain the properties described below. | |||
219 | Value type: <phandle> | 220 | Value type: <phandle> |
220 | Definition: Specifies the ACC[2] node associated with this CPU. | 221 | Definition: Specifies the ACC[2] node associated with this CPU. |
221 | 222 | ||
223 | - cpu-idle-states | ||
224 | Usage: Optional | ||
225 | Value type: <prop-encoded-array> | ||
226 | Definition: | ||
227 | # List of phandles to idle state nodes supported | ||
228 | by this cpu [3]. | ||
229 | |||
230 | - rockchip,pmu | ||
231 | Usage: optional for systems that have an "enable-method" | ||
232 | property value of "rockchip,rk3066-smp" | ||
233 | While optional, it is the preferred way to get access to | ||
234 | the cpu-core power-domains. | ||
235 | Value type: <phandle> | ||
236 | Definition: Specifies the syscon node controlling the cpu core | ||
237 | power domains. | ||
222 | 238 | ||
223 | Example 1 (dual-cluster big.LITTLE system 32-bit): | 239 | Example 1 (dual-cluster big.LITTLE system 32-bit): |
224 | 240 | ||
@@ -415,3 +431,5 @@ cpus { | |||
415 | -- | 431 | -- |
416 | [1] arm/msm/qcom,saw2.txt | 432 | [1] arm/msm/qcom,saw2.txt |
417 | [2] arm/msm/qcom,kpss-acc.txt | 433 | [2] arm/msm/qcom,kpss-acc.txt |
434 | [3] ARM Linux kernel documentation - idle states bindings | ||
435 | Documentation/devicetree/bindings/arm/idle-states.txt | ||
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index 8b4f7b7fe88b..abde1ea8a119 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt | |||
@@ -8,6 +8,8 @@ Required Properties: | |||
8 | * samsung,exynos4210-pd - for exynos4210 type power domain. | 8 | * samsung,exynos4210-pd - for exynos4210 type power domain. |
9 | - reg: physical base address of the controller and length of memory mapped | 9 | - reg: physical base address of the controller and length of memory mapped |
10 | region. | 10 | region. |
11 | - #power-domain-cells: number of cells in power domain specifier; | ||
12 | must be 0. | ||
11 | 13 | ||
12 | Optional Properties: | 14 | Optional Properties: |
13 | - clocks: List of clock handles. The parent clocks of the input clocks to the | 15 | - clocks: List of clock handles. The parent clocks of the input clocks to the |
@@ -29,6 +31,7 @@ Example: | |||
29 | lcd0: power-domain-lcd0 { | 31 | lcd0: power-domain-lcd0 { |
30 | compatible = "samsung,exynos4210-pd"; | 32 | compatible = "samsung,exynos4210-pd"; |
31 | reg = <0x10023C00 0x10>; | 33 | reg = <0x10023C00 0x10>; |
34 | #power-domain-cells = <0>; | ||
32 | }; | 35 | }; |
33 | 36 | ||
34 | mfc_pd: power-domain@10044060 { | 37 | mfc_pd: power-domain@10044060 { |
@@ -37,12 +40,8 @@ Example: | |||
37 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, | 40 | clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, |
38 | <&clock CLK_MOUT_USER_ACLK333>; | 41 | <&clock CLK_MOUT_USER_ACLK333>; |
39 | clock-names = "oscclk", "pclk0", "clk0"; | 42 | clock-names = "oscclk", "pclk0", "clk0"; |
43 | #power-domain-cells = <0>; | ||
40 | }; | 44 | }; |
41 | 45 | ||
42 | Example of the node using power domain: | 46 | See Documentation/devicetree/bindings/power/power_domain.txt for description |
43 | 47 | of consumer-side bindings. | |
44 | node { | ||
45 | /* ... */ | ||
46 | samsung,power-domain = <&lcd0>; | ||
47 | /* ... */ | ||
48 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt index e935d7d4ac43..4e8b7df7fc62 100644 --- a/Documentation/devicetree/bindings/arm/fsl.txt +++ b/Documentation/devicetree/bindings/arm/fsl.txt | |||
@@ -74,3 +74,41 @@ Required root node properties: | |||
74 | i.MX6q generic board | 74 | i.MX6q generic board |
75 | Required root node properties: | 75 | Required root node properties: |
76 | - compatible = "fsl,imx6q"; | 76 | - compatible = "fsl,imx6q"; |
77 | |||
78 | |||
79 | Freescale LS1021A Platform Device Tree Bindings | ||
80 | ------------------------------------------------ | ||
81 | |||
82 | Required root node compatible properties: | ||
83 | - compatible = "fsl,ls1021a"; | ||
84 | |||
85 | Freescale LS1021A SoC-specific Device Tree Bindings | ||
86 | ------------------------------------------- | ||
87 | |||
88 | Freescale SCFG | ||
89 | SCFG is the supplemental configuration unit, that provides SoC specific | ||
90 | configuration and status registers for the chip. Such as getting PEX port | ||
91 | status. | ||
92 | Required properties: | ||
93 | - compatible: should be "fsl,ls1021a-scfg" | ||
94 | - reg: should contain base address and length of SCFG memory-mapped registers | ||
95 | |||
96 | Example: | ||
97 | scfg: scfg@1570000 { | ||
98 | compatible = "fsl,ls1021a-scfg"; | ||
99 | reg = <0x0 0x1570000 0x0 0x10000>; | ||
100 | }; | ||
101 | |||
102 | Freescale DCFG | ||
103 | DCFG is the device configuration unit, that provides general purpose | ||
104 | configuration and status for the device. Such as setting the secondary | ||
105 | core start address and release the secondary core from holdoff and startup. | ||
106 | Required properties: | ||
107 | - compatible: should be "fsl,ls1021a-dcfg" | ||
108 | - reg : should contain base address and length of DCFG memory-mapped registers | ||
109 | |||
110 | Example: | ||
111 | dcfg: dcfg@1ee0000 { | ||
112 | compatible = "fsl,ls1021a-dcfg"; | ||
113 | reg = <0x0 0x1ee0000 0x0 0x10000>; | ||
114 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/geniatech.txt b/Documentation/devicetree/bindings/arm/geniatech.txt new file mode 100644 index 000000000000..74ccba40b73b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/geniatech.txt | |||
@@ -0,0 +1,5 @@ | |||
1 | Geniatech platforms device tree bindings | ||
2 | ------------------------------------------- | ||
3 | |||
4 | Geniatech ATV1200 | ||
5 | - compatible = "geniatech,atv1200" | ||
diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt index 33cd05e6c125..ddfade40ac59 100644 --- a/Documentation/devicetree/bindings/arm/gic-v3.txt +++ b/Documentation/devicetree/bindings/arm/gic-v3.txt | |||
@@ -49,11 +49,29 @@ Optional | |||
49 | occupied by the redistributors. Required if more than one such | 49 | occupied by the redistributors. Required if more than one such |
50 | region is present. | 50 | region is present. |
51 | 51 | ||
52 | Sub-nodes: | ||
53 | |||
54 | GICv3 has one or more Interrupt Translation Services (ITS) that are | ||
55 | used to route Message Signalled Interrupts (MSI) to the CPUs. | ||
56 | |||
57 | These nodes must have the following properties: | ||
58 | - compatible : Should at least contain "arm,gic-v3-its". | ||
59 | - msi-controller : Boolean property. Identifies the node as an MSI controller | ||
60 | - reg: Specifies the base physical address and size of the ITS | ||
61 | registers. | ||
62 | |||
63 | The main GIC node must contain the appropriate #address-cells, | ||
64 | #size-cells and ranges properties for the reg property of all ITS | ||
65 | nodes. | ||
66 | |||
52 | Examples: | 67 | Examples: |
53 | 68 | ||
54 | gic: interrupt-controller@2cf00000 { | 69 | gic: interrupt-controller@2cf00000 { |
55 | compatible = "arm,gic-v3"; | 70 | compatible = "arm,gic-v3"; |
56 | #interrupt-cells = <3>; | 71 | #interrupt-cells = <3>; |
72 | #address-cells = <2>; | ||
73 | #size-cells = <2>; | ||
74 | ranges; | ||
57 | interrupt-controller; | 75 | interrupt-controller; |
58 | reg = <0x0 0x2f000000 0 0x10000>, // GICD | 76 | reg = <0x0 0x2f000000 0 0x10000>, // GICD |
59 | <0x0 0x2f100000 0 0x200000>, // GICR | 77 | <0x0 0x2f100000 0 0x200000>, // GICR |
@@ -61,11 +79,20 @@ Examples: | |||
61 | <0x0 0x2c010000 0 0x2000>, // GICH | 79 | <0x0 0x2c010000 0 0x2000>, // GICH |
62 | <0x0 0x2c020000 0 0x2000>; // GICV | 80 | <0x0 0x2c020000 0 0x2000>; // GICV |
63 | interrupts = <1 9 4>; | 81 | interrupts = <1 9 4>; |
82 | |||
83 | gic-its@2c200000 { | ||
84 | compatible = "arm,gic-v3-its"; | ||
85 | msi-controller; | ||
86 | reg = <0x0 0x2c200000 0 0x200000>; | ||
87 | }; | ||
64 | }; | 88 | }; |
65 | 89 | ||
66 | gic: interrupt-controller@2c010000 { | 90 | gic: interrupt-controller@2c010000 { |
67 | compatible = "arm,gic-v3"; | 91 | compatible = "arm,gic-v3"; |
68 | #interrupt-cells = <3>; | 92 | #interrupt-cells = <3>; |
93 | #address-cells = <2>; | ||
94 | #size-cells = <2>; | ||
95 | ranges; | ||
69 | interrupt-controller; | 96 | interrupt-controller; |
70 | redistributor-stride = <0x0 0x40000>; // 256kB stride | 97 | redistributor-stride = <0x0 0x40000>; // 256kB stride |
71 | #redistributor-regions = <2>; | 98 | #redistributor-regions = <2>; |
@@ -76,4 +103,16 @@ Examples: | |||
76 | <0x0 0x2c060000 0 0x2000>, // GICH | 103 | <0x0 0x2c060000 0 0x2000>, // GICH |
77 | <0x0 0x2c080000 0 0x2000>; // GICV | 104 | <0x0 0x2c080000 0 0x2000>; // GICV |
78 | interrupts = <1 9 4>; | 105 | interrupts = <1 9 4>; |
106 | |||
107 | gic-its@2c200000 { | ||
108 | compatible = "arm,gic-v3-its"; | ||
109 | msi-controller; | ||
110 | reg = <0x0 0x2c200000 0 0x200000>; | ||
111 | }; | ||
112 | |||
113 | gic-its@2c400000 { | ||
114 | compatible = "arm,gic-v3-its"; | ||
115 | msi-controller; | ||
116 | reg = <0x0 0x2c400000 0 0x200000>; | ||
117 | }; | ||
79 | }; | 118 | }; |
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt index c7d2fa156678..8112d0c3675a 100644 --- a/Documentation/devicetree/bindings/arm/gic.txt +++ b/Documentation/devicetree/bindings/arm/gic.txt | |||
@@ -17,6 +17,7 @@ Main node required properties: | |||
17 | "arm,cortex-a7-gic" | 17 | "arm,cortex-a7-gic" |
18 | "arm,arm11mp-gic" | 18 | "arm,arm11mp-gic" |
19 | "brcm,brahma-b15-gic" | 19 | "brcm,brahma-b15-gic" |
20 | "arm,arm1176jzf-devchip-gic" | ||
20 | - interrupt-controller : Identifies the node as an interrupt controller | 21 | - interrupt-controller : Identifies the node as an interrupt controller |
21 | - #interrupt-cells : Specifies the number of cells needed to encode an | 22 | - #interrupt-cells : Specifies the number of cells needed to encode an |
22 | interrupt source. The type shall be a <u32> and the value shall be 3. | 23 | interrupt source. The type shall be a <u32> and the value shall be 3. |
@@ -96,3 +97,56 @@ Example: | |||
96 | <0x2c006000 0x2000>; | 97 | <0x2c006000 0x2000>; |
97 | interrupts = <1 9 0xf04>; | 98 | interrupts = <1 9 0xf04>; |
98 | }; | 99 | }; |
100 | |||
101 | |||
102 | * GICv2m extension for MSI/MSI-x support (Optional) | ||
103 | |||
104 | Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). | ||
105 | This is enabled by specifying v2m sub-node(s). | ||
106 | |||
107 | Required properties: | ||
108 | |||
109 | - compatible : The value here should contain "arm,gic-v2m-frame". | ||
110 | |||
111 | - msi-controller : Identifies the node as an MSI controller. | ||
112 | |||
113 | - reg : GICv2m MSI interface register base and size | ||
114 | |||
115 | Optional properties: | ||
116 | |||
117 | - arm,msi-base-spi : When the MSI_TYPER register contains an incorrect | ||
118 | value, this property should contain the SPI base of | ||
119 | the MSI frame, overriding the HW value. | ||
120 | |||
121 | - arm,msi-num-spis : When the MSI_TYPER register contains an incorrect | ||
122 | value, this property should contain the number of | ||
123 | SPIs assigned to the frame, overriding the HW value. | ||
124 | |||
125 | Example: | ||
126 | |||
127 | interrupt-controller@e1101000 { | ||
128 | compatible = "arm,gic-400"; | ||
129 | #interrupt-cells = <3>; | ||
130 | #address-cells = <2>; | ||
131 | #size-cells = <2>; | ||
132 | interrupt-controller; | ||
133 | interrupts = <1 8 0xf04>; | ||
134 | ranges = <0 0 0 0xe1100000 0 0x100000>; | ||
135 | reg = <0x0 0xe1110000 0 0x01000>, | ||
136 | <0x0 0xe112f000 0 0x02000>, | ||
137 | <0x0 0xe1140000 0 0x10000>, | ||
138 | <0x0 0xe1160000 0 0x10000>; | ||
139 | v2m0: v2m@0x8000 { | ||
140 | compatible = "arm,gic-v2m-frame"; | ||
141 | msi-controller; | ||
142 | reg = <0x0 0x80000 0 0x1000>; | ||
143 | }; | ||
144 | |||
145 | .... | ||
146 | |||
147 | v2mN: v2m@0x9000 { | ||
148 | compatible = "arm,gic-v2m-frame"; | ||
149 | msi-controller; | ||
150 | reg = <0x0 0x90000 0 0x1000>; | ||
151 | }; | ||
152 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 934f00025cc4..f717c7b48603 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt | |||
@@ -5,6 +5,11 @@ Hi4511 Board | |||
5 | Required root node properties: | 5 | Required root node properties: |
6 | - compatible = "hisilicon,hi3620-hi4511"; | 6 | - compatible = "hisilicon,hi3620-hi4511"; |
7 | 7 | ||
8 | HiP04 D01 Board | ||
9 | Required root node properties: | ||
10 | - compatible = "hisilicon,hip04-d01"; | ||
11 | |||
12 | |||
8 | Hisilicon system controller | 13 | Hisilicon system controller |
9 | 14 | ||
10 | Required properties: | 15 | Required properties: |
@@ -55,3 +60,21 @@ Example: | |||
55 | compatible = "hisilicon,pctrl"; | 60 | compatible = "hisilicon,pctrl"; |
56 | reg = <0xfca09000 0x1000>; | 61 | reg = <0xfca09000 0x1000>; |
57 | }; | 62 | }; |
63 | |||
64 | ----------------------------------------------------------------------- | ||
65 | Fabric: | ||
66 | |||
67 | Required Properties: | ||
68 | - compatible: "hisilicon,hip04-fabric"; | ||
69 | - reg: Address and size of Fabric | ||
70 | |||
71 | ----------------------------------------------------------------------- | ||
72 | Bootwrapper boot method (software protocol on SMP): | ||
73 | |||
74 | Required Properties: | ||
75 | - compatible: "hisilicon,hip04-bootwrapper"; | ||
76 | - boot-method: Address and size of boot method. | ||
77 | [0]: bootwrapper physical address | ||
78 | [1]: bootwrapper size | ||
79 | [2]: relocation physical address | ||
80 | [3]: relocation size | ||
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt new file mode 100644 index 000000000000..a8274eabae2e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/idle-states.txt | |||
@@ -0,0 +1,699 @@ | |||
1 | ========================================== | ||
2 | ARM idle states binding description | ||
3 | ========================================== | ||
4 | |||
5 | ========================================== | ||
6 | 1 - Introduction | ||
7 | ========================================== | ||
8 | |||
9 | ARM systems contain HW capable of managing power consumption dynamically, | ||
10 | where cores can be put in different low-power states (ranging from simple | ||
11 | wfi to power gating) according to OS PM policies. The CPU states representing | ||
12 | the range of dynamic idle states that a processor can enter at run-time, can be | ||
13 | specified through device tree bindings representing the parameters required | ||
14 | to enter/exit specific idle states on a given processor. | ||
15 | |||
16 | According to the Server Base System Architecture document (SBSA, [3]), the | ||
17 | power states an ARM CPU can be put into are identified by the following list: | ||
18 | |||
19 | - Running | ||
20 | - Idle_standby | ||
21 | - Idle_retention | ||
22 | - Sleep | ||
23 | - Off | ||
24 | |||
25 | The power states described in the SBSA document define the basic CPU states on | ||
26 | top of which ARM platforms implement power management schemes that allow an OS | ||
27 | PM implementation to put the processor in different idle states (which include | ||
28 | states listed above; "off" state is not an idle state since it does not have | ||
29 | wake-up capabilities, hence it is not considered in this document). | ||
30 | |||
31 | Idle state parameters (eg entry latency) are platform specific and need to be | ||
32 | characterized with bindings that provide the required information to OS PM | ||
33 | code so that it can build the required tables and use them at runtime. | ||
34 | |||
35 | The device tree binding definition for ARM idle states is the subject of this | ||
36 | document. | ||
37 | |||
38 | =========================================== | ||
39 | 2 - idle-states definitions | ||
40 | =========================================== | ||
41 | |||
42 | Idle states are characterized for a specific system through a set of | ||
43 | timing and energy related properties, that underline the HW behaviour | ||
44 | triggered upon idle states entry and exit. | ||
45 | |||
46 | The following diagram depicts the CPU execution phases and related timing | ||
47 | properties required to enter and exit an idle state: | ||
48 | |||
49 | ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__.. | ||
50 | | | | | | | ||
51 | |||
52 | |<------ entry ------->| | ||
53 | | latency | | ||
54 | |<- exit ->| | ||
55 | | latency | | ||
56 | |<-------- min-residency -------->| | ||
57 | |<------- wakeup-latency ------->| | ||
58 | |||
59 | Diagram 1: CPU idle state execution phases | ||
60 | |||
61 | EXEC: Normal CPU execution. | ||
62 | |||
63 | PREP: Preparation phase before committing the hardware to idle mode | ||
64 | like cache flushing. This is abortable on pending wake-up | ||
65 | event conditions. The abort latency is assumed to be negligible | ||
66 | (i.e. less than the ENTRY + EXIT duration). If aborted, CPU | ||
67 | goes back to EXEC. This phase is optional. If not abortable, | ||
68 | this should be included in the ENTRY phase instead. | ||
69 | |||
70 | ENTRY: The hardware is committed to idle mode. This period must run | ||
71 | to completion up to IDLE before anything else can happen. | ||
72 | |||
73 | IDLE: This is the actual energy-saving idle period. This may last | ||
74 | between 0 and infinite time, until a wake-up event occurs. | ||
75 | |||
76 | EXIT: Period during which the CPU is brought back to operational | ||
77 | mode (EXEC). | ||
78 | |||
79 | entry-latency: Worst case latency required to enter the idle state. The | ||
80 | exit-latency may be guaranteed only after entry-latency has passed. | ||
81 | |||
82 | min-residency: Minimum period, including preparation and entry, for a given | ||
83 | idle state to be worthwhile energywise. | ||
84 | |||
85 | wakeup-latency: Maximum delay between the signaling of a wake-up event and the | ||
86 | CPU being able to execute normal code again. If not specified, this is assumed | ||
87 | to be entry-latency + exit-latency. | ||
88 | |||
89 | These timing parameters can be used by an OS in different circumstances. | ||
90 | |||
91 | An idle CPU requires the expected min-residency time to select the most | ||
92 | appropriate idle state based on the expected expiry time of the next IRQ | ||
93 | (ie wake-up) that causes the CPU to return to the EXEC phase. | ||
94 | |||
95 | An operating system scheduler may need to compute the shortest wake-up delay | ||
96 | for CPUs in the system by detecting how long will it take to get a CPU out | ||
97 | of an idle state, eg: | ||
98 | |||
99 | wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0) | ||
100 | |||
101 | In other words, the scheduler can make its scheduling decision by selecting | ||
102 | (eg waking-up) the CPU with the shortest wake-up latency. | ||
103 | The wake-up latency must take into account the entry latency if that period | ||
104 | has not expired. The abortable nature of the PREP period can be ignored | ||
105 | if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than | ||
106 | the worst case since it depends on the CPU operating conditions, ie caches | ||
107 | state). | ||
108 | |||
109 | An OS has to reliably probe the wakeup-latency since some devices can enforce | ||
110 | latency constraints guarantees to work properly, so the OS has to detect the | ||
111 | worst case wake-up latency it can incur if a CPU is allowed to enter an | ||
112 | idle state, and possibly to prevent that to guarantee reliable device | ||
113 | functioning. | ||
114 | |||
115 | The min-residency time parameter deserves further explanation since it is | ||
116 | expressed in time units but must factor in energy consumption coefficients. | ||
117 | |||
118 | The energy consumption of a cpu when it enters a power state can be roughly | ||
119 | characterised by the following graph: | ||
120 | |||
121 | | | ||
122 | | | ||
123 | | | ||
124 | e | | ||
125 | n | /--- | ||
126 | e | /------ | ||
127 | r | /------ | ||
128 | g | /----- | ||
129 | y | /------ | ||
130 | | ---- | ||
131 | | /| | ||
132 | | / | | ||
133 | | / | | ||
134 | | / | | ||
135 | | / | | ||
136 | | / | | ||
137 | |/ | | ||
138 | -----|-------+---------------------------------- | ||
139 | 0| 1 time(ms) | ||
140 | |||
141 | Graph 1: Energy vs time example | ||
142 | |||
143 | The graph is split in two parts delimited by time 1ms on the X-axis. | ||
144 | The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope | ||
145 | and denotes the energy costs incurred whilst entering and leaving the idle | ||
146 | state. | ||
147 | The graph curve in the area delimited by X-axis values = {x | x > 1ms } has | ||
148 | shallower slope and essentially represents the energy consumption of the idle | ||
149 | state. | ||
150 | |||
151 | min-residency is defined for a given idle state as the minimum expected | ||
152 | residency time for a state (inclusive of preparation and entry) after | ||
153 | which choosing that state become the most energy efficient option. A good | ||
154 | way to visualise this, is by taking the same graph above and comparing some | ||
155 | states energy consumptions plots. | ||
156 | |||
157 | For sake of simplicity, let's consider a system with two idle states IDLE1, | ||
158 | and IDLE2: | ||
159 | |||
160 | | | ||
161 | | | ||
162 | | | ||
163 | | /-- IDLE1 | ||
164 | e | /--- | ||
165 | n | /---- | ||
166 | e | /--- | ||
167 | r | /-----/--------- IDLE2 | ||
168 | g | /-------/--------- | ||
169 | y | ------------ /---| | ||
170 | | / /---- | | ||
171 | | / /--- | | ||
172 | | / /---- | | ||
173 | | / /--- | | ||
174 | | --- | | ||
175 | | / | | ||
176 | | / | | ||
177 | |/ | time | ||
178 | ---/----------------------------+------------------------ | ||
179 | |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy | ||
180 | | | ||
181 | IDLE2-min-residency | ||
182 | |||
183 | Graph 2: idle states min-residency example | ||
184 | |||
185 | In graph 2 above, that takes into account idle states entry/exit energy | ||
186 | costs, it is clear that if the idle state residency time (ie time till next | ||
187 | wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state | ||
188 | choice energywise. | ||
189 | |||
190 | This is mainly down to the fact that IDLE1 entry/exit energy costs are lower | ||
191 | than IDLE2. | ||
192 | |||
193 | However, the lower power consumption (ie shallower energy curve slope) of idle | ||
194 | state IDLE2 implies that after a suitable time, IDLE2 becomes more energy | ||
195 | efficient. | ||
196 | |||
197 | The time at which IDLE2 becomes more energy efficient than IDLE1 (and other | ||
198 | shallower states in a system with multiple idle states) is defined | ||
199 | IDLE2-min-residency and corresponds to the time when energy consumption of | ||
200 | IDLE1 and IDLE2 states breaks even. | ||
201 | |||
202 | The definitions provided in this section underpin the idle states | ||
203 | properties specification that is the subject of the following sections. | ||
204 | |||
205 | =========================================== | ||
206 | 3 - idle-states node | ||
207 | =========================================== | ||
208 | |||
209 | ARM processor idle states are defined within the idle-states node, which is | ||
210 | a direct child of the cpus node [1] and provides a container where the | ||
211 | processor idle states, defined as device tree nodes, are listed. | ||
212 | |||
213 | - idle-states node | ||
214 | |||
215 | Usage: Optional - On ARM systems, it is a container of processor idle | ||
216 | states nodes. If the system does not provide CPU | ||
217 | power management capabilities or the processor just | ||
218 | supports idle_standby an idle-states node is not | ||
219 | required. | ||
220 | |||
221 | Description: idle-states node is a container node, where its | ||
222 | subnodes describe the CPU idle states. | ||
223 | |||
224 | Node name must be "idle-states". | ||
225 | |||
226 | The idle-states node's parent node must be the cpus node. | ||
227 | |||
228 | The idle-states node's child nodes can be: | ||
229 | |||
230 | - one or more state nodes | ||
231 | |||
232 | Any other configuration is considered invalid. | ||
233 | |||
234 | An idle-states node defines the following properties: | ||
235 | |||
236 | - entry-method | ||
237 | Value type: <stringlist> | ||
238 | Usage and definition depend on ARM architecture version. | ||
239 | # On ARM v8 64-bit this property is required and must | ||
240 | be one of: | ||
241 | - "psci" (see bindings in [2]) | ||
242 | # On ARM 32-bit systems this property is optional | ||
243 | |||
244 | The nodes describing the idle states (state) can only be defined within the | ||
245 | idle-states node, any other configuration is considered invalid and therefore | ||
246 | must be ignored. | ||
247 | |||
248 | =========================================== | ||
249 | 4 - state node | ||
250 | =========================================== | ||
251 | |||
252 | A state node represents an idle state description and must be defined as | ||
253 | follows: | ||
254 | |||
255 | - state node | ||
256 | |||
257 | Description: must be child of the idle-states node | ||
258 | |||
259 | The state node name shall follow standard device tree naming | ||
260 | rules ([5], 2.2.1 "Node names"), in particular state nodes which | ||
261 | are siblings within a single common parent must be given a unique name. | ||
262 | |||
263 | The idle state entered by executing the wfi instruction (idle_standby | ||
264 | SBSA,[3][4]) is considered standard on all ARM platforms and therefore | ||
265 | must not be listed. | ||
266 | |||
267 | With the definitions provided above, the following list represents | ||
268 | the valid properties for a state node: | ||
269 | |||
270 | - compatible | ||
271 | Usage: Required | ||
272 | Value type: <stringlist> | ||
273 | Definition: Must be "arm,idle-state". | ||
274 | |||
275 | - local-timer-stop | ||
276 | Usage: See definition | ||
277 | Value type: <none> | ||
278 | Definition: if present the CPU local timer control logic is | ||
279 | lost on state entry, otherwise it is retained. | ||
280 | |||
281 | - entry-latency-us | ||
282 | Usage: Required | ||
283 | Value type: <prop-encoded-array> | ||
284 | Definition: u32 value representing worst case latency in | ||
285 | microseconds required to enter the idle state. | ||
286 | The exit-latency-us duration may be guaranteed | ||
287 | only after entry-latency-us has passed. | ||
288 | |||
289 | - exit-latency-us | ||
290 | Usage: Required | ||
291 | Value type: <prop-encoded-array> | ||
292 | Definition: u32 value representing worst case latency | ||
293 | in microseconds required to exit the idle state. | ||
294 | |||
295 | - min-residency-us | ||
296 | Usage: Required | ||
297 | Value type: <prop-encoded-array> | ||
298 | Definition: u32 value representing minimum residency duration | ||
299 | in microseconds, inclusive of preparation and | ||
300 | entry, for this idle state to be considered | ||
301 | worthwhile energy wise (refer to section 2 of | ||
302 | this document for a complete description). | ||
303 | |||
304 | - wakeup-latency-us: | ||
305 | Usage: Optional | ||
306 | Value type: <prop-encoded-array> | ||
307 | Definition: u32 value representing maximum delay between the | ||
308 | signaling of a wake-up event and the CPU being | ||
309 | able to execute normal code again. If omitted, | ||
310 | this is assumed to be equal to: | ||
311 | |||
312 | entry-latency-us + exit-latency-us | ||
313 | |||
314 | It is important to supply this value on systems | ||
315 | where the duration of PREP phase (see diagram 1, | ||
316 | section 2) is non-neglibigle. | ||
317 | In such systems entry-latency-us + exit-latency-us | ||
318 | will exceed wakeup-latency-us by this duration. | ||
319 | |||
320 | - status: | ||
321 | Usage: Optional | ||
322 | Value type: <string> | ||
323 | Definition: A standard device tree property [5] that indicates | ||
324 | the operational status of an idle-state. | ||
325 | If present, it shall be: | ||
326 | "okay": to indicate that the idle state is | ||
327 | operational. | ||
328 | "disabled": to indicate that the idle state has | ||
329 | been disabled in firmware so it is not | ||
330 | operational. | ||
331 | If the property is not present the idle-state must | ||
332 | be considered operational. | ||
333 | |||
334 | - idle-state-name: | ||
335 | Usage: Optional | ||
336 | Value type: <string> | ||
337 | Definition: A string used as a descriptive name for the idle | ||
338 | state. | ||
339 | |||
340 | In addition to the properties listed above, a state node may require | ||
341 | additional properties specifics to the entry-method defined in the | ||
342 | idle-states node, please refer to the entry-method bindings | ||
343 | documentation for properties definitions. | ||
344 | |||
345 | =========================================== | ||
346 | 4 - Examples | ||
347 | =========================================== | ||
348 | |||
349 | Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method): | ||
350 | |||
351 | cpus { | ||
352 | #size-cells = <0>; | ||
353 | #address-cells = <2>; | ||
354 | |||
355 | CPU0: cpu@0 { | ||
356 | device_type = "cpu"; | ||
357 | compatible = "arm,cortex-a57"; | ||
358 | reg = <0x0 0x0>; | ||
359 | enable-method = "psci"; | ||
360 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
361 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
362 | }; | ||
363 | |||
364 | CPU1: cpu@1 { | ||
365 | device_type = "cpu"; | ||
366 | compatible = "arm,cortex-a57"; | ||
367 | reg = <0x0 0x1>; | ||
368 | enable-method = "psci"; | ||
369 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
370 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
371 | }; | ||
372 | |||
373 | CPU2: cpu@100 { | ||
374 | device_type = "cpu"; | ||
375 | compatible = "arm,cortex-a57"; | ||
376 | reg = <0x0 0x100>; | ||
377 | enable-method = "psci"; | ||
378 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
379 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
380 | }; | ||
381 | |||
382 | CPU3: cpu@101 { | ||
383 | device_type = "cpu"; | ||
384 | compatible = "arm,cortex-a57"; | ||
385 | reg = <0x0 0x101>; | ||
386 | enable-method = "psci"; | ||
387 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
388 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
389 | }; | ||
390 | |||
391 | CPU4: cpu@10000 { | ||
392 | device_type = "cpu"; | ||
393 | compatible = "arm,cortex-a57"; | ||
394 | reg = <0x0 0x10000>; | ||
395 | enable-method = "psci"; | ||
396 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
397 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
398 | }; | ||
399 | |||
400 | CPU5: cpu@10001 { | ||
401 | device_type = "cpu"; | ||
402 | compatible = "arm,cortex-a57"; | ||
403 | reg = <0x0 0x10001>; | ||
404 | enable-method = "psci"; | ||
405 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
406 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
407 | }; | ||
408 | |||
409 | CPU6: cpu@10100 { | ||
410 | device_type = "cpu"; | ||
411 | compatible = "arm,cortex-a57"; | ||
412 | reg = <0x0 0x10100>; | ||
413 | enable-method = "psci"; | ||
414 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
415 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
416 | }; | ||
417 | |||
418 | CPU7: cpu@10101 { | ||
419 | device_type = "cpu"; | ||
420 | compatible = "arm,cortex-a57"; | ||
421 | reg = <0x0 0x10101>; | ||
422 | enable-method = "psci"; | ||
423 | cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0 | ||
424 | &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>; | ||
425 | }; | ||
426 | |||
427 | CPU8: cpu@100000000 { | ||
428 | device_type = "cpu"; | ||
429 | compatible = "arm,cortex-a53"; | ||
430 | reg = <0x1 0x0>; | ||
431 | enable-method = "psci"; | ||
432 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
433 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
434 | }; | ||
435 | |||
436 | CPU9: cpu@100000001 { | ||
437 | device_type = "cpu"; | ||
438 | compatible = "arm,cortex-a53"; | ||
439 | reg = <0x1 0x1>; | ||
440 | enable-method = "psci"; | ||
441 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
442 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
443 | }; | ||
444 | |||
445 | CPU10: cpu@100000100 { | ||
446 | device_type = "cpu"; | ||
447 | compatible = "arm,cortex-a53"; | ||
448 | reg = <0x1 0x100>; | ||
449 | enable-method = "psci"; | ||
450 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
451 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
452 | }; | ||
453 | |||
454 | CPU11: cpu@100000101 { | ||
455 | device_type = "cpu"; | ||
456 | compatible = "arm,cortex-a53"; | ||
457 | reg = <0x1 0x101>; | ||
458 | enable-method = "psci"; | ||
459 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
460 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
461 | }; | ||
462 | |||
463 | CPU12: cpu@100010000 { | ||
464 | device_type = "cpu"; | ||
465 | compatible = "arm,cortex-a53"; | ||
466 | reg = <0x1 0x10000>; | ||
467 | enable-method = "psci"; | ||
468 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
469 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
470 | }; | ||
471 | |||
472 | CPU13: cpu@100010001 { | ||
473 | device_type = "cpu"; | ||
474 | compatible = "arm,cortex-a53"; | ||
475 | reg = <0x1 0x10001>; | ||
476 | enable-method = "psci"; | ||
477 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
478 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
479 | }; | ||
480 | |||
481 | CPU14: cpu@100010100 { | ||
482 | device_type = "cpu"; | ||
483 | compatible = "arm,cortex-a53"; | ||
484 | reg = <0x1 0x10100>; | ||
485 | enable-method = "psci"; | ||
486 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
487 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
488 | }; | ||
489 | |||
490 | CPU15: cpu@100010101 { | ||
491 | device_type = "cpu"; | ||
492 | compatible = "arm,cortex-a53"; | ||
493 | reg = <0x1 0x10101>; | ||
494 | enable-method = "psci"; | ||
495 | cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0 | ||
496 | &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>; | ||
497 | }; | ||
498 | |||
499 | idle-states { | ||
500 | entry-method = "arm,psci"; | ||
501 | |||
502 | CPU_RETENTION_0_0: cpu-retention-0-0 { | ||
503 | compatible = "arm,idle-state"; | ||
504 | arm,psci-suspend-param = <0x0010000>; | ||
505 | entry-latency-us = <20>; | ||
506 | exit-latency-us = <40>; | ||
507 | min-residency-us = <80>; | ||
508 | }; | ||
509 | |||
510 | CLUSTER_RETENTION_0: cluster-retention-0 { | ||
511 | compatible = "arm,idle-state"; | ||
512 | local-timer-stop; | ||
513 | arm,psci-suspend-param = <0x1010000>; | ||
514 | entry-latency-us = <50>; | ||
515 | exit-latency-us = <100>; | ||
516 | min-residency-us = <250>; | ||
517 | wakeup-latency-us = <130>; | ||
518 | }; | ||
519 | |||
520 | CPU_SLEEP_0_0: cpu-sleep-0-0 { | ||
521 | compatible = "arm,idle-state"; | ||
522 | local-timer-stop; | ||
523 | arm,psci-suspend-param = <0x0010000>; | ||
524 | entry-latency-us = <250>; | ||
525 | exit-latency-us = <500>; | ||
526 | min-residency-us = <950>; | ||
527 | }; | ||
528 | |||
529 | CLUSTER_SLEEP_0: cluster-sleep-0 { | ||
530 | compatible = "arm,idle-state"; | ||
531 | local-timer-stop; | ||
532 | arm,psci-suspend-param = <0x1010000>; | ||
533 | entry-latency-us = <600>; | ||
534 | exit-latency-us = <1100>; | ||
535 | min-residency-us = <2700>; | ||
536 | wakeup-latency-us = <1500>; | ||
537 | }; | ||
538 | |||
539 | CPU_RETENTION_1_0: cpu-retention-1-0 { | ||
540 | compatible = "arm,idle-state"; | ||
541 | arm,psci-suspend-param = <0x0010000>; | ||
542 | entry-latency-us = <20>; | ||
543 | exit-latency-us = <40>; | ||
544 | min-residency-us = <90>; | ||
545 | }; | ||
546 | |||
547 | CLUSTER_RETENTION_1: cluster-retention-1 { | ||
548 | compatible = "arm,idle-state"; | ||
549 | local-timer-stop; | ||
550 | arm,psci-suspend-param = <0x1010000>; | ||
551 | entry-latency-us = <50>; | ||
552 | exit-latency-us = <100>; | ||
553 | min-residency-us = <270>; | ||
554 | wakeup-latency-us = <100>; | ||
555 | }; | ||
556 | |||
557 | CPU_SLEEP_1_0: cpu-sleep-1-0 { | ||
558 | compatible = "arm,idle-state"; | ||
559 | local-timer-stop; | ||
560 | arm,psci-suspend-param = <0x0010000>; | ||
561 | entry-latency-us = <70>; | ||
562 | exit-latency-us = <100>; | ||
563 | min-residency-us = <300>; | ||
564 | wakeup-latency-us = <150>; | ||
565 | }; | ||
566 | |||
567 | CLUSTER_SLEEP_1: cluster-sleep-1 { | ||
568 | compatible = "arm,idle-state"; | ||
569 | local-timer-stop; | ||
570 | arm,psci-suspend-param = <0x1010000>; | ||
571 | entry-latency-us = <500>; | ||
572 | exit-latency-us = <1200>; | ||
573 | min-residency-us = <3500>; | ||
574 | wakeup-latency-us = <1300>; | ||
575 | }; | ||
576 | }; | ||
577 | |||
578 | }; | ||
579 | |||
580 | Example 2 (ARM 32-bit, 8-cpu system, two clusters): | ||
581 | |||
582 | cpus { | ||
583 | #size-cells = <0>; | ||
584 | #address-cells = <1>; | ||
585 | |||
586 | CPU0: cpu@0 { | ||
587 | device_type = "cpu"; | ||
588 | compatible = "arm,cortex-a15"; | ||
589 | reg = <0x0>; | ||
590 | cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; | ||
591 | }; | ||
592 | |||
593 | CPU1: cpu@1 { | ||
594 | device_type = "cpu"; | ||
595 | compatible = "arm,cortex-a15"; | ||
596 | reg = <0x1>; | ||
597 | cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; | ||
598 | }; | ||
599 | |||
600 | CPU2: cpu@2 { | ||
601 | device_type = "cpu"; | ||
602 | compatible = "arm,cortex-a15"; | ||
603 | reg = <0x2>; | ||
604 | cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; | ||
605 | }; | ||
606 | |||
607 | CPU3: cpu@3 { | ||
608 | device_type = "cpu"; | ||
609 | compatible = "arm,cortex-a15"; | ||
610 | reg = <0x3>; | ||
611 | cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>; | ||
612 | }; | ||
613 | |||
614 | CPU4: cpu@100 { | ||
615 | device_type = "cpu"; | ||
616 | compatible = "arm,cortex-a7"; | ||
617 | reg = <0x100>; | ||
618 | cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; | ||
619 | }; | ||
620 | |||
621 | CPU5: cpu@101 { | ||
622 | device_type = "cpu"; | ||
623 | compatible = "arm,cortex-a7"; | ||
624 | reg = <0x101>; | ||
625 | cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; | ||
626 | }; | ||
627 | |||
628 | CPU6: cpu@102 { | ||
629 | device_type = "cpu"; | ||
630 | compatible = "arm,cortex-a7"; | ||
631 | reg = <0x102>; | ||
632 | cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; | ||
633 | }; | ||
634 | |||
635 | CPU7: cpu@103 { | ||
636 | device_type = "cpu"; | ||
637 | compatible = "arm,cortex-a7"; | ||
638 | reg = <0x103>; | ||
639 | cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>; | ||
640 | }; | ||
641 | |||
642 | idle-states { | ||
643 | CPU_SLEEP_0_0: cpu-sleep-0-0 { | ||
644 | compatible = "arm,idle-state"; | ||
645 | local-timer-stop; | ||
646 | entry-latency-us = <200>; | ||
647 | exit-latency-us = <100>; | ||
648 | min-residency-us = <400>; | ||
649 | wakeup-latency-us = <250>; | ||
650 | }; | ||
651 | |||
652 | CLUSTER_SLEEP_0: cluster-sleep-0 { | ||
653 | compatible = "arm,idle-state"; | ||
654 | local-timer-stop; | ||
655 | entry-latency-us = <500>; | ||
656 | exit-latency-us = <1500>; | ||
657 | min-residency-us = <2500>; | ||
658 | wakeup-latency-us = <1700>; | ||
659 | }; | ||
660 | |||
661 | CPU_SLEEP_1_0: cpu-sleep-1-0 { | ||
662 | compatible = "arm,idle-state"; | ||
663 | local-timer-stop; | ||
664 | entry-latency-us = <300>; | ||
665 | exit-latency-us = <500>; | ||
666 | min-residency-us = <900>; | ||
667 | wakeup-latency-us = <600>; | ||
668 | }; | ||
669 | |||
670 | CLUSTER_SLEEP_1: cluster-sleep-1 { | ||
671 | compatible = "arm,idle-state"; | ||
672 | local-timer-stop; | ||
673 | entry-latency-us = <800>; | ||
674 | exit-latency-us = <2000>; | ||
675 | min-residency-us = <6500>; | ||
676 | wakeup-latency-us = <2300>; | ||
677 | }; | ||
678 | }; | ||
679 | |||
680 | }; | ||
681 | |||
682 | =========================================== | ||
683 | 5 - References | ||
684 | =========================================== | ||
685 | |||
686 | [1] ARM Linux Kernel documentation - CPUs bindings | ||
687 | Documentation/devicetree/bindings/arm/cpus.txt | ||
688 | |||
689 | [2] ARM Linux Kernel documentation - PSCI bindings | ||
690 | Documentation/devicetree/bindings/arm/psci.txt | ||
691 | |||
692 | [3] ARM Server Base System Architecture (SBSA) | ||
693 | http://infocenter.arm.com/help/index.jsp | ||
694 | |||
695 | [4] ARM Architecture Reference Manuals | ||
696 | http://infocenter.arm.com/help/index.jsp | ||
697 | |||
698 | [5] ePAPR standard | ||
699 | https://www.power.org/documentation/epapr-version-1-1/ | ||
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index af527ee111c2..292ef7ca3058 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt | |||
@@ -2,6 +2,10 @@ | |||
2 | 2 | ||
3 | ARM cores often have a separate level 2 cache controller. There are various | 3 | ARM cores often have a separate level 2 cache controller. There are various |
4 | implementations of the L2 cache controller with compatible programming models. | 4 | implementations of the L2 cache controller with compatible programming models. |
5 | Some of the properties that are just prefixed "cache-*" are taken from section | ||
6 | 3.7.3 of the ePAPR v1.1 specification which can be found at: | ||
7 | https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf | ||
8 | |||
5 | The ARM L2 cache representation in the device tree should be done as follows: | 9 | The ARM L2 cache representation in the device tree should be done as follows: |
6 | 10 | ||
7 | Required properties: | 11 | Required properties: |
@@ -44,6 +48,12 @@ Optional properties: | |||
44 | I/O coherent mode. Valid only when the arm,pl310-cache compatible | 48 | I/O coherent mode. Valid only when the arm,pl310-cache compatible |
45 | string is used. | 49 | string is used. |
46 | - interrupts : 1 combined interrupt. | 50 | - interrupts : 1 combined interrupt. |
51 | - cache-size : specifies the size in bytes of the cache | ||
52 | - cache-sets : specifies the number of associativity sets of the cache | ||
53 | - cache-block-size : specifies the size in bytes of a cache block | ||
54 | - cache-line-size : specifies the size in bytes of a line in the cache, | ||
55 | if this is not specified, the line size is assumed to be equal to the | ||
56 | cache block size | ||
47 | - cache-id-part: cache id part number to be used if it is not present | 57 | - cache-id-part: cache id part number to be used if it is not present |
48 | on hardware | 58 | on hardware |
49 | - wt-override: If present then L2 is forced to Write through mode | 59 | - wt-override: If present then L2 is forced to Write through mode |
diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 904de5781f44..a99eb9eb14c0 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt | |||
@@ -106,11 +106,21 @@ Required subnode-properties: | |||
106 | - groups: a list of strings describing the group names. | 106 | - groups: a list of strings describing the group names. |
107 | - function: a string describing the function used to mux the groups. | 107 | - function: a string describing the function used to mux the groups. |
108 | 108 | ||
109 | * Reset controller binding | ||
110 | |||
111 | A reset controller is part of the chip control registers set. The chip control | ||
112 | node also provides the reset. The register set is not at the same offset between | ||
113 | Berlin SoCs. | ||
114 | |||
115 | Required property: | ||
116 | - #reset-cells: must be set to 2 | ||
117 | |||
109 | Example: | 118 | Example: |
110 | 119 | ||
111 | chip: chip-control@ea0000 { | 120 | chip: chip-control@ea0000 { |
112 | compatible = "marvell,berlin2-chip-ctrl"; | 121 | compatible = "marvell,berlin2-chip-ctrl"; |
113 | #clock-cells = <1>; | 122 | #clock-cells = <1>; |
123 | #reset-cells = <2>; | ||
114 | reg = <0xea0000 0x400>; | 124 | reg = <0xea0000 0x400>; |
115 | clocks = <&refclk>, <&externaldev 0>; | 125 | clocks = <&refclk>, <&externaldev 0>; |
116 | clock-names = "refclk", "video_ext0"; | 126 | clock-names = "refclk", "video_ext0"; |
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index d6ac71f37314..3be40139cfbb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt | |||
@@ -1,8 +1,27 @@ | |||
1 | Mediatek MT6589 Platforms Device Tree Bindings | 1 | MediaTek mt65xx & mt81xx Platforms Device Tree Bindings |
2 | 2 | ||
3 | Boards with a SoC of the Mediatek MT6589 shall have the following property: | 3 | Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property: |
4 | 4 | ||
5 | Required root node property: | 5 | Required root node property: |
6 | 6 | ||
7 | compatible: must contain "mediatek,mt6589" | 7 | compatible: Must contain one of |
8 | "mediatek,mt6589" | ||
9 | "mediatek,mt6592" | ||
10 | "mediatek,mt8127" | ||
11 | "mediatek,mt8135" | ||
8 | 12 | ||
13 | |||
14 | Supported boards: | ||
15 | |||
16 | - bq Aquaris5 smart phone: | ||
17 | Required root node properties: | ||
18 | - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; | ||
19 | - Evaluation board for MT6592: | ||
20 | Required root node properties: | ||
21 | - compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; | ||
22 | - MTK mt8127 tablet moose EVB: | ||
23 | Required root node properties: | ||
24 | - compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; | ||
25 | - MTK mt8135 tablet EVB: | ||
26 | Required root node properties: | ||
27 | - compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; | ||
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt new file mode 100644 index 000000000000..d680b07ec6e8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sysirq.txt | |||
@@ -0,0 +1,28 @@ | |||
1 | Mediatek 65xx/81xx sysirq | ||
2 | |||
3 | Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI | ||
4 | interrupt. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: should be one of: | ||
8 | "mediatek,mt8135-sysirq" | ||
9 | "mediatek,mt8127-sysirq" | ||
10 | "mediatek,mt6589-sysirq" | ||
11 | "mediatek,mt6582-sysirq" | ||
12 | "mediatek,mt6577-sysirq" | ||
13 | - interrupt-controller : Identifies the node as an interrupt controller | ||
14 | - #interrupt-cells : Use the same format as specified by GIC in | ||
15 | Documentation/devicetree/bindings/arm/gic.txt | ||
16 | - interrupt-parent: phandle of irq parent for sysirq. The parent must | ||
17 | use the same interrupt-cells format as GIC. | ||
18 | - reg: Physical base address of the intpol registers and length of memory | ||
19 | mapped region. | ||
20 | |||
21 | Example: | ||
22 | sysirq: interrupt-controller@10200100 { | ||
23 | compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; | ||
24 | interrupt-controller; | ||
25 | #interrupt-cells = <3>; | ||
26 | interrupt-parent = <&gic>; | ||
27 | reg = <0 0x10200100 0 0x1c>; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt index 83f405bde138..763695db2bd9 100644 --- a/Documentation/devicetree/bindings/arm/omap/mpu.txt +++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt | |||
@@ -10,6 +10,9 @@ Required properties: | |||
10 | Should be "ti,omap5-mpu" for OMAP5 | 10 | Should be "ti,omap5-mpu" for OMAP5 |
11 | - ti,hwmods: "mpu" | 11 | - ti,hwmods: "mpu" |
12 | 12 | ||
13 | Optional properties: | ||
14 | - sram: Phandle to the ocmcram node | ||
15 | |||
13 | Examples: | 16 | Examples: |
14 | 17 | ||
15 | - For an OMAP5 SMP system: | 18 | - For an OMAP5 SMP system: |
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 0edc90305dfe..4f6a82cef1d1 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt | |||
@@ -85,6 +85,18 @@ SoCs: | |||
85 | - DRA722 | 85 | - DRA722 |
86 | compatible = "ti,dra722", "ti,dra72", "ti,dra7" | 86 | compatible = "ti,dra722", "ti,dra72", "ti,dra7" |
87 | 87 | ||
88 | - AM5728 | ||
89 | compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" | ||
90 | |||
91 | - AM5726 | ||
92 | compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7" | ||
93 | |||
94 | - AM5718 | ||
95 | compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7" | ||
96 | |||
97 | - AM5716 | ||
98 | compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7" | ||
99 | |||
88 | - AM4372 | 100 | - AM4372 |
89 | compatible = "ti,am4372", "ti,am43" | 101 | compatible = "ti,am4372", "ti,am43" |
90 | 102 | ||
@@ -120,6 +132,9 @@ Boards: | |||
120 | - AM335X Bone : Low cost community board | 132 | - AM335X Bone : Low cost community board |
121 | compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" | 133 | compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" |
122 | 134 | ||
135 | - AM335X OrionLXm : Substation Automation Platform | ||
136 | compatible = "novatech,am335x-lxm", "ti,am33xx" | ||
137 | |||
123 | - OMAP5 EVM : Evaluation Module | 138 | - OMAP5 EVM : Evaluation Module |
124 | compatible = "ti,omap5-evm", "ti,omap5" | 139 | compatible = "ti,omap5-evm", "ti,omap5" |
125 | 140 | ||
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt index b4a58f39223c..5aa40ede0e99 100644 --- a/Documentation/devicetree/bindings/arm/psci.txt +++ b/Documentation/devicetree/bindings/arm/psci.txt | |||
@@ -50,6 +50,16 @@ Main node optional properties: | |||
50 | 50 | ||
51 | - migrate : Function ID for MIGRATE operation | 51 | - migrate : Function ID for MIGRATE operation |
52 | 52 | ||
53 | Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle | ||
54 | state nodes, as per bindings in [1]) must specify the following properties: | ||
55 | |||
56 | - arm,psci-suspend-param | ||
57 | Usage: Required for state nodes[1] if the corresponding | ||
58 | idle-states node entry-method property is set | ||
59 | to "psci". | ||
60 | Value type: <u32> | ||
61 | Definition: power_state parameter to pass to the PSCI | ||
62 | suspend call. | ||
53 | 63 | ||
54 | Example: | 64 | Example: |
55 | 65 | ||
@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only. | |||
64 | migrate = <0x95c10003>; | 74 | migrate = <0x95c10003>; |
65 | }; | 75 | }; |
66 | 76 | ||
67 | |||
68 | Case 2: PSCI v0.2 only | 77 | Case 2: PSCI v0.2 only |
69 | 78 | ||
70 | psci { | 79 | psci { |
@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1. | |||
88 | 97 | ||
89 | ... | 98 | ... |
90 | }; | 99 | }; |
100 | |||
101 | [1] Kernel documentation - ARM idle states bindings | ||
102 | Documentation/devicetree/bindings/arm/idle-states.txt | ||
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 857f12636eb2..eaa3d1a0eb05 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt | |||
@@ -1,6 +1,10 @@ | |||
1 | Rockchip platforms device tree bindings | 1 | Rockchip platforms device tree bindings |
2 | --------------------------------------- | 2 | --------------------------------------- |
3 | 3 | ||
4 | - MarsBoard RK3066 board: | ||
5 | Required root node properties: | ||
6 | - compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; | ||
7 | |||
4 | - bq Curie 2 tablet: | 8 | - bq Curie 2 tablet: |
5 | Required root node properties: | 9 | Required root node properties: |
6 | - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; | 10 | - compatible = "mundoreader,bq-curie2", "rockchip,rk3066a"; |
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt index 2168ed31e1b0..43589d2466a7 100644 --- a/Documentation/devicetree/bindings/arm/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt | |||
@@ -1,11 +1,20 @@ | |||
1 | * Samsung's Exynos4210 based SMDKV310 evaluation board | 1 | * Samsung's Exynos SoC based boards |
2 | |||
3 | SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC. | ||
4 | 2 | ||
5 | Required root node properties: | 3 | Required root node properties: |
6 | - compatible = should be one or more of the following. | 4 | - compatible = should be one or more of the following. |
7 | (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board. | 5 | - "samsung,monk" - for Exynos3250-based Samsung Simband board. |
8 | (b) "samsung,exynos4210" - for boards based on Exynos4210 SoC. | 6 | - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board. |
7 | - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. | ||
8 | - "samsung,trats" - for Exynos4210-based Tizen Reference board. | ||
9 | - "samsung,universal_c210" - for Exynos4210-based Samsung board. | ||
10 | - "samsung,smdk4412", - for Exynos4412-based Samsung SMDK4412 eval board. | ||
11 | - "samsung,trats2" - for Exynos4412-based Tizen Reference board. | ||
12 | - "samsung,smdk5250" - for Exynos5250-based Samsung SMDK5250 eval board. | ||
13 | - "samsung,xyref5260" - for Exynos5260-based Samsung board. | ||
14 | - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board. | ||
15 | - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board. | ||
16 | - "samsung,sd5v1" - for Exynos5440-based Samsung board. | ||
17 | - "samsung,ssdk5440" - for Exynos5440-based Samsung board. | ||
9 | 18 | ||
10 | Optional: | 19 | Optional: |
11 | - firmware node, specifying presence and type of secure firmware: | 20 | - firmware node, specifying presence and type of secure firmware: |
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt index adc61b095bd1..f46ca9a316a2 100644 --- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt | |||
@@ -11,13 +11,27 @@ New driver handles the following | |||
11 | 11 | ||
12 | Required properties: | 12 | Required properties: |
13 | - compatible: Must be "samsung,exynos-adc-v1" | 13 | - compatible: Must be "samsung,exynos-adc-v1" |
14 | for exynos4412/5250 controllers. | 14 | for exynos4412/5250 and s5pv210 controllers. |
15 | Must be "samsung,exynos-adc-v2" for | 15 | Must be "samsung,exynos-adc-v2" for |
16 | future controllers. | 16 | future controllers. |
17 | Must be "samsung,exynos3250-adc" for | 17 | Must be "samsung,exynos3250-adc" for |
18 | controllers compatible with ADC of Exynos3250. | 18 | controllers compatible with ADC of Exynos3250. |
19 | - reg: Contains ADC register address range (base address and | 19 | Must be "samsung,exynos7-adc" for |
20 | length) and the address of the phy enable register. | 20 | the ADC in Exynos7 and compatibles |
21 | Must be "samsung,s3c2410-adc" for | ||
22 | the ADC in s3c2410 and compatibles | ||
23 | Must be "samsung,s3c2416-adc" for | ||
24 | the ADC in s3c2416 and compatibles | ||
25 | Must be "samsung,s3c2440-adc" for | ||
26 | the ADC in s3c2440 and compatibles | ||
27 | Must be "samsung,s3c2443-adc" for | ||
28 | the ADC in s3c2443 and compatibles | ||
29 | Must be "samsung,s3c6410-adc" for | ||
30 | the ADC in s3c6410 and compatibles | ||
31 | - reg: List of ADC register address range | ||
32 | - The base address and range of ADC register | ||
33 | - The base address and range of ADC_PHY register (every | ||
34 | SoC except for s3c24xx/s3c64xx ADC) | ||
21 | - interrupts: Contains the interrupt information for the timer. The | 35 | - interrupts: Contains the interrupt information for the timer. The |
22 | format is being dependent on which interrupt controller | 36 | format is being dependent on which interrupt controller |
23 | the Samsung device uses. | 37 | the Samsung device uses. |
@@ -31,13 +45,16 @@ Required properties: | |||
31 | compatible ADC block) | 45 | compatible ADC block) |
32 | - vdd-supply VDD input supply. | 46 | - vdd-supply VDD input supply. |
33 | 47 | ||
48 | - samsung,syscon-phandle Contains the PMU system controller node | ||
49 | (To access the ADC_PHY register on Exynos5250/5420/5800/3250) | ||
50 | |||
34 | Note: child nodes can be added for auto probing from device tree. | 51 | Note: child nodes can be added for auto probing from device tree. |
35 | 52 | ||
36 | Example: adding device info in dtsi file | 53 | Example: adding device info in dtsi file |
37 | 54 | ||
38 | adc: adc@12D10000 { | 55 | adc: adc@12D10000 { |
39 | compatible = "samsung,exynos-adc-v1"; | 56 | compatible = "samsung,exynos-adc-v1"; |
40 | reg = <0x12D10000 0x100>, <0x10040718 0x4>; | 57 | reg = <0x12D10000 0x100>; |
41 | interrupts = <0 106 0>; | 58 | interrupts = <0 106 0>; |
42 | #io-channel-cells = <1>; | 59 | #io-channel-cells = <1>; |
43 | io-channel-ranges; | 60 | io-channel-ranges; |
@@ -46,13 +63,14 @@ adc: adc@12D10000 { | |||
46 | clock-names = "adc"; | 63 | clock-names = "adc"; |
47 | 64 | ||
48 | vdd-supply = <&buck5_reg>; | 65 | vdd-supply = <&buck5_reg>; |
66 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
49 | }; | 67 | }; |
50 | 68 | ||
51 | Example: adding device info in dtsi file for Exynos3250 with additional sclk | 69 | Example: adding device info in dtsi file for Exynos3250 with additional sclk |
52 | 70 | ||
53 | adc: adc@126C0000 { | 71 | adc: adc@126C0000 { |
54 | compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2; | 72 | compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2; |
55 | reg = <0x126C0000 0x100>, <0x10020718 0x4>; | 73 | reg = <0x126C0000 0x100>; |
56 | interrupts = <0 137 0>; | 74 | interrupts = <0 137 0>; |
57 | #io-channel-cells = <1>; | 75 | #io-channel-cells = <1>; |
58 | io-channel-ranges; | 76 | io-channel-ranges; |
@@ -61,6 +79,7 @@ adc: adc@126C0000 { | |||
61 | clock-names = "adc", "sclk"; | 79 | clock-names = "adc", "sclk"; |
62 | 80 | ||
63 | vdd-supply = <&buck5_reg>; | 81 | vdd-supply = <&buck5_reg>; |
82 | samsung,syscon-phandle = <&pmu_system_controller>; | ||
64 | }; | 83 | }; |
65 | 84 | ||
66 | Example: Adding child nodes in dts file | 85 | Example: Adding child nodes in dts file |
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt new file mode 100644 index 000000000000..51147cb5c036 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/shmobile.txt | |||
@@ -0,0 +1,71 @@ | |||
1 | Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings | ||
2 | -------------------------------------------------------------------- | ||
3 | |||
4 | SoCs: | ||
5 | |||
6 | - Emma Mobile EV2 | ||
7 | compatible = "renesas,emev2" | ||
8 | - RZ/A1H (R7S72100) | ||
9 | compatible = "renesas,r7s72100" | ||
10 | - SH-Mobile AP4 (R8A73720/SH7372) | ||
11 | compatible = "renesas,sh7372" | ||
12 | - SH-Mobile AG5 (R8A73A00/SH73A0) | ||
13 | compatible = "renesas,sh73a0" | ||
14 | - R-Mobile APE6 (R8A73A40) | ||
15 | compatible = "renesas,r8a73a4" | ||
16 | - R-Mobile A1 (R8A77400) | ||
17 | compatible = "renesas,r8a7740" | ||
18 | - R-Car M1A (R8A77781) | ||
19 | compatible = "renesas,r8a7778" | ||
20 | - R-Car H1 (R8A77790) | ||
21 | compatible = "renesas,r8a7779" | ||
22 | - R-Car H2 (R8A77900) | ||
23 | compatible = "renesas,r8a7790" | ||
24 | - R-Car M2-W (R8A77910) | ||
25 | compatible = "renesas,r8a7791" | ||
26 | - R-Car V2H (R8A77920) | ||
27 | compatible = "renesas,r8a7792" | ||
28 | - R-Car M2-N (R8A77930) | ||
29 | compatible = "renesas,r8a7793" | ||
30 | - R-Car E2 (R8A77940) | ||
31 | compatible = "renesas,r8a7794" | ||
32 | |||
33 | |||
34 | Boards: | ||
35 | |||
36 | - Alt | ||
37 | compatible = "renesas,alt", "renesas,r8a7794" | ||
38 | - APE6-EVM | ||
39 | compatible = "renesas,ape6evm", "renesas,r8a73a4" | ||
40 | - APE6-EVM - Reference Device Tree Implementation | ||
41 | compatible = "renesas,ape6evm-reference", "renesas,r8a73a4" | ||
42 | - Atmark Techno Armadillo-800 EVA | ||
43 | compatible = "renesas,armadillo800eva" | ||
44 | - BOCK-W | ||
45 | compatible = "renesas,bockw", "renesas,r8a7778" | ||
46 | - BOCK-W - Reference Device Tree Implementation | ||
47 | compatible = "renesas,bockw-reference", "renesas,r8a7778" | ||
48 | - Genmai (RTK772100BC00000BR) | ||
49 | compatible = "renesas,genmai", "renesas,r7s72100" | ||
50 | - Gose | ||
51 | compatible = "renesas,gose", "renesas,r8a7793" | ||
52 | - Henninger | ||
53 | compatible = "renesas,henninger", "renesas,r8a7791" | ||
54 | - Koelsch (RTP0RC7791SEB00010S) | ||
55 | compatible = "renesas,koelsch", "renesas,r8a7791" | ||
56 | - Kyoto Microcomputer Co. KZM-A9-Dual | ||
57 | compatible = "renesas,kzm9d", "renesas,emev2" | ||
58 | - Kyoto Microcomputer Co. KZM-A9-GT | ||
59 | compatible = "renesas,kzm9g", "renesas,sh73a0" | ||
60 | - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation | ||
61 | compatible = "renesas,kzm9g-reference", "renesas,sh73a0" | ||
62 | - Lager (RTP0RC7790SEB00010S) | ||
63 | compatible = "renesas,lager", "renesas,r8a7790" | ||
64 | - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd) | ||
65 | compatible = "renesas,mackerel" | ||
66 | - Marzen | ||
67 | compatible = "renesas,marzen", "renesas,r8a7779" | ||
68 | |||
69 | Note: Reference Device Tree Implementations are temporary implementations | ||
70 | to ease the migration from platform devices to Device Tree, and are | ||
71 | intended to be removed in the future. | ||
diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt index 6256ec31666d..2fdff5a806cf 100644 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt | |||
@@ -10,6 +10,12 @@ Required root node property: src | |||
10 | 10 | ||
11 | Boards with the Nomadik SoC include: | 11 | Boards with the Nomadik SoC include: |
12 | 12 | ||
13 | Nomadik NHK-15 board manufactured by ST Microelectronics: | ||
14 | |||
15 | Required root node property: | ||
16 | |||
17 | compatible="st,nomadik-nhk-15"; | ||
18 | |||
13 | S8815 "MiniKit" manufactured by Calao Systems: | 19 | S8815 "MiniKit" manufactured by Calao Systems: |
14 | 20 | ||
15 | Required root node property: | 21 | Required root node property: |
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt new file mode 100644 index 000000000000..42941fdefb11 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunxi.txt | |||
@@ -0,0 +1,12 @@ | |||
1 | Allwinner sunXi Platforms Device Tree Bindings | ||
2 | |||
3 | Each device tree must specify which Allwinner SoC it uses, | ||
4 | using one of the following compatible strings: | ||
5 | |||
6 | allwinner,sun4i-a10 | ||
7 | allwinner,sun5i-a10s | ||
8 | allwinner,sun5i-a13 | ||
9 | allwinner,sun6i-a31 | ||
10 | allwinner,sun7i-a20 | ||
11 | allwinner,sun8i-a23 | ||
12 | allwinner,sun9i-a80 | ||
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt new file mode 100644 index 000000000000..ccf0adddc820 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt | |||
@@ -0,0 +1,12 @@ | |||
1 | NVIDIA Tegra Flow Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "nvidia,tegra<chip>-flowctrl" | ||
5 | - reg: Should contain one register range (address and length) | ||
6 | |||
7 | Example: | ||
8 | |||
9 | flow-controller@60007000 { | ||
10 | compatible = "nvidia,tegra20-flowctrl"; | ||
11 | reg = <0x60007000 0x1000>; | ||
12 | }; | ||
diff --git a/Documentation/devicetree/bindings/arm/ux500/power_domain.txt b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt new file mode 100644 index 000000000000..5679d1742d3e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt | |||
@@ -0,0 +1,35 @@ | |||
1 | * ST-Ericsson UX500 PM Domains | ||
2 | |||
3 | UX500 supports multiple PM domains which are used to gate power to one or | ||
4 | more peripherals on the SOC. | ||
5 | |||
6 | The implementation of PM domains for UX500 are based upon the generic PM domain | ||
7 | and use the corresponding DT bindings. | ||
8 | |||
9 | ==PM domain providers== | ||
10 | |||
11 | Required properties: | ||
12 | - compatible: Must be "stericsson,ux500-pm-domains". | ||
13 | - #power-domain-cells : Number of cells in a power domain specifier, must be 1. | ||
14 | |||
15 | Example: | ||
16 | pm_domains: pm_domains0 { | ||
17 | compatible = "stericsson,ux500-pm-domains"; | ||
18 | #power-domain-cells = <1>; | ||
19 | }; | ||
20 | |||
21 | ==PM domain consumers== | ||
22 | |||
23 | Required properties: | ||
24 | - power-domains: A phandle and PM domain specifier. Below are the list of | ||
25 | valid specifiers: | ||
26 | |||
27 | Index Specifier | ||
28 | ----- --------- | ||
29 | 0 DOMAIN_VAPE | ||
30 | |||
31 | Example: | ||
32 | sdi0_per1@80126000 { | ||
33 | compatible = "arm,pl18x", "arm,primecell"; | ||
34 | power-domains = <&pm_domains DOMAIN_VAPE> | ||
35 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt index 1c8351604d38..b460edd12766 100644 --- a/Documentation/devicetree/bindings/ata/marvell.txt +++ b/Documentation/devicetree/bindings/ata/marvell.txt | |||
@@ -6,11 +6,17 @@ Required Properties: | |||
6 | - interrupts : Interrupt controller is using | 6 | - interrupts : Interrupt controller is using |
7 | - nr-ports : Number of SATA ports in use. | 7 | - nr-ports : Number of SATA ports in use. |
8 | 8 | ||
9 | Optional Properties: | ||
10 | - phys : List of phandles to sata phys | ||
11 | - phy-names : Should be "0", "1", etc, one number per phandle | ||
12 | |||
9 | Example: | 13 | Example: |
10 | 14 | ||
11 | sata@80000 { | 15 | sata@80000 { |
12 | compatible = "marvell,orion-sata"; | 16 | compatible = "marvell,orion-sata"; |
13 | reg = <0x80000 0x5000>; | 17 | reg = <0x80000 0x5000>; |
14 | interrupts = <21>; | 18 | interrupts = <21>; |
19 | phys = <&sata_phy0>, <&sata_phy1>; | ||
20 | phy-names = "0", "1"; | ||
15 | nr-ports = <2>; | 21 | nr-ports = <2>; |
16 | } | 22 | } |
diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt b/Documentation/devicetree/bindings/ata/qcom-sata.txt new file mode 100644 index 000000000000..094de91cd9fd --- /dev/null +++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt | |||
@@ -0,0 +1,48 @@ | |||
1 | * Qualcomm AHCI SATA Controller | ||
2 | |||
3 | SATA nodes are defined to describe on-chip Serial ATA controllers. | ||
4 | Each SATA controller should have its own node. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : compatible list, must contain "generic-ahci" | ||
8 | - interrupts : <interrupt mapping for SATA IRQ> | ||
9 | - reg : <registers mapping> | ||
10 | - phys : Must contain exactly one entry as specified | ||
11 | in phy-bindings.txt | ||
12 | - phy-names : Must be "sata-phy" | ||
13 | |||
14 | Required properties for "qcom,ipq806x-ahci" compatible: | ||
15 | - clocks : Must contain an entry for each entry in clock-names. | ||
16 | - clock-names : Shall be: | ||
17 | "slave_iface" - Fabric port AHB clock for SATA | ||
18 | "iface" - AHB clock | ||
19 | "core" - core clock | ||
20 | "rxoob" - RX out-of-band clock | ||
21 | "pmalive" - Power Module Alive clock | ||
22 | - assigned-clocks : Shall be: | ||
23 | SATA_RXOOB_CLK | ||
24 | SATA_PMALIVE_CLK | ||
25 | - assigned-clock-rates : Shall be: | ||
26 | 100Mhz (100000000) for SATA_RXOOB_CLK | ||
27 | 100Mhz (100000000) for SATA_PMALIVE_CLK | ||
28 | |||
29 | Example: | ||
30 | sata@29000000 { | ||
31 | compatible = "qcom,ipq806x-ahci", "generic-ahci"; | ||
32 | reg = <0x29000000 0x180>; | ||
33 | |||
34 | interrupts = <0 209 0x0>; | ||
35 | |||
36 | clocks = <&gcc SFAB_SATA_S_H_CLK>, | ||
37 | <&gcc SATA_H_CLK>, | ||
38 | <&gcc SATA_A_CLK>, | ||
39 | <&gcc SATA_RXOOB_CLK>, | ||
40 | <&gcc SATA_PMALIVE_CLK>; | ||
41 | clock-names = "slave_iface", "iface", "core", | ||
42 | "rxoob", "pmalive"; | ||
43 | assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; | ||
44 | assigned-clock-rates = <100000000>, <100000000>; | ||
45 | |||
46 | phys = <&sata_phy>; | ||
47 | phy-names = "sata-phy"; | ||
48 | }; | ||
diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt index 1e6111333fa8..2493a5a31655 100644 --- a/Documentation/devicetree/bindings/ata/sata_rcar.txt +++ b/Documentation/devicetree/bindings/ata/sata_rcar.txt | |||
@@ -3,16 +3,21 @@ | |||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : should contain one of the following: | 4 | - compatible : should contain one of the following: |
5 | - "renesas,sata-r8a7779" for R-Car H1 | 5 | - "renesas,sata-r8a7779" for R-Car H1 |
6 | - "renesas,sata-r8a7790" for R-Car H2 | 6 | ("renesas,rcar-sata" is deprecated) |
7 | - "renesas,sata-r8a7791" for R-Car M2 | 7 | - "renesas,sata-r8a7790-es1" for R-Car H2 ES1 |
8 | - "renesas,sata-r8a7790" for R-Car H2 other than ES1 | ||
9 | - "renesas,sata-r8a7791" for R-Car M2-W | ||
10 | - "renesas,sata-r8a7793" for R-Car M2-N | ||
8 | - reg : address and length of the SATA registers; | 11 | - reg : address and length of the SATA registers; |
9 | - interrupts : must consist of one interrupt specifier. | 12 | - interrupts : must consist of one interrupt specifier. |
13 | - clocks : must contain a reference to the functional clock. | ||
10 | 14 | ||
11 | Example: | 15 | Example: |
12 | 16 | ||
13 | sata: sata@fc600000 { | 17 | sata0: sata@ee300000 { |
14 | compatible = "renesas,sata-r8a7779"; | 18 | compatible = "renesas,sata-r8a7791"; |
15 | reg = <0xfc600000 0x2000>; | 19 | reg = <0 0xee300000 0 0x2000>; |
16 | interrupt-parent = <&gic>; | 20 | interrupt-parent = <&gic>; |
17 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | 21 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
22 | clocks = <&mstp8_clks R8A7791_CLK_SATA0>; | ||
18 | }; | 23 | }; |
diff --git a/Documentation/devicetree/bindings/btmrvl.txt b/Documentation/devicetree/bindings/btmrvl.txt new file mode 100644 index 000000000000..58f964bb0a52 --- /dev/null +++ b/Documentation/devicetree/bindings/btmrvl.txt | |||
@@ -0,0 +1,29 @@ | |||
1 | btmrvl | ||
2 | ------ | ||
3 | |||
4 | Required properties: | ||
5 | |||
6 | - compatible : must be "btmrvl,cfgdata" | ||
7 | |||
8 | Optional properties: | ||
9 | |||
10 | - btmrvl,cal-data : Calibration data downloaded to the device during | ||
11 | initialization. This is an array of 28 values(u8). | ||
12 | |||
13 | - btmrvl,gpio-gap : gpio and gap (in msecs) combination to be | ||
14 | configured. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | GPIO pin 13 is configured as a wakeup source and GAP is set to 100 msecs | ||
19 | in below example. | ||
20 | |||
21 | btmrvl { | ||
22 | compatible = "btmrvl,cfgdata"; | ||
23 | |||
24 | btmrvl,cal-data = /bits/ 8 < | ||
25 | 0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02 | ||
26 | 0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00 | ||
27 | 0x00 0x00 0xf0 0x00>; | ||
28 | btmrvl,gpio-gap = <0x0d64>; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/bus/bcma.txt b/Documentation/devicetree/bindings/bus/bcma.txt new file mode 100644 index 000000000000..edd44d802139 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/bcma.txt | |||
@@ -0,0 +1,53 @@ | |||
1 | Driver for ARM AXI Bus with Broadcom Plugins (bcma) | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : brcm,bus-axi | ||
6 | |||
7 | - reg : iomem address range of chipcommon core | ||
8 | |||
9 | The cores on the AXI bus are automatically detected by bcma with the | ||
10 | memory ranges they are using and they get registered afterwards. | ||
11 | Automatic detection of the IRQ number is not working on | ||
12 | BCM47xx/BCM53xx ARM SoCs. To assign IRQ numbers to the cores, provide | ||
13 | them manually through device tree. Use an interrupt-map to specify the | ||
14 | IRQ used by the devices on the bus. The first address is just an index, | ||
15 | because we do not have any special register. | ||
16 | |||
17 | The top-level axi bus may contain children representing attached cores | ||
18 | (devices). This is needed since some hardware details can't be auto | ||
19 | detected (e.g. IRQ numbers). Also some of the cores may be responsible | ||
20 | for extra things, e.g. ChipCommon providing access to the GPIO chip. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | axi@18000000 { | ||
25 | compatible = "brcm,bus-axi"; | ||
26 | reg = <0x18000000 0x1000>; | ||
27 | ranges = <0x00000000 0x18000000 0x00100000>; | ||
28 | #address-cells = <1>; | ||
29 | #size-cells = <1>; | ||
30 | #interrupt-cells = <1>; | ||
31 | interrupt-map-mask = <0x000fffff 0xffff>; | ||
32 | interrupt-map = | ||
33 | /* Ethernet Controller 0 */ | ||
34 | <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, | ||
35 | |||
36 | /* Ethernet Controller 1 */ | ||
37 | <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | ||
38 | |||
39 | /* PCIe Controller 0 */ | ||
40 | <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | ||
41 | <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, | ||
42 | <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | ||
43 | <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | ||
44 | <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | ||
45 | <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; | ||
46 | |||
47 | chipcommon { | ||
48 | reg = <0x00000000 0x1000>; | ||
49 | |||
50 | gpio-controller; | ||
51 | #gpio-cells = <2>; | ||
52 | }; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt index e2d501d20c9a..1eceefb20f01 100644 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt | |||
@@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible: should be "brcm,gisb-arb" | 5 | - compatible: |
6 | "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips | ||
7 | "brcm,bcm7435-gisb-arb" for newer 40nm chips | ||
8 | "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips | ||
9 | "brcm,bcm7038-gisb-arb" for 130nm chips | ||
6 | - reg: specifies the base physical address and size of the registers | 10 | - reg: specifies the base physical address and size of the registers |
7 | - interrupt-parent: specifies the phandle to the parent interrupt controller | 11 | - interrupt-parent: specifies the phandle to the parent interrupt controller |
8 | this arbiter gets interrupt line from | 12 | this arbiter gets interrupt line from |
diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt index 5fa44f52a0b8..5e16c3ccb061 100644 --- a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt +++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt | |||
@@ -48,9 +48,12 @@ Required properties: | |||
48 | - compatible: Should be set to "marvell,mbus-controller". | 48 | - compatible: Should be set to "marvell,mbus-controller". |
49 | 49 | ||
50 | - reg: Device's register space. | 50 | - reg: Device's register space. |
51 | Two entries are expected (see the examples below): | 51 | Two or three entries are expected (see the examples below): |
52 | the first one controls the devices decoding window and | 52 | the first one controls the devices decoding window, |
53 | the second one controls the SDRAM decoding window. | 53 | the second one controls the SDRAM decoding window and |
54 | the third controls the MBus bridge (only with the | ||
55 | marvell,armada370-mbus and marvell,armadaxp-mbus | ||
56 | compatible strings) | ||
54 | 57 | ||
55 | Example: | 58 | Example: |
56 | 59 | ||
@@ -67,7 +70,7 @@ Example: | |||
67 | 70 | ||
68 | mbusc: mbus-controller@20000 { | 71 | mbusc: mbus-controller@20000 { |
69 | compatible = "marvell,mbus-controller"; | 72 | compatible = "marvell,mbus-controller"; |
70 | reg = <0x20000 0x100>, <0x20180 0x20>; | 73 | reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; |
71 | }; | 74 | }; |
72 | 75 | ||
73 | /* more children ...*/ | 76 | /* more children ...*/ |
@@ -126,7 +129,7 @@ are skipped. | |||
126 | 129 | ||
127 | mbusc: mbus-controller@20000 { | 130 | mbusc: mbus-controller@20000 { |
128 | compatible = "marvell,mbus-controller"; | 131 | compatible = "marvell,mbus-controller"; |
129 | reg = <0x20000 0x100>, <0x20180 0x20>; | 132 | reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; |
130 | }; | 133 | }; |
131 | 134 | ||
132 | /* more children ...*/ | 135 | /* more children ...*/ |
@@ -170,7 +173,7 @@ Using this macro, the above example would be: | |||
170 | 173 | ||
171 | mbusc: mbus-controller@20000 { | 174 | mbusc: mbus-controller@20000 { |
172 | compatible = "marvell,mbus-controller"; | 175 | compatible = "marvell,mbus-controller"; |
173 | reg = <0x20000 0x100>, <0x20180 0x20>; | 176 | reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; |
174 | }; | 177 | }; |
175 | 178 | ||
176 | /* other children */ | 179 | /* other children */ |
@@ -266,7 +269,7 @@ See the example below, where a more complete device tree is shown: | |||
266 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; | 269 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
267 | 270 | ||
268 | mbusc: mbus-controller@20000 { | 271 | mbusc: mbus-controller@20000 { |
269 | reg = <0x20000 0x100>, <0x20180 0x20>; | 272 | reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; |
270 | }; | 273 | }; |
271 | 274 | ||
272 | interrupt-controller@20000 { | 275 | interrupt-controller@20000 { |
diff --git a/Documentation/devicetree/bindings/chosen.txt b/Documentation/devicetree/bindings/chosen.txt new file mode 100644 index 000000000000..ed838f453f7a --- /dev/null +++ b/Documentation/devicetree/bindings/chosen.txt | |||
@@ -0,0 +1,46 @@ | |||
1 | The chosen node | ||
2 | --------------- | ||
3 | |||
4 | The chosen node does not represent a real device, but serves as a place | ||
5 | for passing data between firmware and the operating system, like boot | ||
6 | arguments. Data in the chosen node does not represent the hardware. | ||
7 | |||
8 | |||
9 | stdout-path property | ||
10 | -------------------- | ||
11 | |||
12 | Device trees may specify the device to be used for boot console output | ||
13 | with a stdout-path property under /chosen, as described in ePAPR, e.g. | ||
14 | |||
15 | / { | ||
16 | chosen { | ||
17 | stdout-path = "/serial@f00:115200"; | ||
18 | }; | ||
19 | |||
20 | serial@f00 { | ||
21 | compatible = "vendor,some-uart"; | ||
22 | reg = <0xf00 0x10>; | ||
23 | }; | ||
24 | }; | ||
25 | |||
26 | If the character ":" is present in the value, this terminates the path. | ||
27 | The meaning of any characters following the ":" is device-specific, and | ||
28 | must be specified in the relevant binding documentation. | ||
29 | |||
30 | For UART devices, the preferred binding is a string in the form: | ||
31 | |||
32 | <baud>{<parity>{<bits>{<flow>}}} | ||
33 | |||
34 | where | ||
35 | |||
36 | baud - baud rate in decimal | ||
37 | parity - 'n' (none), 'o', (odd) or 'e' (even) | ||
38 | bits - number of data bits | ||
39 | flow - 'r' (rts) | ||
40 | |||
41 | For example: 115200n8r | ||
42 | |||
43 | Implementation note: Linux will look for the property "linux,stdout-path" or | ||
44 | on PowerPC "stdout" if "stdout-path" is not found. However, the | ||
45 | "linux,stdout-path" and "stdout" properties are deprecated. New platforms | ||
46 | should only use the "stdout-path" property. | ||
diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt index ecc69520bcea..11f5f95f571b 100644 --- a/Documentation/devicetree/bindings/clock/arm-integrator.txt +++ b/Documentation/devicetree/bindings/clock/arm-integrator.txt | |||
@@ -1,6 +1,6 @@ | |||
1 | Clock bindings for ARM Integrator and Versatile Core Module clocks | 1 | Clock bindings for ARM Integrator and Versatile Core Module clocks |
2 | 2 | ||
3 | Auxilary Oscillator Clock | 3 | Auxiliary Oscillator Clock |
4 | 4 | ||
5 | This is a configurable clock fed from a 24 MHz chrystal, | 5 | This is a configurable clock fed from a 24 MHz chrystal, |
6 | used for generating e.g. video clocks. It is located on the | 6 | used for generating e.g. video clocks. It is located on the |
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt index b3d544ca522a..7a4d4926f44e 100644 --- a/Documentation/devicetree/bindings/clock/at91-clock.txt +++ b/Documentation/devicetree/bindings/clock/at91-clock.txt | |||
@@ -74,6 +74,9 @@ Required properties: | |||
74 | "atmel,at91sam9x5-clk-utmi": | 74 | "atmel,at91sam9x5-clk-utmi": |
75 | at91 utmi clock | 75 | at91 utmi clock |
76 | 76 | ||
77 | "atmel,sama5d4-clk-h32mx": | ||
78 | at91 h32mx clock | ||
79 | |||
77 | Required properties for SCKC node: | 80 | Required properties for SCKC node: |
78 | - reg : defines the IO memory reserved for the SCKC. | 81 | - reg : defines the IO memory reserved for the SCKC. |
79 | - #size-cells : shall be 0 (reg is used to encode clk id). | 82 | - #size-cells : shall be 0 (reg is used to encode clk id). |
@@ -447,3 +450,14 @@ For example: | |||
447 | #clock-cells = <0>; | 450 | #clock-cells = <0>; |
448 | clocks = <&main>; | 451 | clocks = <&main>; |
449 | }; | 452 | }; |
453 | |||
454 | Required properties for 32 bits bus Matrix clock (h32mx clock): | ||
455 | - #clock-cells : from common clock binding; shall be set to 0. | ||
456 | - clocks : shall be the master clock source phandle. | ||
457 | |||
458 | For example: | ||
459 | h32ck: h32mxck { | ||
460 | #clock-cells = <0>; | ||
461 | compatible = "atmel,sama5d4-clk-h32mx"; | ||
462 | clocks = <&mck>; | ||
463 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt new file mode 100644 index 000000000000..00d26edec8bc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt | |||
@@ -0,0 +1,34 @@ | |||
1 | Broadcom Cygnus Clocks | ||
2 | |||
3 | This binding uses the common clock binding: | ||
4 | Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
5 | |||
6 | Currently various "fixed" clocks are declared for peripheral drivers that use | ||
7 | the common clock framework to reference their core clocks. Proper support of | ||
8 | these clocks will be added later | ||
9 | |||
10 | Device tree example: | ||
11 | |||
12 | clocks { | ||
13 | #address-cells = <1>; | ||
14 | #size-cells = <1>; | ||
15 | ranges; | ||
16 | |||
17 | osc: oscillator { | ||
18 | compatible = "fixed-clock"; | ||
19 | #clock-cells = <1>; | ||
20 | clock-frequency = <25000000>; | ||
21 | }; | ||
22 | |||
23 | apb_clk: apb_clk { | ||
24 | compatible = "fixed-clock"; | ||
25 | #clock-cells = <0>; | ||
26 | clock-frequency = <1000000000>; | ||
27 | }; | ||
28 | |||
29 | periph_clk: periph_clk { | ||
30 | compatible = "fixed-clock"; | ||
31 | #clock-cells = <0>; | ||
32 | clock-frequency = <500000000>; | ||
33 | }; | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt index aadc9c59e2d1..f57d9dd9ea85 100644 --- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt | |||
@@ -7,6 +7,8 @@ Required Properties: | |||
7 | 7 | ||
8 | - compatible: should be one of the following. | 8 | - compatible: should be one of the following. |
9 | - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. | 9 | - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC. |
10 | - "samsung,exynos3250-cmu-dmc" - controller compatible with | ||
11 | Exynos3250 SoC for Dynamic Memory Controller domain. | ||
10 | 12 | ||
11 | - reg: physical base address of the controller and length of memory mapped | 13 | - reg: physical base address of the controller and length of memory mapped |
12 | region. | 14 | region. |
@@ -20,7 +22,7 @@ All available clocks are defined as preprocessor macros in | |||
20 | dt-bindings/clock/exynos3250.h header and can be used in device | 22 | dt-bindings/clock/exynos3250.h header and can be used in device |
21 | tree sources. | 23 | tree sources. |
22 | 24 | ||
23 | Example 1: An example of a clock controller node is listed below. | 25 | Example 1: Examples of clock controller nodes are listed below. |
24 | 26 | ||
25 | cmu: clock-controller@10030000 { | 27 | cmu: clock-controller@10030000 { |
26 | compatible = "samsung,exynos3250-cmu"; | 28 | compatible = "samsung,exynos3250-cmu"; |
@@ -28,6 +30,12 @@ Example 1: An example of a clock controller node is listed below. | |||
28 | #clock-cells = <1>; | 30 | #clock-cells = <1>; |
29 | }; | 31 | }; |
30 | 32 | ||
33 | cmu_dmc: clock-controller@105C0000 { | ||
34 | compatible = "samsung,exynos3250-cmu-dmc"; | ||
35 | reg = <0x105C0000 0x2000>; | ||
36 | #clock-cells = <1>; | ||
37 | }; | ||
38 | |||
31 | Example 2: UART controller node that consumes the clock generated by the clock | 39 | Example 2: UART controller node that consumes the clock generated by the clock |
32 | controller. Refer to the standard clock bindings for information | 40 | controller. Refer to the standard clock bindings for information |
33 | about 'clocks' and 'clock-names' property. | 41 | about 'clocks' and 'clock-names' property. |
diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt new file mode 100644 index 000000000000..847d98bae8cf --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt | |||
@@ -0,0 +1,38 @@ | |||
1 | * Samsung Exynos4415 Clock Controller | ||
2 | |||
3 | The Exynos4415 clock controller generates and supplies clock to various | ||
4 | consumer devices within the Exynos4415 SoC. | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible: should be one of the following: | ||
9 | - "samsung,exynos4415-cmu" - for the main system clocks controller | ||
10 | (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains). | ||
11 | - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory | ||
12 | Controller (DMC) domain clock controller. | ||
13 | |||
14 | - reg: physical base address of the controller and length of memory mapped | ||
15 | region. | ||
16 | |||
17 | - #clock-cells: should be 1. | ||
18 | |||
19 | Each clock is assigned an identifier and client nodes can use this identifier | ||
20 | to specify the clock which they consume. | ||
21 | |||
22 | All available clocks are defined as preprocessor macros in | ||
23 | dt-bindings/clock/exynos4415.h header and can be used in device | ||
24 | tree sources. | ||
25 | |||
26 | Example 1: An example of a clock controller node is listed below. | ||
27 | |||
28 | cmu: clock-controller@10030000 { | ||
29 | compatible = "samsung,exynos4415-cmu"; | ||
30 | reg = <0x10030000 0x18000>; | ||
31 | #clock-cells = <1>; | ||
32 | }; | ||
33 | |||
34 | cmu-dmc: clock-controller@105C0000 { | ||
35 | compatible = "samsung,exynos4415-cmu-dmc"; | ||
36 | reg = <0x105C0000 0x3000>; | ||
37 | #clock-cells = <1>; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt new file mode 100644 index 000000000000..6d3d5f80c1c3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt | |||
@@ -0,0 +1,93 @@ | |||
1 | * Samsung Exynos7 Clock Controller | ||
2 | |||
3 | Exynos7 clock controller has various blocks which are instantiated | ||
4 | independently from the device-tree. These clock controllers | ||
5 | generate and supply clocks to various hardware blocks within | ||
6 | the SoC. | ||
7 | |||
8 | Each clock is assigned an identifier and client nodes can use | ||
9 | this identifier to specify the clock which they consume. All | ||
10 | available clocks are defined as preprocessor macros in | ||
11 | dt-bindings/clock/exynos7-clk.h header and can be used in | ||
12 | device tree sources. | ||
13 | |||
14 | External clocks: | ||
15 | |||
16 | There are several clocks that are generated outside the SoC. It | ||
17 | is expected that they are defined using standard clock bindings | ||
18 | with following clock-output-names: | ||
19 | |||
20 | - "fin_pll" - PLL input clock from XXTI | ||
21 | |||
22 | Required Properties for Clock Controller: | ||
23 | |||
24 | - compatible: clock controllers will use one of the following | ||
25 | compatible strings to indicate the clock controller | ||
26 | functionality. | ||
27 | |||
28 | - "samsung,exynos7-clock-topc" | ||
29 | - "samsung,exynos7-clock-top0" | ||
30 | - "samsung,exynos7-clock-top1" | ||
31 | - "samsung,exynos7-clock-ccore" | ||
32 | - "samsung,exynos7-clock-peric0" | ||
33 | - "samsung,exynos7-clock-peric1" | ||
34 | - "samsung,exynos7-clock-peris" | ||
35 | - "samsung,exynos7-clock-fsys0" | ||
36 | - "samsung,exynos7-clock-fsys1" | ||
37 | |||
38 | - reg: physical base address of the controller and the length of | ||
39 | memory mapped region. | ||
40 | |||
41 | - #clock-cells: should be 1. | ||
42 | |||
43 | - clocks: list of clock identifiers which are fed as the input to | ||
44 | the given clock controller. Please refer the next section to | ||
45 | find the input clocks for a given controller. | ||
46 | |||
47 | - clock-names: list of names of clocks which are fed as the input | ||
48 | to the given clock controller. | ||
49 | |||
50 | Input clocks for top0 clock controller: | ||
51 | - fin_pll | ||
52 | - dout_sclk_bus0_pll | ||
53 | - dout_sclk_bus1_pll | ||
54 | - dout_sclk_cc_pll | ||
55 | - dout_sclk_mfc_pll | ||
56 | |||
57 | Input clocks for top1 clock controller: | ||
58 | - fin_pll | ||
59 | - dout_sclk_bus0_pll | ||
60 | - dout_sclk_bus1_pll | ||
61 | - dout_sclk_cc_pll | ||
62 | - dout_sclk_mfc_pll | ||
63 | |||
64 | Input clocks for ccore clock controller: | ||
65 | - fin_pll | ||
66 | - dout_aclk_ccore_133 | ||
67 | |||
68 | Input clocks for peric0 clock controller: | ||
69 | - fin_pll | ||
70 | - dout_aclk_peric0_66 | ||
71 | - sclk_uart0 | ||
72 | |||
73 | Input clocks for peric1 clock controller: | ||
74 | - fin_pll | ||
75 | - dout_aclk_peric1_66 | ||
76 | - sclk_uart1 | ||
77 | - sclk_uart2 | ||
78 | - sclk_uart3 | ||
79 | |||
80 | Input clocks for peris clock controller: | ||
81 | - fin_pll | ||
82 | - dout_aclk_peris_66 | ||
83 | |||
84 | Input clocks for fsys0 clock controller: | ||
85 | - fin_pll | ||
86 | - dout_aclk_fsys0_200 | ||
87 | - dout_sclk_mmc2 | ||
88 | |||
89 | Input clocks for fsys1 clock controller: | ||
90 | - fin_pll | ||
91 | - dout_aclk_fsys1_200 | ||
92 | - dout_sclk_mmc0 | ||
93 | - dout_sclk_mmc1 | ||
diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt new file mode 100644 index 000000000000..d3379ff9b84b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | Binding for simple gpio gated clock. | ||
2 | |||
3 | This binding uses the common clock binding[1]. | ||
4 | |||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : shall be "gpio-gate-clock". | ||
9 | - #clock-cells : from common clock binding; shall be set to 0. | ||
10 | - enable-gpios : GPIO reference for enabling and disabling the clock. | ||
11 | |||
12 | Optional properties: | ||
13 | - clocks: Maximum of one parent clock is supported. | ||
14 | |||
15 | Example: | ||
16 | clock { | ||
17 | compatible = "gpio-gate-clock"; | ||
18 | clocks = <&parentclk>; | ||
19 | #clock-cells = <0>; | ||
20 | enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt new file mode 100644 index 000000000000..af376a01f2b7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * Marvell MMP2 Clock Controller | ||
2 | |||
3 | The MMP2 clock subsystem generates and supplies clock to various | ||
4 | controllers within the MMP2 SoC. | ||
5 | |||
6 | Required Properties: | ||
7 | |||
8 | - compatible: should be one of the following. | ||
9 | - "marvell,mmp2-clock" - controller compatible with MMP2 SoC. | ||
10 | |||
11 | - reg: physical base address of the clock subsystem and length of memory mapped | ||
12 | region. There are 3 places in SOC has clock control logic: | ||
13 | "mpmu", "apmu", "apbc". So three reg spaces need to be defined. | ||
14 | |||
15 | - #clock-cells: should be 1. | ||
16 | - #reset-cells: should be 1. | ||
17 | |||
18 | Each clock is assigned an identifier and client nodes use this identifier | ||
19 | to specify the clock which they consume. | ||
20 | |||
21 | All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>. | ||
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt new file mode 100644 index 000000000000..c62eb1d173a6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * Marvell PXA168 Clock Controller | ||
2 | |||
3 | The PXA168 clock subsystem generates and supplies clock to various | ||
4 | controllers within the PXA168 SoC. | ||
5 | |||
6 | Required Properties: | ||
7 | |||
8 | - compatible: should be one of the following. | ||
9 | - "marvell,pxa168-clock" - controller compatible with PXA168 SoC. | ||
10 | |||
11 | - reg: physical base address of the clock subsystem and length of memory mapped | ||
12 | region. There are 3 places in SOC has clock control logic: | ||
13 | "mpmu", "apmu", "apbc". So three reg spaces need to be defined. | ||
14 | |||
15 | - #clock-cells: should be 1. | ||
16 | - #reset-cells: should be 1. | ||
17 | |||
18 | Each clock is assigned an identifier and client nodes use this identifier | ||
19 | to specify the clock which they consume. | ||
20 | |||
21 | All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>. | ||
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt new file mode 100644 index 000000000000..d9f41f3c03a0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * Marvell PXA910 Clock Controller | ||
2 | |||
3 | The PXA910 clock subsystem generates and supplies clock to various | ||
4 | controllers within the PXA910 SoC. | ||
5 | |||
6 | Required Properties: | ||
7 | |||
8 | - compatible: should be one of the following. | ||
9 | - "marvell,pxa910-clock" - controller compatible with PXA910 SoC. | ||
10 | |||
11 | - reg: physical base address of the clock subsystem and length of memory mapped | ||
12 | region. There are 4 places in SOC has clock control logic: | ||
13 | "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined. | ||
14 | |||
15 | - #clock-cells: should be 1. | ||
16 | - #reset-cells: should be 1. | ||
17 | |||
18 | Each clock is assigned an identifier and client nodes use this identifier | ||
19 | to specify the clock which they consume. | ||
20 | |||
21 | All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>. | ||
diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt index 96ce71bbd745..9c40739a661a 100644 --- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt +++ b/Documentation/devicetree/bindings/clock/maxim,max77686.txt | |||
@@ -9,13 +9,21 @@ The MAX77686 contains three 32.768khz clock outputs that can be controlled | |||
9 | Following properties should be presend in main device node of the MFD chip. | 9 | Following properties should be presend in main device node of the MFD chip. |
10 | 10 | ||
11 | Required properties: | 11 | Required properties: |
12 | - #clock-cells: simple one-cell clock specifier format is used, where the | 12 | |
13 | only cell is used as an index of the clock inside the provider. Following | 13 | - #clock-cells: from common clock binding; shall be set to 1. |
14 | indices are allowed: | 14 | |
15 | Optional properties: | ||
16 | - clock-output-names: From common clock binding. | ||
17 | |||
18 | Each clock is assigned an identifier and client nodes can use this identifier | ||
19 | to specify the clock which they consume. Following indices are allowed: | ||
15 | - 0: 32khz_ap clock, | 20 | - 0: 32khz_ap clock, |
16 | - 1: 32khz_cp clock, | 21 | - 1: 32khz_cp clock, |
17 | - 2: 32khz_pmic clock. | 22 | - 2: 32khz_pmic clock. |
18 | 23 | ||
24 | Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h | ||
25 | header and can be used in device tree sources. | ||
26 | |||
19 | Example: Node of the MFD chip | 27 | Example: Node of the MFD chip |
20 | 28 | ||
21 | max77686: max77686@09 { | 29 | max77686: max77686@09 { |
@@ -34,5 +42,5 @@ Example: Clock consumer node | |||
34 | compatible = "bar,foo"; | 42 | compatible = "bar,foo"; |
35 | /* ... */ | 43 | /* ... */ |
36 | clock-names = "my-clock"; | 44 | clock-names = "my-clock"; |
37 | clocks = <&max77686 2>; | 45 | clocks = <&max77686 MAX77686_CLK_PMIC>; |
38 | }; | 46 | }; |
diff --git a/Documentation/devicetree/bindings/clock/maxim,max77802.txt b/Documentation/devicetree/bindings/clock/maxim,max77802.txt new file mode 100644 index 000000000000..c6dc7835f06c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/maxim,max77802.txt | |||
@@ -0,0 +1,44 @@ | |||
1 | Binding for Maxim MAX77802 32k clock generator block | ||
2 | |||
3 | This is a part of device tree bindings of MAX77802 multi-function device. | ||
4 | More information can be found in bindings/mfd/max77802.txt file. | ||
5 | |||
6 | The MAX77802 contains two 32.768khz clock outputs that can be controlled | ||
7 | (gated/ungated) over I2C. | ||
8 | |||
9 | Following properties should be present in main device node of the MFD chip. | ||
10 | |||
11 | Required properties: | ||
12 | - #clock-cells: From common clock binding; shall be set to 1. | ||
13 | |||
14 | Optional properties: | ||
15 | - clock-output-names: From common clock binding. | ||
16 | |||
17 | Each clock is assigned an identifier and client nodes can use this identifier | ||
18 | to specify the clock which they consume. Following indices are allowed: | ||
19 | - 0: 32khz_ap clock, | ||
20 | - 1: 32khz_cp clock. | ||
21 | |||
22 | Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h | ||
23 | header and can be used in device tree sources. | ||
24 | |||
25 | Example: Node of the MFD chip | ||
26 | |||
27 | max77802: max77802@09 { | ||
28 | compatible = "maxim,max77802"; | ||
29 | interrupt-parent = <&wakeup_eint>; | ||
30 | interrupts = <26 0>; | ||
31 | reg = <0x09>; | ||
32 | #clock-cells = <1>; | ||
33 | |||
34 | /* ... */ | ||
35 | }; | ||
36 | |||
37 | Example: Clock consumer node | ||
38 | |||
39 | foo@0 { | ||
40 | compatible = "bar,foo"; | ||
41 | /* ... */ | ||
42 | clock-names = "my-clock"; | ||
43 | clocks = <&max77802 MAX77802_CLK_32K_AP>; | ||
44 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/pxa-clock.txt b/Documentation/devicetree/bindings/clock/pxa-clock.txt new file mode 100644 index 000000000000..4b4a9024bd99 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/pxa-clock.txt | |||
@@ -0,0 +1,16 @@ | |||
1 | * Clock bindings for Marvell PXA chips | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "marvell,pxa-clocks" | ||
5 | - #clock-cells: Should be <1> | ||
6 | |||
7 | The clock consumer should specify the desired clock by having the clock | ||
8 | ID in its "clocks" phandle cell (see include/.../pxa-clock.h). | ||
9 | |||
10 | Examples: | ||
11 | |||
12 | pxa2xx_clks: pxa2xx_clks@41300004 { | ||
13 | compatible = "marvell,pxa-clocks"; | ||
14 | #clock-cells = <1>; | ||
15 | status = "okay"; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index 5666812fc42b..266ff9d23229 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt | |||
@@ -62,6 +62,8 @@ Required properties: | |||
62 | It takes parent's clock-frequency as its clock. | 62 | It takes parent's clock-frequency as its clock. |
63 | * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). | 63 | * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). |
64 | It takes parent's clock-frequency as its clock. | 64 | It takes parent's clock-frequency as its clock. |
65 | * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) | ||
66 | * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) | ||
65 | - #clock-cells: From common clock binding. The number of cells in a | 67 | - #clock-cells: From common clock binding. The number of cells in a |
66 | clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" | 68 | clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" |
67 | clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. | 69 | clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. |
@@ -128,8 +130,16 @@ Example for clock block and clock provider: | |||
128 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; | 130 | clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; |
129 | clock-output-names = "cmux1"; | 131 | clock-output-names = "cmux1"; |
130 | }; | 132 | }; |
133 | |||
134 | platform-pll: platform-pll@c00 { | ||
135 | #clock-cells = <1>; | ||
136 | reg = <0xc00 0x4>; | ||
137 | compatible = "fsl,qoriq-platform-pll-1.0"; | ||
138 | clocks = <&sysclk>; | ||
139 | clock-output-names = "platform-pll", "platform-pll-div2"; | ||
140 | }; | ||
131 | }; | 141 | }; |
132 | } | 142 | }; |
133 | 143 | ||
134 | Example for clock consumer: | 144 | Example for clock consumer: |
135 | 145 | ||
@@ -139,4 +149,4 @@ Example for clock consumer: | |||
139 | clocks = <&mux0>; | 149 | clocks = <&mux0>; |
140 | ... | 150 | ... |
141 | }; | 151 | }; |
142 | } | 152 | }; |
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt index 952e373178d2..054f65f9319c 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | |||
@@ -7,11 +7,16 @@ to 64. | |||
7 | Required Properties: | 7 | Required Properties: |
8 | 8 | ||
9 | - compatible: Must be one of the following | 9 | - compatible: Must be one of the following |
10 | - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks | ||
11 | - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks | ||
10 | - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks | 12 | - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks |
11 | - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks | 13 | - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks |
14 | - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks | ||
12 | - "renesas,cpg-div6-clock" for generic DIV6 clocks | 15 | - "renesas,cpg-div6-clock" for generic DIV6 clocks |
13 | - reg: Base address and length of the memory resource used by the DIV6 clock | 16 | - reg: Base address and length of the memory resource used by the DIV6 clock |
14 | - clocks: Reference to the parent clock | 17 | - clocks: Reference to the parent clock(s); either one, four, or eight |
18 | clocks must be specified. For clocks with multiple parents, invalid | ||
19 | settings must be specified as "<0>". | ||
15 | - #clock-cells: Must be 0 | 20 | - #clock-cells: Must be 0 |
16 | - clock-output-names: The name of the clock as a free-form string | 21 | - clock-output-names: The name of the clock as a free-form string |
17 | 22 | ||
@@ -19,10 +24,11 @@ Required Properties: | |||
19 | Example | 24 | Example |
20 | ------- | 25 | ------- |
21 | 26 | ||
22 | sd2_clk: sd2_clk@e6150078 { | 27 | sdhi2_clk: sdhi2_clk@e615007c { |
23 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | 28 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
24 | reg = <0 0xe6150078 0 4>; | 29 | reg = <0 0xe615007c 0 4>; |
25 | clocks = <&pll1_div2_clk>; | 30 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
31 | <0>, <&extal2_clk>; | ||
26 | #clock-cells = <0>; | 32 | #clock-cells = <0>; |
27 | clock-output-names = "sd2"; | 33 | clock-output-names = "sdhi2ck"; |
28 | }; | 34 | }; |
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt index 8a92b5fb3540..2e18676bd4b5 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | |||
@@ -11,9 +11,12 @@ Required Properties: | |||
11 | 11 | ||
12 | - compatible: Must be one of the following | 12 | - compatible: Must be one of the following |
13 | - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks | 13 | - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks |
14 | - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks | ||
14 | - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks | 15 | - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks |
15 | - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks | 16 | - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks |
16 | - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks | 17 | - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks |
18 | - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks | ||
19 | - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks | ||
17 | - "renesas,cpg-mstp-clock" for generic MSTP gate clocks | 20 | - "renesas,cpg-mstp-clock" for generic MSTP gate clocks |
18 | - reg: Base address and length of the I/O mapped registers used by the MSTP | 21 | - reg: Base address and length of the I/O mapped registers used by the MSTP |
19 | clocks. The first register is the clock control register and is mandatory. | 22 | clocks. The first register is the clock control register and is mandatory. |
@@ -23,11 +26,11 @@ Required Properties: | |||
23 | must appear in the same order as the output clocks. | 26 | must appear in the same order as the output clocks. |
24 | - #clock-cells: Must be 1 | 27 | - #clock-cells: Must be 1 |
25 | - clock-output-names: The name of the clocks as free-form strings | 28 | - clock-output-names: The name of the clocks as free-form strings |
26 | - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31) | 29 | - clock-indices: Indices of the gate clocks into the group (0 to 31) |
27 | 30 | ||
28 | The clocks, clock-output-names and renesas,clock-indices properties contain one | 31 | The clocks, clock-output-names and clock-indices properties contain one entry |
29 | entry per gate clock. The MSTP groups are sparsely populated. Unimplemented | 32 | per gate clock. The MSTP groups are sparsely populated. Unimplemented gate |
30 | gate clocks must not be declared. | 33 | clocks must not be declared. |
31 | 34 | ||
32 | 35 | ||
33 | Example | 36 | Example |
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt index 7b41c2fe54db..e6ad35b894f9 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | |||
@@ -8,6 +8,7 @@ Required Properties: | |||
8 | - compatible: Must be one of | 8 | - compatible: Must be one of |
9 | - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG | 9 | - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG |
10 | - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG | 10 | - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG |
11 | - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG | ||
11 | - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG | 12 | - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG |
12 | 13 | ||
13 | - reg: Base address and length of the memory resource used by the CPG | 14 | - reg: Base address and length of the memory resource used by the CPG |
diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 1d3ace088172..b7ee5c7e0f75 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt | |||
@@ -11,7 +11,7 @@ Please find an example below: | |||
11 | 11 | ||
12 | Clockgen block diagram | 12 | Clockgen block diagram |
13 | ------------------------------------------------------------------- | 13 | ------------------------------------------------------------------- |
14 | | Flexgen stucture | | 14 | | Flexgen structure | |
15 | | --------------------------------------------- | | 15 | | --------------------------------------------- | |
16 | | | ------- -------- -------- | | | 16 | | | ------- -------- -------- | | |
17 | clk_sysin | | | | | | | | | | 17 | clk_sysin | | | | | | | | | |
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index d3a5c3c6d677..67b2b99f2b33 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt | |||
@@ -10,14 +10,17 @@ Required properties: | |||
10 | "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 | 10 | "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 |
11 | "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 | 11 | "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 |
12 | "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 | 12 | "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 |
13 | "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 | ||
13 | "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock | 14 | "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock |
14 | "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock | 15 | "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock |
15 | "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 | 16 | "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31 |
17 | "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80 | ||
16 | "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock | 18 | "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock |
17 | "allwinner,sun4i-a10-axi-clk" - for the AXI clock | 19 | "allwinner,sun4i-a10-axi-clk" - for the AXI clock |
18 | "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 | 20 | "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 |
19 | "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates | 21 | "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates |
20 | "allwinner,sun4i-a10-ahb-clk" - for the AHB clock | 22 | "allwinner,sun4i-a10-ahb-clk" - for the AHB clock |
23 | "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 | ||
21 | "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 | 24 | "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 |
22 | "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 | 25 | "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 |
23 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s | 26 | "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s |
@@ -26,27 +29,36 @@ Required properties: | |||
26 | "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 | 29 | "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31 |
27 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 | 30 | "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31 |
28 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 | 31 | "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23 |
32 | "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80 | ||
33 | "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80 | ||
34 | "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80 | ||
29 | "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock | 35 | "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock |
30 | "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 | 36 | "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31 |
31 | "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 | 37 | "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23 |
38 | "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80 | ||
32 | "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 | 39 | "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10 |
33 | "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 | 40 | "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 |
34 | "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s | 41 | "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s |
35 | "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 | 42 | "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31 |
36 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 | 43 | "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20 |
37 | "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 | 44 | "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23 |
45 | "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80 | ||
38 | "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock | 46 | "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock |
39 | "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing | 47 | "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80 |
40 | "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 | 48 | "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10 |
41 | "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 | 49 | "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 |
42 | "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s | 50 | "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s |
43 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 | 51 | "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31 |
44 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 | 52 | "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20 |
45 | "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 | 53 | "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23 |
46 | "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31 | 54 | "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80 |
47 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 | 55 | "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 |
48 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 | 56 | "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23 |
57 | "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13 | ||
58 | "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10 | ||
59 | "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10 | ||
49 | "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks | 60 | "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks |
61 | "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23 | ||
50 | "allwinner,sun7i-a20-out-clk" - for the external output clocks | 62 | "allwinner,sun7i-a20-out-clk" - for the external output clocks |
51 | "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 | 63 | "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31 |
52 | "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 | 64 | "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 |
@@ -59,8 +71,9 @@ Required properties for all clocks: | |||
59 | multiplexed clocks, the list order must match the hardware | 71 | multiplexed clocks, the list order must match the hardware |
60 | programming order. | 72 | programming order. |
61 | - #clock-cells : from common clock binding; shall be set to 0 except for | 73 | - #clock-cells : from common clock binding; shall be set to 0 except for |
62 | "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and | 74 | the following compatibles where it shall be set to 1: |
63 | "allwinner,sun4i-pll6-clk" where it shall be set to 1 | 75 | "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk", |
76 | "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk" | ||
64 | - clock-output-names : shall be the corresponding names of the outputs. | 77 | - clock-output-names : shall be the corresponding names of the outputs. |
65 | If the clock module only has one output, the name shall be the | 78 | If the clock module only has one output, the name shall be the |
66 | module name. | 79 | module name. |
@@ -75,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a | |||
75 | "clocks" phandle cell. Consumers that are using a gated clock should | 88 | "clocks" phandle cell. Consumers that are using a gated clock should |
76 | provide an additional ID in their clock property. This ID is the | 89 | provide an additional ID in their clock property. This ID is the |
77 | offset of the bit controlling this particular gate in the register. | 90 | offset of the bit controlling this particular gate in the register. |
91 | For the other clocks with "#clock-cells" = 1, the additional ID shall | ||
92 | refer to the index of the output. | ||
93 | |||
94 | For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output | ||
95 | is the normal PLL6 output, or "pll6". The second output is rate doubled | ||
96 | PLL6, or "pll6x2". | ||
78 | 97 | ||
79 | For example: | 98 | For example: |
80 | 99 | ||
@@ -102,6 +121,14 @@ pll5: clk@01c20020 { | |||
102 | clock-output-names = "pll5_ddr", "pll5_other"; | 121 | clock-output-names = "pll5_ddr", "pll5_other"; |
103 | }; | 122 | }; |
104 | 123 | ||
124 | pll6: clk@01c20028 { | ||
125 | #clock-cells = <1>; | ||
126 | compatible = "allwinner,sun6i-a31-pll6-clk"; | ||
127 | reg = <0x01c20028 0x4>; | ||
128 | clocks = <&osc24M>; | ||
129 | clock-output-names = "pll6", "pll6x2"; | ||
130 | }; | ||
131 | |||
105 | cpu: cpu@01c20054 { | 132 | cpu: cpu@01c20054 { |
106 | #clock-cells = <0>; | 133 | #clock-cells = <0>; |
107 | compatible = "allwinner,sun4i-a10-cpu-clk"; | 134 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt index c80863d344ac..63f9f1ac3439 100644 --- a/Documentation/devicetree/bindings/clock/vf610-clock.txt +++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt | |||
@@ -5,6 +5,19 @@ Required properties: | |||
5 | - reg: Address and length of the register set | 5 | - reg: Address and length of the register set |
6 | - #clock-cells: Should be <1> | 6 | - #clock-cells: Should be <1> |
7 | 7 | ||
8 | Optional properties: | ||
9 | - clocks: list of clock identifiers which are external input clocks to the | ||
10 | given clock controller. Please refer the next section to find | ||
11 | the input clocks for a given controller. | ||
12 | - clock-names: list of names of clocks which are exteral input clocks to the | ||
13 | given clock controller. | ||
14 | |||
15 | Input clocks for top clock controller: | ||
16 | - sxosc (external crystal oscillator 32KHz, recommended) | ||
17 | - fxosc (external crystal oscillator 24MHz, recommended) | ||
18 | - audio_ext | ||
19 | - enet_ext | ||
20 | |||
8 | The clock consumer should specify the desired clock by having the clock | 21 | The clock consumer should specify the desired clock by having the clock |
9 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h | 22 | ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h |
10 | for the full list of VF610 clock IDs. | 23 | for the full list of VF610 clock IDs. |
@@ -15,6 +28,8 @@ clks: ccm@4006b000 { | |||
15 | compatible = "fsl,vf610-ccm"; | 28 | compatible = "fsl,vf610-ccm"; |
16 | reg = <0x4006b000 0x1000>; | 29 | reg = <0x4006b000 0x1000>; |
17 | #clock-cells = <1>; | 30 | #clock-cells = <1>; |
31 | clocks = <&sxosc>, <&fxosc>; | ||
32 | clock-names = "sxosc", "fxosc"; | ||
18 | }; | 33 | }; |
19 | 34 | ||
20 | uart1: serial@40028000 { | 35 | uart1: serial@40028000 { |
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt index 366690cb86a3..e41c98ffbccb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt | |||
@@ -1,8 +1,8 @@ | |||
1 | Generic CPU0 cpufreq driver | 1 | Generic cpufreq driver |
2 | 2 | ||
3 | It is a generic cpufreq driver for CPU0 frequency management. It | 3 | It is a generic DT based cpufreq driver for frequency management. It supports |
4 | supports both uniprocessor (UP) and symmetric multiprocessor (SMP) | 4 | both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share |
5 | systems which share clock and voltage across all CPUs. | 5 | clock and voltage across all CPUs. |
6 | 6 | ||
7 | Both required and optional properties listed below must be defined | 7 | Both required and optional properties listed below must be defined |
8 | under node /cpus/cpu@0. | 8 | under node /cpus/cpu@0. |
diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt index 5c65eccd0e56..e8a35c71e947 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt | |||
@@ -1,5 +1,5 @@ | |||
1 | Freescale SAHARA Cryptographic Accelerator included in some i.MX chips. | 1 | Freescale SAHARA Cryptographic Accelerator included in some i.MX chips. |
2 | Currently only i.MX27 is supported. | 2 | Currently only i.MX27 and i.MX53 are supported. |
3 | 3 | ||
4 | Required properties: | 4 | Required properties: |
5 | - compatible : Should be "fsl,<soc>-sahara" | 5 | - compatible : Should be "fsl,<soc>-sahara" |
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt index c0a20cd972e3..baf8a3c1b469 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt | |||
@@ -1,5 +1,5 @@ | |||
1 | SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM). | 1 | SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM). |
2 | Currently Freescale powerpc chip C29X is embeded with SEC 6. | 2 | Currently Freescale powerpc chip C29X is embedded with SEC 6. |
3 | SEC 6 device tree binding include: | 3 | SEC 6 device tree binding include: |
4 | -SEC 6 Node | 4 | -SEC 6 Node |
5 | -Job Ring Node | 5 | -Job Ring Node |
diff --git a/Documentation/devicetree/bindings/dma/atmel-xdma.txt b/Documentation/devicetree/bindings/dma/atmel-xdma.txt new file mode 100644 index 000000000000..0eb2b3207e08 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/atmel-xdma.txt | |||
@@ -0,0 +1,54 @@ | |||
1 | * Atmel Extensible Direct Memory Access Controller (XDMAC) | ||
2 | |||
3 | * XDMA Controller | ||
4 | Required properties: | ||
5 | - compatible: Should be "atmel,<chip>-dma". | ||
6 | <chip> compatible description: | ||
7 | - sama5d4: first SoC adding the XDMAC | ||
8 | - reg: Should contain DMA registers location and length. | ||
9 | - interrupts: Should contain DMA interrupt. | ||
10 | - #dma-cells: Must be <1>, used to represent the number of integer cells in | ||
11 | the dmas property of client devices. | ||
12 | - The 1st cell specifies the channel configuration register: | ||
13 | - bit 13: SIF, source interface identifier, used to get the memory | ||
14 | interface identifier, | ||
15 | - bit 14: DIF, destination interface identifier, used to get the peripheral | ||
16 | interface identifier, | ||
17 | - bit 30-24: PERID, peripheral identifier. | ||
18 | |||
19 | Example: | ||
20 | |||
21 | dma1: dma-controller@f0004000 { | ||
22 | compatible = "atmel,sama5d4-dma"; | ||
23 | reg = <0xf0004000 0x200>; | ||
24 | interrupts = <50 4 0>; | ||
25 | #dma-cells = <1>; | ||
26 | }; | ||
27 | |||
28 | |||
29 | * DMA clients | ||
30 | DMA clients connected to the Atmel XDMA controller must use the format | ||
31 | described in the dma.txt file, using a one-cell specifier for each channel. | ||
32 | The two cells in order are: | ||
33 | 1. A phandle pointing to the DMA controller. | ||
34 | 2. Channel configuration register. Configurable fields are: | ||
35 | - bit 13: SIF, source interface identifier, used to get the memory | ||
36 | interface identifier, | ||
37 | - bit 14: DIF, destination interface identifier, used to get the peripheral | ||
38 | interface identifier, | ||
39 | - bit 30-24: PERID, peripheral identifier. | ||
40 | |||
41 | Example: | ||
42 | |||
43 | i2c2: i2c@f8024000 { | ||
44 | compatible = "atmel,at91sam9x5-i2c"; | ||
45 | reg = <0xf8024000 0x4000>; | ||
46 | interrupts = <34 4 6>; | ||
47 | dmas = <&dma1 | ||
48 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | ||
49 | | AT91_XDMAC_DT_PERID(6))>, | ||
50 | <&dma1 | ||
51 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | ||
52 | | AT91_XDMAC_DT_PERID(7))>; | ||
53 | dma-names = "tx", "rx"; | ||
54 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 4659fd952301..dc8d3aac1aa9 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | |||
@@ -48,6 +48,7 @@ The full ID of peripheral types can be found below. | |||
48 | 21 ESAI | 48 | 21 ESAI |
49 | 22 SSI Dual FIFO (needs firmware ver >= 2) | 49 | 22 SSI Dual FIFO (needs firmware ver >= 2) |
50 | 23 Shared ASRC | 50 | 23 Shared ASRC |
51 | 24 SAI | ||
51 | 52 | ||
52 | The third cell specifies the transfer priority as below. | 53 | The third cell specifies the transfer priority as below. |
53 | 54 | ||
diff --git a/Documentation/devicetree/bindings/dma/qcom_adm.txt b/Documentation/devicetree/bindings/dma/qcom_adm.txt new file mode 100644 index 000000000000..9bcab9115982 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom_adm.txt | |||
@@ -0,0 +1,62 @@ | |||
1 | QCOM ADM DMA Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must contain "qcom,adm" for IPQ/APQ8064 and MSM8960 | ||
5 | - reg: Address range for DMA registers | ||
6 | - interrupts: Should contain one interrupt shared by all channels | ||
7 | - #dma-cells: must be <2>. First cell denotes the channel number. Second cell | ||
8 | denotes CRCI (client rate control interface) flow control assignment. | ||
9 | - clocks: Should contain the core clock and interface clock. | ||
10 | - clock-names: Must contain "core" for the core clock and "iface" for the | ||
11 | interface clock. | ||
12 | - resets: Must contain an entry for each entry in reset names. | ||
13 | - reset-names: Must include the following entries: | ||
14 | - clk | ||
15 | - c0 | ||
16 | - c1 | ||
17 | - c2 | ||
18 | - qcom,ee: indicates the security domain identifier used in the secure world. | ||
19 | |||
20 | Example: | ||
21 | adm_dma: dma@18300000 { | ||
22 | compatible = "qcom,adm"; | ||
23 | reg = <0x18300000 0x100000>; | ||
24 | interrupts = <0 170 0>; | ||
25 | #dma-cells = <2>; | ||
26 | |||
27 | clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; | ||
28 | clock-names = "core", "iface"; | ||
29 | |||
30 | resets = <&gcc ADM0_RESET>, | ||
31 | <&gcc ADM0_C0_RESET>, | ||
32 | <&gcc ADM0_C1_RESET>, | ||
33 | <&gcc ADM0_C2_RESET>; | ||
34 | reset-names = "clk", "c0", "c1", "c2"; | ||
35 | qcom,ee = <0>; | ||
36 | }; | ||
37 | |||
38 | DMA clients must use the format descripted in the dma.txt file, using a three | ||
39 | cell specifier for each channel. | ||
40 | |||
41 | Each dmas request consists of 3 cells: | ||
42 | 1. phandle pointing to the DMA controller | ||
43 | 2. channel number | ||
44 | 3. CRCI assignment, if applicable. If no CRCI flow control is required, use 0. | ||
45 | The CRCI is used for flow control. It identifies the peripheral device that | ||
46 | is the source/destination for the transferred data. | ||
47 | |||
48 | Example: | ||
49 | |||
50 | spi4: spi@1a280000 { | ||
51 | status = "ok"; | ||
52 | spi-max-frequency = <50000000>; | ||
53 | |||
54 | pinctrl-0 = <&spi_pins>; | ||
55 | pinctrl-names = "default"; | ||
56 | |||
57 | cs-gpios = <&qcom_pinmux 20 0>; | ||
58 | |||
59 | dmas = <&adm_dma 6 9>, | ||
60 | <&adm_dma 5 10>; | ||
61 | dma-names = "rx", "tx"; | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt index d75a9d767022..f8c3311b7153 100644 --- a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt +++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt | |||
@@ -1,7 +1,9 @@ | |||
1 | QCOM BAM DMA controller | 1 | QCOM BAM DMA controller |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: must contain "qcom,bam-v1.4.0" for MSM8974 | 4 | - compatible: must be one of the following: |
5 | * "qcom,bam-v1.4.0" for MSM8974, APQ8074 and APQ8084 | ||
6 | * "qcom,bam-v1.3.0" for APQ8064, IPQ8064 and MSM8960 | ||
5 | - reg: Address range for DMA registers | 7 | - reg: Address range for DMA registers |
6 | - interrupts: Should contain the one interrupt shared by all channels | 8 | - interrupts: Should contain the one interrupt shared by all channels |
7 | - #dma-cells: must be <1>, the cell in the dmas property of the client device | 9 | - #dma-cells: must be <1>, the cell in the dmas property of the client device |
diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt index 3e145c1675b1..9cdcba24d7c3 100644 --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt | |||
@@ -4,7 +4,7 @@ This driver follows the generic DMA bindings defined in dma.txt. | |||
4 | 4 | ||
5 | Required properties: | 5 | Required properties: |
6 | 6 | ||
7 | - compatible: Must be "allwinner,sun6i-a31-dma" | 7 | - compatible: Must be "allwinner,sun6i-a31-dma" or "allwinner,sun8i-a23-dma" |
8 | - reg: Should contain the registers base address and length | 8 | - reg: Should contain the registers base address and length |
9 | - interrupts: Should contain a reference to the interrupt used by this device | 9 | - interrupts: Should contain a reference to the interrupt used by this device |
10 | - clocks: Should contain a reference to the parent AHB clock | 10 | - clocks: Should contain a reference to the parent AHB clock |
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt new file mode 100644 index 000000000000..2291c4098730 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | |||
@@ -0,0 +1,65 @@ | |||
1 | Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream | ||
2 | target devices. It can be configured to have one channel or two channels. | ||
3 | If configured as two channels, one is to transmit to the device and another | ||
4 | is to receive from the device. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: Should be "xlnx,axi-dma-1.00.a" | ||
8 | - #dma-cells: Should be <1>, see "dmas" property below | ||
9 | - reg: Should contain DMA registers location and length. | ||
10 | - dma-channel child node: Should have atleast one channel and can have upto | ||
11 | two channels per device. This node specifies the properties of each | ||
12 | DMA channel (see child node properties below). | ||
13 | |||
14 | Optional properties: | ||
15 | - xlnx,include-sg: Tells whether configured for Scatter-mode in | ||
16 | the hardware. | ||
17 | |||
18 | Required child node properties: | ||
19 | - compatible: It should be either "xlnx,axi-dma-mm2s-channel" or | ||
20 | "xlnx,axi-dma-s2mm-channel". | ||
21 | - interrupts: Should contain per channel DMA interrupts. | ||
22 | - xlnx,datawidth: Should contain the stream data width, take values | ||
23 | {32,64...1024}. | ||
24 | |||
25 | Option child node properties: | ||
26 | - xlnx,include-dre: Tells whether hardware is configured for Data | ||
27 | Realignment Engine. | ||
28 | |||
29 | Example: | ||
30 | ++++++++ | ||
31 | |||
32 | axi_dma_0: axidma@40400000 { | ||
33 | compatible = "xlnx,axi-dma-1.00.a"; | ||
34 | #dma_cells = <1>; | ||
35 | reg = < 0x40400000 0x10000 >; | ||
36 | dma-channel@40400000 { | ||
37 | compatible = "xlnx,axi-dma-mm2s-channel"; | ||
38 | interrupts = < 0 59 4 >; | ||
39 | xlnx,datawidth = <0x40>; | ||
40 | } ; | ||
41 | dma-channel@40400030 { | ||
42 | compatible = "xlnx,axi-dma-s2mm-channel"; | ||
43 | interrupts = < 0 58 4 >; | ||
44 | xlnx,datawidth = <0x40>; | ||
45 | } ; | ||
46 | } ; | ||
47 | |||
48 | |||
49 | * DMA client | ||
50 | |||
51 | Required properties: | ||
52 | - dmas: a list of <[DMA device phandle] [Channel ID]> pairs, | ||
53 | where Channel ID is '0' for write/tx and '1' for read/rx | ||
54 | channel. | ||
55 | - dma-names: a list of DMA channel names, one per "dmas" entry | ||
56 | |||
57 | Example: | ||
58 | ++++++++ | ||
59 | |||
60 | dmatest_0: dmatest@0 { | ||
61 | compatible ="xlnx,axi-dma-test-1.00.a"; | ||
62 | dmas = <&axi_dma_0 0 | ||
63 | &axi_dma_0 1>; | ||
64 | dma-names = "dma0", "dma1"; | ||
65 | } ; | ||
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt index 1405ed071bb4..e4c4d47f8137 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_vdma.txt | |||
@@ -25,7 +25,7 @@ Required child node properties: | |||
25 | - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or | 25 | - compatible: It should be either "xlnx,axi-vdma-mm2s-channel" or |
26 | "xlnx,axi-vdma-s2mm-channel". | 26 | "xlnx,axi-vdma-s2mm-channel". |
27 | - interrupts: Should contain per channel VDMA interrupts. | 27 | - interrupts: Should contain per channel VDMA interrupts. |
28 | - xlnx,data-width: Should contain the stream data width, take values | 28 | - xlnx,datawidth: Should contain the stream data width, take values |
29 | {32,64...1024}. | 29 | {32,64...1024}. |
30 | 30 | ||
31 | Optional child node properties: | 31 | Optional child node properties: |
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt index e75f0e549fff..e75f0e549fff 100644 --- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/drm/imx/fsl-imx-drm.txt | |||
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt b/Documentation/devicetree/bindings/drm/imx/hdmi.txt index 1b756cf9afb0..1b756cf9afb0 100644 --- a/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt +++ b/Documentation/devicetree/bindings/drm/imx/hdmi.txt | |||
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt b/Documentation/devicetree/bindings/drm/imx/ldb.txt index 443bcb6134d5..443bcb6134d5 100644 --- a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt +++ b/Documentation/devicetree/bindings/drm/imx/ldb.txt | |||
diff --git a/Documentation/devicetree/bindings/drm/tilcdc/panel.txt b/Documentation/devicetree/bindings/drm/tilcdc/panel.txt index 9301c330d1a6..4ab9e2300907 100644 --- a/Documentation/devicetree/bindings/drm/tilcdc/panel.txt +++ b/Documentation/devicetree/bindings/drm/tilcdc/panel.txt | |||
@@ -18,6 +18,10 @@ Required properties: | |||
18 | Documentation/devicetree/bindings/video/display-timing.txt for display | 18 | Documentation/devicetree/bindings/video/display-timing.txt for display |
19 | timing binding details. | 19 | timing binding details. |
20 | 20 | ||
21 | Optional properties: | ||
22 | - backlight: phandle of the backlight device attached to the panel | ||
23 | - enable-gpios: GPIO pin to enable or disable the panel | ||
24 | |||
21 | Recommended properties: | 25 | Recommended properties: |
22 | - pinctrl-names, pinctrl-0: the pincontrol settings to configure | 26 | - pinctrl-names, pinctrl-0: the pincontrol settings to configure |
23 | muxing properly for pins that connect to TFP410 device | 27 | muxing properly for pins that connect to TFP410 device |
@@ -29,6 +33,9 @@ Example: | |||
29 | compatible = "ti,tilcdc,panel"; | 33 | compatible = "ti,tilcdc,panel"; |
30 | pinctrl-names = "default"; | 34 | pinctrl-names = "default"; |
31 | pinctrl-0 = <&bone_lcd3_cape_lcd_pins>; | 35 | pinctrl-0 = <&bone_lcd3_cape_lcd_pins>; |
36 | backlight = <&backlight>; | ||
37 | enable-gpios = <&gpio3 19 0>; | ||
38 | |||
32 | panel-info { | 39 | panel-info { |
33 | ac-bias = <255>; | 40 | ac-bias = <255>; |
34 | ac-bias-intrpt = <0>; | 41 | ac-bias-intrpt = <0>; |
diff --git a/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt b/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt new file mode 100644 index 000000000000..6dede7d11532 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | |||
2 | * Richtek RT8973A - Micro USB Switch device | ||
3 | |||
4 | The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A | ||
5 | is a USB port accessory detector and switch that is optimized to protect low | ||
6 | voltage system from abnormal high input voltage (up to 28V) and supports high | ||
7 | speed USB operation. Also, RT8973A support 'auto-configuration' mode. | ||
8 | If auto-configuration mode is enabled, RT8973A would control internal h/w patch | ||
9 | for USB D-/D+ switching. | ||
10 | |||
11 | Required properties: | ||
12 | - compatible: Should be "richtek,rt8973a-muic" | ||
13 | - reg: Specifies the I2C slave address of the MUIC block. It should be 0x14 | ||
14 | - interrupt-parent: Specifies the phandle of the interrupt controller to which | ||
15 | the interrupts from rt8973a are delivered to. | ||
16 | - interrupts: Interrupt specifiers for detection interrupt sources. | ||
17 | |||
18 | Example: | ||
19 | |||
20 | rt8973a@14 { | ||
21 | compatible = "richtek,rt8973a-muic"; | ||
22 | interrupt-parent = <&gpx1>; | ||
23 | interrupts = <5 0>; | ||
24 | reg = <0x14>; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt b/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt new file mode 100644 index 000000000000..7bb1a9d60133 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | * 74XX MMIO GPIO driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should contain one of the following: | ||
5 | "ti,741g125": for 741G125 (1-bit Input), | ||
6 | "ti,741g174": for 741G74 (1-bit Output), | ||
7 | "ti,742g125": for 742G125 (2-bit Input), | ||
8 | "ti,7474" : for 7474 (2-bit Output), | ||
9 | "ti,74125" : for 74125 (4-bit Input), | ||
10 | "ti,74175" : for 74175 (4-bit Output), | ||
11 | "ti,74365" : for 74365 (6-bit Input), | ||
12 | "ti,74174" : for 74174 (6-bit Output), | ||
13 | "ti,74244" : for 74244 (8-bit Input), | ||
14 | "ti,74273" : for 74273 (8-bit Output), | ||
15 | "ti,741624" : for 741624 (16-bit Input), | ||
16 | "ti,7416374": for 7416374 (16-bit Output). | ||
17 | - reg: Physical base address and length where IC resides. | ||
18 | - gpio-controller: Marks the device node as a gpio controller. | ||
19 | - #gpio-cells: Should be two. The first cell is the pin number and | ||
20 | the second cell is used to specify the GPIO polarity: | ||
21 | 0 = Active High, | ||
22 | 1 = Active Low. | ||
23 | |||
24 | Example: | ||
25 | ctrl: gpio@30008004 { | ||
26 | compatible = "ti,74174"; | ||
27 | reg = <0x30008004 0x1>; | ||
28 | gpio-controller; | ||
29 | #gpio-cells = <2>; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt new file mode 100644 index 000000000000..6c7e6c7302f5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | Keystone 2 DSP GPIO controller bindings | ||
2 | |||
3 | HOST OS userland running on ARM can send interrupts to DSP cores using | ||
4 | the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core. | ||
5 | This is one of the component used by the IPC mechanism used on Keystone SOCs. | ||
6 | |||
7 | For example TCI6638K2K SoC has 8 DSP GPIO controllers: | ||
8 | - 8 for C66x CorePacx CPUs 0-7 | ||
9 | |||
10 | Keystone 2 DSP GPIO controller has specific features: | ||
11 | - each GPIO can be configured only as output pin; | ||
12 | - setting GPIO value to 1 causes IRQ generation on target DSP core; | ||
13 | - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still | ||
14 | pending. | ||
15 | |||
16 | Required Properties: | ||
17 | - compatible: should be "ti,keystone-dsp-gpio" | ||
18 | - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to | ||
19 | access device state control registers and the offset of device's specific | ||
20 | registers within device state control registers range. | ||
21 | - gpio-controller: Marks the device node as a gpio controller. | ||
22 | - #gpio-cells: Should be 2. | ||
23 | |||
24 | Please refer to gpio.txt in this directory for details of the common GPIO | ||
25 | bindings used by client devices. | ||
26 | |||
27 | Example: | ||
28 | dspgpio0: keystone_dsp_gpio@02620240 { | ||
29 | compatible = "ti,keystone-dsp-gpio"; | ||
30 | ti,syscon-dev = <&devctrl 0x240>; | ||
31 | gpio-controller; | ||
32 | #gpio-cells = <2>; | ||
33 | }; | ||
34 | |||
35 | dsp0: dsp0 { | ||
36 | compatible = "linux,rproc-user"; | ||
37 | ... | ||
38 | kick-gpio = <&dspgpio0 27>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt index c306a2d0f2b1..f3332b9a8ed4 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt | |||
@@ -57,6 +57,8 @@ Optional device specific properties: | |||
57 | occurred on. If it is not set, the interrupt are only generated for the | 57 | occurred on. If it is not set, the interrupt are only generated for the |
58 | bank they belong to. | 58 | bank they belong to. |
59 | On devices with only one interrupt output this property is useless. | 59 | On devices with only one interrupt output this property is useless. |
60 | - microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This | ||
61 | configures the IRQ output polarity as active high. | ||
60 | 62 | ||
61 | Example I2C (with interrupt): | 63 | Example I2C (with interrupt): |
62 | gpiom1: gpio@20 { | 64 | gpiom1: gpio@20 { |
diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt new file mode 100644 index 000000000000..b9a42f294dd0 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | * NXP PCA953x I2C GPIO multiplexer | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Has to contain one of the following: | ||
5 | nxp,pca9505 | ||
6 | nxp,pca9534 | ||
7 | nxp,pca9535 | ||
8 | nxp,pca9536 | ||
9 | nxp,pca9537 | ||
10 | nxp,pca9538 | ||
11 | nxp,pca9539 | ||
12 | nxp,pca9554 | ||
13 | nxp,pca9555 | ||
14 | nxp,pca9556 | ||
15 | nxp,pca9557 | ||
16 | nxp,pca9574 | ||
17 | nxp,pca9575 | ||
18 | nxp,pca9698 | ||
19 | maxim,max7310 | ||
20 | maxim,max7312 | ||
21 | maxim,max7313 | ||
22 | maxim,max7315 | ||
23 | ti,pca6107 | ||
24 | ti,tca6408 | ||
25 | ti,tca6416 | ||
26 | ti,tca6424 | ||
27 | exar,xra1202 | ||
28 | |||
29 | Example: | ||
30 | |||
31 | |||
32 | gpio@20 { | ||
33 | compatible = "nxp,pca9505"; | ||
34 | reg = <0x20>; | ||
35 | pinctrl-names = "default"; | ||
36 | pinctrl-0 = <&pinctrl_pca9505>; | ||
37 | interrupt-parent = <&gpio3>; | ||
38 | interrupts = <23 IRQ_TYPE_LEVEL_LOW>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-restart.txt b/Documentation/devicetree/bindings/gpio/gpio-restart.txt new file mode 100644 index 000000000000..af3701bc15c4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-restart.txt | |||
@@ -0,0 +1,54 @@ | |||
1 | Drive a GPIO line that can be used to restart the system from a restart | ||
2 | handler. | ||
3 | |||
4 | This binding supports level and edge triggered reset. At driver load | ||
5 | time, the driver will request the given gpio line and install a restart | ||
6 | handler. If the optional properties 'open-source' is not found, the GPIO line | ||
7 | will be driven in the inactive state. Otherwise its not driven until | ||
8 | the restart is initiated. | ||
9 | |||
10 | When the system is restarted, the restart handler will be invoked in | ||
11 | priority order. The gpio is configured as an output, and driven active, | ||
12 | triggering a level triggered reset condition. This will also cause an | ||
13 | inactive->active edge condition, triggering positive edge triggered | ||
14 | reset. After a delay specified by active-delay, the GPIO is set to | ||
15 | inactive, thus causing an active->inactive edge, triggering negative edge | ||
16 | triggered reset. After a delay specified by inactive-delay, the GPIO | ||
17 | is driven active again. After a delay specified by wait-delay, the | ||
18 | restart handler completes allowing other restart handlers to be attempted. | ||
19 | |||
20 | Required properties: | ||
21 | - compatible : should be "gpio-restart". | ||
22 | - gpios : The GPIO to set high/low, see "gpios property" in | ||
23 | Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be | ||
24 | low to reset the board set it to "Active Low", otherwise set | ||
25 | gpio to "Active High". | ||
26 | |||
27 | Optional properties: | ||
28 | - open-source : Treat the GPIO as being open source and defer driving | ||
29 | it to when the restart is initiated. If this optional property is not | ||
30 | specified, the GPIO is initialized as an output in its inactive state. | ||
31 | - priority : A priority ranging from 0 to 255 (default 128) according to | ||
32 | the following guidelines: | ||
33 | 0: Restart handler of last resort, with limited restart | ||
34 | capabilities | ||
35 | 128: Default restart handler; use if no other restart handler is | ||
36 | expected to be available, and/or if restart functionality is | ||
37 | sufficient to restart the entire system | ||
38 | 255: Highest priority restart handler, will preempt all other | ||
39 | restart handlers | ||
40 | - active-delay: Delay (default 100) to wait after driving gpio active [ms] | ||
41 | - inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms] | ||
42 | - wait-delay: Delay (default 3000) to wait after completing restart | ||
43 | sequence [ms] | ||
44 | |||
45 | Examples: | ||
46 | |||
47 | gpio-restart { | ||
48 | compatible = "gpio-restart"; | ||
49 | gpios = <&gpio 4 0>; | ||
50 | priority = <128>; | ||
51 | active-delay = <100>; | ||
52 | inactive-delay = <100>; | ||
53 | wait-delay = <3000>; | ||
54 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt new file mode 100644 index 000000000000..436cc99c6598 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt | |||
@@ -0,0 +1,55 @@ | |||
1 | * Freescale VF610 PORT/GPIO module | ||
2 | |||
3 | The Freescale PORT/GPIO modules are two adjacent modules providing GPIO | ||
4 | functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of | ||
5 | each, and each PORT module has its own interrupt. | ||
6 | |||
7 | Required properties for GPIO node: | ||
8 | - compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio" | ||
9 | - reg : The first reg tuple represents the PORT module, the second tuple | ||
10 | the GPIO module. | ||
11 | - interrupts : Should be the port interrupt shared by all 32 pins. | ||
12 | - gpio-controller : Marks the device node as a gpio controller. | ||
13 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
14 | the second cell is used to specify the gpio polarity: | ||
15 | 0 = active high | ||
16 | 1 = active low | ||
17 | - interrupt-controller: Marks the device node as an interrupt controller. | ||
18 | - #interrupt-cells : Should be 2. The first cell is the GPIO number. | ||
19 | The second cell bits[3:0] is used to specify trigger type and level flags: | ||
20 | 1 = low-to-high edge triggered. | ||
21 | 2 = high-to-low edge triggered. | ||
22 | 4 = active high level-sensitive. | ||
23 | 8 = active low level-sensitive. | ||
24 | |||
25 | Note: Each GPIO port should have an alias correctly numbered in "aliases" | ||
26 | node. | ||
27 | |||
28 | Examples: | ||
29 | |||
30 | aliases { | ||
31 | gpio0 = &gpio1; | ||
32 | gpio1 = &gpio2; | ||
33 | }; | ||
34 | |||
35 | gpio1: gpio@40049000 { | ||
36 | compatible = "fsl,vf610-gpio"; | ||
37 | reg = <0x40049000 0x1000 0x400ff000 0x40>; | ||
38 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | ||
39 | gpio-controller; | ||
40 | #gpio-cells = <2>; | ||
41 | interrupt-controller; | ||
42 | #interrupt-cells = <2>; | ||
43 | gpio-ranges = <&iomuxc 0 0 32>; | ||
44 | }; | ||
45 | |||
46 | gpio2: gpio@4004a000 { | ||
47 | compatible = "fsl,vf610-gpio"; | ||
48 | reg = <0x4004a000 0x1000 0x400ff040 0x40>; | ||
49 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | ||
50 | gpio-controller; | ||
51 | #gpio-cells = <2>; | ||
52 | interrupt-controller; | ||
53 | #interrupt-cells = <2>; | ||
54 | gpio-ranges = <&iomuxc 0 32 32>; | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt new file mode 100644 index 000000000000..86dbb05e7758 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt | |||
@@ -0,0 +1,22 @@ | |||
1 | APM X-Gene SoC GPIO controller bindings | ||
2 | |||
3 | This is a gpio controller that is part of the flash controller. | ||
4 | This gpio controller controls a total of 48 gpios. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "apm,xgene-gpio" for X-Gene GPIO controller | ||
8 | - reg: Physical base address and size of the controller's registers | ||
9 | - #gpio-cells: Should be two. | ||
10 | - first cell is the pin number | ||
11 | - second cell is used to specify the gpio polarity: | ||
12 | 0 = active high | ||
13 | 1 = active low | ||
14 | - gpio-controller: Marks the device node as a GPIO controller. | ||
15 | |||
16 | Example: | ||
17 | gpio0: gpio0@1701c000 { | ||
18 | compatible = "apm,xgene-gpio"; | ||
19 | reg = <0x0 0x1701c000 0x0 0x40>; | ||
20 | gpio-controller; | ||
21 | #gpio-cells = <2>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index 3fb8f53071b8..b9bd1d64cfa6 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt | |||
@@ -13,13 +13,22 @@ properties, each containing a 'gpio-list': | |||
13 | gpio-specifier : Array of #gpio-cells specifying specific gpio | 13 | gpio-specifier : Array of #gpio-cells specifying specific gpio |
14 | (controller specific) | 14 | (controller specific) |
15 | 15 | ||
16 | GPIO properties should be named "[<name>-]gpios". The exact | 16 | GPIO properties should be named "[<name>-]gpios", with <name> being the purpose |
17 | meaning of each gpios property must be documented in the device tree | 17 | of this GPIO for the device. While a non-existent <name> is considered valid |
18 | binding for each device. | 18 | for compatibility reasons (resolving to the "gpios" property), it is not allowed |
19 | for new bindings. | ||
19 | 20 | ||
20 | For example, the following could be used to describe GPIO pins used | 21 | GPIO properties can contain one or more GPIO phandles, but only in exceptional |
21 | as chip select lines; with chip selects 0, 1 and 3 populated, and chip | 22 | cases should they contain more than one. If your device uses several GPIOs with |
22 | select 2 left empty: | 23 | distinct functions, reference each of them under its own property, giving it a |
24 | meaningful name. The only case where an array of GPIOs is accepted is when | ||
25 | several GPIOs serve the same function (e.g. a parallel data line). | ||
26 | |||
27 | The exact purpose of each gpios property must be documented in the device tree | ||
28 | binding of the device. | ||
29 | |||
30 | The following example could be used to describe GPIO pins used as device enable | ||
31 | and bit-banged data signals: | ||
23 | 32 | ||
24 | gpio1: gpio1 { | 33 | gpio1: gpio1 { |
25 | gpio-controller | 34 | gpio-controller |
@@ -30,10 +39,12 @@ select 2 left empty: | |||
30 | #gpio-cells = <1>; | 39 | #gpio-cells = <1>; |
31 | }; | 40 | }; |
32 | [...] | 41 | [...] |
33 | chipsel-gpios = <&gpio1 12 0>, | 42 | |
34 | <&gpio1 13 0>, | 43 | enable-gpios = <&gpio2 2>; |
35 | <0>, /* holes are permitted, means no GPIO 2 */ | 44 | data-gpios = <&gpio1 12 0>, |
36 | <&gpio2 2>; | 45 | <&gpio1 13 0>, |
46 | <&gpio1 14 0>, | ||
47 | <&gpio1 15 0>; | ||
37 | 48 | ||
38 | Note that gpio-specifier length is controller dependent. In the | 49 | Note that gpio-specifier length is controller dependent. In the |
39 | above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 | 50 | above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 |
@@ -42,16 +53,17 @@ only uses one. | |||
42 | gpio-specifier may encode: bank, pin position inside the bank, | 53 | gpio-specifier may encode: bank, pin position inside the bank, |
43 | whether pin is open-drain and whether pin is logically inverted. | 54 | whether pin is open-drain and whether pin is logically inverted. |
44 | Exact meaning of each specifier cell is controller specific, and must | 55 | Exact meaning of each specifier cell is controller specific, and must |
45 | be documented in the device tree binding for the device. | 56 | be documented in the device tree binding for the device. Use the macros |
57 | defined in include/dt-bindings/gpio/gpio.h whenever possible: | ||
46 | 58 | ||
47 | Example of a node using GPIOs: | 59 | Example of a node using GPIOs: |
48 | 60 | ||
49 | node { | 61 | node { |
50 | gpios = <&qe_pio_e 18 0>; | 62 | enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; |
51 | }; | 63 | }; |
52 | 64 | ||
53 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | 65 | GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes |
54 | and GPIO flags as accepted by the "qe_pio_e" gpio-controller. | 66 | GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. |
55 | 67 | ||
56 | 1.1) GPIO specifier best practices | 68 | 1.1) GPIO specifier best practices |
57 | ---------------------------------- | 69 | ---------------------------------- |
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index 66416261e14d..b2afdb27adeb 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt | |||
@@ -19,7 +19,7 @@ Required properties: | |||
19 | - gpio-controller : Marks the device node as a gpio controller. | 19 | - gpio-controller : Marks the device node as a gpio controller. |
20 | - #gpio-cells : Should be one. It is the pin number. | 20 | - #gpio-cells : Should be one. It is the pin number. |
21 | 21 | ||
22 | Example: | 22 | Example for a MMP platform: |
23 | 23 | ||
24 | gpio: gpio@d4019000 { | 24 | gpio: gpio@d4019000 { |
25 | compatible = "marvell,mmp-gpio"; | 25 | compatible = "marvell,mmp-gpio"; |
@@ -32,6 +32,19 @@ Example: | |||
32 | #interrupt-cells = <1>; | 32 | #interrupt-cells = <1>; |
33 | }; | 33 | }; |
34 | 34 | ||
35 | Example for a PXA3xx platform: | ||
36 | |||
37 | gpio: gpio@40e00000 { | ||
38 | compatible = "intel,pxa3xx-gpio"; | ||
39 | reg = <0x40e00000 0x10000>; | ||
40 | interrupt-names = "gpio0", "gpio1", "gpio_mux"; | ||
41 | interrupts = <8 9 10>; | ||
42 | gpio-controller; | ||
43 | #gpio-cells = <0x2>; | ||
44 | interrupt-controller; | ||
45 | #interrupt-cells = <0x2>; | ||
46 | }; | ||
47 | |||
35 | * Marvell Orion GPIO Controller | 48 | * Marvell Orion GPIO Controller |
36 | 49 | ||
37 | Required properties: | 50 | Required properties: |
diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt index a2c416bcbccc..89058d375b7c 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt | |||
@@ -7,4 +7,4 @@ Required properties: | |||
7 | - bit 0 specifies polarity (0 for normal, 1 for inverted) | 7 | - bit 0 specifies polarity (0 for normal, 1 for inverted) |
8 | - gpio-controller : Marks the device node as a GPIO controller. | 8 | - gpio-controller : Marks the device node as a GPIO controller. |
9 | - interrupts : Interrupt mapping for GPIO IRQ. | 9 | - interrupts : Interrupt mapping for GPIO IRQ. |
10 | 10 | - gpio-ranges : Interaction with the PINCTRL subsystem. | |
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 941a26aa4322..38fb86f28ba2 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | |||
@@ -6,7 +6,9 @@ Required Properties: | |||
6 | - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. | 6 | - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. |
7 | - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. | 7 | - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. |
8 | - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. | 8 | - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. |
9 | - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2) compatible GPIO controller. | 9 | - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. |
10 | - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. | ||
11 | - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. | ||
10 | - "renesas,gpio-rcar": for generic R-Car GPIO controller. | 12 | - "renesas,gpio-rcar": for generic R-Car GPIO controller. |
11 | 13 | ||
12 | - reg: Base address and length of each memory resource used by the GPIO | 14 | - reg: Base address and length of each memory resource used by the GPIO |
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt index b48f4ef31d93..4c32ef0b7db8 100644 --- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt | |||
@@ -191,6 +191,8 @@ of the following host1x client modules: | |||
191 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection | 191 | - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection |
192 | - nvidia,edid: supplies a binary EDID blob | 192 | - nvidia,edid: supplies a binary EDID blob |
193 | - nvidia,panel: phandle of a display panel | 193 | - nvidia,panel: phandle of a display panel |
194 | - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang | ||
195 | up with in order to support up to 8 data lanes | ||
194 | 196 | ||
195 | - sor: serial output resource | 197 | - sor: serial output resource |
196 | 198 | ||
diff --git a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt index 2d150c311a05..c99eb34e640b 100644 --- a/Documentation/devicetree/bindings/gpu/st,stih4xx.txt +++ b/Documentation/devicetree/bindings/gpu/st,stih4xx.txt | |||
@@ -68,7 +68,7 @@ STMicroelectronics stih4xx platforms | |||
68 | number of clocks may depend of the SoC type. | 68 | number of clocks may depend of the SoC type. |
69 | - clock-names: names of the clocks listed in clocks property in the same | 69 | - clock-names: names of the clocks listed in clocks property in the same |
70 | order. | 70 | order. |
71 | - hdmi,hpd-gpio: gpio id to detect if an hdmi cable is plugged or not. | 71 | - ddc: phandle of an I2C controller used for DDC EDID probing |
72 | 72 | ||
73 | sti-hda: | 73 | sti-hda: |
74 | Required properties: | 74 | Required properties: |
@@ -83,6 +83,22 @@ sti-hda: | |||
83 | - clock-names: names of the clocks listed in clocks property in the same | 83 | - clock-names: names of the clocks listed in clocks property in the same |
84 | order. | 84 | order. |
85 | 85 | ||
86 | sti-hqvdp: | ||
87 | must be a child of sti-display-subsystem | ||
88 | Required properties: | ||
89 | - compatible: "st,stih<chip>-hqvdp" | ||
90 | - reg: Physical base address of the IP registers and length of memory mapped region. | ||
91 | - clocks: from common clock binding: handle hardware IP needed clocks, the | ||
92 | number of clocks may depend of the SoC type. | ||
93 | See ../clocks/clock-bindings.txt for details. | ||
94 | - clock-names: names of the clocks listed in clocks property in the same | ||
95 | order. | ||
96 | - resets: resets to be used by the device | ||
97 | See ../reset/reset.txt for details. | ||
98 | - reset-names: names of the resets listed in resets property in the same | ||
99 | order. | ||
100 | - st,vtg: phandle on vtg main device node. | ||
101 | |||
86 | Example: | 102 | Example: |
87 | 103 | ||
88 | / { | 104 | / { |
@@ -173,7 +189,6 @@ Example: | |||
173 | interrupt-names = "irq"; | 189 | interrupt-names = "irq"; |
174 | clock-names = "pix", "tmds", "phy", "audio"; | 190 | clock-names = "pix", "tmds", "phy", "audio"; |
175 | clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>; | 191 | clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>; |
176 | hdmi,hpd-gpio = <&PIO2 5>; | ||
177 | }; | 192 | }; |
178 | 193 | ||
179 | sti-hda@fe85a000 { | 194 | sti-hda@fe85a000 { |
@@ -184,6 +199,16 @@ Example: | |||
184 | clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; | 199 | clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>; |
185 | }; | 200 | }; |
186 | }; | 201 | }; |
202 | |||
203 | sti-hqvdp@9c000000 { | ||
204 | compatible = "st,stih407-hqvdp"; | ||
205 | reg = <0x9C00000 0x100000>; | ||
206 | clock-names = "hqvdp", "pix_main"; | ||
207 | clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>; | ||
208 | reset-names = "hqvdp"; | ||
209 | resets = <&softreset STIH407_HDQVDP_SOFTRESET>; | ||
210 | st,vtg = <&vtg_main>; | ||
211 | }; | ||
187 | }; | 212 | }; |
188 | ... | 213 | ... |
189 | }; | 214 | }; |
diff --git a/Documentation/devicetree/bindings/hwmon/ltc2978.txt b/Documentation/devicetree/bindings/hwmon/ltc2978.txt new file mode 100644 index 000000000000..ed2f09dc2483 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/ltc2978.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | ltc2978 | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should contain one of: | ||
5 | * "lltc,ltc2974" | ||
6 | * "lltc,ltc2977" | ||
7 | * "lltc,ltc2978" | ||
8 | * "lltc,ltc3880" | ||
9 | * "lltc,ltc3883" | ||
10 | * "lltc,ltm4676" | ||
11 | - reg: I2C slave address | ||
12 | |||
13 | Optional properties: | ||
14 | - regulators: A node that houses a sub-node for each regulator controlled by | ||
15 | the device. Each sub-node is identified using the node's name, with valid | ||
16 | values listed below. The content of each sub-node is defined by the | ||
17 | standard binding for regulators; see regulator.txt. | ||
18 | |||
19 | Valid names of regulators depend on number of supplies supported per device: | ||
20 | * ltc2974 : vout0 - vout3 | ||
21 | * ltc2977 : vout0 - vout7 | ||
22 | * ltc2978 : vout0 - vout7 | ||
23 | * ltc3880 : vout0 - vout1 | ||
24 | * ltc3883 : vout0 | ||
25 | * ltm4676 : vout0 - vout1 | ||
26 | |||
27 | Example: | ||
28 | ltc2978@5e { | ||
29 | compatible = "lltc,ltc2978"; | ||
30 | reg = <0x5e>; | ||
31 | regulators { | ||
32 | vout0 { | ||
33 | regulator-name = "FPGA-2.5V"; | ||
34 | }; | ||
35 | vout2 { | ||
36 | regulator-name = "FPGA-1.5V"; | ||
37 | }; | ||
38 | }; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt index 2391e5c41999..fcca8e744f41 100644 --- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt +++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt | |||
@@ -25,6 +25,9 @@ Requires node properties: | |||
25 | - "io-channels" Channel node of ADC to be used for | 25 | - "io-channels" Channel node of ADC to be used for |
26 | conversion. | 26 | conversion. |
27 | 27 | ||
28 | Optional node properties: | ||
29 | - "#thermal-sensor-cells" Used to expose itself to thermal fw. | ||
30 | |||
28 | Read more about iio bindings at | 31 | Read more about iio bindings at |
29 | Documentation/devicetree/bindings/iio/iio-bindings.txt | 32 | Documentation/devicetree/bindings/iio/iio-bindings.txt |
30 | 33 | ||
diff --git a/Documentation/devicetree/bindings/hwrng/atmel-trng.txt b/Documentation/devicetree/bindings/hwrng/atmel-trng.txt new file mode 100644 index 000000000000..4ac5aaa2d024 --- /dev/null +++ b/Documentation/devicetree/bindings/hwrng/atmel-trng.txt | |||
@@ -0,0 +1,16 @@ | |||
1 | Atmel TRNG (True Random Number Generator) block | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "atmel,at91sam9g45-trng" | ||
5 | - reg : Offset and length of the register set of this block | ||
6 | - interrupts : the interrupt number for the TRNG block | ||
7 | - clocks: should contain the TRNG clk source | ||
8 | |||
9 | Example: | ||
10 | |||
11 | trng@fffcc000 { | ||
12 | compatible = "atmel,at91sam9g45-trng"; | ||
13 | reg = <0xfffcc000 0x4000>; | ||
14 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; | ||
15 | clocks = <&trng_clk>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt b/Documentation/devicetree/bindings/i2c/i2c-axxia.txt new file mode 100644 index 000000000000..2296d782b4c2 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-axxia.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | LSI Axxia I2C | ||
2 | |||
3 | Required properties : | ||
4 | - compatible : Must be "lsi,api2c" | ||
5 | - reg : Offset and length of the register set for the device | ||
6 | - interrupts : the interrupt specifier | ||
7 | - #address-cells : Must be <1>; | ||
8 | - #size-cells : Must be <0>; | ||
9 | - clock-names : Must contain "i2c". | ||
10 | - clocks: Must contain an entry for each name in clock-names. See the common | ||
11 | clock bindings. | ||
12 | |||
13 | Optional properties : | ||
14 | - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, | ||
15 | the default 100 kHz frequency will be used. As only Normal and Fast modes | ||
16 | are supported, possible values are 100000 and 400000. | ||
17 | |||
18 | Example : | ||
19 | |||
20 | i2c@02010084000 { | ||
21 | compatible = "lsi,api2c"; | ||
22 | device_type = "i2c"; | ||
23 | #address-cells = <1>; | ||
24 | #size-cells = <0>; | ||
25 | reg = <0x20 0x10084000 0x00 0x1000>; | ||
26 | interrupts = <0 19 4>; | ||
27 | clocks = <&clk_per>; | ||
28 | clock-names = "i2c"; | ||
29 | clock-frequency = <400000>; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt index 5199b0c8cf7a..fee26dc3e858 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt | |||
@@ -14,10 +14,10 @@ Optional properties : | |||
14 | - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds. | 14 | - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds. |
15 | This option is only supported in hardware blocks version 1.11a or newer. | 15 | This option is only supported in hardware blocks version 1.11a or newer. |
16 | 16 | ||
17 | - i2c-scl-falling-time : should contain the SCL falling time in nanoseconds. | 17 | - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds. |
18 | This value which is by default 300ns is used to compute the tLOW period. | 18 | This value which is by default 300ns is used to compute the tLOW period. |
19 | 19 | ||
20 | - i2c-sda-falling-time : should contain the SDA falling time in nanoseconds. | 20 | - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds. |
21 | This value which is by default 300ns is used to compute the tHIGH period. | 21 | This value which is by default 300ns is used to compute the tHIGH period. |
22 | 22 | ||
23 | Example : | 23 | Example : |
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt index d4745e31f5c6..2dbc0b62daa6 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt | |||
@@ -12,6 +12,8 @@ Required properties: | |||
12 | on Exynos5250 and Exynos5420 SoCs. | 12 | on Exynos5250 and Exynos5420 SoCs. |
13 | -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available | 13 | -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available |
14 | on Exynos5260 SoCs. | 14 | on Exynos5260 SoCs. |
15 | -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available | ||
16 | on Exynos7 SoCs. | ||
15 | 17 | ||
16 | - reg: physical base address of the controller and length of memory mapped | 18 | - reg: physical base address of the controller and length of memory mapped |
17 | region. | 19 | region. |
diff --git a/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt new file mode 100644 index 000000000000..f98b37401e6e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-hix5hd2.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | I2C for Hisilicon hix5hd2 chipset platform | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "hisilicon,hix5hd2-i2c" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: interrupt number to the cpu. | ||
8 | - #address-cells = <1>; | ||
9 | - #size-cells = <0>; | ||
10 | - clocks: phandles to input clocks. | ||
11 | |||
12 | Optional properties: | ||
13 | - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 | ||
14 | - Child nodes conforming to i2c bus binding | ||
15 | |||
16 | Examples: | ||
17 | I2C0@f8b10000 { | ||
18 | compatible = "hisilicon,hix5hd2-i2c"; | ||
19 | reg = <0xf8b10000 0x1000>; | ||
20 | interrupts = <0 38 4>; | ||
21 | clocks = <&clock HIX5HD2_I2C0_RST>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | } | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt b/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt new file mode 100644 index 000000000000..b6461602dca5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-img-scb.txt | |||
@@ -0,0 +1,26 @@ | |||
1 | IMG Serial Control Bus (SCB) I2C Controller | ||
2 | |||
3 | Required Properties: | ||
4 | - compatible: "img,scb-i2c" | ||
5 | - reg: Physical base address and length of controller registers | ||
6 | - interrupts: Interrupt number used by the controller | ||
7 | - clocks : Should contain a clock specifier for each entry in clock-names | ||
8 | - clock-names : Should contain the following entries: | ||
9 | "scb", for the SCB core clock. | ||
10 | "sys", for the system clock. | ||
11 | - clock-frequency: The I2C bus frequency in Hz | ||
12 | - #address-cells: Should be <1> | ||
13 | - #size-cells: Should be <0> | ||
14 | |||
15 | Example: | ||
16 | |||
17 | i2c@18100000 { | ||
18 | compatible = "img,scb-i2c"; | ||
19 | reg = <0x18100000 0x200>; | ||
20 | interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; | ||
21 | clocks = <&i2c0_clk>, <&system_clk>; | ||
22 | clock-names = "scb", "sys"; | ||
23 | clock-frequency = <400000>; | ||
24 | #address-cells = <1>; | ||
25 | #size-cells = <0>; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt index 4a8513e44740..52d37fd8d3e5 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-imx.txt | |||
@@ -11,6 +11,8 @@ Required properties: | |||
11 | Optional properties: | 11 | Optional properties: |
12 | - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. | 12 | - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz. |
13 | The absence of the propoerty indicates the default frequency 100 kHz. | 13 | The absence of the propoerty indicates the default frequency 100 kHz. |
14 | - dmas: A list of two dma specifiers, one for each entry in dma-names. | ||
15 | - dma-names: should contain "tx" and "rx". | ||
14 | 16 | ||
15 | Examples: | 17 | Examples: |
16 | 18 | ||
@@ -26,3 +28,12 @@ i2c@70038000 { /* HS-I2C on i.MX51 */ | |||
26 | interrupts = <64>; | 28 | interrupts = <64>; |
27 | clock-frequency = <400000>; | 29 | clock-frequency = <400000>; |
28 | }; | 30 | }; |
31 | |||
32 | i2c0: i2c@40066000 { /* i2c0 on vf610 */ | ||
33 | compatible = "fsl,vf610-i2c"; | ||
34 | reg = <0x40066000 0x1000>; | ||
35 | interrupts =<0 71 0x04>; | ||
36 | dmas = <&edma0 0 50>, | ||
37 | <&edma0 0 51>; | ||
38 | dma-names = "rx","tx"; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-meson.txt b/Documentation/devicetree/bindings/i2c/i2c-meson.txt new file mode 100644 index 000000000000..682f9a6f766e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-meson.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | Amlogic Meson I2C controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "amlogic,meson6-i2c" | ||
5 | - reg: physical address and length of the device registers | ||
6 | - interrupts: a single interrupt specifier | ||
7 | - clocks: clock for the device | ||
8 | - #address-cells: should be <1> | ||
9 | - #size-cells: should be <0> | ||
10 | |||
11 | Optional properties: | ||
12 | - clock-frequency: the desired I2C bus clock frequency in Hz; in | ||
13 | absence of this property the default value is used (100 kHz). | ||
14 | |||
15 | Examples: | ||
16 | |||
17 | i2c@c8100500 { | ||
18 | compatible = "amlogic,meson6-i2c"; | ||
19 | reg = <0xc8100500 0x20>; | ||
20 | interrupts = <0 92 1>; | ||
21 | clocks = <&clk81>; | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <0>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-opal.txt b/Documentation/devicetree/bindings/i2c/i2c-opal.txt new file mode 100644 index 000000000000..12bc61465ee5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-opal.txt | |||
@@ -0,0 +1,37 @@ | |||
1 | Device-tree bindings for I2C OPAL driver | ||
2 | ---------------------------------------- | ||
3 | |||
4 | Most of the device node and properties layout is specific to the firmware and | ||
5 | used by the firmware itself for configuring the port. From the linux | ||
6 | perspective, the properties of use are "ibm,port-name" and "ibm,opal-id". | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - reg: Port-id within a given master | ||
11 | - compatible: must be "ibm,opal-i2c" | ||
12 | - ibm,opal-id: Refers to a specific bus and used to identify it when calling | ||
13 | the relevant OPAL functions. | ||
14 | - bus-frequency: Operating frequency of the i2c bus (in HZ). Informational for | ||
15 | linux, used by the FW though. | ||
16 | |||
17 | Optional properties: | ||
18 | - ibm,port-name: Firmware provides this name that uniquely identifies the i2c | ||
19 | port. | ||
20 | |||
21 | The node contains a number of other properties that are used by the FW itself | ||
22 | and depend on the specific hardware implementation. The example below depicts | ||
23 | a P8 on-chip bus. | ||
24 | |||
25 | Example: | ||
26 | |||
27 | i2c-bus@0 { | ||
28 | reg = <0x0>; | ||
29 | bus-frequency = <0x61a80>; | ||
30 | compatible = "ibm,power8-i2c-port", "ibm,opal-i2c"; | ||
31 | ibm,opal-id = <0x1>; | ||
32 | ibm,port-name = "p8_00000000_e1p0"; | ||
33 | #address-cells = <0x1>; | ||
34 | phandle = <0x10000006>; | ||
35 | #size-cells = <0x0>; | ||
36 | linux,phandle = <0x10000006>; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt index 278de8e64bbf..89b3250f049b 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt | |||
@@ -32,6 +32,7 @@ Optional properties: | |||
32 | specified, default value is 0. | 32 | specified, default value is 0. |
33 | - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not | 33 | - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not |
34 | specified, the default value in Hz is 100000. | 34 | specified, the default value in Hz is 100000. |
35 | - samsung,sysreg-phandle - handle to syscon used to control the system registers | ||
35 | 36 | ||
36 | Example: | 37 | Example: |
37 | 38 | ||
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt index d2153ce36fa8..2bfc6e7ed094 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt | |||
@@ -2,6 +2,15 @@ Device tree configuration for Renesas IIC (sh_mobile) driver | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "renesas,iic-<soctype>". "renesas,rmobile-iic" as fallback | 4 | - compatible : "renesas,iic-<soctype>". "renesas,rmobile-iic" as fallback |
5 | Examples with soctypes are: | ||
6 | - "renesas,iic-r8a73a4" (R-Mobile APE6) | ||
7 | - "renesas,iic-r8a7740" (R-Mobile A1) | ||
8 | - "renesas,iic-r8a7790" (R-Car H2) | ||
9 | - "renesas,iic-r8a7791" (R-Car M2-W) | ||
10 | - "renesas,iic-r8a7792" (R-Car V2H) | ||
11 | - "renesas,iic-r8a7793" (R-Car M2-N) | ||
12 | - "renesas,iic-r8a7794" (R-Car E2) | ||
13 | - "renesas,iic-sh73a0" (SH-Mobile AG5) | ||
5 | - reg : address start and address range size of device | 14 | - reg : address start and address range size of device |
6 | - interrupts : interrupt of device | 15 | - interrupts : interrupt of device |
7 | - clocks : clock for device | 16 | - clocks : clock for device |
@@ -10,6 +19,11 @@ Required properties: | |||
10 | 19 | ||
11 | Optional properties: | 20 | Optional properties: |
12 | - clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset. | 21 | - clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset. |
22 | - dmas : Must contain a list of two references to DMA | ||
23 | specifiers, one for transmission, and one for | ||
24 | reception. | ||
25 | - dma-names : Must contain a list of two DMA names, "tx" and "rx". | ||
26 | |||
13 | 27 | ||
14 | Pinctrl properties might be needed, too. See there. | 28 | Pinctrl properties might be needed, too. See there. |
15 | 29 | ||
diff --git a/Documentation/devicetree/bindings/i2c/ti,bq32k.txt b/Documentation/devicetree/bindings/i2c/ti,bq32k.txt new file mode 100644 index 000000000000..e204906b9ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ti,bq32k.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | * TI BQ32000 I2C Serial Real-Time Clock | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should contain "ti,bq32000". | ||
5 | - reg: I2C address for chip | ||
6 | |||
7 | Optional properties: | ||
8 | - trickle-resistor-ohms : Selected resistor for trickle charger | ||
9 | Values usable are 1120 and 20180 | ||
10 | Should be given if trickle charger should be enabled | ||
11 | - trickle-diode-disable : Do not use internal trickle charger diode | ||
12 | Should be given if internal trickle charger diode should be disabled | ||
13 | Example: | ||
14 | bq32000: rtc@68 { | ||
15 | compatible = "ti,bq32000"; | ||
16 | trickle-resistor-ohms = <1120>; | ||
17 | reg = <0x68>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt index 6af570ec53b4..9f4e3824e71e 100644 --- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt +++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt | |||
@@ -17,6 +17,9 @@ adi,adt7473 +/-1C TDM Extended Temp Range I.C | |||
17 | adi,adt7475 +/-1C TDM Extended Temp Range I.C | 17 | adi,adt7475 +/-1C TDM Extended Temp Range I.C |
18 | adi,adt7476 +/-1C TDM Extended Temp Range I.C | 18 | adi,adt7476 +/-1C TDM Extended Temp Range I.C |
19 | adi,adt7490 +/-1C TDM Extended Temp Range I.C | 19 | adi,adt7490 +/-1C TDM Extended Temp Range I.C |
20 | adi,adxl345 Three-Axis Digital Accelerometer | ||
21 | adi,adxl346 Three-Axis Digital Accelerometer | ||
22 | adi,adxl34x Three-Axis Digital Accelerometer | ||
20 | at,24c08 i2c serial eeprom (24cxx) | 23 | at,24c08 i2c serial eeprom (24cxx) |
21 | atmel,24c00 i2c serial eeprom (24cxx) | 24 | atmel,24c00 i2c serial eeprom (24cxx) |
22 | atmel,24c01 i2c serial eeprom (24cxx) | 25 | atmel,24c01 i2c serial eeprom (24cxx) |
@@ -35,7 +38,6 @@ catalyst,24c32 i2c serial eeprom | |||
35 | cirrus,cs42l51 Cirrus Logic CS42L51 audio codec | 38 | cirrus,cs42l51 Cirrus Logic CS42L51 audio codec |
36 | dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock | 39 | dallas,ds1307 64 x 8, Serial, I2C Real-Time Clock |
37 | dallas,ds1338 I2C RTC with 56-Byte NV RAM | 40 | dallas,ds1338 I2C RTC with 56-Byte NV RAM |
38 | dallas,ds1339 I2C Serial Real-Time Clock | ||
39 | dallas,ds1340 I2C RTC with Trickle Charger | 41 | dallas,ds1340 I2C RTC with Trickle Charger |
40 | dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output | 42 | dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output |
41 | dallas,ds1631 High-Precision Digital Thermometer | 43 | dallas,ds1631 High-Precision Digital Thermometer |
@@ -44,7 +46,7 @@ dallas,ds1775 Tiny Digital Thermometer and Thermostat | |||
44 | dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM | 46 | dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM |
45 | dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O | 47 | dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O |
46 | dallas,ds75 Digital Thermometer and Thermostat | 48 | dallas,ds75 Digital Thermometer and Thermostat |
47 | dialog,da9053 DA9053: flexible system level PMIC with multicore support | 49 | dlg,da9053 DA9053: flexible system level PMIC with multicore support |
48 | epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE | 50 | epson,rx8025 High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE |
49 | epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE | 51 | epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE |
50 | fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer | 52 | fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer |
@@ -57,6 +59,8 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In | |||
57 | infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) | 59 | infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) |
58 | infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) | 60 | infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) |
59 | isl,isl12057 Intersil ISL12057 I2C RTC Chip | 61 | isl,isl12057 Intersil ISL12057 I2C RTC Chip |
62 | isil,isl29028 (deprecated, use isl) | ||
63 | isl,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor | ||
60 | maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator | 64 | maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator |
61 | maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs | 65 | maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs |
62 | maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface | 66 | maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface |
@@ -75,7 +79,12 @@ ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI an | |||
75 | pericom,pt7c4338 Real-time Clock Module | 79 | pericom,pt7c4338 Real-time Clock Module |
76 | plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch | 80 | plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch |
77 | ramtron,24c64 i2c serial eeprom (24cxx) | 81 | ramtron,24c64 i2c serial eeprom (24cxx) |
82 | ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | ||
83 | ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | ||
78 | ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | 84 | ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC |
85 | ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | ||
86 | ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | ||
87 | ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC | ||
79 | samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) | 88 | samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power) |
80 | sii,s35390a 2-wire CMOS real-time clock | 89 | sii,s35390a 2-wire CMOS real-time clock |
81 | st-micro,24c256 i2c serial eeprom (24cxx) | 90 | st-micro,24c256 i2c serial eeprom (24cxx) |
diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt new file mode 100644 index 000000000000..4e36d6e2f7b6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-iadc.txt | |||
@@ -0,0 +1,46 @@ | |||
1 | Qualcomm's SPMI PMIC current ADC | ||
2 | |||
3 | QPNP PMIC current ADC (IADC) provides interface to clients to read current. | ||
4 | A 16 bit ADC is used for current measurements. IADC can measure the current | ||
5 | through an external resistor (channel 1) or internal (built-in) resistor | ||
6 | (channel 0). When using an external resistor it is to be described by | ||
7 | qcom,external-resistor-micro-ohms property. | ||
8 | |||
9 | IADC node: | ||
10 | |||
11 | - compatible: | ||
12 | Usage: required | ||
13 | Value type: <string> | ||
14 | Definition: Should contain "qcom,spmi-iadc". | ||
15 | |||
16 | - reg: | ||
17 | Usage: required | ||
18 | Value type: <prop-encoded-array> | ||
19 | Definition: IADC base address and length in the SPMI PMIC register map | ||
20 | |||
21 | - interrupts: | ||
22 | Usage: optional | ||
23 | Value type: <prop-encoded-array> | ||
24 | Definition: End of ADC conversion. | ||
25 | |||
26 | - qcom,external-resistor-micro-ohms: | ||
27 | Usage: optional | ||
28 | Value type: <u32> | ||
29 | Definition: Sense resister value in micro Ohm. | ||
30 | If not defined value of 10000 micro Ohms will be used. | ||
31 | |||
32 | Example: | ||
33 | /* IADC node */ | ||
34 | pmic_iadc: iadc@3600 { | ||
35 | compatible = "qcom,spmi-iadc"; | ||
36 | reg = <0x3600 0x100>; | ||
37 | interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; | ||
38 | qcom,external-resistor-micro-ohms = <10000>; | ||
39 | #io-channel-cells = <1>; | ||
40 | }; | ||
41 | |||
42 | /* IIO client node */ | ||
43 | bat { | ||
44 | io-channels = <&pmic_iadc 0>; | ||
45 | io-channel-names = "iadc"; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt new file mode 100644 index 000000000000..a9a5fe19ff2a --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | Rockchip Successive Approximation Register (SAR) A/D Converter bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "rockchip,saradc" or "rockchip,rk3066-tsadc" | ||
5 | - reg: physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts: The interrupt number to the cpu. The interrupt specifier format | ||
8 | depends on the interrupt controller. | ||
9 | - clocks: Must contain an entry for each entry in clock-names. | ||
10 | - clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for | ||
11 | the peripheral clock. | ||
12 | - vref-supply: The regulator supply ADC reference voltage. | ||
13 | - #io-channel-cells: Should be 1, see ../iio-bindings.txt | ||
14 | |||
15 | Example: | ||
16 | saradc: saradc@2006c000 { | ||
17 | compatible = "rockchip,saradc"; | ||
18 | reg = <0x2006c000 0x100>; | ||
19 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | ||
20 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | ||
21 | clock-names = "saradc", "apb_pclk"; | ||
22 | #io-channel-cells = <1>; | ||
23 | vref-supply = <&vcc18>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt index dcebff1928e1..1a4a43d5c9ea 100644 --- a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt | |||
@@ -9,7 +9,7 @@ Required properties: | |||
9 | - interrupts: Should contain the interrupt for the device | 9 | - interrupts: Should contain the interrupt for the device |
10 | - clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock. | 10 | - clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock. |
11 | - clock-names: Must contain "adc", matching entry in the clocks property. | 11 | - clock-names: Must contain "adc", matching entry in the clocks property. |
12 | - vref-supply: The regulator supply ADC refrence voltage. | 12 | - vref-supply: The regulator supply ADC reference voltage. |
13 | 13 | ||
14 | Example: | 14 | Example: |
15 | adc0: adc@4003b000 { | 15 | adc0: adc@4003b000 { |
diff --git a/Documentation/devicetree/bindings/iio/dac/max5821.txt b/Documentation/devicetree/bindings/iio/dac/max5821.txt new file mode 100644 index 000000000000..54276ce8c971 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/max5821.txt | |||
@@ -0,0 +1,14 @@ | |||
1 | Maxim max5821 DAC device driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "maxim,max5821" | ||
5 | - reg: Should contain the DAC I2C address | ||
6 | - vref-supply: Phandle to the vref power supply | ||
7 | |||
8 | Example: | ||
9 | |||
10 | max5821@38 { | ||
11 | compatible = "maxim,max5821"; | ||
12 | reg = <0x38>; | ||
13 | vref-supply = <®_max5821>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt index 2742e9cfd6b1..f292917fa00d 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt | |||
@@ -2,7 +2,7 @@ | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: Should be "atmel,<chip>-aic" | 4 | - compatible: Should be "atmel,<chip>-aic" |
5 | <chip> can be "at91rm9200" or "sama5d3" | 5 | <chip> can be "at91rm9200", "sama5d3" or "sama5d4" |
6 | - interrupt-controller: Identifies the node as an interrupt controller. | 6 | - interrupt-controller: Identifies the node as an interrupt controller. |
7 | - interrupt-parent: For single AIC system, it is an empty property. | 7 | - interrupt-parent: For single AIC system, it is an empty property. |
8 | - #interrupt-cells: The number of cells to define the interrupts. It should be 3. | 8 | - #interrupt-cells: The number of cells to define the interrupts. It should be 3. |
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt new file mode 100644 index 000000000000..bae1f2187226 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt | |||
@@ -0,0 +1,96 @@ | |||
1 | Broadcom BCM7120-style Level 2 interrupt controller | ||
2 | |||
3 | This interrupt controller hardware is a second level interrupt controller that | ||
4 | is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based | ||
5 | platforms. It can be found on BCM7xxx products starting with BCM7120. | ||
6 | |||
7 | Such an interrupt controller has the following hardware design: | ||
8 | |||
9 | - outputs multiple interrupts signals towards its interrupt controller parent | ||
10 | |||
11 | - controls how some of the interrupts will be flowing, whether they will | ||
12 | directly output an interrupt signal towards the interrupt controller parent, | ||
13 | or if they will output an interrupt signal at this 2nd level interrupt | ||
14 | controller, in particular for UARTs | ||
15 | |||
16 | - typically has one 32-bit enable word and one 32-bit status word, but on | ||
17 | some hardware may have more than one enable/status pair | ||
18 | |||
19 | - no atomic set/clear operations | ||
20 | |||
21 | - not all bits within the interrupt controller actually map to an interrupt | ||
22 | |||
23 | The typical hardware layout for this controller is represented below: | ||
24 | |||
25 | 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) | ||
26 | |||
27 | 0 -----[ MUX ] ------------|==========> GIC interrupt 75 | ||
28 | \-----------\ | ||
29 | | | ||
30 | 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 | ||
31 | \------------| | ||
32 | | | ||
33 | 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 | ||
34 | \------------| | ||
35 | | | ||
36 | 3 ---------------------| | ||
37 | 4 ---------------------| | ||
38 | 5 ---------------------| | ||
39 | 7 ---------------------|---|===========> GIC interrupt 66 | ||
40 | 9 ---------------------| | ||
41 | 10 --------------------| | ||
42 | 11 --------------------/ | ||
43 | |||
44 | 6 ------------------------\ | ||
45 | |===========> GIC interrupt 64 | ||
46 | 8 ------------------------/ | ||
47 | |||
48 | 12 ........................ X | ||
49 | 13 ........................ X (not connected) | ||
50 | .. | ||
51 | 31 ........................ X | ||
52 | |||
53 | Required properties: | ||
54 | |||
55 | - compatible: should be "brcm,bcm7120-l2-intc" | ||
56 | - reg: specifies the base physical address and size of the registers; | ||
57 | multiple pairs may be specified, with the first pair handling IRQ offsets | ||
58 | 0..31 and the second pair handling 32..63 | ||
59 | - interrupt-controller: identifies the node as an interrupt controller | ||
60 | - #interrupt-cells: specifies the number of cells needed to encode an interrupt | ||
61 | source, should be 1. | ||
62 | - interrupt-parent: specifies the phandle to the parent interrupt controller | ||
63 | this one is cascaded from | ||
64 | - interrupts: specifies the interrupt line(s) in the interrupt-parent controller | ||
65 | node, valid values depend on the type of parent interrupt controller | ||
66 | - brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts | ||
67 | are wired to this 2nd level interrupt controller, and how they match their | ||
68 | respective interrupt parents. Should match exactly the number of interrupts | ||
69 | specified in the 'interrupts' property, multiplied by the number of | ||
70 | enable/status register pairs implemented by this controller. For | ||
71 | multiple parent IRQs with multiple enable/status words, this looks like: | ||
72 | <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...> | ||
73 | |||
74 | Optional properties: | ||
75 | |||
76 | - brcm,irq-can-wake: if present, this means the L2 controller can be used as a | ||
77 | wakeup source for system suspend/resume. | ||
78 | |||
79 | - brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which | ||
80 | have a mux gate, typically UARTs. Setting these bits will make their | ||
81 | respective interrupt outputs bypass this 2nd level interrupt controller | ||
82 | completely; it is completely transparent for the interrupt controller | ||
83 | parent. This should have one 32-bit word per enable/status pair. | ||
84 | |||
85 | Example: | ||
86 | |||
87 | irq0_intc: interrupt-controller@f0406800 { | ||
88 | compatible = "brcm,bcm7120-l2-intc"; | ||
89 | interrupt-parent = <&intc>; | ||
90 | #interrupt-cells = <1>; | ||
91 | reg = <0xf0406800 0x8>; | ||
92 | interrupt-controller; | ||
93 | interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; | ||
94 | brcm,int-map-mask = <0xeb8>, <0x140>; | ||
95 | brcm,int-fwd-mask = <0x7>; | ||
96 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt index ce6a1a072028..8a3c40829899 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt | |||
@@ -30,10 +30,6 @@ should only be used when a device has multiple interrupt parents. | |||
30 | Example: | 30 | Example: |
31 | interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; | 31 | interrupts-extended = <&intc1 5 1>, <&intc2 1 0>; |
32 | 32 | ||
33 | A device node may contain either "interrupts" or "interrupts-extended", but not | ||
34 | both. If both properties are present, then the operating system should log an | ||
35 | error and use only the data in "interrupts". | ||
36 | |||
37 | 2) Interrupt controller nodes | 33 | 2) Interrupt controller nodes |
38 | ----------------------------- | 34 | ----------------------------- |
39 | 35 | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt new file mode 100644 index 000000000000..5a65478e5d40 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt | |||
@@ -0,0 +1,55 @@ | |||
1 | MIPS Global Interrupt Controller (GIC) | ||
2 | |||
3 | The MIPS GIC routes external interrupts to individual VPEs and IRQ pins. | ||
4 | It also supports local (per-processor) interrupts and software-generated | ||
5 | interrupts which can be used as IPIs. The GIC also includes a free-running | ||
6 | global timer, per-CPU count/compare timers, and a watchdog. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible : Should be "mti,gic". | ||
10 | - interrupt-controller : Identifies the node as an interrupt controller | ||
11 | - #interrupt-cells : Specifies the number of cells needed to encode an | ||
12 | interrupt specifier. Should be 3. | ||
13 | - The first cell is the type of interrupt, local or shared. | ||
14 | See <include/dt-bindings/interrupt-controller/mips-gic.h>. | ||
15 | - The second cell is the GIC interrupt number. | ||
16 | - The third cell encodes the interrupt flags. | ||
17 | See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid | ||
18 | flags. | ||
19 | |||
20 | Optional properties: | ||
21 | - reg : Base address and length of the GIC registers. If not present, | ||
22 | the base address reported by the hardware GCR_GIC_BASE will be used. | ||
23 | - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors | ||
24 | to which the GIC may not route interrupts. Valid values are 2 - 7. | ||
25 | This property is ignored if the CPU is started in EIC mode. | ||
26 | |||
27 | Required properties for timer sub-node: | ||
28 | - compatible : Should be "mti,gic-timer". | ||
29 | - interrupts : Interrupt for the GIC local timer. | ||
30 | - clock-frequency : Clock frequency at which the GIC timers operate. | ||
31 | |||
32 | Example: | ||
33 | |||
34 | gic: interrupt-controller@1bdc0000 { | ||
35 | compatible = "mti,gic"; | ||
36 | reg = <0x1bdc0000 0x20000>; | ||
37 | |||
38 | interrupt-controller; | ||
39 | #interrupt-cells = <3>; | ||
40 | |||
41 | mti,reserved-cpu-vectors = <7>; | ||
42 | |||
43 | timer { | ||
44 | compatible = "mti,gic-timer"; | ||
45 | interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; | ||
46 | clock-frequency = <50000000>; | ||
47 | }; | ||
48 | }; | ||
49 | |||
50 | uart@18101400 { | ||
51 | ... | ||
52 | interrupt-parent = <&gic>; | ||
53 | interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; | ||
54 | ... | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt index 1f8b0c507c26..c73acd060093 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt | |||
@@ -2,7 +2,13 @@ DT bindings for the R-/SH-Mobile irqpin controller | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible: has to be "renesas,intc-irqpin" | 5 | - compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin" |
6 | as fallback. | ||
7 | Examples with soctypes are: | ||
8 | - "renesas,intc-irqpin-r8a7740" (R-Mobile A1) | ||
9 | - "renesas,intc-irqpin-r8a7778" (R-Car M1A) | ||
10 | - "renesas,intc-irqpin-r8a7779" (R-Car H1) | ||
11 | - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5) | ||
6 | - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in | 12 | - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in |
7 | interrupts.txt in this directory | 13 | interrupts.txt in this directory |
8 | 14 | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt new file mode 100644 index 000000000000..1a88e62228e5 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt | |||
@@ -0,0 +1,32 @@ | |||
1 | DT bindings for the R-Mobile/R-Car interrupt controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback. | ||
6 | Examples with soctypes are: | ||
7 | - "renesas,irqc-r8a73a4" (R-Mobile AP6) | ||
8 | - "renesas,irqc-r8a7790" (R-Car H2) | ||
9 | - "renesas,irqc-r8a7791" (R-Car M2-W) | ||
10 | - "renesas,irqc-r8a7792" (R-Car V2H) | ||
11 | - "renesas,irqc-r8a7793" (R-Car M2-N) | ||
12 | - "renesas,irqc-r8a7794" (R-Car E2) | ||
13 | - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in | ||
14 | interrupts.txt in this directory | ||
15 | |||
16 | Optional properties: | ||
17 | |||
18 | - any properties, listed in interrupts.txt, and any standard resource allocation | ||
19 | properties | ||
20 | |||
21 | Example: | ||
22 | |||
23 | irqc0: interrupt-controller@e61c0000 { | ||
24 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; | ||
25 | #interrupt-cells = <2>; | ||
26 | interrupt-controller; | ||
27 | reg = <0 0xe61c0000 0 0x200>; | ||
28 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, | ||
29 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | ||
30 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | ||
31 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | ||
32 | }; | ||
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt new file mode 100644 index 000000000000..d9bb106bdd16 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | Keystone 2 IRQ controller IP | ||
2 | |||
3 | On Keystone SOCs, DSP cores can send interrupts to ARM | ||
4 | host using the IRQ controller IP. It provides 28 IRQ signals to ARM. | ||
5 | The IRQ handler running on HOST OS can identify DSP signal source by | ||
6 | analyzing SRCCx bits in IPCARx registers. This is one of the component | ||
7 | used by the IPC mechanism used on Keystone SOCs. | ||
8 | |||
9 | Required Properties: | ||
10 | - compatible: should be "ti,keystone-irq" | ||
11 | - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to | ||
12 | access device control registers and the offset inside | ||
13 | device control registers range. | ||
14 | - interrupt-controller : Identifies the node as an interrupt controller | ||
15 | - #interrupt-cells : Specifies the number of cells needed to encode interrupt | ||
16 | source should be 1. | ||
17 | - interrupts: interrupt reference to primary interrupt controller | ||
18 | |||
19 | Please refer to interrupts.txt in this directory for details of the common | ||
20 | Interrupt Controllers bindings used by client devices. | ||
21 | |||
22 | Example: | ||
23 | kirq0: keystone_irq0@026202a0 { | ||
24 | compatible = "ti,keystone-irq"; | ||
25 | ti,syscon-dev = <&devctrl 0x2a0>; | ||
26 | interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; | ||
27 | interrupt-controller; | ||
28 | #interrupt-cells = <1>; | ||
29 | }; | ||
30 | |||
31 | dsp0: dsp0 { | ||
32 | compatible = "linux,rproc-user"; | ||
33 | ... | ||
34 | interrupt-parent = <&kirq0>; | ||
35 | interrupts = <10 2>; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 2d0f7cd867ea..06760503a819 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt | |||
@@ -14,6 +14,7 @@ conditions. | |||
14 | "arm,smmu-v1" | 14 | "arm,smmu-v1" |
15 | "arm,smmu-v2" | 15 | "arm,smmu-v2" |
16 | "arm,mmu-400" | 16 | "arm,mmu-400" |
17 | "arm,mmu-401" | ||
17 | "arm,mmu-500" | 18 | "arm,mmu-500" |
18 | 19 | ||
19 | depending on the particular implementation and/or the | 20 | depending on the particular implementation and/or the |
diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt new file mode 100644 index 000000000000..9a55ac3735e5 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt | |||
@@ -0,0 +1,26 @@ | |||
1 | Rockchip IOMMU | ||
2 | ============== | ||
3 | |||
4 | A Rockchip DRM iommu translates io virtual addresses to physical addresses for | ||
5 | its master device. Each slave device is bound to a single master device, and | ||
6 | shares its clocks, power domain and irq. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible : Should be "rockchip,iommu" | ||
10 | - reg : Address space for the configuration registers | ||
11 | - interrupts : Interrupt specifier for the IOMMU instance | ||
12 | - interrupt-names : Interrupt name for the IOMMU instance | ||
13 | - #iommu-cells : Should be <0>. This indicates the iommu is a | ||
14 | "single-master" device, and needs no additional information | ||
15 | to associate with its master device. See: | ||
16 | Documentation/devicetree/bindings/iommu/iommu.txt | ||
17 | |||
18 | Example: | ||
19 | |||
20 | vopl_mmu: iommu@ff940300 { | ||
21 | compatible = "rockchip,iommu"; | ||
22 | reg = <0xff940300 0x100>; | ||
23 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | ||
24 | interrupt-names = "vopl_mmu"; | ||
25 | #iommu-cells = <0>; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/leds/leds-lp8860.txt b/Documentation/devicetree/bindings/leds/leds-lp8860.txt new file mode 100644 index 000000000000..aad38dd94d4b --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-lp8860.txt | |||
@@ -0,0 +1,29 @@ | |||
1 | * Texas Instruments - lp8860 4-Channel LED Driver | ||
2 | |||
3 | The LP8860-Q1 is an high-efficiency LED | ||
4 | driver with boost controller. It has 4 high-precision | ||
5 | current sinks that can be controlled by a PWM input | ||
6 | signal, a SPI/I2C master, or both. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: | ||
10 | "ti,lp8860" | ||
11 | - reg - I2C slave address | ||
12 | - label - Used for naming LEDs | ||
13 | |||
14 | Optional properties: | ||
15 | - enable-gpio - gpio pin to enable/disable the device. | ||
16 | - supply - "vled" - LED supply | ||
17 | |||
18 | Example: | ||
19 | |||
20 | leds: leds@6 { | ||
21 | compatible = "ti,lp8860"; | ||
22 | reg = <0x2d>; | ||
23 | label = "display_cluster"; | ||
24 | enable-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; | ||
25 | vled-supply = <&vbatt>; | ||
26 | } | ||
27 | |||
28 | For more product information please see the link below: | ||
29 | http://www.ti.com/product/lp8860-q1 | ||
diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.txt b/Documentation/devicetree/bindings/leds/register-bit-led.txt new file mode 100644 index 000000000000..379cefdc0bda --- /dev/null +++ b/Documentation/devicetree/bindings/leds/register-bit-led.txt | |||
@@ -0,0 +1,99 @@ | |||
1 | Device Tree Bindings for Register Bit LEDs | ||
2 | |||
3 | Register bit leds are used with syscon multifunctional devices | ||
4 | where single bits in a certain register can turn on/off a | ||
5 | single LED. The register bit LEDs appear as children to the | ||
6 | syscon device, with the proper compatible string. For the | ||
7 | syscon bindings see: | ||
8 | Documentation/devicetree/bindings/mfd/syscon.txt | ||
9 | |||
10 | Each LED is represented as a sub-node of the syscon device. Each | ||
11 | node's name represents the name of the corresponding LED. | ||
12 | |||
13 | LED sub-node properties: | ||
14 | |||
15 | Required properties: | ||
16 | - compatible : must be "register-bit-led" | ||
17 | - offset : register offset to the register controlling this LED | ||
18 | - mask : bit mask for the bit controlling this LED in the register | ||
19 | typically 0x01, 0x02, 0x04 ... | ||
20 | |||
21 | Optional properties: | ||
22 | - label : (optional) | ||
23 | see Documentation/devicetree/bindings/leds/common.txt | ||
24 | - linux,default-trigger : (optional) | ||
25 | see Documentation/devicetree/bindings/leds/common.txt | ||
26 | - default-state: (optional) The initial state of the LED. Valid | ||
27 | values are "on", "off", and "keep". If the LED is already on or off | ||
28 | and the default-state property is set the to same value, then no | ||
29 | glitch should be produced where the LED momentarily turns off (or | ||
30 | on). The "keep" setting will keep the LED at whatever its current | ||
31 | state is, without producing a glitch. The default is off if this | ||
32 | property is not present. | ||
33 | |||
34 | Example: | ||
35 | |||
36 | syscon: syscon@10000000 { | ||
37 | compatible = "arm,realview-pb1176-syscon", "syscon"; | ||
38 | reg = <0x10000000 0x1000>; | ||
39 | |||
40 | led@08.0 { | ||
41 | compatible = "register-bit-led"; | ||
42 | offset = <0x08>; | ||
43 | mask = <0x01>; | ||
44 | label = "versatile:0"; | ||
45 | linux,default-trigger = "heartbeat"; | ||
46 | default-state = "on"; | ||
47 | }; | ||
48 | led@08.1 { | ||
49 | compatible = "register-bit-led"; | ||
50 | offset = <0x08>; | ||
51 | mask = <0x02>; | ||
52 | label = "versatile:1"; | ||
53 | linux,default-trigger = "mmc0"; | ||
54 | default-state = "off"; | ||
55 | }; | ||
56 | led@08.2 { | ||
57 | compatible = "register-bit-led"; | ||
58 | offset = <0x08>; | ||
59 | mask = <0x04>; | ||
60 | label = "versatile:2"; | ||
61 | linux,default-trigger = "cpu0"; | ||
62 | default-state = "off"; | ||
63 | }; | ||
64 | led@08.3 { | ||
65 | compatible = "register-bit-led"; | ||
66 | offset = <0x08>; | ||
67 | mask = <0x08>; | ||
68 | label = "versatile:3"; | ||
69 | default-state = "off"; | ||
70 | }; | ||
71 | led@08.4 { | ||
72 | compatible = "register-bit-led"; | ||
73 | offset = <0x08>; | ||
74 | mask = <0x10>; | ||
75 | label = "versatile:4"; | ||
76 | default-state = "off"; | ||
77 | }; | ||
78 | led@08.5 { | ||
79 | compatible = "register-bit-led"; | ||
80 | offset = <0x08>; | ||
81 | mask = <0x20>; | ||
82 | label = "versatile:5"; | ||
83 | default-state = "off"; | ||
84 | }; | ||
85 | led@08.6 { | ||
86 | compatible = "register-bit-led"; | ||
87 | offset = <0x08>; | ||
88 | mask = <0x40>; | ||
89 | label = "versatile:6"; | ||
90 | default-state = "off"; | ||
91 | }; | ||
92 | led@08.7 { | ||
93 | compatible = "register-bit-led"; | ||
94 | offset = <0x08>; | ||
95 | mask = <0x80>; | ||
96 | label = "versatile:7"; | ||
97 | default-state = "off"; | ||
98 | }; | ||
99 | }; | ||
diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Documentation/devicetree/bindings/mailbox/mailbox.txt new file mode 100644 index 000000000000..1a2cd3d266db --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mailbox.txt | |||
@@ -0,0 +1,38 @@ | |||
1 | * Generic Mailbox Controller and client driver bindings | ||
2 | |||
3 | Generic binding to provide a way for Mailbox controller drivers to | ||
4 | assign appropriate mailbox channel to client drivers. | ||
5 | |||
6 | * Mailbox Controller | ||
7 | |||
8 | Required property: | ||
9 | - #mbox-cells: Must be at least 1. Number of cells in a mailbox | ||
10 | specifier. | ||
11 | |||
12 | Example: | ||
13 | mailbox: mailbox { | ||
14 | ... | ||
15 | #mbox-cells = <1>; | ||
16 | }; | ||
17 | |||
18 | |||
19 | * Mailbox Client | ||
20 | |||
21 | Required property: | ||
22 | - mboxes: List of phandle and mailbox channel specifiers. | ||
23 | |||
24 | Optional property: | ||
25 | - mbox-names: List of identifier strings for each mailbox channel | ||
26 | required by the client. The use of this property | ||
27 | is discouraged in favor of using index in list of | ||
28 | 'mboxes' while requesting a mailbox. Instead the | ||
29 | platforms may define channel indices, in DT headers, | ||
30 | to something legible. | ||
31 | |||
32 | Example: | ||
33 | pwr_cntrl: power { | ||
34 | ... | ||
35 | mbox-names = "pwr-ctrl", "rpc"; | ||
36 | mboxes = <&mailbox 0 | ||
37 | &mailbox 1>; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt new file mode 100644 index 000000000000..d1a043339c11 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt | |||
@@ -0,0 +1,131 @@ | |||
1 | OMAP2+ Mailbox Driver | ||
2 | ===================== | ||
3 | |||
4 | The OMAP mailbox hardware facilitates communication between different processors | ||
5 | using a queued mailbox interrupt mechanism. The IP block is external to the | ||
6 | various processor subsystems and is connected on an interconnect bus. The | ||
7 | communication is achieved through a set of registers for message storage and | ||
8 | interrupt configuration registers. | ||
9 | |||
10 | Each mailbox IP block has a certain number of h/w fifo queues and output | ||
11 | interrupt lines. An output interrupt line is routed to an interrupt controller | ||
12 | within a processor subsystem, and there can be more than one line going to a | ||
13 | specific processor's interrupt controller. The interrupt line connections are | ||
14 | fixed for an instance and are dictated by the IP integration into the SoC | ||
15 | (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is | ||
16 | programmable through a set of interrupt configuration registers, and have a rx | ||
17 | and tx interrupt source per h/w fifo. Communication between different processors | ||
18 | is achieved through the appropriate programming of the rx and tx interrupt | ||
19 | sources on the appropriate interrupt lines. | ||
20 | |||
21 | The number of h/w fifo queues and interrupt lines dictate the usable registers. | ||
22 | All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP | ||
23 | instance. DRA7xx has multiple instances with different number of h/w fifo queues | ||
24 | and interrupt lines between different instances. The interrupt lines can also be | ||
25 | routed to different processor sub-systems on DRA7xx as they are routed through | ||
26 | the Crossbar, a kind of interrupt router/multiplexer. | ||
27 | |||
28 | Mailbox Device Node: | ||
29 | ==================== | ||
30 | A Mailbox device node is used to represent a Mailbox IP instance within a SoC. | ||
31 | The sub-mailboxes are represented as child nodes of this parent node. | ||
32 | |||
33 | Required properties: | ||
34 | -------------------- | ||
35 | - compatible: Should be one of the following, | ||
36 | "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs | ||
37 | "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs | ||
38 | "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, | ||
39 | AM43xx and DRA7xx SoCs | ||
40 | - reg: Contains the mailbox register address range (base | ||
41 | address and length) | ||
42 | - interrupts: Contains the interrupt information for the mailbox | ||
43 | device. The format is dependent on which interrupt | ||
44 | controller the OMAP device uses | ||
45 | - ti,hwmods: Name of the hwmod associated with the mailbox | ||
46 | - #mbox-cells: Common mailbox binding property to identify the number | ||
47 | of cells required for the mailbox specifier. Should be | ||
48 | 1 | ||
49 | - ti,mbox-num-users: Number of targets (processor devices) that the mailbox | ||
50 | device can interrupt | ||
51 | - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block | ||
52 | |||
53 | Child Nodes: | ||
54 | ============ | ||
55 | A child node is used for representing the actual sub-mailbox device that is | ||
56 | used for the communication between the host processor and a remote processor. | ||
57 | Each child node should have a unique node name across all the different | ||
58 | mailbox device nodes. | ||
59 | |||
60 | Required properties: | ||
61 | -------------------- | ||
62 | - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo | ||
63 | - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo | ||
64 | |||
65 | Sub-mailbox Descriptor Data | ||
66 | --------------------------- | ||
67 | Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of | ||
68 | data that represent the following: | ||
69 | Cell #1 (fifo_id) - mailbox fifo id used either for transmitting | ||
70 | (ti,mbox-tx) or for receiving (ti,mbox-rx) | ||
71 | Cell #2 (irq_id) - irq identifier index number to use from the parent's | ||
72 | interrupts data. Should be 0 for most of the cases, a | ||
73 | positive index value is seen only on mailboxes that have | ||
74 | multiple interrupt lines connected to the MPU processor. | ||
75 | Cell #3 (usr_id) - mailbox user id for identifying the interrupt line | ||
76 | associated with generating a tx/rx fifo interrupt. | ||
77 | |||
78 | Mailbox Users: | ||
79 | ============== | ||
80 | A device needing to communicate with a target processor device should specify | ||
81 | them using the common mailbox binding properties, "mboxes" and the optional | ||
82 | "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt | ||
83 | for details). Each value of the mboxes property should contain a phandle to the | ||
84 | mailbox controller device node and an args specifier that will be the phandle to | ||
85 | the intended sub-mailbox child node to be used for communication. The equivalent | ||
86 | "mbox-names" property value can be used to give a name to the communication channel | ||
87 | to be used by the client user. | ||
88 | |||
89 | |||
90 | Example: | ||
91 | -------- | ||
92 | |||
93 | /* OMAP4 */ | ||
94 | mailbox: mailbox@4a0f4000 { | ||
95 | compatible = "ti,omap4-mailbox"; | ||
96 | reg = <0x4a0f4000 0x200>; | ||
97 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | ||
98 | ti,hwmods = "mailbox"; | ||
99 | #mbox-cells = <1>; | ||
100 | ti,mbox-num-users = <3>; | ||
101 | ti,mbox-num-fifos = <8>; | ||
102 | mbox_ipu: mbox_ipu { | ||
103 | ti,mbox-tx = <0 0 0>; | ||
104 | ti,mbox-rx = <1 0 0>; | ||
105 | }; | ||
106 | mbox_dsp: mbox_dsp { | ||
107 | ti,mbox-tx = <3 0 0>; | ||
108 | ti,mbox-rx = <2 0 0>; | ||
109 | }; | ||
110 | }; | ||
111 | |||
112 | dsp { | ||
113 | ... | ||
114 | mboxes = <&mailbox &mbox_dsp>; | ||
115 | ... | ||
116 | }; | ||
117 | |||
118 | /* AM33xx */ | ||
119 | mailbox: mailbox@480C8000 { | ||
120 | compatible = "ti,omap4-mailbox"; | ||
121 | reg = <0x480C8000 0x200>; | ||
122 | interrupts = <77>; | ||
123 | ti,hwmods = "mailbox"; | ||
124 | #mbox-cells = <1>; | ||
125 | ti,mbox-num-users = <4>; | ||
126 | ti,mbox-num-fifos = <8>; | ||
127 | mbox_wkupm3: wkup_m3 { | ||
128 | ti,mbox-tx = <0 0 0>; | ||
129 | ti,mbox-rx = <0 0 3>; | ||
130 | }; | ||
131 | }; | ||
diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt new file mode 100644 index 000000000000..fb5e7606643a --- /dev/null +++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | Device-Tree bindings for hix5hd2 ir IP | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should contain "hisilicon,hix5hd2-ir". | ||
5 | - reg: Base physical address of the controller and length of memory | ||
6 | mapped region. | ||
7 | - interrupts: interrupt-specifier for the sole interrupt generated by | ||
8 | the device. The interrupt specifier format depends on the interrupt | ||
9 | controller parent. | ||
10 | - clocks: clock phandle and specifier pair. | ||
11 | - hisilicon,power-syscon: phandle of syscon used to control power. | ||
12 | |||
13 | Optional properties: | ||
14 | - linux,rc-map-name : Remote control map name. | ||
15 | |||
16 | Example node: | ||
17 | |||
18 | ir: ir@f8001000 { | ||
19 | compatible = "hisilicon,hix5hd2-ir"; | ||
20 | reg = <0xf8001000 0x1000>; | ||
21 | interrupts = <0 47 4>; | ||
22 | clocks = <&clock HIX5HD2_FIXED_24M>; | ||
23 | hisilicon,power-syscon = <&sysctrl>; | ||
24 | linux,rc-map-name = "rc-tivo"; | ||
25 | }; | ||
diff --git a/Documentation/devicetree/bindings/media/meson-ir.txt b/Documentation/devicetree/bindings/media/meson-ir.txt new file mode 100644 index 000000000000..407848e85f31 --- /dev/null +++ b/Documentation/devicetree/bindings/media/meson-ir.txt | |||
@@ -0,0 +1,14 @@ | |||
1 | * Amlogic Meson IR remote control receiver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "amlogic,meson6-ir" | ||
5 | - reg : physical base address and length of the device registers | ||
6 | - interrupts : a single specifier for the interrupt from the device | ||
7 | |||
8 | Example: | ||
9 | |||
10 | ir-receiver@c8100480 { | ||
11 | compatible= "amlogic,meson6-ir"; | ||
12 | reg = <0xc8100480 0x20>; | ||
13 | interrupts = <0 15 1>; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt index ba61782c2af9..9dafe6b06cd2 100644 --- a/Documentation/devicetree/bindings/media/rcar_vin.txt +++ b/Documentation/devicetree/bindings/media/rcar_vin.txt | |||
@@ -6,6 +6,8 @@ family of devices. The current blocks are always slaves and suppot one input | |||
6 | channel which can be either RGB, YUYV or BT656. | 6 | channel which can be either RGB, YUYV or BT656. |
7 | 7 | ||
8 | - compatible: Must be one of the following | 8 | - compatible: Must be one of the following |
9 | - "renesas,vin-r8a7794" for the R8A7794 device | ||
10 | - "renesas,vin-r8a7793" for the R8A7793 device | ||
9 | - "renesas,vin-r8a7791" for the R8A7791 device | 11 | - "renesas,vin-r8a7791" for the R8A7791 device |
10 | - "renesas,vin-r8a7790" for the R8A7790 device | 12 | - "renesas,vin-r8a7790" for the R8A7790 device |
11 | - "renesas,vin-r8a7779" for the R8A7779 device | 13 | - "renesas,vin-r8a7779" for the R8A7779 device |
diff --git a/Documentation/devicetree/bindings/media/si4713.txt b/Documentation/devicetree/bindings/media/si4713.txt new file mode 100644 index 000000000000..5ee5552d3465 --- /dev/null +++ b/Documentation/devicetree/bindings/media/si4713.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | * Silicon Labs FM Radio transmitter | ||
2 | |||
3 | The Silicon Labs Si4713 is an FM radio transmitter with receive power scan | ||
4 | supporting 76-108 MHz. It includes an RDS encoder and has both, a stereo-analog | ||
5 | and a digital interface, which supports I2S, left-justified and a custom | ||
6 | DSP-mode format. It is programmable through an I2C interface. | ||
7 | |||
8 | Required Properties: | ||
9 | - compatible: Should contain "silabs,si4713" | ||
10 | - reg: the I2C address of the device | ||
11 | |||
12 | Optional Properties: | ||
13 | - interrupts-extended: Interrupt specifier for the chips interrupt | ||
14 | - reset-gpios: GPIO specifier for the chips reset line | ||
15 | - vdd-supply: phandle for Vdd regulator | ||
16 | - vio-supply: phandle for Vio regulator | ||
17 | |||
18 | Example: | ||
19 | |||
20 | &i2c2 { | ||
21 | fmtx: si4713@63 { | ||
22 | compatible = "silabs,si4713"; | ||
23 | reg = <0x63>; | ||
24 | |||
25 | interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ | ||
26 | reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ | ||
27 | vio-supply = <&vio>; | ||
28 | vdd-supply = <&vaux1>; | ||
29 | }; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt new file mode 100644 index 000000000000..89657d1d4cd4 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | Device Tree bindings for MVEBU SDRAM controllers | ||
2 | |||
3 | The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller | ||
4 | differs from one SoC variant to another, but they also share a number | ||
5 | of commonalities. | ||
6 | |||
7 | For now, this Device Tree binding documentation only documents the | ||
8 | Armada XP SDRAM controller. | ||
9 | |||
10 | Required properties: | ||
11 | |||
12 | - compatible: for Armada XP, "marvell,armada-xp-sdram-controller" | ||
13 | - reg: a resource specifier for the register space, which should | ||
14 | include all SDRAM controller registers as per the datasheet. | ||
15 | |||
16 | Example: | ||
17 | |||
18 | sdramc@1400 { | ||
19 | compatible = "marvell,armada-xp-sdram-controller"; | ||
20 | reg = <0x1400 0x500>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt new file mode 100644 index 000000000000..f3db93c85eea --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | NVIDIA Tegra Memory Controller device tree bindings | ||
2 | =================================================== | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: Should be "nvidia,tegra<chip>-mc" | ||
6 | - reg: Physical base address and length of the controller's registers. | ||
7 | - clocks: Must contain an entry for each entry in clock-names. | ||
8 | See ../clocks/clock-bindings.txt for details. | ||
9 | - clock-names: Must include the following entries: | ||
10 | - mc: the module's clock input | ||
11 | - interrupts: The interrupt outputs from the controller. | ||
12 | - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines | ||
13 | the SWGROUP of the master. | ||
14 | |||
15 | This device implements an IOMMU that complies with the generic IOMMU binding. | ||
16 | See ../iommu/iommu.txt for details. | ||
17 | |||
18 | Example: | ||
19 | -------- | ||
20 | |||
21 | mc: memory-controller@0,70019000 { | ||
22 | compatible = "nvidia,tegra124-mc"; | ||
23 | reg = <0x0 0x70019000 0x0 0x1000>; | ||
24 | clocks = <&tegra_car TEGRA124_CLK_MC>; | ||
25 | clock-names = "mc"; | ||
26 | |||
27 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; | ||
28 | |||
29 | #iommu-cells = <1>; | ||
30 | }; | ||
31 | |||
32 | sdhci@0,700b0000 { | ||
33 | compatible = "nvidia,tegra124-sdhci"; | ||
34 | ... | ||
35 | iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt new file mode 100644 index 000000000000..f9c6454146b6 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt | |||
@@ -0,0 +1,11 @@ | |||
1 | Binding for Synopsys IntelliDDR Multi Protocol Memory Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be 'xlnx,zynq-ddrc-a05' | ||
5 | - reg: Base address and size of the controllers memory area | ||
6 | |||
7 | Example: | ||
8 | memory-controller@f8006000 { | ||
9 | compatible = "xlnx,zynq-ddrc-a05"; | ||
10 | reg = <0xf8006000 0x1000>; | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt index 5c7e7230984a..7bd1273f571a 100644 --- a/Documentation/devicetree/bindings/mfd/arizona.txt +++ b/Documentation/devicetree/bindings/mfd/arizona.txt | |||
@@ -42,6 +42,13 @@ Optional properties: | |||
42 | the chip default will be used. If present exactly five values must | 42 | the chip default will be used. If present exactly five values must |
43 | be specified. | 43 | be specified. |
44 | 44 | ||
45 | - wlf,inmode : A list of INn_MODE register values, where n is the number | ||
46 | of input signals. Valid values are 0 (Differential), 1 (Single-ended) and | ||
47 | 2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default. | ||
48 | If present, values must be specified less than or equal to the number of | ||
49 | input singals. If values less than the number of input signals, elements | ||
50 | that has not been specifed are set to 0 by default. | ||
51 | |||
45 | - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if | 52 | - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if |
46 | they are being externally supplied. As covered in | 53 | they are being externally supplied. As covered in |
47 | Documentation/devicetree/bindings/regulator/regulator.txt | 54 | Documentation/devicetree/bindings/regulator/regulator.txt |
diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt new file mode 100644 index 000000000000..a28569540683 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | * Device tree bindings for Atmel GPBR (General Purpose Backup Registers) | ||
2 | |||
3 | The GPBR are a set of battery-backed registers. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: "atmel,at91sam9260-gpbr", "syscon" | ||
7 | - reg: contains offset/length value of the GPBR memory | ||
8 | region. | ||
9 | |||
10 | Example: | ||
11 | |||
12 | gpbr: gpbr@fffffd50 { | ||
13 | compatible = "atmel,at91sam9260-gpbr", "syscon"; | ||
14 | reg = <0xfffffd50 0x10>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt new file mode 100644 index 000000000000..f64de95a8e8b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | |||
@@ -0,0 +1,51 @@ | |||
1 | Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: value should be one of the following: | ||
5 | "atmel,sama5d3-hlcdc" | ||
6 | - reg: base address and size of the HLCDC device registers. | ||
7 | - clock-names: the name of the 3 clocks requested by the HLCDC device. | ||
8 | Should contain "periph_clk", "sys_clk" and "slow_clk". | ||
9 | - clocks: should contain the 3 clocks requested by the HLCDC device. | ||
10 | - interrupts: should contain the description of the HLCDC interrupt line | ||
11 | |||
12 | The HLCDC IP exposes two subdevices: | ||
13 | - a PWM chip: see ../pwm/atmel-hlcdc-pwm.txt | ||
14 | - a Display Controller: see ../drm/atmel-hlcdc-dc.txt | ||
15 | |||
16 | Example: | ||
17 | |||
18 | hlcdc: hlcdc@f0030000 { | ||
19 | compatible = "atmel,sama5d3-hlcdc"; | ||
20 | reg = <0xf0030000 0x2000>; | ||
21 | clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | ||
22 | clock-names = "periph_clk","sys_clk", "slow_clk"; | ||
23 | interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | ||
24 | status = "disabled"; | ||
25 | |||
26 | hlcdc-display-controller { | ||
27 | compatible = "atmel,hlcdc-display-controller"; | ||
28 | pinctrl-names = "default"; | ||
29 | pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>; | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <0>; | ||
32 | |||
33 | port@0 { | ||
34 | #address-cells = <1>; | ||
35 | #size-cells = <0>; | ||
36 | reg = <0>; | ||
37 | |||
38 | hlcdc_panel_output: endpoint@0 { | ||
39 | reg = <0>; | ||
40 | remote-endpoint = <&panel_input>; | ||
41 | }; | ||
42 | }; | ||
43 | }; | ||
44 | |||
45 | hlcdc_pwm: hlcdc-pwm { | ||
46 | compatible = "atmel,hlcdc-pwm"; | ||
47 | pinctrl-names = "default"; | ||
48 | pinctrl-0 = <&pinctrl_lcd_pwm>; | ||
49 | #pwm-cells = <3>; | ||
50 | }; | ||
51 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/hi6421.txt b/Documentation/devicetree/bindings/mfd/hi6421.txt new file mode 100644 index 000000000000..0d5a4466a494 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/hi6421.txt | |||
@@ -0,0 +1,38 @@ | |||
1 | * HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd. | ||
2 | |||
3 | Required parent device properties: | ||
4 | - compatible : contains "hisilicon,hi6421-pmic"; | ||
5 | - reg : register range space of hi6421; | ||
6 | |||
7 | Supported Hi6421 sub-devices include: | ||
8 | |||
9 | Device IRQ Names Supply Names Description | ||
10 | ------ --------- ------------ ----------- | ||
11 | regulators : None : None : Regulators | ||
12 | |||
13 | Required child device properties: | ||
14 | None. | ||
15 | |||
16 | Example: | ||
17 | hi6421 { | ||
18 | compatible = "hisilicon,hi6421-pmic"; | ||
19 | reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */ | ||
20 | |||
21 | regulators { | ||
22 | // supply for MLC NAND/ eMMC | ||
23 | hi6421_vout0_reg: hi6421_vout0 { | ||
24 | regulator-name = "VOUT0"; | ||
25 | regulator-min-microvolt = <2850000>; | ||
26 | regulator-max-microvolt = <2850000>; | ||
27 | }; | ||
28 | |||
29 | // supply for 26M Oscillator | ||
30 | hi6421_vout1_reg: hi6421_vout1 { | ||
31 | regulator-name = "VOUT1"; | ||
32 | regulator-min-microvolt = <1700000>; | ||
33 | regulator-max-microvolt = <2000000>; | ||
34 | regulator-boot-on; | ||
35 | regulator-always-on; | ||
36 | }; | ||
37 | }; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/max14577.txt b/Documentation/devicetree/bindings/mfd/max14577.txt new file mode 100644 index 000000000000..236264c10b92 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/max14577.txt | |||
@@ -0,0 +1,146 @@ | |||
1 | Maxim MAX14577/77836 Multi-Function Device | ||
2 | |||
3 | MAX14577 is a Multi-Function Device with Micro-USB Interface Circuit, Li+ | ||
4 | Battery Charger and SFOUT LDO output for powering USB devices. It is | ||
5 | interfaced to host controller using I2C. | ||
6 | |||
7 | MAX77836 additionally contains PMIC (with two LDO regulators) and Fuel Gauge. | ||
8 | |||
9 | |||
10 | Required properties: | ||
11 | - compatible : Must be "maxim,max14577" or "maxim,max77836". | ||
12 | - reg : I2C slave address for the max14577 chip (0x25 for max14577/max77836) | ||
13 | - interrupts : IRQ line for the chip. | ||
14 | - interrupt-parent : The parent interrupt controller. | ||
15 | |||
16 | |||
17 | Required nodes: | ||
18 | - charger : | ||
19 | Node for configuring the charger driver. | ||
20 | Required properties: | ||
21 | - compatible : "maxim,max14577-charger" | ||
22 | or "maxim,max77836-charger" | ||
23 | - maxim,fast-charge-uamp : Current in uA for Fast Charge; | ||
24 | Valid values: | ||
25 | - for max14577: 90000 - 950000; | ||
26 | - for max77836: 45000 - 475000; | ||
27 | - maxim,eoc-uamp : Current in uA for End-Of-Charge mode; | ||
28 | Valid values: | ||
29 | - for max14577: 50000 - 200000; | ||
30 | - for max77836: 5000 - 100000; | ||
31 | - maxim,ovp-uvolt : OverVoltage Protection Threshold in uV; | ||
32 | In an overvoltage condition, INT asserts and charging | ||
33 | stops. Valid values: | ||
34 | - 6000000, 6500000, 7000000, 7500000; | ||
35 | - maxim,constant-uvolt : Battery Constant Voltage in uV; | ||
36 | Valid values: | ||
37 | - 4000000 - 4280000 (step by 20000); | ||
38 | - 4350000; | ||
39 | |||
40 | |||
41 | Optional nodes: | ||
42 | - max14577-muic/max77836-muic : | ||
43 | Node used only by extcon consumers. | ||
44 | Required properties: | ||
45 | - compatible : "maxim,max14577-muic" or "maxim,max77836-muic" | ||
46 | |||
47 | - regulators : | ||
48 | Required properties: | ||
49 | - compatible : "maxim,max14577-regulator" | ||
50 | or "maxim,max77836-regulator" | ||
51 | |||
52 | May contain a sub-node per regulator from the list below. Each | ||
53 | sub-node should contain the constraints and initialization information | ||
54 | for that regulator. See regulator.txt for a description of standard | ||
55 | properties for these sub-nodes. | ||
56 | |||
57 | List of valid regulator names: | ||
58 | - for max14577: CHARGER, SAFEOUT. | ||
59 | - for max77836: CHARGER, SAFEOUT, LDO1, LDO2. | ||
60 | |||
61 | The SAFEOUT is a fixed voltage regulator so there is no need to specify | ||
62 | voltages for it. | ||
63 | |||
64 | |||
65 | Example: | ||
66 | |||
67 | #include <dt-bindings/interrupt-controller/irq.h> | ||
68 | |||
69 | max14577@25 { | ||
70 | compatible = "maxim,max14577"; | ||
71 | reg = <0x25>; | ||
72 | interrupt-parent = <&gpx1>; | ||
73 | interrupts = <5 IRQ_TYPE_NONE>; | ||
74 | |||
75 | muic: max14577-muic { | ||
76 | compatible = "maxim,max14577-muic"; | ||
77 | }; | ||
78 | |||
79 | regulators { | ||
80 | compatible = "maxim,max14577-regulator"; | ||
81 | |||
82 | SAFEOUT { | ||
83 | regulator-name = "SAFEOUT"; | ||
84 | }; | ||
85 | CHARGER { | ||
86 | regulator-name = "CHARGER"; | ||
87 | regulator-min-microamp = <90000>; | ||
88 | regulator-max-microamp = <950000>; | ||
89 | regulator-boot-on; | ||
90 | }; | ||
91 | }; | ||
92 | |||
93 | charger { | ||
94 | compatible = "maxim,max14577-charger"; | ||
95 | |||
96 | maxim,constant-uvolt = <4350000>; | ||
97 | maxim,fast-charge-uamp = <450000>; | ||
98 | maxim,eoc-uamp = <50000>; | ||
99 | maxim,ovp-uvolt = <6500000>; | ||
100 | }; | ||
101 | }; | ||
102 | |||
103 | |||
104 | max77836@25 { | ||
105 | compatible = "maxim,max77836"; | ||
106 | reg = <0x25>; | ||
107 | interrupt-parent = <&gpx1>; | ||
108 | interrupts = <5 IRQ_TYPE_NONE>; | ||
109 | |||
110 | muic: max77836-muic { | ||
111 | compatible = "maxim,max77836-muic"; | ||
112 | }; | ||
113 | |||
114 | regulators { | ||
115 | compatible = "maxim,max77836-regulator"; | ||
116 | |||
117 | SAFEOUT { | ||
118 | regulator-name = "SAFEOUT"; | ||
119 | }; | ||
120 | CHARGER { | ||
121 | regulator-name = "CHARGER"; | ||
122 | regulator-min-microamp = <90000>; | ||
123 | regulator-max-microamp = <950000>; | ||
124 | regulator-boot-on; | ||
125 | }; | ||
126 | LDO1 { | ||
127 | regulator-name = "LDO1"; | ||
128 | regulator-min-microvolt = <2700000>; | ||
129 | regulator-max-microvolt = <2700000>; | ||
130 | }; | ||
131 | LDO2 { | ||
132 | regulator-name = "LDO2"; | ||
133 | regulator-min-microvolt = <800000>; | ||
134 | regulator-max-microvolt = <3950000>; | ||
135 | }; | ||
136 | }; | ||
137 | |||
138 | charger { | ||
139 | compatible = "maxim,max77836-charger"; | ||
140 | |||
141 | maxim,constant-uvolt = <4350000>; | ||
142 | maxim,fast-charge-uamp = <225000>; | ||
143 | maxim,eoc-uamp = <7500>; | ||
144 | maxim,ovp-uvolt = <6500000>; | ||
145 | }; | ||
146 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/max77686.txt b/Documentation/devicetree/bindings/mfd/max77686.txt index 678f3cf0b8f0..75fdfaf41831 100644 --- a/Documentation/devicetree/bindings/mfd/max77686.txt +++ b/Documentation/devicetree/bindings/mfd/max77686.txt | |||
@@ -34,6 +34,12 @@ to get matched with their hardware counterparts as follow: | |||
34 | -BUCKn : for BUCKs, where n can lie in range 1 to 9. | 34 | -BUCKn : for BUCKs, where n can lie in range 1 to 9. |
35 | example: BUCK1, BUCK5, BUCK9. | 35 | example: BUCK1, BUCK5, BUCK9. |
36 | 36 | ||
37 | Regulators which can be turned off during system suspend: | ||
38 | -LDOn : 2, 6-8, 10-12, 14-16, | ||
39 | -BUCKn : 1-4. | ||
40 | Use standard regulator bindings for it ('regulator-off-in-suspend'). | ||
41 | |||
42 | |||
37 | Example: | 43 | Example: |
38 | 44 | ||
39 | max77686@09 { | 45 | max77686@09 { |
diff --git a/Documentation/devicetree/bindings/mfd/max77693.txt b/Documentation/devicetree/bindings/mfd/max77693.txt index 11921cc417bf..01e9f30fe678 100644 --- a/Documentation/devicetree/bindings/mfd/max77693.txt +++ b/Documentation/devicetree/bindings/mfd/max77693.txt | |||
@@ -27,6 +27,20 @@ Optional properties: | |||
27 | 27 | ||
28 | [*] refer Documentation/devicetree/bindings/regulator/regulator.txt | 28 | [*] refer Documentation/devicetree/bindings/regulator/regulator.txt |
29 | 29 | ||
30 | - haptic : The MAX77693 haptic device utilises a PWM controlled motor to provide | ||
31 | users with tactile feedback. PWM period and duty-cycle are varied in | ||
32 | order to provide the approprite level of feedback. | ||
33 | |||
34 | Required properties: | ||
35 | - compatible : Must be "maxim,max77693-hpatic" | ||
36 | - haptic-supply : power supply for the haptic motor | ||
37 | [*] refer Documentation/devicetree/bindings/regulator/regulator.txt | ||
38 | - pwms : phandle to the physical PWM(Pulse Width Modulation) device. | ||
39 | PWM properties should be named "pwms". And number of cell is different | ||
40 | for each pwm device. | ||
41 | To get more informations, please refer to documentaion. | ||
42 | [*] refer Documentation/devicetree/bindings/pwm/pwm.txt | ||
43 | |||
30 | Example: | 44 | Example: |
31 | max77693@66 { | 45 | max77693@66 { |
32 | compatible = "maxim,max77693"; | 46 | compatible = "maxim,max77693"; |
@@ -52,4 +66,11 @@ Example: | |||
52 | regulator-boot-on; | 66 | regulator-boot-on; |
53 | }; | 67 | }; |
54 | }; | 68 | }; |
69 | |||
70 | haptic { | ||
71 | compatible = "maxim,max77693-haptic"; | ||
72 | haptic-supply = <&haptic_supply>; | ||
73 | pwms = <&pwm 0 40000 0>; | ||
74 | pwm-names = "haptic"; | ||
75 | }; | ||
55 | }; | 76 | }; |
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt new file mode 100644 index 000000000000..7182b8857f57 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt | |||
@@ -0,0 +1,64 @@ | |||
1 | Qualcomm SPMI PMICs multi-function device bindings | ||
2 | |||
3 | The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084 | ||
4 | PMICs. These PMICs use a QPNP scheme through SPMI interface. | ||
5 | QPNP is effectively a partitioning scheme for dividing the SPMI extended | ||
6 | register space up into logical pieces, and set of fixed register | ||
7 | locations/definitions within these regions, with some of these regions | ||
8 | specifically used for interrupt handling. | ||
9 | |||
10 | The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are | ||
11 | interfaced to the chip via the SPMI (System Power Management Interface) bus. | ||
12 | Support for multiple independent functions are implemented by splitting the | ||
13 | 16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes | ||
14 | each. A function can consume one or more of these fixed-size register regions. | ||
15 | |||
16 | Required properties: | ||
17 | - compatible: Should contain one of: | ||
18 | "qcom,pm8941" | ||
19 | "qcom,pm8841" | ||
20 | "qcom,pma8084" | ||
21 | or generalized "qcom,spmi-pmic". | ||
22 | - reg: Specifies the SPMI USID slave address for this device. | ||
23 | For more information see: | ||
24 | Documentation/devicetree/bindings/spmi/spmi.txt | ||
25 | |||
26 | Required properties for peripheral child nodes: | ||
27 | - compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name. | ||
28 | |||
29 | Optional properties for peripheral child nodes: | ||
30 | - interrupts: Interrupts are specified as a 4-tuple. For more information | ||
31 | see: | ||
32 | Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt | ||
33 | - interrupt-names: Corresponding interrupt name to the interrupts property | ||
34 | |||
35 | Each child node of SPMI slave id represents a function of the PMIC. In the | ||
36 | example below the rtc device node represents a peripheral of pm8941 | ||
37 | SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1. | ||
38 | |||
39 | Example: | ||
40 | |||
41 | spmi { | ||
42 | compatible = "qcom,spmi-pmic-arb"; | ||
43 | |||
44 | pm8941@0 { | ||
45 | compatible = "qcom,pm8941", "qcom,spmi-pmic"; | ||
46 | reg = <0x0 SPMI_USID>; | ||
47 | |||
48 | rtc { | ||
49 | compatible = "qcom,rtc"; | ||
50 | interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; | ||
51 | interrupt-names = "alarm"; | ||
52 | }; | ||
53 | }; | ||
54 | |||
55 | pm8941@1 { | ||
56 | compatible = "qcom,pm8941", "qcom,spmi-pmic"; | ||
57 | reg = <0x1 SPMI_USID>; | ||
58 | |||
59 | regulator { | ||
60 | compatible = "qcom,regulator"; | ||
61 | regulator-name = "8941_boost"; | ||
62 | }; | ||
63 | }; | ||
64 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt index 03518dc8b6bd..f24f33409164 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt +++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt | |||
@@ -61,6 +61,7 @@ The below bindings specify the set of valid subnodes. | |||
61 | Definition: must be one of: | 61 | Definition: must be one of: |
62 | "qcom,pm8058-rtc" | 62 | "qcom,pm8058-rtc" |
63 | "qcom,pm8921-rtc" | 63 | "qcom,pm8921-rtc" |
64 | "qcom,pm8941-rtc" | ||
64 | 65 | ||
65 | - reg: | 66 | - reg: |
66 | Usage: required | 67 | Usage: required |
diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt new file mode 100644 index 000000000000..9e6e2592e5c8 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rk808.txt | |||
@@ -0,0 +1,177 @@ | |||
1 | RK808 Power Management Integrated Circuit | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "rockchip,rk808" | ||
5 | - reg: I2C slave address | ||
6 | - interrupt-parent: The parent interrupt controller. | ||
7 | - interrupts: the interrupt outputs of the controller. | ||
8 | - #clock-cells: from common clock binding; shall be set to 1 (multiple clock | ||
9 | outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. | ||
10 | |||
11 | Optional properties: | ||
12 | - clock-output-names: From common clock binding to override the | ||
13 | default output clock name | ||
14 | - rockchip,system-power-controller: Telling whether or not this pmic is controlling | ||
15 | the system power. | ||
16 | - vcc1-supply: The input supply for DCDC_REG1 | ||
17 | - vcc2-supply: The input supply for DCDC_REG2 | ||
18 | - vcc3-supply: The input supply for DCDC_REG3 | ||
19 | - vcc4-supply: The input supply for DCDC_REG4 | ||
20 | - vcc6-supply: The input supply for LDO_REG1 and LDO_REG2 | ||
21 | - vcc7-supply: The input supply for LDO_REG3 and LDO_REG7 | ||
22 | - vcc8-supply: The input supply for SWITCH_REG1 | ||
23 | - vcc9-supply: The input supply for LDO_REG4 and LDO_REG5 | ||
24 | - vcc10-supply: The input supply for LDO_REG6 | ||
25 | - vcc11-supply: The input supply for LDO_REG8 | ||
26 | - vcc12-supply: The input supply for SWITCH_REG2 | ||
27 | |||
28 | Regulators: All the regulators of RK808 to be instantiated shall be | ||
29 | listed in a child node named 'regulators'. Each regulator is represented | ||
30 | by a child node of the 'regulators' node. | ||
31 | |||
32 | regulator-name { | ||
33 | /* standard regulator bindings here */ | ||
34 | }; | ||
35 | |||
36 | Following regulators of the RK808 PMIC block are supported. Note that | ||
37 | the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO | ||
38 | number as described in RK808 datasheet. | ||
39 | |||
40 | - DCDC_REGn | ||
41 | - valid values for n are 1 to 4. | ||
42 | - LDO_REGn | ||
43 | - valid values for n are 1 to 8. | ||
44 | - SWITCH_REGn | ||
45 | - valid values for n are 1 to 2 | ||
46 | |||
47 | Standard regulator bindings are used inside regulator subnodes. Check | ||
48 | Documentation/devicetree/bindings/regulator/regulator.txt | ||
49 | for more details | ||
50 | |||
51 | Example: | ||
52 | rk808: pmic@1b { | ||
53 | compatible = "rockchip,rk808"; | ||
54 | clock-output-names = "xin32k", "rk808-clkout2"; | ||
55 | interrupt-parent = <&gpio0>; | ||
56 | interrupts = <4 IRQ_TYPE_LEVEL_LOW>; | ||
57 | pinctrl-names = "default"; | ||
58 | pinctrl-0 = <&pmic_int>; | ||
59 | reg = <0x1b>; | ||
60 | rockchip,system-power-controller; | ||
61 | wakeup-source; | ||
62 | #clock-cells = <1>; | ||
63 | |||
64 | vcc8-supply = <&vcc_18>; | ||
65 | vcc9-supply = <&vcc_io>; | ||
66 | vcc10-supply = <&vcc_io>; | ||
67 | vcc12-supply = <&vcc_io>; | ||
68 | vddio-supply = <&vccio_pmu>; | ||
69 | |||
70 | regulators { | ||
71 | vdd_cpu: DCDC_REG1 { | ||
72 | regulator-always-on; | ||
73 | regulator-boot-on; | ||
74 | regulator-min-microvolt = <750000>; | ||
75 | regulator-max-microvolt = <1300000>; | ||
76 | regulator-name = "vdd_arm"; | ||
77 | }; | ||
78 | |||
79 | vdd_gpu: DCDC_REG2 { | ||
80 | regulator-always-on; | ||
81 | regulator-boot-on; | ||
82 | regulator-min-microvolt = <850000>; | ||
83 | regulator-max-microvolt = <1250000>; | ||
84 | regulator-name = "vdd_gpu"; | ||
85 | }; | ||
86 | |||
87 | vcc_ddr: DCDC_REG3 { | ||
88 | regulator-always-on; | ||
89 | regulator-boot-on; | ||
90 | regulator-name = "vcc_ddr"; | ||
91 | }; | ||
92 | |||
93 | vcc_io: DCDC_REG4 { | ||
94 | regulator-always-on; | ||
95 | regulator-boot-on; | ||
96 | regulator-min-microvolt = <3300000>; | ||
97 | regulator-max-microvolt = <3300000>; | ||
98 | regulator-name = "vcc_io"; | ||
99 | }; | ||
100 | |||
101 | vccio_pmu: LDO_REG1 { | ||
102 | regulator-always-on; | ||
103 | regulator-boot-on; | ||
104 | regulator-min-microvolt = <3300000>; | ||
105 | regulator-max-microvolt = <3300000>; | ||
106 | regulator-name = "vccio_pmu"; | ||
107 | }; | ||
108 | |||
109 | vcc_tp: LDO_REG2 { | ||
110 | regulator-always-on; | ||
111 | regulator-boot-on; | ||
112 | regulator-min-microvolt = <3300000>; | ||
113 | regulator-max-microvolt = <3300000>; | ||
114 | regulator-name = "vcc_tp"; | ||
115 | }; | ||
116 | |||
117 | vdd_10: LDO_REG3 { | ||
118 | regulator-always-on; | ||
119 | regulator-boot-on; | ||
120 | regulator-min-microvolt = <1000000>; | ||
121 | regulator-max-microvolt = <1000000>; | ||
122 | regulator-name = "vdd_10"; | ||
123 | }; | ||
124 | |||
125 | vcc18_lcd: LDO_REG4 { | ||
126 | regulator-always-on; | ||
127 | regulator-boot-on; | ||
128 | regulator-min-microvolt = <1800000>; | ||
129 | regulator-max-microvolt = <1800000>; | ||
130 | regulator-name = "vcc18_lcd"; | ||
131 | }; | ||
132 | |||
133 | vccio_sd: LDO_REG5 { | ||
134 | regulator-always-on; | ||
135 | regulator-boot-on; | ||
136 | regulator-min-microvolt = <1800000>; | ||
137 | regulator-max-microvolt = <3300000>; | ||
138 | regulator-name = "vccio_sd"; | ||
139 | }; | ||
140 | |||
141 | vdd10_lcd: LDO_REG6 { | ||
142 | regulator-always-on; | ||
143 | regulator-boot-on; | ||
144 | regulator-min-microvolt = <1000000>; | ||
145 | regulator-max-microvolt = <1000000>; | ||
146 | regulator-name = "vdd10_lcd"; | ||
147 | }; | ||
148 | |||
149 | vcc_18: LDO_REG7 { | ||
150 | regulator-always-on; | ||
151 | regulator-boot-on; | ||
152 | regulator-min-microvolt = <1800000>; | ||
153 | regulator-max-microvolt = <1800000>; | ||
154 | regulator-name = "vcc_18"; | ||
155 | }; | ||
156 | |||
157 | vcca_codec: LDO_REG8 { | ||
158 | regulator-always-on; | ||
159 | regulator-boot-on; | ||
160 | regulator-min-microvolt = <3300000>; | ||
161 | regulator-max-microvolt = <3300000>; | ||
162 | regulator-name = "vcca_codec"; | ||
163 | }; | ||
164 | |||
165 | vcc_wl: SWITCH_REG1 { | ||
166 | regulator-always-on; | ||
167 | regulator-boot-on; | ||
168 | regulator-name = "vcc_wl"; | ||
169 | }; | ||
170 | |||
171 | vcc_lcd: SWITCH_REG2 { | ||
172 | regulator-always-on; | ||
173 | regulator-boot-on; | ||
174 | regulator-name = "vcc_lcd"; | ||
175 | }; | ||
176 | }; | ||
177 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/rn5t618.txt b/Documentation/devicetree/bindings/mfd/rn5t618.txt new file mode 100644 index 000000000000..937785a3eddc --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rn5t618.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | * Ricoh RN5T618 PMIC | ||
2 | |||
3 | Ricoh RN5T618 is a power management IC which integrates 3 step-down | ||
4 | DCDC converters, 7 low-dropout regulators, a Li-ion battery charger, | ||
5 | fuel gauge, ADC, GPIOs and a watchdog timer. It can be controlled | ||
6 | through a I2C interface. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: should be "ricoh,rn5t618" | ||
10 | - reg: the I2C slave address of the device | ||
11 | |||
12 | Sub-nodes: | ||
13 | - regulators: the node is required if the regulator functionality is | ||
14 | needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, LDO1, | ||
15 | LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2. | ||
16 | The common bindings for each individual regulator can be found in: | ||
17 | Documentation/devicetree/bindings/regulator/regulator.txt | ||
18 | |||
19 | Example: | ||
20 | |||
21 | pmic@32 { | ||
22 | compatible = "ricoh,rn5t618"; | ||
23 | reg = <0x32>; | ||
24 | |||
25 | regulators { | ||
26 | DCDC1 { | ||
27 | regulator-min-microvolt = <1050000>; | ||
28 | regulator-max-microvolt = <1050000>; | ||
29 | }; | ||
30 | |||
31 | DCDC2 { | ||
32 | regulator-min-microvolt = <1175000>; | ||
33 | regulator-max-microvolt = <1175000>; | ||
34 | }; | ||
35 | }; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt index ba2d7f0f9c5f..57a045016fca 100644 --- a/Documentation/devicetree/bindings/mfd/s2mps11.txt +++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt | |||
@@ -1,5 +1,5 @@ | |||
1 | 1 | ||
2 | * Samsung S2MPS11, S2MPS14 and S2MPU02 Voltage and Current Regulator | 2 | * Samsung S2MPS11, S2MPS13, S2MPS14 and S2MPU02 Voltage and Current Regulator |
3 | 3 | ||
4 | The Samsung S2MPS11 is a multi-function device which includes voltage and | 4 | The Samsung S2MPS11 is a multi-function device which includes voltage and |
5 | current regulators, RTC, charger controller and other sub-blocks. It is | 5 | current regulators, RTC, charger controller and other sub-blocks. It is |
@@ -7,8 +7,8 @@ interfaced to the host controller using an I2C interface. Each sub-block is | |||
7 | addressed by the host system using different I2C slave addresses. | 7 | addressed by the host system using different I2C slave addresses. |
8 | 8 | ||
9 | Required properties: | 9 | Required properties: |
10 | - compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic" | 10 | - compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps13-pmic" |
11 | or "samsung,s2mpu02-pmic". | 11 | or "samsung,s2mps14-pmic" or "samsung,s2mpu02-pmic". |
12 | - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. | 12 | - reg: Specifies the I2C slave address of the pmic block. It should be 0x66. |
13 | 13 | ||
14 | Optional properties: | 14 | Optional properties: |
@@ -17,8 +17,8 @@ Optional properties: | |||
17 | - interrupts: Interrupt specifiers for interrupt sources. | 17 | - interrupts: Interrupt specifiers for interrupt sources. |
18 | 18 | ||
19 | Optional nodes: | 19 | Optional nodes: |
20 | - clocks: s2mps11 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz | 20 | - clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768 |
21 | outputs, so to register these as clocks with common clock framework | 21 | KHz outputs, so to register these as clocks with common clock framework |
22 | instantiate a sub-node named "clocks". It uses the common clock binding | 22 | instantiate a sub-node named "clocks". It uses the common clock binding |
23 | documented in : | 23 | documented in : |
24 | [Documentation/devicetree/bindings/clock/clock-bindings.txt] | 24 | [Documentation/devicetree/bindings/clock/clock-bindings.txt] |
@@ -30,12 +30,12 @@ Optional nodes: | |||
30 | the clock which they consume. | 30 | the clock which they consume. |
31 | Clock ID Devices | 31 | Clock ID Devices |
32 | ---------------------------------------------------------- | 32 | ---------------------------------------------------------- |
33 | 32KhzAP 0 S2MPS11, S2MPS14, S5M8767 | 33 | 32KhzAP 0 S2MPS11, S2MPS13, S2MPS14, S5M8767 |
34 | 32KhzCP 1 S2MPS11, S5M8767 | 34 | 32KhzCP 1 S2MPS11, S2MPS13, S5M8767 |
35 | 32KhzBT 2 S2MPS11, S2MPS14, S5M8767 | 35 | 32KhzBT 2 S2MPS11, S2MPS13, S2MPS14, S5M8767 |
36 | 36 | ||
37 | - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps14-clk", | 37 | - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps13-clk", |
38 | "samsung,s5m8767-clk" | 38 | "samsung,s2mps14-clk", "samsung,s5m8767-clk" |
39 | 39 | ||
40 | - regulators: The regulators of s2mps11 that have to be instantiated should be | 40 | - regulators: The regulators of s2mps11 that have to be instantiated should be |
41 | included in a sub-node named 'regulators'. Regulator nodes included in this | 41 | included in a sub-node named 'regulators'. Regulator nodes included in this |
@@ -47,7 +47,7 @@ sub-node should be of the format as listed below. | |||
47 | 47 | ||
48 | regulator-ramp-delay for BUCKs = [6250/12500/25000(default)/50000] uV/us | 48 | regulator-ramp-delay for BUCKs = [6250/12500/25000(default)/50000] uV/us |
49 | 49 | ||
50 | BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explictly | 50 | BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explicitly |
51 | regulator-ramp-delay = <0> can be used for them to disable ramp delay. | 51 | regulator-ramp-delay = <0> can be used for them to disable ramp delay. |
52 | In the absence of the regulator-ramp-delay property, the default ramp | 52 | In the absence of the regulator-ramp-delay property, the default ramp |
53 | delay will be used. | 53 | delay will be used. |
@@ -81,12 +81,14 @@ as per the datasheet of s2mps11. | |||
81 | - LDOn | 81 | - LDOn |
82 | - valid values for n are: | 82 | - valid values for n are: |
83 | - S2MPS11: 1 to 38 | 83 | - S2MPS11: 1 to 38 |
84 | - S2MPS13: 1 to 40 | ||
84 | - S2MPS14: 1 to 25 | 85 | - S2MPS14: 1 to 25 |
85 | - S2MPU02: 1 to 28 | 86 | - S2MPU02: 1 to 28 |
86 | - Example: LDO1, LDO2, LDO28 | 87 | - Example: LDO1, LDO2, LDO28 |
87 | - BUCKn | 88 | - BUCKn |
88 | - valid values for n are: | 89 | - valid values for n are: |
89 | - S2MPS11: 1 to 10 | 90 | - S2MPS11: 1 to 10 |
91 | - S2MPS13: 1 to 10 | ||
90 | - S2MPS14: 1 to 5 | 92 | - S2MPS14: 1 to 5 |
91 | - S2MPU02: 1 to 7 | 93 | - S2MPU02: 1 to 7 |
92 | - Example: BUCK1, BUCK2, BUCK9 | 94 | - Example: BUCK1, BUCK2, BUCK9 |
diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt index 56edb5520685..3fb68bfefc8b 100644 --- a/Documentation/devicetree/bindings/mfd/stmpe.txt +++ b/Documentation/devicetree/bindings/mfd/stmpe.txt | |||
@@ -13,6 +13,7 @@ Optional properties: | |||
13 | - interrupt-parent : Specifies which IRQ controller we're connected to | 13 | - interrupt-parent : Specifies which IRQ controller we're connected to |
14 | - wakeup-source : Marks the input device as wakable | 14 | - wakeup-source : Marks the input device as wakable |
15 | - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 | 15 | - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 |
16 | - irq-gpio : If present, which GPIO to use for event IRQ | ||
16 | 17 | ||
17 | Example: | 18 | Example: |
18 | 19 | ||
diff --git a/Documentation/devicetree/bindings/mfd/twl4030-power.txt b/Documentation/devicetree/bindings/mfd/twl4030-power.txt index b9ee7b98d3e2..3d19963312ce 100644 --- a/Documentation/devicetree/bindings/mfd/twl4030-power.txt +++ b/Documentation/devicetree/bindings/mfd/twl4030-power.txt | |||
@@ -23,8 +23,13 @@ down during off-idle. Note that this does not work on all boards | |||
23 | depending on how the external oscillator is wired. | 23 | depending on how the external oscillator is wired. |
24 | 24 | ||
25 | Optional properties: | 25 | Optional properties: |
26 | - ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or | 26 | |
27 | SLEEP-to-OFF transition when the system poweroffs. | 27 | - ti,system-power-controller: This indicates that TWL4030 is the |
28 | power supply master of the system. With this flag, the chip will | ||
29 | initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the | ||
30 | system poweroffs. | ||
31 | |||
32 | - ti,use_poweroff: Deprecated name for ti,system-power-controller | ||
28 | 33 | ||
29 | Example: | 34 | Example: |
30 | &i2c1 { | 35 | &i2c1 { |
diff --git a/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt b/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt new file mode 100644 index 000000000000..d4e0141d3620 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt | |||
@@ -0,0 +1,37 @@ | |||
1 | * Interrupt Controller | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "brcm,bcm3384-intc" | ||
5 | |||
6 | Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs. | ||
7 | |||
8 | - reg: Address/length pairs for each mask/status register set. Length must | ||
9 | be 8. If multiple register sets are specified, the first set will | ||
10 | handle IRQ offsets 0..31, the second set 32..63, and so on. | ||
11 | |||
12 | - interrupt-controller: This is an interrupt controller. | ||
13 | |||
14 | - #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge | ||
15 | or polarity configuration is possible with this controller. | ||
16 | |||
17 | - interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or | ||
18 | from another INTC. | ||
19 | |||
20 | - interrupts: The IRQ on the parent controller. | ||
21 | |||
22 | Example: | ||
23 | periph_intc: periph_intc@14e00038 { | ||
24 | compatible = "brcm,bcm3384-intc"; | ||
25 | |||
26 | /* | ||
27 | * IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c | ||
28 | * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344 | ||
29 | */ | ||
30 | reg = <0x14e00038 0x8 0x14e00340 0x8>; | ||
31 | |||
32 | interrupt-controller; | ||
33 | #interrupt-cells = <1>; | ||
34 | |||
35 | interrupt-parent = <&cpu_intc>; | ||
36 | interrupts = <4>; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/brcm/bmips.txt b/Documentation/devicetree/bindings/mips/brcm/bmips.txt new file mode 100644 index 000000000000..8ef71b4085ca --- /dev/null +++ b/Documentation/devicetree/bindings/mips/brcm/bmips.txt | |||
@@ -0,0 +1,8 @@ | |||
1 | * Broadcom MIPS (BMIPS) CPUs | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "brcm,bmips3300", "brcm,bmips4350", "brcm,bmips4380", | ||
5 | "brcm,bmips5000" | ||
6 | |||
7 | - mips-hpt-frequency: This is common to all CPUs in the system so it lives | ||
8 | under the "cpus" node. | ||
diff --git a/Documentation/devicetree/bindings/mips/brcm/cm-dsl.txt b/Documentation/devicetree/bindings/mips/brcm/cm-dsl.txt new file mode 100644 index 000000000000..8a139cb3c0b5 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/brcm/cm-dsl.txt | |||
@@ -0,0 +1,11 @@ | |||
1 | * Broadcom cable/DSL platforms | ||
2 | |||
3 | SoCs: | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: "brcm,bcm3384", "brcm,bcm33843" | ||
7 | |||
8 | Boards: | ||
9 | |||
10 | Required properties: | ||
11 | - compatible: "brcm,bcm93384wvg" | ||
diff --git a/Documentation/devicetree/bindings/mips/brcm/usb.txt b/Documentation/devicetree/bindings/mips/brcm/usb.txt new file mode 100644 index 000000000000..452c45c7bf29 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/brcm/usb.txt | |||
@@ -0,0 +1,11 @@ | |||
1 | * Broadcom USB controllers | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "brcm,bcm3384-ohci", "brcm,bcm3384-ehci" | ||
5 | |||
6 | These currently use the generic-ohci and generic-ehci drivers. On some | ||
7 | systems, special handling may be needed in the following cases: | ||
8 | |||
9 | - Restoring state after systemwide power save modes | ||
10 | - Sharing PHYs with the USBD (UDC) hardware | ||
11 | - Figuring out which controllers are disabled on ASIC bondout variants | ||
diff --git a/Documentation/devicetree/bindings/mips/cpu_irq.txt b/Documentation/devicetree/bindings/mips/cpu_irq.txt index 13aa4b62c62a..fc149f326dae 100644 --- a/Documentation/devicetree/bindings/mips/cpu_irq.txt +++ b/Documentation/devicetree/bindings/mips/cpu_irq.txt | |||
@@ -1,6 +1,6 @@ | |||
1 | MIPS CPU interrupt controller | 1 | MIPS CPU interrupt controller |
2 | 2 | ||
3 | On MIPS the mips_cpu_intc_init() helper can be used to initialize the 8 CPU | 3 | On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU |
4 | IRQs from a devicetree file and create a irq_domain for IRQ controller. | 4 | IRQs from a devicetree file and create a irq_domain for IRQ controller. |
5 | 5 | ||
6 | With the irq_domain in place we can describe how the 8 IRQs are wired to the | 6 | With the irq_domain in place we can describe how the 8 IRQs are wired to the |
@@ -36,7 +36,7 @@ Example devicetree: | |||
36 | 36 | ||
37 | Example platform irq.c: | 37 | Example platform irq.c: |
38 | static struct of_device_id __initdata of_irq_ids[] = { | 38 | static struct of_device_id __initdata of_irq_ids[] = { |
39 | { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init }, | 39 | { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init }, |
40 | { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, | 40 | { .compatible = "ralink,rt2880-intc", .data = intc_of_init }, |
41 | {}, | 41 | {}, |
42 | }; | 42 | }; |
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 6cd3525d0e09..ee4fc0576c7d 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt | |||
@@ -18,6 +18,10 @@ Required Properties: | |||
18 | specific extensions. | 18 | specific extensions. |
19 | - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 | 19 | - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 |
20 | specific extensions. | 20 | specific extensions. |
21 | - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7 | ||
22 | specific extensions. | ||
23 | - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7 | ||
24 | specific extensions having an SMU. | ||
21 | 25 | ||
22 | * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface | 26 | * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface |
23 | unit (ciu) clock. This property is applicable only for Exynos5 SoC's and | 27 | unit (ciu) clock. This property is applicable only for Exynos5 SoC's and |
diff --git a/Documentation/devicetree/bindings/mmc/img-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/img-dw-mshc.txt new file mode 100644 index 000000000000..85de99fcaa2f --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/img-dw-mshc.txt | |||
@@ -0,0 +1,29 @@ | |||
1 | * Imagination specific extensions to the Synopsys Designware Mobile Storage | ||
2 | Host Controller | ||
3 | |||
4 | The Synopsys designware mobile storage host controller is used to interface | ||
5 | a SoC with storage medium such as eMMC or SD/MMC cards. This file documents | ||
6 | differences between the core Synopsys dw mshc controller properties described | ||
7 | by synopsys-dw-mshc.txt and the properties used by the Imagination specific | ||
8 | extensions to the Synopsys Designware Mobile Storage Host Controller. | ||
9 | |||
10 | Required Properties: | ||
11 | |||
12 | * compatible: should be | ||
13 | - "img,pistachio-dw-mshc": for Pistachio SoCs | ||
14 | |||
15 | Example: | ||
16 | |||
17 | mmc@18142000 { | ||
18 | compatible = "img,pistachio-dw-mshc"; | ||
19 | reg = <0x18142000 0x400>; | ||
20 | interrupts = <GIC_SHARED 39 IRQ_TYPE_LEVEL_HIGH>; | ||
21 | |||
22 | clocks = <&system_clk>, <&sdhost_clk>; | ||
23 | clock-names = "biu", "ciu"; | ||
24 | |||
25 | fifo-depth = <0x20>; | ||
26 | bus-width = <4>; | ||
27 | num-slots = <1>; | ||
28 | disable-wp; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt index 431716e37a39..b52628b18a53 100644 --- a/Documentation/devicetree/bindings/mmc/mmc.txt +++ b/Documentation/devicetree/bindings/mmc/mmc.txt | |||
@@ -40,6 +40,8 @@ Optional properties: | |||
40 | - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported | 40 | - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported |
41 | - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported | 41 | - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported |
42 | - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported | 42 | - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported |
43 | - dsr: Value the card's (optional) Driver Stage Register (DSR) should be | ||
44 | programmed with. Valid range: [0 .. 0xffff]. | ||
43 | 45 | ||
44 | *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line | 46 | *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line |
45 | polarity properties, we have to fix the meaning of the "normal" and "inverted" | 47 | polarity properties, we have to fix the meaning of the "normal" and "inverted" |
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index c559f3f36309..c327c2d6f23d 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | |||
@@ -10,12 +10,14 @@ extensions to the Synopsys Designware Mobile Storage Host Controller. | |||
10 | Required Properties: | 10 | Required Properties: |
11 | 11 | ||
12 | * compatible: should be | 12 | * compatible: should be |
13 | - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following | 13 | - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, |
14 | before RK3288 | ||
15 | - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 | ||
14 | 16 | ||
15 | Example: | 17 | Example: |
16 | 18 | ||
17 | rkdwmmc0@12200000 { | 19 | rkdwmmc0@12200000 { |
18 | compatible = "rockchip,rk2928-dw-mshc"; | 20 | compatible = "rockchip,rk3288-dw-mshc"; |
19 | reg = <0x12200000 0x1000>; | 21 | reg = <0x12200000 0x1000>; |
20 | interrupts = <0 75 0>; | 22 | interrupts = <0 75 0>; |
21 | #address-cells = <1>; | 23 | #address-cells = <1>; |
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt index 86223c3eda90..4dd6deb90719 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt | |||
@@ -12,6 +12,10 @@ Required properties: | |||
12 | * for "marvell,armada-380-sdhci", two register areas. The first one | 12 | * for "marvell,armada-380-sdhci", two register areas. The first one |
13 | for the SDHCI registers themselves, and the second one for the | 13 | for the SDHCI registers themselves, and the second one for the |
14 | AXI/Mbus bridge registers of the SDHCI unit. | 14 | AXI/Mbus bridge registers of the SDHCI unit. |
15 | - clocks: Array of clocks required for SDHCI; requires at least one for | ||
16 | I/O clock. | ||
17 | - clock-names: Array of names corresponding to clocks property; shall be | ||
18 | "io" for I/O clock and "core" for optional core clock. | ||
15 | 19 | ||
16 | Optional properties: | 20 | Optional properties: |
17 | - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. | 21 | - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning. |
@@ -23,6 +27,8 @@ sdhci@d4280800 { | |||
23 | reg = <0xd4280800 0x800>; | 27 | reg = <0xd4280800 0x800>; |
24 | bus-width = <8>; | 28 | bus-width = <8>; |
25 | interrupts = <27>; | 29 | interrupts = <27>; |
30 | clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; | ||
31 | clock-names = "io", "core"; | ||
26 | non-removable; | 32 | non-removable; |
27 | mrvl,clk-delay-cycles = <31>; | 33 | mrvl,clk-delay-cycles = <31>; |
28 | }; | 34 | }; |
@@ -32,5 +38,6 @@ sdhci@d8000 { | |||
32 | reg = <0xd8000 0x1000>, <0xdc000 0x100>; | 38 | reg = <0xd8000 0x1000>, <0xdc000 0x100>; |
33 | interrupts = <0 25 0x4>; | 39 | interrupts = <0 25 0x4>; |
34 | clocks = <&gateclk 17>; | 40 | clocks = <&gateclk 17>; |
41 | clock-names = "io"; | ||
35 | mrvl,clk-delay-cycles = <0x1F>; | 42 | mrvl,clk-delay-cycles = <0x1F>; |
36 | }; | 43 | }; |
diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt index fa0f327cde01..400b640fabc7 100644 --- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt +++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt | |||
@@ -19,6 +19,9 @@ Required properties: | |||
19 | "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC | 19 | "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC |
20 | "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC | 20 | "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC |
21 | "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC | 21 | "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC |
22 | "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC | ||
23 | "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC | ||
24 | "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC | ||
22 | 25 | ||
23 | Optional properties: | 26 | Optional properties: |
24 | - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable | 27 | - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable |
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt index c4728839d0c1..1fe6dde98499 100644 --- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt +++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt | |||
@@ -5,7 +5,9 @@ Required properties: | |||
5 | - reg : should specify localbus address and size used for the chip, | 5 | - reg : should specify localbus address and size used for the chip, |
6 | and hardware ECC controller if available. | 6 | and hardware ECC controller if available. |
7 | If the hardware ECC is PMECC, it should contain address and size for | 7 | If the hardware ECC is PMECC, it should contain address and size for |
8 | PMECC, PMECC Error Location controller and ROM which has lookup tables. | 8 | PMECC and PMECC Error Location controller. |
9 | The PMECC lookup table address and size in ROM is optional. If not | ||
10 | specified, driver will build it in runtime. | ||
9 | - atmel,nand-addr-offset : offset for the address latch. | 11 | - atmel,nand-addr-offset : offset for the address latch. |
10 | - atmel,nand-cmd-offset : offset for the command latch. | 12 | - atmel,nand-cmd-offset : offset for the command latch. |
11 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | 13 | - #address-cells, #size-cells : Must be present if the device has sub-nodes |
@@ -27,7 +29,7 @@ Optional properties: | |||
27 | are: 512, 1024. | 29 | are: 512, 1024. |
28 | - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM | 30 | - atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM |
29 | for different sector size. First one is for sector size 512, the next is for | 31 | for different sector size. First one is for sector size 512, the next is for |
30 | sector size 1024. | 32 | sector size 1024. If not specified, driver will build the table in runtime. |
31 | - nand-bus-width : 8 or 16 bus width if not present 8 | 33 | - nand-bus-width : 8 or 16 bus width if not present 8 |
32 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false | 34 | - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false |
33 | - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash | 35 | - Nand Flash Controller(NFC) is a slave driver under Atmel nand flash |
@@ -36,6 +38,7 @@ Optional properties: | |||
36 | - reg : should specify the address and size used for NFC command registers, | 38 | - reg : should specify the address and size used for NFC command registers, |
37 | NFC registers and NFC Sram. NFC Sram address and size can be absent | 39 | NFC registers and NFC Sram. NFC Sram address and size can be absent |
38 | if don't want to use it. | 40 | if don't want to use it. |
41 | - clocks: phandle to the peripheral clock | ||
39 | - Optional properties: | 42 | - Optional properties: |
40 | - atmel,write-by-sram: boolean to enable NFC write by sram. | 43 | - atmel,write-by-sram: boolean to enable NFC write by sram. |
41 | 44 | ||
@@ -98,6 +101,7 @@ nand0: nand@40000000 { | |||
98 | compatible = "atmel,sama5d3-nfc"; | 101 | compatible = "atmel,sama5d3-nfc"; |
99 | #address-cells = <1>; | 102 | #address-cells = <1>; |
100 | #size-cells = <1>; | 103 | #size-cells = <1>; |
104 | clocks = <&hsmc_clk> | ||
101 | reg = < | 105 | reg = < |
102 | 0x70000000 0x10000000 /* NFC Command Registers */ | 106 | 0x70000000 0x10000000 /* NFC Command Registers */ |
103 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | 107 | 0xffffc000 0x00000070 /* NFC HSMC regs */ |
diff --git a/Documentation/devicetree/bindings/mtd/diskonchip.txt b/Documentation/devicetree/bindings/mtd/diskonchip.txt new file mode 100644 index 000000000000..3e13bfdbea5b --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/diskonchip.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | M-Systems and Sandisk DiskOnChip devices | ||
2 | |||
3 | M-System DiskOnChip G3 | ||
4 | ====================== | ||
5 | The Sandisk (formerly M-Systems) docg3 is a nand device of 64M to 256MB. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: should be "m-systems,diskonchip-g3" | ||
9 | - reg: register base and size | ||
10 | |||
11 | Example: | ||
12 | docg3: flash@0 { | ||
13 | compatible = "m-systems,diskonchip-g3"; | ||
14 | reg = <0x0 0x2000>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt index 36ef07d3c90f..af8915b41ccf 100644 --- a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt | |||
@@ -11,8 +11,8 @@ Required properties: | |||
11 | are made in native endianness. | 11 | are made in native endianness. |
12 | - #address-cells, #size-cells : Must be present if the device has sub-nodes | 12 | - #address-cells, #size-cells : Must be present if the device has sub-nodes |
13 | representing partitions. | 13 | representing partitions. |
14 | - gpios : specifies the gpio pins to control the NAND device. nwp is an | 14 | - gpios : Specifies the GPIO pins to control the NAND device. The order of |
15 | optional gpio and may be set to 0 if not present. | 15 | GPIO references is: RDY, nCE, ALE, CLE, and an optional nWP. |
16 | 16 | ||
17 | Optional properties: | 17 | Optional properties: |
18 | - bank-width : Width (in bytes) of the device. If not present, the width | 18 | - bank-width : Width (in bytes) of the device. If not present, the width |
@@ -35,11 +35,11 @@ gpio-nand@1,0 { | |||
35 | reg = <1 0x0000 0x2>; | 35 | reg = <1 0x0000 0x2>; |
36 | #address-cells = <1>; | 36 | #address-cells = <1>; |
37 | #size-cells = <1>; | 37 | #size-cells = <1>; |
38 | gpios = <&banka 1 0 /* rdy */ | 38 | gpios = <&banka 1 0>, /* RDY */ |
39 | &banka 2 0 /* nce */ | 39 | <&banka 2 0>, /* nCE */ |
40 | &banka 3 0 /* ale */ | 40 | <&banka 3 0>, /* ALE */ |
41 | &banka 4 0 /* cle */ | 41 | <&banka 4 0>, /* CLE */ |
42 | 0 /* nwp */>; | 42 | <0>; /* nWP */ |
43 | 43 | ||
44 | partition@0 { | 44 | partition@0 { |
45 | ... | 45 | ... |
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt index ee654e95d8ad..fb733c4e1c11 100644 --- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt | |||
@@ -110,8 +110,8 @@ on various other factors also like; | |||
110 | Other factor which governs the selection of ecc-scheme is oob-size. | 110 | Other factor which governs the selection of ecc-scheme is oob-size. |
111 | Higher ECC schemes require more OOB/Spare area to store ECC syndrome, | 111 | Higher ECC schemes require more OOB/Spare area to store ECC syndrome, |
112 | so the device should have enough free bytes available its OOB/Spare | 112 | so the device should have enough free bytes available its OOB/Spare |
113 | area to accomodate ECC for entire page. In general following expression | 113 | area to accommodate ECC for entire page. In general following expression |
114 | helps in determining if given device can accomodate ECC syndrome: | 114 | helps in determining if given device can accommodate ECC syndrome: |
115 | "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE" | 115 | "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE" |
116 | where | 116 | where |
117 | OOBSIZE number of bytes in OOB/spare area | 117 | OOBSIZE number of bytes in OOB/spare area |
@@ -133,5 +133,5 @@ on various other factors also like; | |||
133 | Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and | 133 | Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and |
134 | trying to use BCH16 (ECC_BYTES=26) ecc-scheme. | 134 | trying to use BCH16 (ECC_BYTES=26) ecc-scheme. |
135 | Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B | 135 | Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B |
136 | which can be accomodate in the OOB/Spare area of this device | 136 | which can be accommodated in the OOB/Spare area of this device |
137 | (OOBSIZE=128). So this device can use BCH16 ecc-scheme. | 137 | (OOBSIZE=128). So this device can use BCH16 ecc-scheme. |
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt index 61c5ec850f2f..6b9f680cb579 100644 --- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt +++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt | |||
@@ -4,8 +4,8 @@ Flash chips (Memory Technology Devices) are often used for solid state | |||
4 | file systems on embedded devices. | 4 | file systems on embedded devices. |
5 | 5 | ||
6 | - compatible : should contain the specific model of mtd chip(s) | 6 | - compatible : should contain the specific model of mtd chip(s) |
7 | used, if known, followed by either "cfi-flash", "jedec-flash" | 7 | used, if known, followed by either "cfi-flash", "jedec-flash", |
8 | or "mtd-ram". | 8 | "mtd-ram" or "mtd-rom". |
9 | - reg : Address range(s) of the mtd chip(s) | 9 | - reg : Address range(s) of the mtd chip(s) |
10 | It's possible to (optionally) define multiple "reg" tuples so that | 10 | It's possible to (optionally) define multiple "reg" tuples so that |
11 | non-identical chips can be described in one node. | 11 | non-identical chips can be described in one node. |
diff --git a/Documentation/devicetree/bindings/mtd/sunxi-nand.txt b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt new file mode 100644 index 000000000000..0273adb8638c --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/sunxi-nand.txt | |||
@@ -0,0 +1,45 @@ | |||
1 | Allwinner NAND Flash Controller (NFC) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "allwinner,sun4i-a10-nand". | ||
5 | - reg : shall contain registers location and length for data and reg. | ||
6 | - interrupts : shall define the nand controller interrupt. | ||
7 | - #address-cells: shall be set to 1. Encode the nand CS. | ||
8 | - #size-cells : shall be set to 0. | ||
9 | - clocks : shall reference nand controller clocks. | ||
10 | - clock-names : nand controller internal clock names. Shall contain : | ||
11 | * "ahb" : AHB gating clock | ||
12 | * "mod" : nand controller clock | ||
13 | |||
14 | Optional children nodes: | ||
15 | Children nodes represent the available nand chips. | ||
16 | |||
17 | Optional properties: | ||
18 | - allwinner,rb : shall contain the native Ready/Busy ids. | ||
19 | or | ||
20 | - rb-gpios : shall contain the gpios used as R/B pins. | ||
21 | - nand-ecc-mode : one of the supported ECC modes ("hw", "hw_syndrome", "soft", | ||
22 | "soft_bch" or "none") | ||
23 | |||
24 | see Documentation/devicetree/mtd/nand.txt for generic bindings. | ||
25 | |||
26 | |||
27 | Examples: | ||
28 | nfc: nand@01c03000 { | ||
29 | compatible = "allwinner,sun4i-a10-nand"; | ||
30 | reg = <0x01c03000 0x1000>; | ||
31 | interrupts = <0 37 1>; | ||
32 | clocks = <&ahb_gates 13>, <&nand_clk>; | ||
33 | clock-names = "ahb", "mod"; | ||
34 | #address-cells = <1>; | ||
35 | #size-cells = <0>; | ||
36 | pinctrl-names = "default"; | ||
37 | pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; | ||
38 | status = "okay"; | ||
39 | |||
40 | nand@0 { | ||
41 | reg = <0>; | ||
42 | allwinner,rb = <0>; | ||
43 | nand-ecc-mode = "soft_bch"; | ||
44 | }; | ||
45 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/amd-xgbe.txt b/Documentation/devicetree/bindings/net/amd-xgbe.txt index 41354f730beb..26efd526d16c 100644 --- a/Documentation/devicetree/bindings/net/amd-xgbe.txt +++ b/Documentation/devicetree/bindings/net/amd-xgbe.txt | |||
@@ -7,7 +7,10 @@ Required properties: | |||
7 | - PCS registers | 7 | - PCS registers |
8 | - interrupt-parent: Should be the phandle for the interrupt controller | 8 | - interrupt-parent: Should be the phandle for the interrupt controller |
9 | that services interrupts for this device | 9 | that services interrupts for this device |
10 | - interrupts: Should contain the amd-xgbe interrupt | 10 | - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt |
11 | listed is required and is the general device interrupt. If the optional | ||
12 | amd,per-channel-interrupt property is specified, then one additional | ||
13 | interrupt for each DMA channel supported by the device should be specified | ||
11 | - clocks: | 14 | - clocks: |
12 | - DMA clock for the amd-xgbe device (used for calculating the | 15 | - DMA clock for the amd-xgbe device (used for calculating the |
13 | correct Rx interrupt watchdog timer value on a DMA channel | 16 | correct Rx interrupt watchdog timer value on a DMA channel |
@@ -23,6 +26,9 @@ Optional properties: | |||
23 | - mac-address: mac address to be assigned to the device. Can be overridden | 26 | - mac-address: mac address to be assigned to the device. Can be overridden |
24 | by UEFI. | 27 | by UEFI. |
25 | - dma-coherent: Present if dma operations are coherent | 28 | - dma-coherent: Present if dma operations are coherent |
29 | - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate | ||
30 | a unique interrupt for each DMA channel - this requires an additional | ||
31 | interrupt be configured for each DMA channel | ||
26 | 32 | ||
27 | Example: | 33 | Example: |
28 | xgbe@e0700000 { | 34 | xgbe@e0700000 { |
@@ -30,7 +36,9 @@ Example: | |||
30 | reg = <0 0xe0700000 0 0x80000>, | 36 | reg = <0 0xe0700000 0 0x80000>, |
31 | <0 0xe0780000 0 0x80000>; | 37 | <0 0xe0780000 0 0x80000>; |
32 | interrupt-parent = <&gic>; | 38 | interrupt-parent = <&gic>; |
33 | interrupts = <0 325 4>; | 39 | interrupts = <0 325 4>, |
40 | <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>; | ||
41 | amd,per-channel-interrupt; | ||
34 | clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; | 42 | clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>; |
35 | clock-names = "dma_clk", "ptp_clk"; | 43 | clock-names = "dma_clk", "ptp_clk"; |
36 | phy-handle = <&phy>; | 44 | phy-handle = <&phy>; |
diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt index ebcad25efd0a..cfcc52705ed8 100644 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt | |||
@@ -3,7 +3,7 @@ APM X-Gene SoC Ethernet nodes | |||
3 | Ethernet nodes are defined to describe on-chip ethernet interfaces in | 3 | Ethernet nodes are defined to describe on-chip ethernet interfaces in |
4 | APM X-Gene SoC. | 4 | APM X-Gene SoC. |
5 | 5 | ||
6 | Required properties: | 6 | Required properties for all the ethernet interfaces: |
7 | - compatible: Should be "apm,xgene-enet" | 7 | - compatible: Should be "apm,xgene-enet" |
8 | - reg: Address and length of the register set for the device. It contains the | 8 | - reg: Address and length of the register set for the device. It contains the |
9 | information of registers in the same order as described by reg-names | 9 | information of registers in the same order as described by reg-names |
@@ -15,6 +15,8 @@ Required properties: | |||
15 | - clocks: Reference to the clock entry. | 15 | - clocks: Reference to the clock entry. |
16 | - local-mac-address: MAC address assigned to this device | 16 | - local-mac-address: MAC address assigned to this device |
17 | - phy-connection-type: Interface type between ethernet device and PHY device | 17 | - phy-connection-type: Interface type between ethernet device and PHY device |
18 | |||
19 | Required properties for ethernet interfaces that have external PHY: | ||
18 | - phy-handle: Reference to a PHY node connected to this device | 20 | - phy-handle: Reference to a PHY node connected to this device |
19 | 21 | ||
20 | - mdio: Device tree subnode with the following required properties: | 22 | - mdio: Device tree subnode with the following required properties: |
diff --git a/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt b/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt new file mode 100644 index 000000000000..ab0bb4247d14 --- /dev/null +++ b/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | * Broadcom UniMAC MDIO bus controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2", | ||
5 | "brcm,genet-mdio-v3", "brcm,genet-mdio-v4" or "brcm,unimac-mdio" | ||
6 | - reg: address and length of the regsiter set for the device, first one is the | ||
7 | base register, and the second one is optional and for indirect accesses to | ||
8 | larger than 16-bits MDIO transactions | ||
9 | - reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw" | ||
10 | - #size-cells: must be 1 | ||
11 | - #address-cells: must be 0 | ||
12 | |||
13 | Optional properties: | ||
14 | - interrupts: must be one if the interrupt is shared with the Ethernet MAC or | ||
15 | Ethernet switch this MDIO block is integrated from, or must be two, if there | ||
16 | are two separate interrupts, first one must be "mdio done" and second must be | ||
17 | for "mdio error" | ||
18 | - interrupt-names: must be "mdio_done_error" when there is a share interrupt fed | ||
19 | to this hardware block, or must be "mdio_done" for the first interrupt and | ||
20 | "mdio_error" for the second when there are separate interrupts | ||
21 | |||
22 | Child nodes of this MDIO bus controller node are standard Ethernet PHY device | ||
23 | nodes as described in Documentation/devicetree/bindings/net/phy.txt | ||
24 | |||
25 | Example: | ||
26 | |||
27 | mdio@403c0 { | ||
28 | compatible = "brcm,unimac-mdio"; | ||
29 | reg = <0x403c0 0x8 0x40300 0x18>; | ||
30 | reg-names = "mdio", "mdio_indir_rw"; | ||
31 | #size-cells = <1>; | ||
32 | #address-cells = <0>; | ||
33 | |||
34 | ... | ||
35 | phy@0 { | ||
36 | compatible = "ethernet-phy-ieee802.3-c22"; | ||
37 | reg = <0>; | ||
38 | }; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/broadcom-sf2.txt b/Documentation/devicetree/bindings/net/broadcom-sf2.txt new file mode 100644 index 000000000000..30d487597ecb --- /dev/null +++ b/Documentation/devicetree/bindings/net/broadcom-sf2.txt | |||
@@ -0,0 +1,78 @@ | |||
1 | * Broadcom Starfighter 2 integrated swich | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: should be "brcm,bcm7445-switch-v4.0" | ||
6 | - reg: addresses and length of the register sets for the device, must be 6 | ||
7 | pairs of register addresses and lengths | ||
8 | - interrupts: interrupts for the devices, must be two interrupts | ||
9 | - dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt | ||
10 | - dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt | ||
11 | - #size-cells: must be 0 | ||
12 | - #address-cells: must be 2, see dsa/dsa.txt | ||
13 | |||
14 | Subnodes: | ||
15 | |||
16 | The integrated switch subnode should be specified according to the binding | ||
17 | described in dsa/dsa.txt. | ||
18 | |||
19 | Optional properties: | ||
20 | |||
21 | - reg-names: litteral names for the device base register addresses, when present | ||
22 | must be: "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" | ||
23 | |||
24 | - interrupt-names: litternal names for the device interrupt lines, when present | ||
25 | must be: "switch_0" and "switch_1" | ||
26 | |||
27 | - brcm,num-gphy: specify the maximum number of integrated gigabit PHYs in the | ||
28 | switch | ||
29 | |||
30 | - brcm,num-rgmii-ports: specify the maximum number of RGMII interfaces supported | ||
31 | by the switch | ||
32 | |||
33 | - brcm,fcb-pause-override: boolean property, if present indicates that the switch | ||
34 | supports Failover Control Block pause override capability | ||
35 | |||
36 | - brcm,acb-packets-inflight: boolean property, if present indicates that the switch | ||
37 | Admission Control Block supports reporting the number of packets in-flight in a | ||
38 | switch queue | ||
39 | |||
40 | Example: | ||
41 | |||
42 | switch_top@f0b00000 { | ||
43 | compatible = "simple-bus"; | ||
44 | #size-cells = <1>; | ||
45 | #address-cells = <1>; | ||
46 | ranges = <0 0xf0b00000 0x40804>; | ||
47 | |||
48 | ethernet_switch@0 { | ||
49 | compatible = "brcm,bcm7445-switch-v4.0"; | ||
50 | #size-cells = <0>; | ||
51 | #address-cells = <2>; | ||
52 | reg = <0x0 0x40000 | ||
53 | 0x40000 0x110 | ||
54 | 0x40340 0x30 | ||
55 | 0x40380 0x30 | ||
56 | 0x40400 0x34 | ||
57 | 0x40600 0x208>; | ||
58 | interrupts = <0 0x18 0 | ||
59 | 0 0x19 0>; | ||
60 | brcm,num-gphy = <1>; | ||
61 | brcm,num-rgmii-ports = <2>; | ||
62 | brcm,fcb-pause-override; | ||
63 | brcm,acb-packets-inflight; | ||
64 | |||
65 | ... | ||
66 | switch@0 { | ||
67 | reg = <0 0>; | ||
68 | #size-cells = <0>; | ||
69 | #address-cells <1>; | ||
70 | |||
71 | port@0 { | ||
72 | label = "gphy"; | ||
73 | reg = <0>; | ||
74 | }; | ||
75 | ... | ||
76 | }; | ||
77 | }; | ||
78 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt index 8f1ae81228e3..5a1d8b0c39e9 100644 --- a/Documentation/devicetree/bindings/net/can/c_can.txt +++ b/Documentation/devicetree/bindings/net/can/c_can.txt | |||
@@ -4,6 +4,8 @@ Bosch C_CAN/D_CAN controller Device Tree Bindings | |||
4 | Required properties: | 4 | Required properties: |
5 | - compatible : Should be "bosch,c_can" for C_CAN controllers and | 5 | - compatible : Should be "bosch,c_can" for C_CAN controllers and |
6 | "bosch,d_can" for D_CAN controllers. | 6 | "bosch,d_can" for D_CAN controllers. |
7 | Can be "ti,dra7-d_can", "ti,am3352-d_can" or | ||
8 | "ti,am4372-d_can". | ||
7 | - reg : physical base address and size of the C_CAN/D_CAN | 9 | - reg : physical base address and size of the C_CAN/D_CAN |
8 | registers map | 10 | registers map |
9 | - interrupts : property with a value describing the interrupt | 11 | - interrupts : property with a value describing the interrupt |
@@ -12,6 +14,9 @@ Required properties: | |||
12 | Optional properties: | 14 | Optional properties: |
13 | - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the | 15 | - ti,hwmods : Must be "d_can<n>" or "c_can<n>", n being the |
14 | instance number | 16 | instance number |
17 | - syscon-raminit : Handle to system control region that contains the | ||
18 | RAMINIT register, register offset to the RAMINIT | ||
19 | register and the CAN instance number (0 offset). | ||
15 | 20 | ||
16 | Note: "ti,hwmods" field is used to fetch the base address and irq | 21 | Note: "ti,hwmods" field is used to fetch the base address and irq |
17 | resources from TI, omap hwmod data base during device registration. | 22 | resources from TI, omap hwmod data base during device registration. |
diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt new file mode 100644 index 000000000000..9e331777c203 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/m_can.txt | |||
@@ -0,0 +1,67 @@ | |||
1 | Bosch MCAN controller Device Tree Bindings | ||
2 | ------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : Should be "bosch,m_can" for M_CAN controllers | ||
6 | - reg : physical base address and size of the M_CAN | ||
7 | registers map and Message RAM | ||
8 | - reg-names : Should be "m_can" and "message_ram" | ||
9 | - interrupts : Should be the interrupt number of M_CAN interrupt | ||
10 | line 0 and line 1, could be same if sharing | ||
11 | the same interrupt. | ||
12 | - interrupt-names : Should contain "int0" and "int1" | ||
13 | - clocks : Clocks used by controller, should be host clock | ||
14 | and CAN clock. | ||
15 | - clock-names : Should contain "hclk" and "cclk" | ||
16 | - pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt | ||
17 | - pinctrl-names : Names corresponding to the numbered pinctrl states | ||
18 | - bosch,mram-cfg : Message RAM configuration data. | ||
19 | Multiple M_CAN instances can share the same Message | ||
20 | RAM and each element(e.g Rx FIFO or Tx Buffer and etc) | ||
21 | number in Message RAM is also configurable, | ||
22 | so this property is telling driver how the shared or | ||
23 | private Message RAM are used by this M_CAN controller. | ||
24 | |||
25 | The format should be as follows: | ||
26 | <offset sidf_elems xidf_elems rxf0_elems rxf1_elems | ||
27 | rxb_elems txe_elems txb_elems> | ||
28 | The 'offset' is an address offset of the Message RAM | ||
29 | where the following elements start from. This is | ||
30 | usually set to 0x0 if you're using a private Message | ||
31 | RAM. The remain cells are used to specify how many | ||
32 | elements are used for each FIFO/Buffer. | ||
33 | |||
34 | M_CAN includes the following elements according to user manual: | ||
35 | 11-bit Filter 0-128 elements / 0-128 words | ||
36 | 29-bit Filter 0-64 elements / 0-128 words | ||
37 | Rx FIFO 0 0-64 elements / 0-1152 words | ||
38 | Rx FIFO 1 0-64 elements / 0-1152 words | ||
39 | Rx Buffers 0-64 elements / 0-1152 words | ||
40 | Tx Event FIFO 0-32 elements / 0-64 words | ||
41 | Tx Buffers 0-32 elements / 0-576 words | ||
42 | |||
43 | Please refer to 2.4.1 Message RAM Configuration in | ||
44 | Bosch M_CAN user manual for details. | ||
45 | |||
46 | Example: | ||
47 | SoC dtsi: | ||
48 | m_can1: can@020e8000 { | ||
49 | compatible = "bosch,m_can"; | ||
50 | reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; | ||
51 | reg-names = "m_can", "message_ram"; | ||
52 | interrupts = <0 114 0x04>, | ||
53 | <0 114 0x04>; | ||
54 | interrupt-names = "int0", "int1"; | ||
55 | clocks = <&clks IMX6SX_CLK_CANFD>, | ||
56 | <&clks IMX6SX_CLK_CANFD>; | ||
57 | clock-names = "hclk", "cclk"; | ||
58 | bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; | ||
59 | status = "disabled"; | ||
60 | }; | ||
61 | |||
62 | Board dts: | ||
63 | &m_can1 { | ||
64 | pinctrl-names = "default"; | ||
65 | pinctrl-0 = <&pinctrl_m_can1>; | ||
66 | status = "enabled"; | ||
67 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt new file mode 100644 index 000000000000..002d8440bf66 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt | |||
@@ -0,0 +1,43 @@ | |||
1 | Renesas R-Car CAN controller Device Tree Bindings | ||
2 | ------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC. | ||
6 | "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC. | ||
7 | "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC. | ||
8 | "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC. | ||
9 | - reg: physical base address and size of the R-Car CAN register map. | ||
10 | - interrupts: interrupt specifier for the sole interrupt. | ||
11 | - clocks: phandles and clock specifiers for 3 CAN clock inputs. | ||
12 | - clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk". | ||
13 | - pinctrl-0: pin control group to be used for this controller. | ||
14 | - pinctrl-names: must be "default". | ||
15 | |||
16 | Optional properties: | ||
17 | - renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: | ||
18 | <0x0> (default) : Peripheral clock (clkp1) | ||
19 | <0x1> : Peripheral clock (clkp2) | ||
20 | <0x3> : Externally input clock | ||
21 | |||
22 | Example | ||
23 | ------- | ||
24 | |||
25 | SoC common .dtsi file: | ||
26 | |||
27 | can0: can@e6e80000 { | ||
28 | compatible = "renesas,can-r8a7791"; | ||
29 | reg = <0 0xe6e80000 0 0x1000>; | ||
30 | interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; | ||
31 | clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, | ||
32 | <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; | ||
33 | clock-names = "clkp1", "clkp2", "can_clk"; | ||
34 | status = "disabled"; | ||
35 | }; | ||
36 | |||
37 | Board specific .dts file: | ||
38 | |||
39 | &can0 { | ||
40 | pinctrl-0 = <&can0_pins>; | ||
41 | pinctrl-names = "default"; | ||
42 | status = "okay"; | ||
43 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt index ae2b8b7f9c38..33fe8462edf4 100644 --- a/Documentation/devicetree/bindings/net/cpsw.txt +++ b/Documentation/devicetree/bindings/net/cpsw.txt | |||
@@ -24,15 +24,17 @@ Optional properties: | |||
24 | - ti,hwmods : Must be "cpgmac0" | 24 | - ti,hwmods : Must be "cpgmac0" |
25 | - no_bd_ram : Must be 0 or 1 | 25 | - no_bd_ram : Must be 0 or 1 |
26 | - dual_emac : Specifies Switch to act as Dual EMAC | 26 | - dual_emac : Specifies Switch to act as Dual EMAC |
27 | - syscon : Phandle to the system control device node, which is | ||
28 | the control module device of the am33x | ||
27 | 29 | ||
28 | Slave Properties: | 30 | Slave Properties: |
29 | Required properties: | 31 | Required properties: |
30 | - phy_id : Specifies slave phy id | 32 | - phy_id : Specifies slave phy id |
31 | - phy-mode : See ethernet.txt file in the same directory | 33 | - phy-mode : See ethernet.txt file in the same directory |
32 | - mac-address : See ethernet.txt file in the same directory | ||
33 | 34 | ||
34 | Optional properties: | 35 | Optional properties: |
35 | - dual_emac_res_vlan : Specifies VID to be used to segregate the ports | 36 | - dual_emac_res_vlan : Specifies VID to be used to segregate the ports |
37 | - mac-address : See ethernet.txt file in the same directory | ||
36 | 38 | ||
37 | Note: "ti,hwmods" field is used to fetch the base address and irq | 39 | Note: "ti,hwmods" field is used to fetch the base address and irq |
38 | resources from TI, omap hwmod data base during device registration. | 40 | resources from TI, omap hwmod data base during device registration. |
@@ -57,6 +59,7 @@ Examples: | |||
57 | active_slave = <0>; | 59 | active_slave = <0>; |
58 | cpts_clock_mult = <0x80000000>; | 60 | cpts_clock_mult = <0x80000000>; |
59 | cpts_clock_shift = <29>; | 61 | cpts_clock_shift = <29>; |
62 | syscon = <&cm>; | ||
60 | cpsw_emac0: slave@0 { | 63 | cpsw_emac0: slave@0 { |
61 | phy_id = <&davinci_mdio>, <0>; | 64 | phy_id = <&davinci_mdio>, <0>; |
62 | phy-mode = "rgmii-txid"; | 65 | phy-mode = "rgmii-txid"; |
@@ -85,6 +88,7 @@ Examples: | |||
85 | active_slave = <0>; | 88 | active_slave = <0>; |
86 | cpts_clock_mult = <0x80000000>; | 89 | cpts_clock_mult = <0x80000000>; |
87 | cpts_clock_shift = <29>; | 90 | cpts_clock_shift = <29>; |
91 | syscon = <&cm>; | ||
88 | cpsw_emac0: slave@0 { | 92 | cpsw_emac0: slave@0 { |
89 | phy_id = <&davinci_mdio>, <0>; | 93 | phy_id = <&davinci_mdio>, <0>; |
90 | phy-mode = "rgmii-txid"; | 94 | phy-mode = "rgmii-txid"; |
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt index 49f4f7ae3f51..e124847443f8 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.txt +++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt | |||
@@ -10,7 +10,7 @@ Required properties: | |||
10 | - dsa,ethernet : Should be a phandle to a valid Ethernet device node | 10 | - dsa,ethernet : Should be a phandle to a valid Ethernet device node |
11 | - dsa,mii-bus : Should be a phandle to a valid MDIO bus device node | 11 | - dsa,mii-bus : Should be a phandle to a valid MDIO bus device node |
12 | 12 | ||
13 | Optionnal properties: | 13 | Optional properties: |
14 | - interrupts : property with a value describing the switch | 14 | - interrupts : property with a value describing the switch |
15 | interrupt number (not supported by the driver) | 15 | interrupt number (not supported by the driver) |
16 | 16 | ||
@@ -23,6 +23,13 @@ Each of these switch child nodes should have the following required properties: | |||
23 | - #address-cells : Must be 1 | 23 | - #address-cells : Must be 1 |
24 | - #size-cells : Must be 0 | 24 | - #size-cells : Must be 0 |
25 | 25 | ||
26 | A switch child node has the following optional property: | ||
27 | |||
28 | - eeprom-length : Set to the length of an EEPROM connected to the | ||
29 | switch. Must be set if the switch can not detect | ||
30 | the presence and/or size of a connected EEPROM, | ||
31 | otherwise optional. | ||
32 | |||
26 | A switch may have multiple "port" children nodes | 33 | A switch may have multiple "port" children nodes |
27 | 34 | ||
28 | Each port children node must have the following mandatory properties: | 35 | Each port children node must have the following mandatory properties: |
@@ -39,6 +46,22 @@ Optionnal property: | |||
39 | This property is only used when switches are being | 46 | This property is only used when switches are being |
40 | chained/cascaded together. | 47 | chained/cascaded together. |
41 | 48 | ||
49 | - phy-handle : Phandle to a PHY on an external MDIO bus, not the | ||
50 | switch internal one. See | ||
51 | Documentation/devicetree/bindings/net/ethernet.txt | ||
52 | for details. | ||
53 | |||
54 | - phy-mode : String representing the connection to the designated | ||
55 | PHY node specified by the 'phy-handle' property. See | ||
56 | Documentation/devicetree/bindings/net/ethernet.txt | ||
57 | for details. | ||
58 | |||
59 | Optional subnodes: | ||
60 | - fixed-link : Fixed-link subnode describing a link to a non-MDIO | ||
61 | managed entity. See | ||
62 | Documentation/devicetree/bindings/net/fixed-link.txt | ||
63 | for details. | ||
64 | |||
42 | Example: | 65 | Example: |
43 | 66 | ||
44 | dsa@0 { | 67 | dsa@0 { |
@@ -58,6 +81,7 @@ Example: | |||
58 | port@0 { | 81 | port@0 { |
59 | reg = <0>; | 82 | reg = <0>; |
60 | label = "lan1"; | 83 | label = "lan1"; |
84 | phy-handle = <&phy0>; | ||
61 | }; | 85 | }; |
62 | 86 | ||
63 | port@1 { | 87 | port@1 { |
diff --git a/Documentation/devicetree/bindings/net/emac_rockchip.txt b/Documentation/devicetree/bindings/net/emac_rockchip.txt new file mode 100644 index 000000000000..8dc1c79fef7f --- /dev/null +++ b/Documentation/devicetree/bindings/net/emac_rockchip.txt | |||
@@ -0,0 +1,50 @@ | |||
1 | * ARC EMAC 10/100 Ethernet platform driver for Rockchip Rk3066/RK3188 SoCs | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "rockchip,rk3066-emac" or "rockchip,rk3188-emac" | ||
5 | according to the target SoC. | ||
6 | - reg: Address and length of the register set for the device | ||
7 | - interrupts: Should contain the EMAC interrupts | ||
8 | - rockchip,grf: phandle to the syscon grf used to control speed and mode | ||
9 | for emac. | ||
10 | - phy: see ethernet.txt file in the same directory. | ||
11 | - phy-mode: see ethernet.txt file in the same directory. | ||
12 | |||
13 | Optional properties: | ||
14 | - phy-supply: phandle to a regulator if the PHY needs one | ||
15 | |||
16 | Clock handling: | ||
17 | - clocks: Must contain an entry for each entry in clock-names. | ||
18 | - clock-names: Shall be "hclk" for the host clock needed to calculate and set | ||
19 | polling period of EMAC and "macref" for the reference clock needed to transfer | ||
20 | data to and from the phy. | ||
21 | |||
22 | Child nodes of the driver are the individual PHY devices connected to the | ||
23 | MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus. | ||
24 | |||
25 | Examples: | ||
26 | |||
27 | ethernet@10204000 { | ||
28 | compatible = "rockchip,rk3188-emac"; | ||
29 | reg = <0xc0fc2000 0x3c>; | ||
30 | interrupts = <6>; | ||
31 | mac-address = [ 00 11 22 33 44 55 ]; | ||
32 | |||
33 | clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; | ||
34 | clock-names = "hclk", "macref"; | ||
35 | |||
36 | pinctrl-names = "default"; | ||
37 | pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; | ||
38 | |||
39 | rockchip,grf = <&grf>; | ||
40 | |||
41 | phy = <&phy0>; | ||
42 | phy-mode = "rmii"; | ||
43 | phy-supply = <&vcc_rmii>; | ||
44 | |||
45 | #address-cells = <1>; | ||
46 | #size-cells = <0>; | ||
47 | phy0: ethernet-phy@0 { | ||
48 | reg = <1>; | ||
49 | }; | ||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 8a2c7b55ec16..0c8775c45798 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt | |||
@@ -16,6 +16,12 @@ Optional properties: | |||
16 | - phy-handle : phandle to the PHY device connected to this device. | 16 | - phy-handle : phandle to the PHY device connected to this device. |
17 | - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. | 17 | - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory. |
18 | Use instead of phy-handle. | 18 | Use instead of phy-handle. |
19 | - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports | ||
20 | hw multi queues. Should specify the tx queue number, otherwise set tx queue | ||
21 | number to 1. | ||
22 | - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports | ||
23 | hw multi queues. Should specify the rx queue number, otherwise set rx queue | ||
24 | number to 1. | ||
19 | 25 | ||
20 | Optional subnodes: | 26 | Optional subnodes: |
21 | - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes | 27 | - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes |
diff --git a/Documentation/devicetree/bindings/net/marvell-pxa168.txt b/Documentation/devicetree/bindings/net/marvell-pxa168.txt new file mode 100644 index 000000000000..845a148a346e --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell-pxa168.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | * Marvell PXA168 Ethernet Controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "marvell,pxa168-eth". | ||
5 | - reg: address and length of the register set for the device. | ||
6 | - interrupts: interrupt for the device. | ||
7 | - clocks: pointer to the clock for the device. | ||
8 | |||
9 | Optional properties: | ||
10 | - port-id: Ethernet port number. Should be '0','1' or '2'. | ||
11 | - #address-cells: must be 1 when using sub-nodes. | ||
12 | - #size-cells: must be 0 when using sub-nodes. | ||
13 | - phy-handle: see ethernet.txt file in the same directory. | ||
14 | - local-mac-address: see ethernet.txt file in the same directory. | ||
15 | |||
16 | Sub-nodes: | ||
17 | Each PHY can be represented as a sub-node. This is not mandatory. | ||
18 | |||
19 | Sub-nodes required properties: | ||
20 | - reg: the MDIO address of the PHY. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | eth0: ethernet@f7b90000 { | ||
25 | compatible = "marvell,pxa168-eth"; | ||
26 | reg = <0xf7b90000 0x10000>; | ||
27 | clocks = <&chip CLKID_GETH0>; | ||
28 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | ||
29 | #address-cells = <1>; | ||
30 | #size-cells = <0>; | ||
31 | phy-handle = <ðphy0>; | ||
32 | |||
33 | ethphy0: ethernet-phy@0 { | ||
34 | reg = <0>; | ||
35 | }; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt new file mode 100644 index 000000000000..ec633d74a8a8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | * Amlogic Meson DWMAC Ethernet controller | ||
2 | |||
3 | The device inherits all the properties of the dwmac/stmmac devices | ||
4 | described in the file net/stmmac.txt with the following changes. | ||
5 | |||
6 | Required properties: | ||
7 | |||
8 | - compatible: should be "amlogic,meson6-dwmac" along with "snps,dwmac" | ||
9 | and any applicable more detailed version number | ||
10 | described in net/stmmac.txt | ||
11 | |||
12 | - reg: should contain a register range for the dwmac controller and | ||
13 | another one for the Amlogic specific configuration | ||
14 | |||
15 | Example: | ||
16 | |||
17 | ethmac: ethernet@c9410000 { | ||
18 | compatible = "amlogic,meson6-dwmac", "snps,dwmac"; | ||
19 | reg = <0xc9410000 0x10000 | ||
20 | 0xc1108108 0x4>; | ||
21 | interrupts = <0 8 1>; | ||
22 | interrupt-names = "macirq"; | ||
23 | clocks = <&clk81>; | ||
24 | clock-names = "stmmaceth"; | ||
25 | } | ||
diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt index 98a3e61f9ee8..87496a8c64ab 100644 --- a/Documentation/devicetree/bindings/net/micrel.txt +++ b/Documentation/devicetree/bindings/net/micrel.txt | |||
@@ -6,13 +6,32 @@ Optional properties: | |||
6 | 6 | ||
7 | - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs. | 7 | - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs. |
8 | 8 | ||
9 | Configure the LED mode with single value. The list of PHYs and | 9 | Configure the LED mode with single value. The list of PHYs and the |
10 | the bits that are currently supported: | 10 | bits that are currently supported: |
11 | 11 | ||
12 | KSZ8001: register 0x1e, bits 15..14 | 12 | KSZ8001: register 0x1e, bits 15..14 |
13 | KSZ8041: register 0x1e, bits 15..14 | 13 | KSZ8041: register 0x1e, bits 15..14 |
14 | KSZ8021: register 0x1f, bits 5..4 | 14 | KSZ8021: register 0x1f, bits 5..4 |
15 | KSZ8031: register 0x1f, bits 5..4 | 15 | KSZ8031: register 0x1f, bits 5..4 |
16 | KSZ8051: register 0x1f, bits 5..4 | 16 | KSZ8051: register 0x1f, bits 5..4 |
17 | KSZ8081: register 0x1f, bits 5..4 | ||
18 | KSZ8091: register 0x1f, bits 5..4 | ||
17 | 19 | ||
18 | See the respective PHY datasheet for the mode values. | 20 | See the respective PHY datasheet for the mode values. |
21 | |||
22 | - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select | ||
23 | bit selects 25 MHz mode | ||
24 | |||
25 | Setting the RMII Reference Clock Select bit enables 25 MHz rather | ||
26 | than 50 MHz clock mode. | ||
27 | |||
28 | Note that this option in only needed for certain PHY revisions with a | ||
29 | non-standard, inverted function of this configuration bit. | ||
30 | Specifically, a clock reference ("rmii-ref" below) is always needed to | ||
31 | actually select a mode. | ||
32 | |||
33 | - clocks, clock-names: contains clocks according to the common clock bindings. | ||
34 | |||
35 | supported clocks: | ||
36 | - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference | ||
37 | input clock. Used to determine the XI input clock. | ||
diff --git a/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt b/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt index 3b58ae480344..9005608cbbd1 100644 --- a/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt +++ b/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt | |||
@@ -26,7 +26,7 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2): | |||
26 | clock-frequency = <400000>; | 26 | clock-frequency = <400000>; |
27 | 27 | ||
28 | interrupt-parent = <&gpio5>; | 28 | interrupt-parent = <&gpio5>; |
29 | interrupts = <2 IRQ_TYPE_LEVEL_LOW>; | 29 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; |
30 | 30 | ||
31 | reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; | 31 | reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; |
32 | }; | 32 | }; |
diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt index 1e436133685f..7c89ca290ced 100644 --- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt +++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt | |||
@@ -13,6 +13,11 @@ Optional SoC Specific Properties: | |||
13 | - pinctrl-names: Contains only one value - "default". | 13 | - pinctrl-names: Contains only one value - "default". |
14 | - pintctrl-0: Specifies the pin control groups used for this controller. | 14 | - pintctrl-0: Specifies the pin control groups used for this controller. |
15 | - autosuspend-delay: Specify autosuspend delay in milliseconds. | 15 | - autosuspend-delay: Specify autosuspend delay in milliseconds. |
16 | - vin-voltage-override: Specify voltage of VIN pin in microvolts. | ||
17 | - irq-status-read-quirk: Specify that the trf7970a being used has the | ||
18 | "IRQ Status Read" erratum. | ||
19 | - en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF" | ||
20 | erratum. | ||
16 | 21 | ||
17 | Example (for ARM-based BeagleBone with TRF7970A on SPI1): | 22 | Example (for ARM-based BeagleBone with TRF7970A on SPI1): |
18 | 23 | ||
@@ -30,7 +35,10 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1): | |||
30 | ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>, | 35 | ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>, |
31 | <&gpio2 5 GPIO_ACTIVE_LOW>; | 36 | <&gpio2 5 GPIO_ACTIVE_LOW>; |
32 | vin-supply = <&ldo3_reg>; | 37 | vin-supply = <&ldo3_reg>; |
38 | vin-voltage-override = <5000000>; | ||
33 | autosuspend-delay = <30000>; | 39 | autosuspend-delay = <30000>; |
40 | irq-status-read-quirk; | ||
41 | en2-rf-quirk; | ||
34 | status = "okay"; | 42 | status = "okay"; |
35 | }; | 43 | }; |
36 | }; | 44 | }; |
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt index 5b8c58903077..40831fbaff72 100644 --- a/Documentation/devicetree/bindings/net/phy.txt +++ b/Documentation/devicetree/bindings/net/phy.txt | |||
@@ -19,7 +19,6 @@ Optional Properties: | |||
19 | specifications. If neither of these are specified, the default is to | 19 | specifications. If neither of these are specified, the default is to |
20 | assume clause 22. The compatible list may also contain other | 20 | assume clause 22. The compatible list may also contain other |
21 | elements. | 21 | elements. |
22 | - max-speed: Maximum PHY supported speed (10, 100, 1000...) | ||
23 | 22 | ||
24 | If the phy's identifier is known then the list may contain an entry | 23 | If the phy's identifier is known then the list may contain an entry |
25 | of the form: "ethernet-phy-idAAAA.BBBB" where | 24 | of the form: "ethernet-phy-idAAAA.BBBB" where |
@@ -29,6 +28,8 @@ Optional Properties: | |||
29 | 4 hex digits. This is the chip vendor OUI bits 19:24, | 28 | 4 hex digits. This is the chip vendor OUI bits 19:24, |
30 | followed by 10 bits of a vendor specific ID. | 29 | followed by 10 bits of a vendor specific ID. |
31 | 30 | ||
31 | - max-speed: Maximum PHY supported speed (10, 100, 1000...) | ||
32 | |||
32 | Example: | 33 | Example: |
33 | 34 | ||
34 | ethernet-phy@0 { | 35 | ethernet-phy@0 { |
diff --git a/Documentation/devicetree/bindings/net/qca-qca7000-spi.txt b/Documentation/devicetree/bindings/net/qca-qca7000-spi.txt new file mode 100644 index 000000000000..c74989c0d8ac --- /dev/null +++ b/Documentation/devicetree/bindings/net/qca-qca7000-spi.txt | |||
@@ -0,0 +1,47 @@ | |||
1 | * Qualcomm QCA7000 (Ethernet over SPI protocol) | ||
2 | |||
3 | Note: The QCA7000 is useable as a SPI device. In this case it must be defined | ||
4 | as a child of a SPI master in the device tree. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : Should be "qca,qca7000" | ||
8 | - reg : Should specify the SPI chip select | ||
9 | - interrupts : The first cell should specify the index of the source interrupt | ||
10 | and the second cell should specify the trigger type as rising edge | ||
11 | - spi-cpha : Must be set | ||
12 | - spi-cpol: Must be set | ||
13 | |||
14 | Optional properties: | ||
15 | - interrupt-parent : Specify the pHandle of the source interrupt | ||
16 | - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at. | ||
17 | Numbers smaller than 1000000 or greater than 16000000 are invalid. Missing | ||
18 | the property will set the SPI frequency to 8000000 Hertz. | ||
19 | - local-mac-address: 6 bytes, MAC address | ||
20 | - qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode. | ||
21 | In this mode the SPI master must toggle the chip select between each data | ||
22 | word. In burst mode these gaps aren't necessary, which is faster. | ||
23 | This setting depends on how the QCA7000 is setup via GPIO pin strapping. | ||
24 | If the property is missing the driver defaults to burst mode. | ||
25 | |||
26 | Example: | ||
27 | |||
28 | /* Freescale i.MX28 SPI master*/ | ||
29 | ssp2: spi@80014000 { | ||
30 | #address-cells = <1>; | ||
31 | #size-cells = <0>; | ||
32 | compatible = "fsl,imx28-spi"; | ||
33 | pinctrl-names = "default"; | ||
34 | pinctrl-0 = <&spi2_pins_a>; | ||
35 | status = "okay"; | ||
36 | |||
37 | qca7000: ethernet@0 { | ||
38 | compatible = "qca,qca7000"; | ||
39 | reg = <0x0>; | ||
40 | interrupt-parent = <&gpio3>; /* GPIO Bank 3 */ | ||
41 | interrupts = <25 0x1>; /* Index: 25, rising edge */ | ||
42 | spi-cpha; /* SPI mode: CPHA=1 */ | ||
43 | spi-cpol; /* SPI mode: CPOL=1 */ | ||
44 | spi-max-frequency = <8000000>; /* freq: 8 MHz */ | ||
45 | local-mac-address = [ A0 B0 C0 D0 E0 F0 ]; | ||
46 | }; | ||
47 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt index 989f6c95cfd5..888c250197fe 100644 --- a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt +++ b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt | |||
@@ -17,7 +17,7 @@ Required properties: | |||
17 | - samsung,pbl: Integer, Programmable Burst Length. | 17 | - samsung,pbl: Integer, Programmable Burst Length. |
18 | Supported values are 1, 2, 4, 8, 16, or 32. | 18 | Supported values are 1, 2, 4, 8, 16, or 32. |
19 | - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe | 19 | - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe |
20 | This is an interger and represents allowable DMA bursts when fixed burst. | 20 | This is an integer and represents allowable DMA bursts when fixed burst. |
21 | Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled. | 21 | Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled. |
22 | When fixed length is needed for burst mode, it can be set within allowable | 22 | When fixed length is needed for burst mode, it can be set within allowable |
23 | range. | 23 | range. |
diff --git a/Documentation/devicetree/bindings/net/sh_eth.txt b/Documentation/devicetree/bindings/net/sh_eth.txt index 34d4db1a4e25..2f6ec85fda8e 100644 --- a/Documentation/devicetree/bindings/net/sh_eth.txt +++ b/Documentation/devicetree/bindings/net/sh_eth.txt | |||
@@ -9,6 +9,7 @@ Required properties: | |||
9 | "renesas,ether-r8a7779" if the device is a part of R8A7779 SoC. | 9 | "renesas,ether-r8a7779" if the device is a part of R8A7779 SoC. |
10 | "renesas,ether-r8a7790" if the device is a part of R8A7790 SoC. | 10 | "renesas,ether-r8a7790" if the device is a part of R8A7790 SoC. |
11 | "renesas,ether-r8a7791" if the device is a part of R8A7791 SoC. | 11 | "renesas,ether-r8a7791" if the device is a part of R8A7791 SoC. |
12 | "renesas,ether-r8a7793" if the device is a part of R8A7793 SoC. | ||
12 | "renesas,ether-r8a7794" if the device is a part of R8A7794 SoC. | 13 | "renesas,ether-r8a7794" if the device is a part of R8A7794 SoC. |
13 | "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC. | 14 | "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC. |
14 | - reg: offset and length of (1) the E-DMAC/feLic register block (required), | 15 | - reg: offset and length of (1) the E-DMAC/feLic register block (required), |
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt index 0f8487b88822..e77e167593db 100644 --- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt +++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt | |||
@@ -11,3 +11,5 @@ Optional properties: | |||
11 | are supported on the device. Valid value for SMSC LAN91c111 are | 11 | are supported on the device. Valid value for SMSC LAN91c111 are |
12 | 1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning | 12 | 1, 2 or 4. If it's omitted or invalid, the size would be 2 meaning |
13 | 16-bit access only. | 13 | 16-bit access only. |
14 | - power-gpios: GPIO to control the PWRDWN pin | ||
15 | - reset-gpios: GPIO to control the RESET pin | ||
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt index 2a60cd3e8d5d..3a9d67951606 100644 --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt +++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt | |||
@@ -12,6 +12,10 @@ Required properties: | |||
12 | - altr,sysmgr-syscon : Should be the phandle to the system manager node that | 12 | - altr,sysmgr-syscon : Should be the phandle to the system manager node that |
13 | encompasses the glue register, the register offset, and the register shift. | 13 | encompasses the glue register, the register offset, and the register shift. |
14 | 14 | ||
15 | Optional properties: | ||
16 | altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if | ||
17 | DWMAC controller is connected emac splitter. | ||
18 | |||
15 | Example: | 19 | Example: |
16 | 20 | ||
17 | gmac0: ethernet@ff700000 { | 21 | gmac0: ethernet@ff700000 { |
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt index 3dd3d0bf112f..6762a6b5da7e 100644 --- a/Documentation/devicetree/bindings/net/sti-dwmac.txt +++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt | |||
@@ -1,58 +1,65 @@ | |||
1 | STMicroelectronics SoC DWMAC glue layer controller | 1 | STMicroelectronics SoC DWMAC glue layer controller |
2 | 2 | ||
3 | This file documents differences between the core properties in | ||
4 | Documentation/devicetree/bindings/net/stmmac.txt | ||
5 | and what is needed on STi platforms to program the stmmac glue logic. | ||
6 | |||
3 | The device node has following properties. | 7 | The device node has following properties. |
4 | 8 | ||
5 | Required properties: | 9 | Required properties: |
6 | - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac" or | 10 | - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac", |
7 | "st,stid127-dwmac". | 11 | "st,stih407-dwmac", "st,stid127-dwmac". |
8 | - reg : Offset of the glue configuration register map in system | 12 | - reg : Offset of the glue configuration register map in system |
9 | configuration regmap pointed by st,syscon property and size. | 13 | configuration regmap pointed by st,syscon property and size. |
10 | 14 | - st,syscon : Should be phandle to system configuration node which | |
11 | - reg-names : Should be "sti-ethconf". | ||
12 | |||
13 | - st,syscon : Should be phandle to system configuration node which | ||
14 | encompases this glue registers. | 15 | encompases this glue registers. |
16 | - st,gmac_en: this is to enable the gmac into a dedicated sysctl control | ||
17 | register available on STiH407 SoC. | ||
18 | - sti-ethconf: this is the gmac glue logic register to enable the GMAC, | ||
19 | select among the different modes and program the clk retiming. | ||
20 | - pinctrl-0: pin-control for all the MII mode supported. | ||
15 | 21 | ||
16 | - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be | 22 | Optional properties: |
17 | wired up in from different sources. One via TXCLK pin and other via CLK_125 | 23 | - resets : phandle pointing to the system reset controller with correct |
18 | pin. This wiring is totally board dependent. However the retiming glue | 24 | reset line index for ethernet reset. |
19 | logic should be configured accordingly. Possible values for this property | 25 | - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or |
20 | 26 | MAC can generate it. | |
21 | "txclk" - if 125Mhz clock is wired up via txclk line. | 27 | - st,tx-retime-src: This specifies which clk is wired up to the mac for |
22 | "clk_125" - if 125Mhz clock is wired up via clk_125 line. | 28 | retimeing tx lines. This is totally board dependent and can take one of the |
23 | 29 | posssible values from "txclk", "clk_125" or "clkgen". | |
24 | This property is only valid for Giga bit setup( GMII, RGMII), and it is | 30 | If not passed, the internal clock will be used by default. |
25 | un-used for non-giga bit (MII and RMII) setups. Also note that internal | 31 | - sti-ethclk: this is the phy clock. |
26 | clockgen can not generate stable 125Mhz clock. | 32 | - sti-clkconf: this is an extra sysconfig register, available in new SoCs, |
27 | 33 | to program the clk retiming. | |
28 | - st,ext-phyclk: This boolean property indicates who is generating the clock | 34 | - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. |
29 | for tx and rx. This property is only valid for RMII case where the clock can | 35 | STiH407. |
30 | be generated from the MAC or PHY. | ||
31 | |||
32 | - clock-names: should be "sti-ethclk". | ||
33 | - clocks: Should point to ethernet clockgen which can generate phyclk. | ||
34 | |||
35 | 36 | ||
36 | Example: | 37 | Example: |
37 | 38 | ||
38 | ethernet0: dwmac@fe810000 { | 39 | ethernet0: dwmac@9630000 { |
39 | device_type = "network"; | 40 | device_type = "network"; |
40 | compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710"; | 41 | status = "disabled"; |
41 | reg = <0xfe810000 0x8000>, <0x8bc 0x4>; | 42 | compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; |
42 | reg-names = "stmmaceth", "sti-ethconf"; | 43 | reg = <0x9630000 0x8000>, <0x80 0x4>; |
43 | interrupts = <0 133 0>, <0 134 0>, <0 135 0>; | 44 | reg-names = "stmmaceth", "sti-ethconf"; |
44 | interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; | ||
45 | phy-mode = "mii"; | ||
46 | 45 | ||
47 | st,syscon = <&syscfg_rear>; | 46 | st,syscon = <&syscfg_sbc_reg>; |
47 | st,gmac_en; | ||
48 | resets = <&softreset STIH407_ETH1_SOFTRESET>; | ||
49 | reset-names = "stmmaceth"; | ||
48 | 50 | ||
49 | snps,pbl = <32>; | 51 | interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, |
52 | <GIC_SPI 99 IRQ_TYPE_NONE>, | ||
53 | <GIC_SPI 100 IRQ_TYPE_NONE>; | ||
54 | interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; | ||
55 | |||
56 | snps,pbl = <32>; | ||
50 | snps,mixed-burst; | 57 | snps,mixed-burst; |
51 | 58 | ||
52 | resets = <&softreset STIH416_ETH0_SOFTRESET>; | 59 | pinctrl-names = "default"; |
53 | reset-names = "stmmaceth"; | 60 | pinctrl-0 = <&pinctrl_rgmii1>; |
54 | pinctrl-0 = <&pinctrl_mii0>; | 61 | |
55 | pinctrl-names = "default"; | 62 | clock-names = "stmmaceth", "sti-ethclk"; |
56 | clocks = <&CLK_S_GMAC0_PHY>; | 63 | clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, |
57 | clock-names = "stmmaceth"; | 64 | <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; |
58 | }; | 65 | }; |
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt index e45ac3f926b1..c41afd963edf 100644 --- a/Documentation/devicetree/bindings/net/stmmac.txt +++ b/Documentation/devicetree/bindings/net/stmmac.txt | |||
@@ -58,5 +58,5 @@ Examples: | |||
58 | snps,multicast-filter-bins = <256>; | 58 | snps,multicast-filter-bins = <256>; |
59 | snps,perfect-filter-entries = <128>; | 59 | snps,perfect-filter-entries = <128>; |
60 | clocks = <&clock>; | 60 | clocks = <&clock>; |
61 | clock-names = "stmmaceth">; | 61 | clock-names = "stmmaceth"; |
62 | }; | 62 | }; |
diff --git a/Documentation/devicetree/bindings/nios2/nios2.txt b/Documentation/devicetree/bindings/nios2/nios2.txt new file mode 100644 index 000000000000..d6d0a94cb3bb --- /dev/null +++ b/Documentation/devicetree/bindings/nios2/nios2.txt | |||
@@ -0,0 +1,62 @@ | |||
1 | * Nios II Processor Binding | ||
2 | |||
3 | This binding specifies what properties available in the device tree | ||
4 | representation of a Nios II Processor Core. | ||
5 | |||
6 | Users can use sopc2dts tool for generating device tree sources (dts) from a | ||
7 | Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts | ||
8 | |||
9 | Required properties: | ||
10 | |||
11 | - compatible: Compatible property value should be "altr,nios2-1.0". | ||
12 | - reg: Contains CPU index. | ||
13 | - interrupt-controller: Specifies that the node is an interrupt controller | ||
14 | - #interrupt-cells: Specifies the number of cells needed to encode an | ||
15 | interrupt source, should be 1. | ||
16 | - clock-frequency: Contains the clock frequency for CPU, in Hz. | ||
17 | - dcache-line-size: Contains data cache line size. | ||
18 | - icache-line-size: Contains instruction line size. | ||
19 | - dcache-size: Contains data cache size. | ||
20 | - icache-size: Contains instruction cache size. | ||
21 | - altr,pid-num-bits: Specifies the number of bits to use to represent the process | ||
22 | identifier (PID). | ||
23 | - altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. | ||
24 | - altr,tlb-num-entries: Specifies the number of entries in the TLB. | ||
25 | - altr,tlb-ptr-sz: Specifies size of TLB pointer. | ||
26 | - altr,has-mul: Specifies CPU hardware multipy support, should be 1. | ||
27 | - altr,has-mmu: Specifies CPU support MMU support, should be 1. | ||
28 | - altr,has-initda: Specifies CPU support initda instruction, should be 1. | ||
29 | - altr,reset-addr: Specifies CPU reset address | ||
30 | - altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address | ||
31 | - altr,exception-addr: Specifies CPU exception address | ||
32 | |||
33 | Optional properties: | ||
34 | - altr,has-div: Specifies CPU hardware divide support | ||
35 | - altr,implementation: Nios II core implementation, this should be "fast"; | ||
36 | |||
37 | Example: | ||
38 | |||
39 | cpu@0x0 { | ||
40 | device_type = "cpu"; | ||
41 | compatible = "altr,nios2-1.0"; | ||
42 | reg = <0>; | ||
43 | interrupt-controller; | ||
44 | #interrupt-cells = <1>; | ||
45 | clock-frequency = <125000000>; | ||
46 | dcache-line-size = <32>; | ||
47 | icache-line-size = <32>; | ||
48 | dcache-size = <32768>; | ||
49 | icache-size = <32768>; | ||
50 | altr,implementation = "fast"; | ||
51 | altr,pid-num-bits = <8>; | ||
52 | altr,tlb-num-ways = <16>; | ||
53 | altr,tlb-num-entries = <128>; | ||
54 | altr,tlb-ptr-sz = <7>; | ||
55 | altr,has-div = <1>; | ||
56 | altr,has-mul = <1>; | ||
57 | altr,reset-addr = <0xc2800000>; | ||
58 | altr,fast-tlb-miss-addr = <0xc7fff400>; | ||
59 | altr,exception-addr = <0xd0000020>; | ||
60 | altr,has-initda = <1>; | ||
61 | altr,has-mmu = <1>; | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/nios2/timer.txt b/Documentation/devicetree/bindings/nios2/timer.txt new file mode 100644 index 000000000000..904a5846d7ac --- /dev/null +++ b/Documentation/devicetree/bindings/nios2/timer.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | Altera Timer | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "altr,timer-1.0" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | - interrupt-parent: phandle of the interrupt controller | ||
8 | - interrupts : Should contain the timer interrupt number | ||
9 | - clock-frequency : The frequency of the clock that drives the counter, in Hz. | ||
10 | |||
11 | Example: | ||
12 | |||
13 | timer { | ||
14 | compatible = "altr,timer-1.0"; | ||
15 | reg = <0x00400000 0x00000020>; | ||
16 | interrupt-parent = <&cpu>; | ||
17 | interrupts = <11>; | ||
18 | clock-frequency = <125000000>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/panel/auo,b101xtn01.txt b/Documentation/devicetree/bindings/panel/auo,b101xtn01.txt new file mode 100644 index 000000000000..889d511d66c9 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/auo,b101xtn01.txt | |||
@@ -0,0 +1,7 @@ | |||
1 | AU Optronics Corporation 10.1" WXGA TFT LCD panel | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "auo,b101xtn01" | ||
5 | |||
6 | This binding is compatible with the simple-panel binding, which is specified | ||
7 | in simple-panel.txt in this directory. | ||
diff --git a/Documentation/devicetree/bindings/panel/auo,b116xw03.txt b/Documentation/devicetree/bindings/panel/auo,b116xw03.txt new file mode 100644 index 000000000000..690d0a568ef3 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/auo,b116xw03.txt | |||
@@ -0,0 +1,7 @@ | |||
1 | AU Optronics Corporation 11.6" HD (1366x768) color TFT-LCD panel | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "auo,b116xw03" | ||
5 | |||
6 | This binding is compatible with the simple-panel binding, which is specified | ||
7 | in simple-panel.txt in this directory. | ||
diff --git a/Documentation/devicetree/bindings/panel/hannstar,hsd070pww1.txt b/Documentation/devicetree/bindings/panel/hannstar,hsd070pww1.txt new file mode 100644 index 000000000000..7da1d5c038ff --- /dev/null +++ b/Documentation/devicetree/bindings/panel/hannstar,hsd070pww1.txt | |||
@@ -0,0 +1,7 @@ | |||
1 | HannStar Display Corp. HSD070PWW1 7.0" WXGA TFT LCD panel | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "hannstar,hsd070pww1" | ||
5 | |||
6 | This binding is compatible with the simple-panel binding, which is specified | ||
7 | in simple-panel.txt in this directory. | ||
diff --git a/Documentation/devicetree/bindings/panel/hit,tx23d38vm0caa.txt b/Documentation/devicetree/bindings/panel/hit,tx23d38vm0caa.txt new file mode 100644 index 000000000000..04caaae19af6 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/hit,tx23d38vm0caa.txt | |||
@@ -0,0 +1,7 @@ | |||
1 | Hitachi Ltd. Corporation 9" WVGA (800x480) TFT LCD panel | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "hit,tx23d38vm0caa" | ||
5 | |||
6 | This binding is compatible with the simple-panel binding, which is specified | ||
7 | in simple-panel.txt in this directory. | ||
diff --git a/Documentation/devicetree/bindings/panel/innolux,g121i1-l01.txt b/Documentation/devicetree/bindings/panel/innolux,g121i1-l01.txt new file mode 100644 index 000000000000..2743b07cd2f2 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/innolux,g121i1-l01.txt | |||
@@ -0,0 +1,7 @@ | |||
1 | Innolux Corporation 12.1" WXGA (1280x800) TFT LCD panel | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "innolux,g121i1-l01" | ||
5 | |||
6 | This binding is compatible with the simple-panel binding, which is specified | ||
7 | in simple-panel.txt in this directory. | ||
diff --git a/Documentation/devicetree/bindings/panel/sharp,lq101r1sx01.txt b/Documentation/devicetree/bindings/panel/sharp,lq101r1sx01.txt new file mode 100644 index 000000000000..f522bb8e47e1 --- /dev/null +++ b/Documentation/devicetree/bindings/panel/sharp,lq101r1sx01.txt | |||
@@ -0,0 +1,49 @@ | |||
1 | Sharp Microelectronics 10.1" WQXGA TFT LCD panel | ||
2 | |||
3 | This panel requires a dual-channel DSI host to operate. It supports two modes: | ||
4 | - left-right: each channel drives the left or right half of the screen | ||
5 | - even-odd: each channel drives the even or odd lines of the screen | ||
6 | |||
7 | Each of the DSI channels controls a separate DSI peripheral. The peripheral | ||
8 | driven by the first link (DSI-LINK1), left or even, is considered the primary | ||
9 | peripheral and controls the device. The 'link2' property contains a phandle | ||
10 | to the peripheral driven by the second link (DSI-LINK2, right or odd). | ||
11 | |||
12 | Note that in video mode the DSI-LINK1 interface always provides the left/even | ||
13 | pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it | ||
14 | is possible to program either link to drive the left/even or right/odd pixels | ||
15 | but for the sake of consistency this binding assumes that the same assignment | ||
16 | is chosen as for video mode. | ||
17 | |||
18 | Required properties: | ||
19 | - compatible: should be "sharp,lq101r1sx01" | ||
20 | - reg: DSI virtual channel of the peripheral | ||
21 | |||
22 | Required properties (for DSI-LINK1 only): | ||
23 | - link2: phandle to the DSI peripheral on the secondary link. Note that the | ||
24 | presence of this property marks the containing node as DSI-LINK1. | ||
25 | - power-supply: phandle of the regulator that provides the supply voltage | ||
26 | |||
27 | Optional properties (for DSI-LINK1 only): | ||
28 | - backlight: phandle of the backlight device attached to the panel | ||
29 | |||
30 | Example: | ||
31 | |||
32 | dsi@54300000 { | ||
33 | panel: panel@0 { | ||
34 | compatible = "sharp,lq101r1sx01"; | ||
35 | reg = <0>; | ||
36 | |||
37 | link2 = <&secondary>; | ||
38 | |||
39 | power-supply = <...>; | ||
40 | backlight = <...>; | ||
41 | }; | ||
42 | }; | ||
43 | |||
44 | dsi@54400000 { | ||
45 | secondary: panel@0 { | ||
46 | compatible = "sharp,lq101r1sx01"; | ||
47 | reg = <0>; | ||
48 | }; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index ed0d9b9fff2b..9f4faa8e8d00 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt | |||
@@ -23,3 +23,6 @@ Required properties: | |||
23 | 23 | ||
24 | Optional properties: | 24 | Optional properties: |
25 | - reset-gpio: gpio pin number of power good signal | 25 | - reset-gpio: gpio pin number of power good signal |
26 | - bus-range: PCI bus numbers covered (it is recommended for new devicetrees to | ||
27 | specify this property, to keep backwards compatibility a range of 0x00-0xff | ||
28 | is assumed if not present) | ||
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index 9455fd0ec830..6fbba53a309b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | |||
@@ -17,7 +17,9 @@ Example: | |||
17 | 17 | ||
18 | pcie@0x01000000 { | 18 | pcie@0x01000000 { |
19 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; | 19 | compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; |
20 | reg = <0x01ffc000 0x4000>; | 20 | reg = <0x01ffc000 0x04000>, |
21 | <0x01f00000 0x80000>; | ||
22 | reg-names = "dbi", "config"; | ||
21 | #address-cells = <3>; | 23 | #address-cells = <3>; |
22 | #size-cells = <2>; | 24 | #size-cells = <2>; |
23 | device_type = "pci"; | 25 | device_type = "pci"; |
diff --git a/Documentation/devicetree/bindings/pci/fsl,pci.txt b/Documentation/devicetree/bindings/pci/fsl,pci.txt new file mode 100644 index 000000000000..d8ac4a768e7e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,pci.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | * Bus Enumeration by Freescale PCI-X Agent | ||
2 | |||
3 | Typically any Freescale PCI-X bridge hardware strapped into Agent mode | ||
4 | is prevented from enumerating the bus. The PrPMC form-factor requires | ||
5 | all mezzanines to be PCI-X Agents, but one per system may still | ||
6 | enumerate the bus. | ||
7 | |||
8 | The property defined below will allow a PCI-X bridge to be used for bus | ||
9 | enumeration despite being strapped into Agent mode. | ||
10 | |||
11 | Required properties: | ||
12 | - fsl,pci-agent-force-enum : There is no value associated with this | ||
13 | property. The property itself is treated as a boolean. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | /* PCI-X bridge known to be PrPMC Monarch */ | ||
18 | pci0: pci@ef008000 { | ||
19 | fsl,pci-agent-force-enum; | ||
20 | #interrupt-cells = <1>; | ||
21 | #size-cells = <2>; | ||
22 | #address-cells = <3>; | ||
23 | compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; | ||
24 | device_type = "pci"; | ||
25 | ... | ||
26 | ... | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt index f0b0436807b4..cf3e205e0b7e 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt | |||
@@ -55,7 +55,7 @@ For CAM, this 24-bit offset is: | |||
55 | cfg_offset(bus, device, function, register) = | 55 | cfg_offset(bus, device, function, register) = |
56 | bus << 16 | device << 11 | function << 8 | register | 56 | bus << 16 | device << 11 | function << 8 | register |
57 | 57 | ||
58 | Whilst ECAM extends this by 4 bits to accomodate 4k of function space: | 58 | Whilst ECAM extends this by 4 bits to accommodate 4k of function space: |
59 | 59 | ||
60 | cfg_offset(bus, device, function, register) = | 60 | cfg_offset(bus, device, function, register) = |
61 | bus << 20 | device << 15 | function << 12 | register | 61 | bus << 20 | device << 15 | function << 12 | register |
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt new file mode 100644 index 000000000000..6286f049bf18 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt | |||
@@ -0,0 +1,42 @@ | |||
1 | Freescale Layerscape PCIe controller | ||
2 | |||
3 | This PCIe host controller is based on the Synopsis Designware PCIe IP | ||
4 | and thus inherits all the common properties defined in designware-pcie.txt. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: should contain the platform identifier such as "fsl,ls1021a-pcie" | ||
8 | - reg: base addresses and lengths of the PCIe controller | ||
9 | - interrupts: A list of interrupt outputs of the controller. Must contain an | ||
10 | entry for each entry in the interrupt-names property. | ||
11 | - interrupt-names: Must include the following entries: | ||
12 | "intr": The interrupt that is asserted for controller interrupts | ||
13 | - fsl,pcie-scfg: Must include two entries. | ||
14 | The first entry must be a link to the SCFG device node | ||
15 | The second entry must be '0' or '1' based on physical PCIe controller index. | ||
16 | This is used to get SCFG PEXN registers | ||
17 | |||
18 | Example: | ||
19 | |||
20 | pcie@3400000 { | ||
21 | compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; | ||
22 | reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ | ||
23 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ | ||
24 | reg-names = "regs", "config"; | ||
25 | interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ | ||
26 | interrupt-names = "intr"; | ||
27 | fsl,pcie-scfg = <&scfg 0>; | ||
28 | #address-cells = <3>; | ||
29 | #size-cells = <2>; | ||
30 | device_type = "pci"; | ||
31 | num-lanes = <4>; | ||
32 | bus-range = <0x0 0xff>; | ||
33 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ | ||
34 | 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */ | ||
35 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | ||
36 | #interrupt-cells = <1>; | ||
37 | interrupt-map-mask = <0 0 0 7>; | ||
38 | interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | ||
39 | <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | ||
40 | <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | ||
41 | <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | ||
42 | }; | ||
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt index 0823362548dc..d763e047c6ae 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt | |||
@@ -1,7 +1,10 @@ | |||
1 | NVIDIA Tegra PCIe controller | 1 | NVIDIA Tegra PCIe controller |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie" | 4 | - compatible: Must be one of: |
5 | - "nvidia,tegra20-pcie" | ||
6 | - "nvidia,tegra30-pcie" | ||
7 | - "nvidia,tegra124-pcie" | ||
5 | - device_type: Must be "pci" | 8 | - device_type: Must be "pci" |
6 | - reg: A list of physical base address and length for each set of controller | 9 | - reg: A list of physical base address and length for each set of controller |
7 | registers. Must contain an entry for each entry in the reg-names property. | 10 | registers. Must contain an entry for each entry in the reg-names property. |
@@ -57,6 +60,11 @@ Required properties: | |||
57 | - afi | 60 | - afi |
58 | - pcie_x | 61 | - pcie_x |
59 | 62 | ||
63 | Required properties on Tegra124 and later: | ||
64 | - phys: Must contain an entry for each entry in phy-names. | ||
65 | - phy-names: Must include the following entries: | ||
66 | - pcie | ||
67 | |||
60 | Power supplies for Tegra20: | 68 | Power supplies for Tegra20: |
61 | - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. | 69 | - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. |
62 | - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. | 70 | - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. |
@@ -84,6 +92,21 @@ Power supplies for Tegra30: | |||
84 | - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. | 92 | - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V. |
85 | - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. | 93 | - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. |
86 | 94 | ||
95 | Power supplies for Tegra124: | ||
96 | - Required: | ||
97 | - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V. | ||
98 | - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V. | ||
99 | - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must | ||
100 | supply 1.05 V. | ||
101 | - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks. | ||
102 | Must supply 3.3 V. | ||
103 | - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3). | ||
104 | Must supply 3.3 V. | ||
105 | - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must | ||
106 | supply 2.8-3.3 V. | ||
107 | - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must | ||
108 | supply 1.05 V. | ||
109 | |||
87 | Root ports are defined as subnodes of the PCIe controller node. | 110 | Root ports are defined as subnodes of the PCIe controller node. |
88 | 111 | ||
89 | Required properties: | 112 | Required properties: |
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt new file mode 100644 index 000000000000..54eae2938174 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt | |||
@@ -0,0 +1,63 @@ | |||
1 | TI Keystone PCIe interface | ||
2 | |||
3 | Keystone PCI host Controller is based on Designware PCI h/w version 3.65. | ||
4 | It shares common functions with PCIe Designware core driver and inherit | ||
5 | common properties defined in | ||
6 | Documentation/devicetree/bindings/pci/designware-pci.txt | ||
7 | |||
8 | Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt | ||
9 | for the details of Designware DT bindings. Additional properties are | ||
10 | described here as well as properties that are not applicable. | ||
11 | |||
12 | Required Properties:- | ||
13 | |||
14 | compatibility: "ti,keystone-pcie" | ||
15 | reg: index 1 is the base address and length of DW application registers. | ||
16 | index 2 is the base address and length of PCI device ID register. | ||
17 | |||
18 | pcie_msi_intc : Interrupt controller device node for MSI IRQ chip | ||
19 | interrupt-cells: should be set to 1 | ||
20 | interrupt-parent: Parent interrupt controller phandle | ||
21 | interrupts: GIC interrupt lines connected to PCI MSI interrupt lines | ||
22 | |||
23 | Example: | ||
24 | pcie_msi_intc: msi-interrupt-controller { | ||
25 | interrupt-controller; | ||
26 | #interrupt-cells = <1>; | ||
27 | interrupt-parent = <&gic>; | ||
28 | interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, | ||
29 | <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, | ||
30 | <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, | ||
31 | <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, | ||
32 | <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, | ||
33 | <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, | ||
34 | <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, | ||
35 | <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; | ||
36 | }; | ||
37 | |||
38 | pcie_intc: Interrupt controller device node for Legacy IRQ chip | ||
39 | interrupt-cells: should be set to 1 | ||
40 | interrupt-parent: Parent interrupt controller phandle | ||
41 | interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines | ||
42 | |||
43 | Example: | ||
44 | pcie_intc: legacy-interrupt-controller { | ||
45 | interrupt-controller; | ||
46 | #interrupt-cells = <1>; | ||
47 | interrupt-parent = <&gic>; | ||
48 | interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, | ||
49 | <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, | ||
50 | <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, | ||
51 | <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; | ||
52 | }; | ||
53 | |||
54 | Optional properties:- | ||
55 | phys: phandle to Generic Keystone SerDes phy for PCI | ||
56 | phy-names: name of the Generic Keystine SerDes phy for PCI | ||
57 | - If boot loader already does PCI link establishment, then phys and | ||
58 | phy-names shouldn't be present. | ||
59 | |||
60 | Designware DT Properties not applicable for Keystone PCI | ||
61 | |||
62 | 1. pcie_bus clock-names not used. Instead, a phandle to phys is used. | ||
63 | |||
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 41aeed38926d..f8fbe9af7b2f 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt | |||
@@ -7,3 +7,14 @@ And for the interrupt mapping part: | |||
7 | 7 | ||
8 | Open Firmware Recommended Practice: Interrupt Mapping | 8 | Open Firmware Recommended Practice: Interrupt Mapping |
9 | http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf | 9 | http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf |
10 | |||
11 | Additionally to the properties specified in the above standards a host bridge | ||
12 | driver implementation may support the following properties: | ||
13 | |||
14 | - linux,pci-domain: | ||
15 | If present this property assigns a fixed PCI domain number to a host bridge, | ||
16 | otherwise an unstable (across boots) unique number will be assigned. | ||
17 | It is required to either not set this property at all or set it for all | ||
18 | host bridges in the system, otherwise potentially conflicting domain numbers | ||
19 | may be assigned to root buses behind different host bridges. The domain | ||
20 | number for each host bridge in the system must be unique. | ||
diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt new file mode 100644 index 000000000000..1070b068c7c6 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt | |||
@@ -0,0 +1,57 @@ | |||
1 | * AppliedMicro X-Gene PCIe interface | ||
2 | |||
3 | Required properties: | ||
4 | - device_type: set to "pci" | ||
5 | - compatible: should contain "apm,xgene-pcie" to identify the core. | ||
6 | - reg: A list of physical base address and length for each set of controller | ||
7 | registers. Must contain an entry for each entry in the reg-names | ||
8 | property. | ||
9 | - reg-names: Must include the following entries: | ||
10 | "csr": controller configuration registers. | ||
11 | "cfg": pcie configuration space registers. | ||
12 | - #address-cells: set to <3> | ||
13 | - #size-cells: set to <2> | ||
14 | - ranges: ranges for the outbound memory, I/O regions. | ||
15 | - dma-ranges: ranges for the inbound memory regions. | ||
16 | - #interrupt-cells: set to <1> | ||
17 | - interrupt-map-mask and interrupt-map: standard PCI properties | ||
18 | to define the mapping of the PCIe interface to interrupt | ||
19 | numbers. | ||
20 | - clocks: from common clock binding: handle to pci clock. | ||
21 | |||
22 | Optional properties: | ||
23 | - status: Either "ok" or "disabled". | ||
24 | - dma-coherent: Present if dma operations are coherent | ||
25 | |||
26 | Example: | ||
27 | |||
28 | SoC specific DT Entry: | ||
29 | |||
30 | pcie0: pcie@1f2b0000 { | ||
31 | status = "disabled"; | ||
32 | device_type = "pci"; | ||
33 | compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; | ||
34 | #interrupt-cells = <1>; | ||
35 | #size-cells = <2>; | ||
36 | #address-cells = <3>; | ||
37 | reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ | ||
38 | 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ | ||
39 | reg-names = "csr", "cfg"; | ||
40 | ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ | ||
41 | 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ | ||
42 | dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 | ||
43 | 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; | ||
44 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; | ||
45 | interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 | ||
46 | 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 | ||
47 | 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 | ||
48 | 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; | ||
49 | dma-coherent; | ||
50 | clocks = <&pcie0clk 0>; | ||
51 | }; | ||
52 | |||
53 | |||
54 | Board specific DT Entry: | ||
55 | &pcie0 { | ||
56 | status = "ok"; | ||
57 | }; | ||
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt new file mode 100644 index 000000000000..3e2c88d97ad4 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt | |||
@@ -0,0 +1,62 @@ | |||
1 | * Xilinx AXI PCIe Root Port Bridge DT description | ||
2 | |||
3 | Required properties: | ||
4 | - #address-cells: Address representation for root ports, set to <3> | ||
5 | - #size-cells: Size representation for root ports, set to <2> | ||
6 | - #interrupt-cells: specifies the number of cells needed to encode an | ||
7 | interrupt source. The value must be 1. | ||
8 | - compatible: Should contain "xlnx,axi-pcie-host-1.00.a" | ||
9 | - reg: Should contain AXI PCIe registers location and length | ||
10 | - device_type: must be "pci" | ||
11 | - interrupts: Should contain AXI PCIe interrupt | ||
12 | - interrupt-map-mask, | ||
13 | interrupt-map: standard PCI properties to define the mapping of the | ||
14 | PCI interface to interrupt numbers. | ||
15 | - ranges: ranges for the PCI memory regions (I/O space region is not | ||
16 | supported by hardware) | ||
17 | Please refer to the standard PCI bus binding document for a more | ||
18 | detailed explanation | ||
19 | |||
20 | Optional properties: | ||
21 | - bus-range: PCI bus numbers covered | ||
22 | |||
23 | Interrupt controller child node | ||
24 | +++++++++++++++++++++++++++++++ | ||
25 | Required properties: | ||
26 | - interrupt-controller: identifies the node as an interrupt controller | ||
27 | - #address-cells: specifies the number of cells needed to encode an | ||
28 | address. The value must be 0. | ||
29 | - #interrupt-cells: specifies the number of cells needed to encode an | ||
30 | interrupt source. The value must be 1. | ||
31 | |||
32 | NOTE: | ||
33 | The core provides a single interrupt for both INTx/MSI messages. So, | ||
34 | created a interrupt controller node to support 'interrupt-map' DT | ||
35 | functionality. The driver will create an IRQ domain for this map, decode | ||
36 | the four INTx interrupts in ISR and route them to this domain. | ||
37 | |||
38 | |||
39 | Example: | ||
40 | ++++++++ | ||
41 | |||
42 | pci_express: axi-pcie@50000000 { | ||
43 | #address-cells = <3>; | ||
44 | #size-cells = <2>; | ||
45 | #interrupt-cells = <1>; | ||
46 | compatible = "xlnx,axi-pcie-host-1.00.a"; | ||
47 | reg = < 0x50000000 0x10000000 >; | ||
48 | device_type = "pci"; | ||
49 | interrupts = < 0 52 4 >; | ||
50 | interrupt-map-mask = <0 0 0 7>; | ||
51 | interrupt-map = <0 0 0 1 &pcie_intc 1>, | ||
52 | <0 0 0 2 &pcie_intc 2>, | ||
53 | <0 0 0 3 &pcie_intc 3>, | ||
54 | <0 0 0 4 &pcie_intc 4>; | ||
55 | ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; | ||
56 | |||
57 | pcie_intc: interrupt-controller { | ||
58 | interrupt-controller; | ||
59 | #address-cells = <0>; | ||
60 | #interrupt-cells = <1>; | ||
61 | } | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt index 88f8c23384c0..c0155f842f62 100644 --- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt +++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt | |||
@@ -2,7 +2,9 @@ Berlin SATA PHY | |||
2 | --------------- | 2 | --------------- |
3 | 3 | ||
4 | Required properties: | 4 | Required properties: |
5 | - compatible: should be "marvell,berlin2q-sata-phy" | 5 | - compatible: should be one of |
6 | "marvell,berlin2-sata-phy" | ||
7 | "marvell,berlin2q-sata-phy" | ||
6 | - address-cells: should be 1 | 8 | - address-cells: should be 1 |
7 | - size-cells: should be 0 | 9 | - size-cells: should be 0 |
8 | - phy-cells: from the generic PHY bindings, must be 1 | 10 | - phy-cells: from the generic PHY bindings, must be 1 |
diff --git a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt new file mode 100644 index 000000000000..be33780f668e --- /dev/null +++ b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt | |||
@@ -0,0 +1,16 @@ | |||
1 | * Marvell Berlin USB PHY | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy" | ||
5 | - reg: base address and length of the registers | ||
6 | - #phys-cells: should be 0 | ||
7 | - resets: reference to the reset controller | ||
8 | |||
9 | Example: | ||
10 | |||
11 | usb-phy@f774000 { | ||
12 | compatible = "marvell,berlin2-usb-phy"; | ||
13 | reg = <0xf774000 0x128>; | ||
14 | #phy-cells = <0>; | ||
15 | resets = <&chip 0x104 14>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/phy-bindings.txt b/Documentation/devicetree/bindings/phy/phy-bindings.txt index 2aa1840200ed..1293c321754c 100644 --- a/Documentation/devicetree/bindings/phy/phy-bindings.txt +++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt | |||
@@ -27,7 +27,7 @@ phys: phy { | |||
27 | }; | 27 | }; |
28 | 28 | ||
29 | That node describes an IP block (PHY provider) that implements 2 different PHYs. | 29 | That node describes an IP block (PHY provider) that implements 2 different PHYs. |
30 | In order to differentiate between these 2 PHYs, an additonal specifier should be | 30 | In order to differentiate between these 2 PHYs, an additional specifier should be |
31 | given while trying to get a reference to it. | 31 | given while trying to get a reference to it. |
32 | 32 | ||
33 | PHY user node | 33 | PHY user node |
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt new file mode 100644 index 000000000000..46a135dae6b3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt | |||
@@ -0,0 +1,128 @@ | |||
1 | STMicroelectronics STi MIPHY28LP PHY binding | ||
2 | ============================================ | ||
3 | |||
4 | This binding describes a miphy device that is used to control PHY hardware | ||
5 | for SATA, PCIe or USB3. | ||
6 | |||
7 | Required properties (controller (parent) node): | ||
8 | - compatible : Should be "st,miphy28lp-phy". | ||
9 | - st,syscfg : Should be a phandle of the system configuration register group | ||
10 | which contain the SATA, PCIe or USB3 mode setting bits. | ||
11 | |||
12 | Required nodes : A sub-node is required for each channel the controller | ||
13 | provides. Address range information including the usual | ||
14 | 'reg' and 'reg-names' properties are used inside these | ||
15 | nodes to describe the controller's topology. These nodes | ||
16 | are translated by the driver's .xlate() function. | ||
17 | |||
18 | Required properties (port (child) node): | ||
19 | - #phy-cells : Should be 1 (See second example) | ||
20 | Cell after port phandle is device type from: | ||
21 | - PHY_TYPE_SATA | ||
22 | - PHY_TYPE_PCI | ||
23 | - PHY_TYPE_USB3 | ||
24 | - reg : Address and length of the register set for the device. | ||
25 | - reg-names : The names of the register addresses corresponding to the registers | ||
26 | filled in "reg". It can also contain the offset of the system configuration | ||
27 | registers used as glue-logic to setup the device for SATA/PCIe or USB3 | ||
28 | devices. | ||
29 | - resets : phandle to the parent reset controller. | ||
30 | - reset-names : Associated name must be "miphy-sw-rst". | ||
31 | |||
32 | Optional properties (port (child) node): | ||
33 | - st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This | ||
34 | is not available in all the MiPHY. For example, for STiH407, only the | ||
35 | MiPHY0 has this bit. | ||
36 | - st,osc-force-ext : to select the external oscillator. This can change from | ||
37 | different MiPHY inside the same SoC. | ||
38 | - st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config | ||
39 | register. | ||
40 | - st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive | ||
41 | line). | ||
42 | - st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe). | ||
43 | - st,tx-impedance-comp : to compensate tx impedance avoiding out of range values. | ||
44 | |||
45 | example: | ||
46 | |||
47 | miphy28lp_phy: miphy28lp@9b22000 { | ||
48 | compatible = "st,miphy28lp-phy"; | ||
49 | st,syscfg = <&syscfg_core>; | ||
50 | #address-cells = <1>; | ||
51 | #size-cells = <1>; | ||
52 | ranges; | ||
53 | |||
54 | phy_port0: port@9b22000 { | ||
55 | reg = <0x9b22000 0xff>, | ||
56 | <0x9b09000 0xff>, | ||
57 | <0x9b04000 0xff>, | ||
58 | <0x114 0x4>, /* sysctrl MiPHY cntrl */ | ||
59 | <0x818 0x4>, /* sysctrl MiPHY status*/ | ||
60 | <0xe0 0x4>, /* sysctrl PCIe */ | ||
61 | <0xec 0x4>; /* sysctrl SATA */ | ||
62 | reg-names = "sata-up", | ||
63 | "pcie-up", | ||
64 | "pipew", | ||
65 | "miphy-ctrl-glue", | ||
66 | "miphy-status-glue", | ||
67 | "pcie-glue", | ||
68 | "sata-glue"; | ||
69 | #phy-cells = <1>; | ||
70 | st,osc-rdy; | ||
71 | reset-names = "miphy-sw-rst"; | ||
72 | resets = <&softreset STIH407_MIPHY0_SOFTRESET>; | ||
73 | }; | ||
74 | |||
75 | phy_port1: port@9b2a000 { | ||
76 | reg = <0x9b2a000 0xff>, | ||
77 | <0x9b19000 0xff>, | ||
78 | <0x9b14000 0xff>, | ||
79 | <0x118 0x4>, | ||
80 | <0x81c 0x4>, | ||
81 | <0xe4 0x4>, | ||
82 | <0xf0 0x4>; | ||
83 | reg-names = "sata-up", | ||
84 | "pcie-up", | ||
85 | "pipew", | ||
86 | "miphy-ctrl-glue", | ||
87 | "miphy-status-glue", | ||
88 | "pcie-glue", | ||
89 | "sata-glue"; | ||
90 | #phy-cells = <1>; | ||
91 | st,osc-force-ext; | ||
92 | reset-names = "miphy-sw-rst"; | ||
93 | resets = <&softreset STIH407_MIPHY1_SOFTRESET>; | ||
94 | }; | ||
95 | |||
96 | phy_port2: port@8f95000 { | ||
97 | reg = <0x8f95000 0xff>, | ||
98 | <0x8f90000 0xff>, | ||
99 | <0x11c 0x4>, | ||
100 | <0x820 0x4>; | ||
101 | reg-names = "pipew", | ||
102 | "usb3-up", | ||
103 | "miphy-ctrl-glue", | ||
104 | "miphy-status-glue"; | ||
105 | #phy-cells = <1>; | ||
106 | reset-names = "miphy-sw-rst"; | ||
107 | resets = <&softreset STIH407_MIPHY2_SOFTRESET>; | ||
108 | }; | ||
109 | }; | ||
110 | |||
111 | |||
112 | Specifying phy control of devices | ||
113 | ================================= | ||
114 | |||
115 | Device nodes should specify the configuration required in their "phys" | ||
116 | property, containing a phandle to the miphy device node and an index | ||
117 | specifying which configuration to use, as described in phy-bindings.txt. | ||
118 | |||
119 | example: | ||
120 | sata0: sata@9b20000 { | ||
121 | ... | ||
122 | phys = <&phy_port0 PHY_TYPE_SATA>; | ||
123 | ... | ||
124 | }; | ||
125 | |||
126 | Macro definitions for the supported miphy configuration can be found in: | ||
127 | |||
128 | include/dt-bindings/phy/phy-miphy28lp.h | ||
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt b/Documentation/devicetree/bindings/phy/phy-mvebu.txt new file mode 100644 index 000000000000..f95b6260a3b3 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt | |||
@@ -0,0 +1,43 @@ | |||
1 | * Marvell MVEBU SATA PHY | ||
2 | |||
3 | Power control for the SATA phy found on Marvell MVEBU SoCs. | ||
4 | |||
5 | This document extends the binding described in phy-bindings.txt | ||
6 | |||
7 | Required properties : | ||
8 | |||
9 | - reg : Offset and length of the register set for the SATA device | ||
10 | - compatible : Should be "marvell,mvebu-sata-phy" | ||
11 | - clocks : phandle of clock and specifier that supplies the device | ||
12 | - clock-names : Should be "sata" | ||
13 | |||
14 | Example: | ||
15 | sata-phy@84000 { | ||
16 | compatible = "marvell,mvebu-sata-phy"; | ||
17 | reg = <0x84000 0x0334>; | ||
18 | clocks = <&gate_clk 15>; | ||
19 | clock-names = "sata"; | ||
20 | #phy-cells = <0>; | ||
21 | status = "ok"; | ||
22 | }; | ||
23 | |||
24 | Armada 375 USB cluster | ||
25 | ---------------------- | ||
26 | |||
27 | Armada 375 comes with an USB2 host and device controller and an USB3 | ||
28 | controller. The USB cluster control register allows to manage common | ||
29 | features of both USB controllers. | ||
30 | |||
31 | Required properties: | ||
32 | |||
33 | - compatible: "marvell,armada-375-usb-cluster" | ||
34 | - reg: Should contain usb cluster register location and length. | ||
35 | - #phy-cells : from the generic phy bindings, must be 1. Possible | ||
36 | values are 1 (USB2), 2 (USB3). | ||
37 | |||
38 | Example: | ||
39 | usbcluster: usb-cluster@18400 { | ||
40 | compatible = "marvell,armada-375-usb-cluster"; | ||
41 | reg = <0x18400 0x4>; | ||
42 | #phy-cells = <1> | ||
43 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt new file mode 100644 index 000000000000..1ef8228db73b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | ST STiH407 USB PHY controller | ||
2 | |||
3 | This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3 | ||
4 | host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : should be "st,stih407-usb2-phy" | ||
8 | - reg : contain the offset and length of the system configuration registers | ||
9 | used as glue logic to control & parameter phy | ||
10 | - reg-names : the names of the system configuration registers in "reg", should be "param" and "reg" | ||
11 | - st,syscfg : sysconfig register to manage phy parameter at driver level | ||
12 | - resets : list of phandle and reset specifier pairs. There should be two entries, one | ||
13 | for the whole phy and one for the port | ||
14 | - reset-names : list of reset signal names. Should be "global" and "port" | ||
15 | See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt | ||
16 | See: Documentation/devicetree/bindings/reset/reset.txt | ||
17 | |||
18 | Example: | ||
19 | |||
20 | usb2_picophy0: usbpicophy@f8 { | ||
21 | compatible = "st,stih407-usb2-phy"; | ||
22 | reg = <0xf8 0x04>, /* syscfg 5062 */ | ||
23 | <0xf4 0x04>; /* syscfg 5061 */ | ||
24 | reg-names = "param", "ctrl"; | ||
25 | #phy-cells = <0>; | ||
26 | st,syscfg = <&syscfg_core>; | ||
27 | resets = <&softreset STIH407_PICOPHY_SOFTRESET>, | ||
28 | <&picophyreset STIH407_PICOPHY0_RESET>; | ||
29 | reset-names = "global", "port"; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt new file mode 100644 index 000000000000..00944a05ee6b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | STMicroelectronics STiH41x USB PHY binding | ||
2 | ------------------------------------------ | ||
3 | |||
4 | This file contains documentation for the usb phy found in STiH415/6 SoCs from | ||
5 | STMicroelectronics. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : should be "st,stih416-usb-phy" or "st,stih415-usb-phy" | ||
9 | - st,syscfg : should be a phandle of the syscfg node | ||
10 | - clock-names : must contain "osc_phy" | ||
11 | - clocks : must contain an entry for each name in clock-names. | ||
12 | See: Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
13 | - #phy-cells : must be 0 for this phy | ||
14 | See: Documentation/devicetree/bindings/phy/phy-bindings.txt | ||
15 | |||
16 | Example: | ||
17 | |||
18 | usb2_phy: usb2phy@0 { | ||
19 | compatible = "st,stih416-usb-phy"; | ||
20 | #phy-cell = <0>; | ||
21 | st,syscfg = <&syscfg_rear>; | ||
22 | clocks = <&clk_sysin>; | ||
23 | clock-names = "osc_phy"; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt new file mode 100644 index 000000000000..86f2dbe07ed4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | Qualcomm DWC3 HS AND SS PHY CONTROLLER | ||
2 | -------------------------------------- | ||
3 | |||
4 | DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer | ||
5 | controllers. Each DWC3 PHY controller should have its own node. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: should contain one of the following: | ||
9 | - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller | ||
10 | - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller | ||
11 | - reg: offset and length of the DWC3 PHY controller register set | ||
12 | - #phy-cells: must be zero | ||
13 | - clocks: a list of phandles and clock-specifier pairs, one for each entry in | ||
14 | clock-names. | ||
15 | - clock-names: Should contain "ref" for the PHY reference clock | ||
16 | |||
17 | Optional clocks: | ||
18 | "xo" External reference clock | ||
19 | |||
20 | Example: | ||
21 | phy@100f8800 { | ||
22 | compatible = "qcom,dwc3-hs-usb-phy"; | ||
23 | reg = <0x100f8800 0x30>; | ||
24 | clocks = <&gcc USB30_0_UTMI_CLK>; | ||
25 | clock-names = "ref"; | ||
26 | #phy-cells = <0>; | ||
27 | |||
28 | status = "ok"; | ||
29 | }; | ||
30 | |||
31 | phy@100f8830 { | ||
32 | compatible = "qcom,dwc3-ss-usb-phy"; | ||
33 | reg = <0x100f8830 0x30>; | ||
34 | clocks = <&gcc USB30_0_MASTER_CLK>; | ||
35 | clock-names = "ref"; | ||
36 | #phy-cells = <0>; | ||
37 | |||
38 | status = "ok"; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt new file mode 100644 index 000000000000..00fc52a034b7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt | |||
@@ -0,0 +1,51 @@ | |||
1 | * Renesas R-Car generation 2 USB PHY | ||
2 | |||
3 | This file provides information on what the device node for the R-Car generation | ||
4 | 2 USB PHY contains. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. | ||
8 | "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. | ||
9 | - reg: offset and length of the register block. | ||
10 | - #address-cells: number of address cells for the USB channel subnodes, must | ||
11 | be <1>. | ||
12 | - #size-cells: number of size cells for the USB channel subnodes, must be <0>. | ||
13 | - clocks: clock phandle and specifier pair. | ||
14 | - clock-names: string, clock input name, must be "usbhs". | ||
15 | |||
16 | The USB PHY device tree node should have the subnodes corresponding to the USB | ||
17 | channels. These subnodes must contain the following properties: | ||
18 | - reg: the USB controller selector; see the table below for the values. | ||
19 | - #phy-cells: see phy-bindings.txt in the same directory, must be <1>. | ||
20 | |||
21 | The phandle's argument in the PHY specifier is the USB controller selector for | ||
22 | the USB channel; see the selector meanings below: | ||
23 | |||
24 | +-----------+---------------+---------------+ | ||
25 | |\ Selector | | | | ||
26 | + --------- + 0 | 1 | | ||
27 | | Channel \| | | | ||
28 | +-----------+---------------+---------------+ | ||
29 | | 0 | PCI EHCI/OHCI | HS-USB | | ||
30 | | 2 | PCI EHCI/OHCI | xHCI | | ||
31 | +-----------+---------------+---------------+ | ||
32 | |||
33 | Example (Lager board): | ||
34 | |||
35 | usb-phy@e6590100 { | ||
36 | compatible = "renesas,usb-phy-r8a7790"; | ||
37 | reg = <0 0xe6590100 0 0x100>; | ||
38 | #address-cells = <1>; | ||
39 | #size-cells = <0>; | ||
40 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; | ||
41 | clock-names = "usbhs"; | ||
42 | |||
43 | usb-channel@0 { | ||
44 | reg = <0>; | ||
45 | #phy-cells = <1>; | ||
46 | }; | ||
47 | usb-channel@2 { | ||
48 | reg = <2>; | ||
49 | #phy-cells = <1>; | ||
50 | }; | ||
51 | }; | ||
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index 7a6feea2a48b..d5bad920827f 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt | |||
@@ -17,8 +17,11 @@ Samsung EXYNOS SoC series Display Port PHY | |||
17 | ------------------------------------------------- | 17 | ------------------------------------------------- |
18 | 18 | ||
19 | Required properties: | 19 | Required properties: |
20 | - compatible : should be "samsung,exynos5250-dp-video-phy"; | 20 | - compatible : should be one of the following supported values: |
21 | - reg : offset and length of the Display Port PHY register set; | 21 | - "samsung,exynos5250-dp-video-phy" |
22 | - "samsung,exynos5420-dp-video-phy" | ||
23 | - samsung,pmu-syscon: phandle for PMU system controller interface, used to | ||
24 | control pmu registers for power isolation. | ||
22 | - #phy-cells : from the generic PHY bindings, must be 0; | 25 | - #phy-cells : from the generic PHY bindings, must be 0; |
23 | 26 | ||
24 | Samsung S5P/EXYNOS SoC series USB PHY | 27 | Samsung S5P/EXYNOS SoC series USB PHY |
@@ -125,6 +128,7 @@ Required properties: | |||
125 | - compatible : Should be set to one of the following supported values: | 128 | - compatible : Should be set to one of the following supported values: |
126 | - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, | 129 | - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, |
127 | - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. | 130 | - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. |
131 | - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC. | ||
128 | - reg : Register offset and length of USB DRD PHY register set; | 132 | - reg : Register offset and length of USB DRD PHY register set; |
129 | - clocks: Clock IDs array as required by the controller | 133 | - clocks: Clock IDs array as required by the controller |
130 | - clock-names: names of clocks correseponding to IDs in the clock property; | 134 | - clock-names: names of clocks correseponding to IDs in the clock property; |
@@ -135,6 +139,11 @@ Required properties: | |||
135 | PHY operations, associated by phy name. It is used to | 139 | PHY operations, associated by phy name. It is used to |
136 | determine bit values for clock settings register. | 140 | determine bit values for clock settings register. |
137 | For Exynos5420 this is given as 'sclk_usbphy30' in CMU. | 141 | For Exynos5420 this is given as 'sclk_usbphy30' in CMU. |
142 | - optional clocks: Exynos7 SoC has now following additional | ||
143 | gate clocks available: | ||
144 | - phy_pipe: for PIPE3 phy | ||
145 | - phy_utmi: for UTMI+ phy | ||
146 | - itp: for ITP generation | ||
138 | - samsung,pmu-syscon: phandle for PMU system controller interface, used to | 147 | - samsung,pmu-syscon: phandle for PMU system controller interface, used to |
139 | control pmu registers for power isolation. | 148 | control pmu registers for power isolation. |
140 | - #phy-cells : from the generic PHY bindings, must be 1; | 149 | - #phy-cells : from the generic PHY bindings, must be 1; |
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt index 02ab5ab198a4..b7a93e80a302 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt | |||
@@ -19,6 +19,7 @@ such as pull-up, multi drive, etc. | |||
19 | 19 | ||
20 | Required properties for iomux controller: | 20 | Required properties for iomux controller: |
21 | - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" | 21 | - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl" |
22 | or "atmel,sama5d3-pinctrl" | ||
22 | - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be | 23 | - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be |
23 | configured in this periph mode. All the periph and bank need to be describe. | 24 | configured in this periph mode. All the periph and bank need to be describe. |
24 | 25 | ||
@@ -85,13 +86,20 @@ Required properties for pin configuration node: | |||
85 | PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... | 86 | PIN_BANK 0 is pioA, PIN_BANK 1 is pioB... |
86 | 87 | ||
87 | Bits used for CONFIG: | 88 | Bits used for CONFIG: |
88 | PULL_UP (1 << 0): indicate this pin need a pull up. | 89 | PULL_UP (1 << 0): indicate this pin needs a pull up. |
89 | MULTIDRIVE (1 << 1): indicate this pin need to be configured as multidrive. | 90 | MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive. |
90 | DEGLITCH (1 << 2): indicate this pin need deglitch. | 91 | Multi-drive is equivalent to open-drain type output. |
91 | PULL_DOWN (1 << 3): indicate this pin need a pull down. | 92 | DEGLITCH (1 << 2): indicate this pin needs deglitch. |
92 | DIS_SCHMIT (1 << 4): indicate this pin need to disable schmit trigger. | 93 | PULL_DOWN (1 << 3): indicate this pin needs a pull down. |
93 | DEBOUNCE (1 << 16): indicate this pin need debounce. | 94 | DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger. |
94 | DEBOUNCE_VAL (0x3fff << 17): debounce val. | 95 | DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the |
96 | following values: | ||
97 | 00 - No change (reset state value kept) | ||
98 | 01 - Low | ||
99 | 10 - Medium | ||
100 | 11 - High | ||
101 | DEBOUNCE (1 << 16): indicate this pin needs debounce. | ||
102 | DEBOUNCE_VAL (0x3fff << 17): debounce value. | ||
95 | 103 | ||
96 | NOTE: | 104 | NOTE: |
97 | Some requirements for using atmel,at91rm9200-pinctrl binding: | 105 | Some requirements for using atmel,at91rm9200-pinctrl binding: |
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt index a186181c402b..51b943cc9770 100644 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt | |||
@@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
9 | common pinctrl bindings used by client devices, including the meaning of the | 9 | common pinctrl bindings used by client devices, including the meaning of the |
10 | phrase "pin configuration node". | 10 | phrase "pin configuration node". |
11 | 11 | ||
12 | TZ1090-PDC's pin configuration nodes act as a container for an abitrary number | 12 | TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number |
13 | of subnodes. Each of these subnodes represents some desired configuration for a | 13 | of subnodes. Each of these subnodes represents some desired configuration for a |
14 | pin, a group, or a list of pins or groups. This configuration can include the | 14 | pin, a group, or a list of pins or groups. This configuration can include the |
15 | mux function to select on those pin(s)/group(s), and various pin configuration | 15 | mux function to select on those pin(s)/group(s), and various pin configuration |
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt index 4b27c99f7f9d..509faa87ad0e 100644 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt | |||
@@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
9 | common pinctrl bindings used by client devices, including the meaning of the | 9 | common pinctrl bindings used by client devices, including the meaning of the |
10 | phrase "pin configuration node". | 10 | phrase "pin configuration node". |
11 | 11 | ||
12 | TZ1090's pin configuration nodes act as a container for an abitrary number of | 12 | TZ1090's pin configuration nodes act as a container for an arbitrary number of |
13 | subnodes. Each of these subnodes represents some desired configuration for a | 13 | subnodes. Each of these subnodes represents some desired configuration for a |
14 | pin, a group, or a list of pins or groups. This configuration can include the | 14 | pin, a group, or a list of pins or groups. This configuration can include the |
15 | mux function to select on those pin(s)/group(s), and various pin configuration | 15 | mux function to select on those pin(s)/group(s), and various pin configuration |
@@ -67,7 +67,7 @@ Valid values for pin and group names are: | |||
67 | They also all support the some form of muxing. Any pins which are contained | 67 | They also all support the some form of muxing. Any pins which are contained |
68 | in one of the mux groups (see below) can be muxed only to the functions | 68 | in one of the mux groups (see below) can be muxed only to the functions |
69 | supported by the mux group. All other pins can be muxed to the "perip" | 69 | supported by the mux group. All other pins can be muxed to the "perip" |
70 | function which which enables them with their intended peripheral. | 70 | function which enables them with their intended peripheral. |
71 | 71 | ||
72 | Different pins in the same mux group cannot be muxed to different functions, | 72 | Different pins in the same mux group cannot be muxed to different functions, |
73 | however it is possible to mux only a subset of the pins in a mux group to a | 73 | however it is possible to mux only a subset of the pins in a mux group to a |
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt index daa768956069..ac4da9fe07bd 100644 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt | |||
@@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
9 | common pinctrl bindings used by client devices, including the meaning of the | 9 | common pinctrl bindings used by client devices, including the meaning of the |
10 | phrase "pin configuration node". | 10 | phrase "pin configuration node". |
11 | 11 | ||
12 | Lantiq's pin configuration nodes act as a container for an abitrary number of | 12 | Lantiq's pin configuration nodes act as a container for an arbitrary number of |
13 | subnodes. Each of these subnodes represents some desired configuration for a | 13 | subnodes. Each of these subnodes represents some desired configuration for a |
14 | pin, a group, or a list of pins or groups. This configuration can include the | 14 | pin, a group, or a list of pins or groups. This configuration can include the |
15 | mux function to select on those group(s), and two pin configuration parameters: | 15 | mux function to select on those group(s), and two pin configuration parameters: |
diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt index b5469db1d7ad..e89b4677567d 100644 --- a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt | |||
@@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
9 | common pinctrl bindings used by client devices, including the meaning of the | 9 | common pinctrl bindings used by client devices, including the meaning of the |
10 | phrase "pin configuration node". | 10 | phrase "pin configuration node". |
11 | 11 | ||
12 | Lantiq's pin configuration nodes act as a container for an abitrary number of | 12 | Lantiq's pin configuration nodes act as a container for an arbitrary number of |
13 | subnodes. Each of these subnodes represents some desired configuration for a | 13 | subnodes. Each of these subnodes represents some desired configuration for a |
14 | pin, a group, or a list of pins or groups. This configuration can include the | 14 | pin, a group, or a list of pins or groups. This configuration can include the |
15 | mux function to select on those group(s), and two pin configuration parameters: | 15 | mux function to select on those group(s), and two pin configuration parameters: |
diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt new file mode 100644 index 000000000000..17e7240c6998 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | |||
@@ -0,0 +1,96 @@ | |||
1 | == Amlogic Meson pinmux controller == | ||
2 | |||
3 | Required properties for the root node: | ||
4 | - compatible: "amlogic,meson8-pinctrl" | ||
5 | - reg: address and size of registers controlling irq functionality | ||
6 | |||
7 | === GPIO sub-nodes === | ||
8 | |||
9 | The 2 power domains of the controller (regular and always-on) are | ||
10 | represented as sub-nodes and each of them acts as a GPIO controller. | ||
11 | |||
12 | Required properties for sub-nodes are: | ||
13 | - reg: should contain address and size for mux, pull-enable, pull and | ||
14 | gpio register sets | ||
15 | - reg-names: an array of strings describing the "reg" entries. Must | ||
16 | contain "mux", "pull" and "gpio". "pull-enable" is optional and | ||
17 | when it is missing the "pull" registers are used instead | ||
18 | - gpio-controller: identifies the node as a gpio controller | ||
19 | - #gpio-cells: must be 2 | ||
20 | |||
21 | Valid sub-node names are: | ||
22 | - "banks" for the regular domain | ||
23 | - "ao-bank" for the always-on domain | ||
24 | |||
25 | === Other sub-nodes === | ||
26 | |||
27 | Child nodes without the "gpio-controller" represent some desired | ||
28 | configuration for a pin or a group. Those nodes can be pinmux nodes or | ||
29 | configuration nodes. | ||
30 | |||
31 | Required properties for pinmux nodes are: | ||
32 | - groups: a list of pinmux groups. The list of all available groups | ||
33 | depends on the SoC and can be found in driver sources. | ||
34 | - function: the name of a function to activate for the specified set | ||
35 | of groups. The list of all available functions depends on the SoC | ||
36 | and can be found in driver sources. | ||
37 | |||
38 | Required properties for configuration nodes: | ||
39 | - pins: a list of pin names | ||
40 | |||
41 | Configuration nodes support the generic properties "bias-disable", | ||
42 | "bias-pull-up" and "bias-pull-down", described in file | ||
43 | pinctrl-bindings.txt | ||
44 | |||
45 | === Example === | ||
46 | |||
47 | pinctrl: pinctrl@c1109880 { | ||
48 | compatible = "amlogic,meson8-pinctrl"; | ||
49 | reg = <0xc1109880 0x10>; | ||
50 | #address-cells = <1>; | ||
51 | #size-cells = <1>; | ||
52 | ranges; | ||
53 | |||
54 | gpio: banks@c11080b0 { | ||
55 | reg = <0xc11080b0 0x28>, | ||
56 | <0xc11080e8 0x18>, | ||
57 | <0xc1108120 0x18>, | ||
58 | <0xc1108030 0x30>; | ||
59 | reg-names = "mux", "pull", "pull-enable", "gpio"; | ||
60 | gpio-controller; | ||
61 | #gpio-cells = <2>; | ||
62 | }; | ||
63 | |||
64 | gpio_ao: ao-bank@c1108030 { | ||
65 | reg = <0xc8100014 0x4>, | ||
66 | <0xc810002c 0x4>, | ||
67 | <0xc8100024 0x8>; | ||
68 | reg-names = "mux", "pull", "gpio"; | ||
69 | gpio-controller; | ||
70 | #gpio-cells = <2>; | ||
71 | }; | ||
72 | |||
73 | nand { | ||
74 | mux { | ||
75 | groups = "nand_io", "nand_io_ce0", "nand_io_ce1", | ||
76 | "nand_io_rb0", "nand_ale", "nand_cle", | ||
77 | "nand_wen_clk", "nand_ren_clk", "nand_dqs", | ||
78 | "nand_ce2", "nand_ce3"; | ||
79 | function = "nand"; | ||
80 | }; | ||
81 | }; | ||
82 | |||
83 | uart_ao_a { | ||
84 | mux { | ||
85 | groups = "uart_tx_ao_a", "uart_rx_ao_a", | ||
86 | "uart_cts_ao_a", "uart_rts_ao_a"; | ||
87 | function = "uart_ao"; | ||
88 | }; | ||
89 | |||
90 | conf { | ||
91 | pins = "GPIOAO_0", "GPIOAO_1", | ||
92 | "GPIOAO_2", "GPIOAO_3"; | ||
93 | bias-disable; | ||
94 | }; | ||
95 | }; | ||
96 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt index 6464bf769460..189814e7cdc7 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt | |||
@@ -10,6 +10,7 @@ Required properties: | |||
10 | - reg: Should contain a list of base address and size pairs for: | 10 | - reg: Should contain a list of base address and size pairs for: |
11 | -- first entry - the drive strength and pad control registers. | 11 | -- first entry - the drive strength and pad control registers. |
12 | -- second entry - the pinmux registers | 12 | -- second entry - the pinmux registers |
13 | -- third entry - the MIPI_PAD_CTRL register | ||
13 | 14 | ||
14 | Tegra124 adds the following optional properties for pin configuration subnodes. | 15 | Tegra124 adds the following optional properties for pin configuration subnodes. |
15 | The macros for options are defined in the | 16 | The macros for options are defined in the |
@@ -91,6 +92,12 @@ Valid values for pin and group names are: | |||
91 | dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg, | 92 | dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg, |
92 | gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4. | 93 | gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4. |
93 | 94 | ||
95 | MIPI pad control groups: | ||
96 | |||
97 | These support only the nvidia,function property. | ||
98 | |||
99 | dsi_b | ||
100 | |||
94 | Valid values for nvidia,functions are: | 101 | Valid values for nvidia,functions are: |
95 | 102 | ||
96 | blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya, | 103 | blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya, |
@@ -101,14 +108,15 @@ Valid values for nvidia,functions are: | |||
101 | sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta, | 108 | sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta, |
102 | uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, | 109 | uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, |
103 | vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1, | 110 | vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1, |
104 | dp, rtck, sys, clk tmds. | 111 | dp, rtck, sys, clk tmds, csi, dsi_b |
105 | 112 | ||
106 | Example: | 113 | Example: |
107 | 114 | ||
108 | pinmux: pinmux { | 115 | pinmux: pinmux { |
109 | compatible = "nvidia,tegra124-pinmux"; | 116 | compatible = "nvidia,tegra124-pinmux"; |
110 | reg = <0x70000868 0x164 /* Pad control registers */ | 117 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ |
111 | 0x70003000 0x434>; /* PinMux registers */ | 118 | <0x0 0x70003000 0x0 0x434>, /* Mux registers */ |
119 | <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */ | ||
112 | }; | 120 | }; |
113 | 121 | ||
114 | Example pinmux entries: | 122 | Example pinmux entries: |
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt index 61e73cde9ae9..3c8ce28baad6 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt | |||
@@ -9,7 +9,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
9 | common pinctrl bindings used by client devices, including the meaning of the | 9 | common pinctrl bindings used by client devices, including the meaning of the |
10 | phrase "pin configuration node". | 10 | phrase "pin configuration node". |
11 | 11 | ||
12 | Tegra's pin configuration nodes act as a container for an abitrary number of | 12 | Tegra's pin configuration nodes act as a container for an arbitrary number of |
13 | subnodes. Each of these subnodes represents some desired configuration for a | 13 | subnodes. Each of these subnodes represents some desired configuration for a |
14 | pin, a group, or a list of pins or groups. This configuration can include the | 14 | pin, a group, or a list of pins or groups. This configuration can include the |
15 | mux function to select on those pin(s)/group(s), and various pin configuration | 15 | mux function to select on those pin(s)/group(s), and various pin configuration |
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index fa40a177164c..47d84b6ee91b 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt | |||
@@ -127,6 +127,24 @@ whether there is any interaction between the child and intermediate parent | |||
127 | nodes, is again defined entirely by the binding for the individual pin | 127 | nodes, is again defined entirely by the binding for the individual pin |
128 | controller device. | 128 | controller device. |
129 | 129 | ||
130 | == Generic pin multiplexing node content == | ||
131 | |||
132 | pin multiplexing nodes: | ||
133 | |||
134 | function - the mux function to select | ||
135 | groups - the list of groups to select with this function | ||
136 | |||
137 | Example: | ||
138 | |||
139 | state_0_node_a { | ||
140 | function = "uart0"; | ||
141 | groups = "u0rxtx", "u0rtscts"; | ||
142 | }; | ||
143 | state_1_node_a { | ||
144 | function = "spi0"; | ||
145 | groups = "spi0pins"; | ||
146 | }; | ||
147 | |||
130 | == Generic pin configuration node content == | 148 | == Generic pin configuration node content == |
131 | 149 | ||
132 | Many data items that are represented in a pin configuration node are common | 150 | Many data items that are represented in a pin configuration node are common |
@@ -139,8 +157,12 @@ structure of the DT nodes that contain these properties. | |||
139 | Supported generic properties are: | 157 | Supported generic properties are: |
140 | 158 | ||
141 | pins - the list of pins that properties in the node | 159 | pins - the list of pins that properties in the node |
142 | apply to | 160 | apply to (either this or "group" has to be |
143 | function - the mux function to select | 161 | specified) |
162 | group - the group to apply the properties to, if the driver | ||
163 | supports configuration of whole groups rather than | ||
164 | individual pins (either this or "pins" has to be | ||
165 | specified) | ||
144 | bias-disable - disable any pin bias | 166 | bias-disable - disable any pin bias |
145 | bias-high-impedance - high impedance mode ("third-state", "floating") | 167 | bias-high-impedance - high impedance mode ("third-state", "floating") |
146 | bias-bus-hold - latch weakly | 168 | bias-bus-hold - latch weakly |
@@ -163,6 +185,21 @@ output-low - set the pin to output mode with low level | |||
163 | output-high - set the pin to output mode with high level | 185 | output-high - set the pin to output mode with high level |
164 | slew-rate - set the slew rate | 186 | slew-rate - set the slew rate |
165 | 187 | ||
188 | For example: | ||
189 | |||
190 | state_0_node_a { | ||
191 | pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ | ||
192 | bias-pull-up; | ||
193 | }; | ||
194 | state_1_node_a { | ||
195 | pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ | ||
196 | output-high; | ||
197 | }; | ||
198 | state_2_node_a { | ||
199 | group = "foo-group"; | ||
200 | bias-pull-up; | ||
201 | }; | ||
202 | |||
166 | Some of the generic properties take arguments. For those that do, the | 203 | Some of the generic properties take arguments. For those that do, the |
167 | arguments are described below. | 204 | arguments are described below. |
168 | 205 | ||
@@ -170,15 +207,6 @@ arguments are described below. | |||
170 | binding for the hardware defines: | 207 | binding for the hardware defines: |
171 | - Whether the entries are integers or strings, and their meaning. | 208 | - Whether the entries are integers or strings, and their meaning. |
172 | 209 | ||
173 | - function takes a list of function names/IDs as a required argument. The | ||
174 | specific binding for the hardware defines: | ||
175 | - Whether the entries are integers or strings, and their meaning. | ||
176 | - Whether only a single entry is allowed (which is applied to all entries | ||
177 | in the pins property), or whether there may alternatively be one entry per | ||
178 | entry in the pins property, in which case the list lengths must match, and | ||
179 | for each list index i, the function at list index i is applied to the pin | ||
180 | at list index i. | ||
181 | |||
182 | - bias-pull-up, -down and -pin-default take as optional argument on hardware | 210 | - bias-pull-up, -down and -pin-default take as optional argument on hardware |
183 | supporting it the pull strength in Ohm. bias-disable will disable the pull. | 211 | supporting it the pull strength in Ohm. bias-disable will disable the pull. |
184 | 212 | ||
@@ -188,4 +216,4 @@ arguments are described below. | |||
188 | or 0 to disable debouncing | 216 | or 0 to disable debouncing |
189 | 217 | ||
190 | More in-depth documentation on these parameters can be found in | 218 | More in-depth documentation on these parameters can be found in |
191 | <include/linux/pinctrl/pinconfig-generic.h> | 219 | <include/linux/pinctrl/pinconf-generic.h> |
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt index c596a6ad3285..5f55be59d914 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt | |||
@@ -13,7 +13,7 @@ Optional properties: | |||
13 | Please refer to pinctrl-bindings.txt in this directory for details of the common | 13 | Please refer to pinctrl-bindings.txt in this directory for details of the common |
14 | pinctrl bindings used by client devices. | 14 | pinctrl bindings used by client devices. |
15 | 15 | ||
16 | SiRFprimaII's pinmux nodes act as a container for an abitrary number of subnodes. | 16 | SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes. |
17 | Each of these subnodes represents some desired configuration for a group of pins. | 17 | Each of these subnodes represents some desired configuration for a group of pins. |
18 | 18 | ||
19 | Required subnode-properties: | 19 | Required subnode-properties: |
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt index b4480d5c3aca..458615596946 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt | |||
@@ -32,7 +32,7 @@ Required properties: | |||
32 | Please refer to pinctrl-bindings.txt in this directory for details of the common | 32 | Please refer to pinctrl-bindings.txt in this directory for details of the common |
33 | pinctrl bindings used by client devices. | 33 | pinctrl bindings used by client devices. |
34 | 34 | ||
35 | SPEAr's pinmux nodes act as a container for an abitrary number of subnodes. Each | 35 | SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each |
36 | of these subnodes represents muxing for a pin, a group, or a list of pins or | 36 | of these subnodes represents muxing for a pin, a group, or a list of pins or |
37 | groups. | 37 | groups. |
38 | 38 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt index 92fae82f35f2..a7bde64798c7 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt | |||
@@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
18 | common pinctrl bindings used by client devices, including the meaning of the | 18 | common pinctrl bindings used by client devices, including the meaning of the |
19 | phrase "pin configuration node". | 19 | phrase "pin configuration node". |
20 | 20 | ||
21 | Qualcomm's pin configuration nodes act as a container for an abitrary number of | 21 | Qualcomm's pin configuration nodes act as a container for an arbitrary number of |
22 | subnodes. Each of these subnodes represents some desired configuration for a | 22 | subnodes. Each of these subnodes represents some desired configuration for a |
23 | pin, a group, or a list of pins or groups. This configuration can include the | 23 | pin, a group, or a list of pins or groups. This configuration can include the |
24 | mux function to select on those pin(s)/group(s), and various pin configuration | 24 | mux function to select on those pin(s)/group(s), and various pin configuration |
@@ -50,7 +50,7 @@ Valid values for function are: | |||
50 | gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, | 50 | gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, |
51 | gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, | 51 | gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, |
52 | gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, | 52 | gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, |
53 | riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, | 53 | riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold |
54 | 54 | ||
55 | Example: | 55 | Example: |
56 | 56 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt new file mode 100644 index 000000000000..c4ea61ac56f2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt | |||
@@ -0,0 +1,179 @@ | |||
1 | Qualcomm APQ8084 TLMM block | ||
2 | |||
3 | This binding describes the Top Level Mode Multiplexer block found in the | ||
4 | MSM8960 platform. | ||
5 | |||
6 | - compatible: | ||
7 | Usage: required | ||
8 | Value type: <string> | ||
9 | Definition: must be "qcom,apq8084-pinctrl" | ||
10 | |||
11 | - reg: | ||
12 | Usage: required | ||
13 | Value type: <prop-encoded-array> | ||
14 | Definition: the base address and size of the TLMM register space. | ||
15 | |||
16 | - interrupts: | ||
17 | Usage: required | ||
18 | Value type: <prop-encoded-array> | ||
19 | Definition: should specify the TLMM summary IRQ. | ||
20 | |||
21 | - interrupt-controller: | ||
22 | Usage: required | ||
23 | Value type: <none> | ||
24 | Definition: identifies this node as an interrupt controller | ||
25 | |||
26 | - #interrupt-cells: | ||
27 | Usage: required | ||
28 | Value type: <u32> | ||
29 | Definition: must be 2. Specifying the pin number and flags, as defined | ||
30 | in <dt-bindings/interrupt-controller/irq.h> | ||
31 | |||
32 | - gpio-controller: | ||
33 | Usage: required | ||
34 | Value type: <none> | ||
35 | Definition: identifies this node as a gpio controller | ||
36 | |||
37 | - #gpio-cells: | ||
38 | Usage: required | ||
39 | Value type: <u32> | ||
40 | Definition: must be 2. Specifying the pin number and flags, as defined | ||
41 | in <dt-bindings/gpio/gpio.h> | ||
42 | |||
43 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | ||
44 | a general description of GPIO and interrupt bindings. | ||
45 | |||
46 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
47 | common pinctrl bindings used by client devices, including the meaning of the | ||
48 | phrase "pin configuration node". | ||
49 | |||
50 | The pin configuration nodes act as a container for an arbitrary number of | ||
51 | subnodes. Each of these subnodes represents some desired configuration for a | ||
52 | pin, a group, or a list of pins or groups. This configuration can include the | ||
53 | mux function to select on those pin(s)/group(s), and various pin configuration | ||
54 | parameters, such as pull-up, drive strength, etc. | ||
55 | |||
56 | |||
57 | PIN CONFIGURATION NODES: | ||
58 | |||
59 | The name of each subnode is not important; all subnodes should be enumerated | ||
60 | and processed purely based on their content. | ||
61 | |||
62 | Each subnode only affects those parameters that are explicitly listed. In | ||
63 | other words, a subnode that lists a mux function but no pin configuration | ||
64 | parameters implies no information about any pin configuration parameters. | ||
65 | Similarly, a pin subnode that describes a pullup parameter implies no | ||
66 | information about e.g. the mux function. | ||
67 | |||
68 | |||
69 | The following generic properties as defined in pinctrl-bindings.txt are valid | ||
70 | to specify in a pin configuration subnode: | ||
71 | |||
72 | - pins: | ||
73 | Usage: required | ||
74 | Value type: <string-array> | ||
75 | Definition: List of gpio pins affected by the properties specified in | ||
76 | this subnode. Valid pins are: | ||
77 | gpio0-gpio146, | ||
78 | sdc1_clk, | ||
79 | sdc1_cmd, | ||
80 | sdc1_data | ||
81 | sdc2_clk, | ||
82 | sdc2_cmd, | ||
83 | sdc2_data | ||
84 | |||
85 | - function: | ||
86 | Usage: required | ||
87 | Value type: <string> | ||
88 | Definition: Specify the alternative function to be configured for the | ||
89 | specified pins. Functions are only valid for gpio pins. | ||
90 | Valid values are: | ||
91 | adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, | ||
92 | blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, | ||
93 | blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, | ||
94 | blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, | ||
95 | blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, | ||
96 | blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, | ||
97 | blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, | ||
98 | blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, | ||
99 | blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, | ||
100 | blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, | ||
101 | blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, | ||
102 | cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1, | ||
103 | cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, | ||
104 | edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i | ||
105 | gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio, | ||
106 | hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic, | ||
107 | ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, | ||
108 | pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s, | ||
109 | qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n, | ||
110 | sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus, | ||
111 | spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1, | ||
112 | tsif2, uim, uim_batt_alarm | ||
113 | |||
114 | - bias-disable: | ||
115 | Usage: optional | ||
116 | Value type: <none> | ||
117 | Definition: The specified pins should be configued as no pull. | ||
118 | |||
119 | - bias-pull-down: | ||
120 | Usage: optional | ||
121 | Value type: <none> | ||
122 | Definition: The specified pins should be configued as pull down. | ||
123 | |||
124 | - bias-pull-up: | ||
125 | Usage: optional | ||
126 | Value type: <none> | ||
127 | Definition: The specified pins should be configued as pull up. | ||
128 | |||
129 | - output-high: | ||
130 | Usage: optional | ||
131 | Value type: <none> | ||
132 | Definition: The specified pins are configured in output mode, driven | ||
133 | high. | ||
134 | Not valid for sdc pins. | ||
135 | |||
136 | - output-low: | ||
137 | Usage: optional | ||
138 | Value type: <none> | ||
139 | Definition: The specified pins are configured in output mode, driven | ||
140 | low. | ||
141 | Not valid for sdc pins. | ||
142 | |||
143 | - drive-strength: | ||
144 | Usage: optional | ||
145 | Value type: <u32> | ||
146 | Definition: Selects the drive strength for the specified pins, in mA. | ||
147 | Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 | ||
148 | |||
149 | Example: | ||
150 | |||
151 | tlmm: pinctrl@fd510000 { | ||
152 | compatible = "qcom,apq8084-pinctrl"; | ||
153 | reg = <0xfd510000 0x4000>; | ||
154 | |||
155 | gpio-controller; | ||
156 | #gpio-cells = <2>; | ||
157 | interrupt-controller; | ||
158 | #interrupt-cells = <2>; | ||
159 | interrupts = <0 208 0>; | ||
160 | |||
161 | uart2: uart2-default { | ||
162 | mux { | ||
163 | pins = "gpio4", "gpio5"; | ||
164 | function = "blsp_uart2"; | ||
165 | }; | ||
166 | |||
167 | tx { | ||
168 | pins = "gpio4"; | ||
169 | drive-strength = <4>; | ||
170 | bias-disable; | ||
171 | }; | ||
172 | |||
173 | rx { | ||
174 | pins = "gpio5"; | ||
175 | drive-strength = <2>; | ||
176 | bias-pull-up; | ||
177 | }; | ||
178 | }; | ||
179 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt index e33e4dcdce79..6e88e91feb11 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.txt | |||
@@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
18 | common pinctrl bindings used by client devices, including the meaning of the | 18 | common pinctrl bindings used by client devices, including the meaning of the |
19 | phrase "pin configuration node". | 19 | phrase "pin configuration node". |
20 | 20 | ||
21 | Qualcomm's pin configuration nodes act as a container for an abitrary number of | 21 | Qualcomm's pin configuration nodes act as a container for an arbitrary number of |
22 | subnodes. Each of these subnodes represents some desired configuration for a | 22 | subnodes. Each of these subnodes represents some desired configuration for a |
23 | pin, a group, or a list of pins or groups. This configuration can include the | 23 | pin, a group, or a list of pins or groups. This configuration can include the |
24 | mux function to select on those pin(s)/group(s), and various pin configuration | 24 | mux function to select on those pin(s)/group(s), and various pin configuration |
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt index 93b7de91b9f6..eb8d8aa41f20 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.txt | |||
@@ -47,7 +47,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
47 | common pinctrl bindings used by client devices, including the meaning of the | 47 | common pinctrl bindings used by client devices, including the meaning of the |
48 | phrase "pin configuration node". | 48 | phrase "pin configuration node". |
49 | 49 | ||
50 | The pin configuration nodes act as a container for an abitrary number of | 50 | The pin configuration nodes act as a container for an arbitrary number of |
51 | subnodes. Each of these subnodes represents some desired configuration for a | 51 | subnodes. Each of these subnodes represents some desired configuration for a |
52 | pin, a group, or a list of pins or groups. This configuration can include the | 52 | pin, a group, or a list of pins or groups. This configuration can include the |
53 | mux function to select on those pin(s)/group(s), and various pin configuration | 53 | mux function to select on those pin(s)/group(s), and various pin configuration |
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt index d2ea80dc43eb..e4d6a9d20f7d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt | |||
@@ -18,7 +18,7 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
18 | common pinctrl bindings used by client devices, including the meaning of the | 18 | common pinctrl bindings used by client devices, including the meaning of the |
19 | phrase "pin configuration node". | 19 | phrase "pin configuration node". |
20 | 20 | ||
21 | Qualcomm's pin configuration nodes act as a container for an abitrary number of | 21 | Qualcomm's pin configuration nodes act as a container for an arbitrary number of |
22 | subnodes. Each of these subnodes represents some desired configuration for a | 22 | subnodes. Each of these subnodes represents some desired configuration for a |
23 | pin, a group, or a list of pins or groups. This configuration can include the | 23 | pin, a group, or a list of pins or groups. This configuration can include the |
24 | mux function to select on those pin(s)/group(s), and various pin configuration | 24 | mux function to select on those pin(s)/group(s), and various pin configuration |
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt new file mode 100644 index 000000000000..7ed08048516a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | |||
@@ -0,0 +1,215 @@ | |||
1 | Qualcomm PMIC GPIO block | ||
2 | |||
3 | This binding describes the GPIO block(s) found in the 8xxx series of | ||
4 | PMIC's from Qualcomm. | ||
5 | |||
6 | - compatible: | ||
7 | Usage: required | ||
8 | Value type: <string> | ||
9 | Definition: must be one of: | ||
10 | "qcom,pm8018-gpio" | ||
11 | "qcom,pm8038-gpio" | ||
12 | "qcom,pm8058-gpio" | ||
13 | "qcom,pm8917-gpio" | ||
14 | "qcom,pm8921-gpio" | ||
15 | "qcom,pm8941-gpio" | ||
16 | "qcom,pma8084-gpio" | ||
17 | |||
18 | - reg: | ||
19 | Usage: required | ||
20 | Value type: <prop-encoded-array> | ||
21 | Definition: Register base of the GPIO block and length. | ||
22 | |||
23 | - interrupts: | ||
24 | Usage: required | ||
25 | Value type: <prop-encoded-array> | ||
26 | Definition: Must contain an array of encoded interrupt specifiers for | ||
27 | each available GPIO | ||
28 | |||
29 | - gpio-controller: | ||
30 | Usage: required | ||
31 | Value type: <none> | ||
32 | Definition: Mark the device node as a GPIO controller | ||
33 | |||
34 | - #gpio-cells: | ||
35 | Usage: required | ||
36 | Value type: <u32> | ||
37 | Definition: Must be 2; | ||
38 | the first cell will be used to define gpio number and the | ||
39 | second denotes the flags for this gpio | ||
40 | |||
41 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | ||
42 | a general description of GPIO and interrupt bindings. | ||
43 | |||
44 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
45 | common pinctrl bindings used by client devices, including the meaning of the | ||
46 | phrase "pin configuration node". | ||
47 | |||
48 | The pin configuration nodes act as a container for an arbitrary number of | ||
49 | subnodes. Each of these subnodes represents some desired configuration for a | ||
50 | pin or a list of pins. This configuration can include the | ||
51 | mux function to select on those pin(s), and various pin configuration | ||
52 | parameters, as listed below. | ||
53 | |||
54 | |||
55 | SUBNODES: | ||
56 | |||
57 | The name of each subnode is not important; all subnodes should be enumerated | ||
58 | and processed purely based on their content. | ||
59 | |||
60 | Each subnode only affects those parameters that are explicitly listed. In | ||
61 | other words, a subnode that lists a mux function but no pin configuration | ||
62 | parameters implies no information about any pin configuration parameters. | ||
63 | Similarly, a pin subnode that describes a pullup parameter implies no | ||
64 | information about e.g. the mux function. | ||
65 | |||
66 | The following generic properties as defined in pinctrl-bindings.txt are valid | ||
67 | to specify in a pin configuration subnode: | ||
68 | |||
69 | - pins: | ||
70 | Usage: required | ||
71 | Value type: <string-array> | ||
72 | Definition: List of gpio pins affected by the properties specified in | ||
73 | this subnode. Valid pins are: | ||
74 | gpio1-gpio6 for pm8018 | ||
75 | gpio1-gpio12 for pm8038 | ||
76 | gpio1-gpio40 for pm8058 | ||
77 | gpio1-gpio38 for pm8917 | ||
78 | gpio1-gpio44 for pm8921 | ||
79 | gpio1-gpio36 for pm8941 | ||
80 | gpio1-gpio22 for pma8084 | ||
81 | |||
82 | - function: | ||
83 | Usage: required | ||
84 | Value type: <string> | ||
85 | Definition: Specify the alternative function to be configured for the | ||
86 | specified pins. Valid values are: | ||
87 | "normal", | ||
88 | "paired", | ||
89 | "func1", | ||
90 | "func2", | ||
91 | "dtest1", | ||
92 | "dtest2", | ||
93 | "dtest3", | ||
94 | "dtest4" | ||
95 | |||
96 | - bias-disable: | ||
97 | Usage: optional | ||
98 | Value type: <none> | ||
99 | Definition: The specified pins should be configured as no pull. | ||
100 | |||
101 | - bias-pull-down: | ||
102 | Usage: optional | ||
103 | Value type: <none> | ||
104 | Definition: The specified pins should be configured as pull down. | ||
105 | |||
106 | - bias-pull-up: | ||
107 | Usage: optional | ||
108 | Value type: <empty> | ||
109 | Definition: The specified pins should be configured as pull up. | ||
110 | |||
111 | - qcom,pull-up-strength: | ||
112 | Usage: optional | ||
113 | Value type: <u32> | ||
114 | Definition: Specifies the strength to use for pull up, if selected. | ||
115 | Valid values are; as defined in | ||
116 | <dt-bindings/pinctrl/qcom,pmic-gpio.h>: | ||
117 | 1: 30uA (PMIC_GPIO_PULL_UP_30) | ||
118 | 2: 1.5uA (PMIC_GPIO_PULL_UP_1P5) | ||
119 | 3: 31.5uA (PMIC_GPIO_PULL_UP_31P5) | ||
120 | 4: 1.5uA + 30uA boost (PMIC_GPIO_PULL_UP_1P5_30) | ||
121 | If this property is ommited 30uA strength will be used if | ||
122 | pull up is selected | ||
123 | |||
124 | - bias-high-impedance: | ||
125 | Usage: optional | ||
126 | Value type: <none> | ||
127 | Definition: The specified pins will put in high-Z mode and disabled. | ||
128 | |||
129 | - input-enable: | ||
130 | Usage: optional | ||
131 | Value type: <none> | ||
132 | Definition: The specified pins are put in input mode. | ||
133 | |||
134 | - output-high: | ||
135 | Usage: optional | ||
136 | Value type: <none> | ||
137 | Definition: The specified pins are configured in output mode, driven | ||
138 | high. | ||
139 | |||
140 | - output-low: | ||
141 | Usage: optional | ||
142 | Value type: <none> | ||
143 | Definition: The specified pins are configured in output mode, driven | ||
144 | low. | ||
145 | |||
146 | - power-source: | ||
147 | Usage: optional | ||
148 | Value type: <u32> | ||
149 | Definition: Selects the power source for the specified pins. Valid | ||
150 | power sources are defined per chip in | ||
151 | <dt-bindings/pinctrl/qcom,pmic-gpio.h> | ||
152 | |||
153 | - qcom,drive-strength: | ||
154 | Usage: optional | ||
155 | Value type: <u32> | ||
156 | Definition: Selects the drive strength for the specified pins. Value | ||
157 | drive strengths are: | ||
158 | 0: no (PMIC_GPIO_STRENGTH_NO) | ||
159 | 1: high (PMIC_GPIO_STRENGTH_HIGH) 0.9mA @ 1.8V - 1.9mA @ 2.6V | ||
160 | 2: medium (PMIC_GPIO_STRENGTH_MED) 0.6mA @ 1.8V - 1.25mA @ 2.6V | ||
161 | 3: low (PMIC_GPIO_STRENGTH_LOW) 0.15mA @ 1.8V - 0.3mA @ 2.6V | ||
162 | as defined in <dt-bindings/pinctrl/qcom,pmic-gpio.h> | ||
163 | |||
164 | - drive-push-pull: | ||
165 | Usage: optional | ||
166 | Value type: <none> | ||
167 | Definition: The specified pins are configured in push-pull mode. | ||
168 | |||
169 | - drive-open-drain: | ||
170 | Usage: optional | ||
171 | Value type: <none> | ||
172 | Definition: The specified pins are configured in open-drain mode. | ||
173 | |||
174 | - drive-open-source: | ||
175 | Usage: optional | ||
176 | Value type: <none> | ||
177 | Definition: The specified pins are configured in open-source mode. | ||
178 | |||
179 | Example: | ||
180 | |||
181 | pm8921_gpio: gpio@150 { | ||
182 | compatible = "qcom,pm8921-gpio"; | ||
183 | reg = <0x150 0x160>; | ||
184 | interrupts = <192 1>, <193 1>, <194 1>, | ||
185 | <195 1>, <196 1>, <197 1>, | ||
186 | <198 1>, <199 1>, <200 1>, | ||
187 | <201 1>, <202 1>, <203 1>, | ||
188 | <204 1>, <205 1>, <206 1>, | ||
189 | <207 1>, <208 1>, <209 1>, | ||
190 | <210 1>, <211 1>, <212 1>, | ||
191 | <213 1>, <214 1>, <215 1>, | ||
192 | <216 1>, <217 1>, <218 1>, | ||
193 | <219 1>, <220 1>, <221 1>, | ||
194 | <222 1>, <223 1>, <224 1>, | ||
195 | <225 1>, <226 1>, <227 1>, | ||
196 | <228 1>, <229 1>, <230 1>, | ||
197 | <231 1>, <232 1>, <233 1>, | ||
198 | <234 1>, <235 1>; | ||
199 | |||
200 | gpio-controller; | ||
201 | #gpio-cells = <2>; | ||
202 | |||
203 | pm8921_gpio_keys: gpio-keys { | ||
204 | volume-keys { | ||
205 | pins = "gpio20", "gpio21"; | ||
206 | function = "normal"; | ||
207 | |||
208 | input-enable; | ||
209 | bias-pull-up; | ||
210 | drive-push-pull; | ||
211 | qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; | ||
212 | power-source = <PM8921_GPIO_S4>; | ||
213 | }; | ||
214 | }; | ||
215 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt new file mode 100644 index 000000000000..854774b194ed --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | |||
@@ -0,0 +1,162 @@ | |||
1 | Qualcomm PMIC Multi-Purpose Pin (MPP) block | ||
2 | |||
3 | This binding describes the MPP block(s) found in the 8xxx series | ||
4 | of PMIC's from Qualcomm. | ||
5 | |||
6 | - compatible: | ||
7 | Usage: required | ||
8 | Value type: <string> | ||
9 | Definition: Should contain one of: | ||
10 | "qcom,pm8841-mpp", | ||
11 | "qcom,pm8941-mpp", | ||
12 | "qcom,pma8084-mpp", | ||
13 | |||
14 | - reg: | ||
15 | Usage: required | ||
16 | Value type: <prop-encoded-array> | ||
17 | Definition: Register base of the MPP block and length. | ||
18 | |||
19 | - interrupts: | ||
20 | Usage: required | ||
21 | Value type: <prop-encoded-array> | ||
22 | Definition: Must contain an array of encoded interrupt specifiers for | ||
23 | each available MPP | ||
24 | |||
25 | - gpio-controller: | ||
26 | Usage: required | ||
27 | Value type: <none> | ||
28 | Definition: Mark the device node as a GPIO controller | ||
29 | |||
30 | - #gpio-cells: | ||
31 | Usage: required | ||
32 | Value type: <u32> | ||
33 | Definition: Must be 2; | ||
34 | the first cell will be used to define MPP number and the | ||
35 | second denotes the flags for this MPP | ||
36 | |||
37 | Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for | ||
38 | a general description of GPIO and interrupt bindings. | ||
39 | |||
40 | Please refer to pinctrl-bindings.txt in this directory for details of the | ||
41 | common pinctrl bindings used by client devices, including the meaning of the | ||
42 | phrase "pin configuration node". | ||
43 | |||
44 | The pin configuration nodes act as a container for an arbitrary number of | ||
45 | subnodes. Each of these subnodes represents some desired configuration for a | ||
46 | pin or a list of pins. This configuration can include the | ||
47 | mux function to select on those pin(s), and various pin configuration | ||
48 | parameters, as listed below. | ||
49 | |||
50 | SUBNODES: | ||
51 | |||
52 | The name of each subnode is not important; all subnodes should be enumerated | ||
53 | and processed purely based on their content. | ||
54 | |||
55 | Each subnode only affects those parameters that are explicitly listed. In | ||
56 | other words, a subnode that lists a mux function but no pin configuration | ||
57 | parameters implies no information about any pin configuration parameters. | ||
58 | Similarly, a pin subnode that describes a pullup parameter implies no | ||
59 | information about e.g. the mux function. | ||
60 | |||
61 | The following generic properties as defined in pinctrl-bindings.txt are valid | ||
62 | to specify in a pin configuration subnode: | ||
63 | |||
64 | - pins: | ||
65 | Usage: required | ||
66 | Value type: <string-array> | ||
67 | Definition: List of MPP pins affected by the properties specified in | ||
68 | this subnode. Valid pins are: | ||
69 | mpp1-mpp4 for pm8841 | ||
70 | mpp1-mpp8 for pm8941 | ||
71 | mpp1-mpp4 for pma8084 | ||
72 | |||
73 | - function: | ||
74 | Usage: required | ||
75 | Value type: <string> | ||
76 | Definition: Specify the alternative function to be configured for the | ||
77 | specified pins. Valid values are: | ||
78 | "normal", | ||
79 | "paired", | ||
80 | "dtest1", | ||
81 | "dtest2", | ||
82 | "dtest3", | ||
83 | "dtest4" | ||
84 | |||
85 | - bias-disable: | ||
86 | Usage: optional | ||
87 | Value type: <none> | ||
88 | Definition: The specified pins should be configured as no pull. | ||
89 | |||
90 | - bias-pull-up: | ||
91 | Usage: optional | ||
92 | Value type: <u32> | ||
93 | Definition: The specified pins should be configured as pull up. | ||
94 | Valid values are 600, 10000 and 30000 in bidirectional mode | ||
95 | only, i.e. when operating in qcom,analog-mode and input and | ||
96 | outputs are enabled. The hardware ignores the configuration | ||
97 | when operating in other modes. | ||
98 | |||
99 | - bias-high-impedance: | ||
100 | Usage: optional | ||
101 | Value type: <none> | ||
102 | Definition: The specified pins will put in high-Z mode and disabled. | ||
103 | |||
104 | - input-enable: | ||
105 | Usage: optional | ||
106 | Value type: <none> | ||
107 | Definition: The specified pins are put in input mode, i.e. their input | ||
108 | buffer is enabled | ||
109 | |||
110 | - output-high: | ||
111 | Usage: optional | ||
112 | Value type: <none> | ||
113 | Definition: The specified pins are configured in output mode, driven | ||
114 | high. | ||
115 | |||
116 | - output-low: | ||
117 | Usage: optional | ||
118 | Value type: <none> | ||
119 | Definition: The specified pins are configured in output mode, driven | ||
120 | low. | ||
121 | |||
122 | - power-source: | ||
123 | Usage: optional | ||
124 | Value type: <u32> | ||
125 | Definition: Selects the power source for the specified pins. Valid power | ||
126 | sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h> | ||
127 | |||
128 | - qcom,analog-mode: | ||
129 | Usage: optional | ||
130 | Value type: <none> | ||
131 | Definition: Selects Analog mode of operation: combined with input-enable | ||
132 | and/or output-high, output-low MPP could operate as | ||
133 | Bidirectional Logic, Analog Input, Analog Output. | ||
134 | |||
135 | - qcom,amux-route: | ||
136 | Usage: optional | ||
137 | Value type: <u32> | ||
138 | Definition: Selects the source for analog input. Valid values are | ||
139 | defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h> | ||
140 | PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6... | ||
141 | |||
142 | Example: | ||
143 | |||
144 | mpps@a000 { | ||
145 | compatible = "qcom,pm8841-mpp"; | ||
146 | reg = <0xa000>; | ||
147 | gpio-controller; | ||
148 | #gpio-cells = <2>; | ||
149 | interrupts = <4 0xa0 0 0>, <4 0xa1 0 0>, <4 0xa2 0 0>, <4 0xa3 0 0>; | ||
150 | |||
151 | pinctrl-names = "default"; | ||
152 | pinctrl-0 = <&pm8841_default>; | ||
153 | |||
154 | pm8841_default: default { | ||
155 | gpio { | ||
156 | pins = "mpp1", "mpp2", "mpp3", "mpp4"; | ||
157 | function = "normal"; | ||
158 | input-enable; | ||
159 | power-source = <PM8841_MPP_S3>; | ||
160 | }; | ||
161 | }; | ||
162 | }; | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 4658b69d4f4d..388b213249fd 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | |||
@@ -2,8 +2,8 @@ | |||
2 | 2 | ||
3 | The Rockchip Pinmux Controller, enables the IC | 3 | The Rockchip Pinmux Controller, enables the IC |
4 | to share one PAD to several functional blocks. The sharing is done by | 4 | to share one PAD to several functional blocks. The sharing is done by |
5 | multiplexing the PAD input/output signals. For each PAD there are up to | 5 | multiplexing the PAD input/output signals. For each PAD there are several |
6 | 4 muxing options with option 0 being the use as a GPIO. | 6 | muxing options with option 0 being the use as a GPIO. |
7 | 7 | ||
8 | Please refer to pinctrl-bindings.txt in this directory for details of the | 8 | Please refer to pinctrl-bindings.txt in this directory for details of the |
9 | common pinctrl bindings used by client devices, including the meaning of the | 9 | common pinctrl bindings used by client devices, including the meaning of the |
@@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes: | |||
58 | Required properties for pin configuration node: | 58 | Required properties for pin configuration node: |
59 | - rockchip,pins: 3 integers array, represents a group of pins mux and config | 59 | - rockchip,pins: 3 integers array, represents a group of pins mux and config |
60 | setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. | 60 | setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. |
61 | The MUX 0 means gpio and MUX 1 to 3 mean the specific device function. | 61 | The MUX 0 means gpio and MUX 1 to N mean the specific device function. |
62 | The phandle of a node containing the generic pinconfig options | 62 | The phandle of a node containing the generic pinconfig options |
63 | to use, as described in pinctrl-bindings.txt in this directory. | 63 | to use, as described in pinctrl-bindings.txt in this directory. |
64 | 64 | ||
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index e82aaf492517..8425838a6dff 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | |||
@@ -18,6 +18,7 @@ Required Properties: | |||
18 | - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. | 18 | - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. |
19 | - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. | 19 | - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. |
20 | - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. | 20 | - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. |
21 | - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. | ||
21 | 22 | ||
22 | - reg: Base address of the pin controller hardware module and length of | 23 | - reg: Base address of the pin controller hardware module and length of |
23 | the address space it occupies. | 24 | the address space it occupies. |
@@ -136,6 +137,8 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a | |||
136 | found on Samsung S3C64xx SoCs, | 137 | found on Samsung S3C64xx SoCs, |
137 | - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller | 138 | - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller |
138 | found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. | 139 | found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. |
140 | - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller | ||
141 | found on Samsung Exynos7 SoC. | ||
139 | - interrupt-parent: phandle of the interrupt parent to which the external | 142 | - interrupt-parent: phandle of the interrupt parent to which the external |
140 | wakeup interrupts are forwarded to. | 143 | wakeup interrupts are forwarded to. |
141 | - interrupts: interrupt used by multiplexed wakeup interrupts. | 144 | - interrupts: interrupt used by multiplexed wakeup interrupts. |
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt index e3865e136067..87697420439e 100644 --- a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt +++ b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt | |||
@@ -8,42 +8,8 @@ Please refer to pinctrl-bindings.txt in this directory for details of the | |||
8 | common pinctrl bindings used by client devices, including the meaning of the | 8 | common pinctrl bindings used by client devices, including the meaning of the |
9 | phrase "pin configuration node". | 9 | phrase "pin configuration node". |
10 | 10 | ||
11 | ST Ericsson's pin configuration nodes act as a container for an arbitrary number of | 11 | ST Ericsson's pin configuration nodes use the generic pin multiplexing |
12 | subnodes. Each of these subnodes represents some desired configuration for a | 12 | and pin configuration bindings, see pinctrl-bindings.txt |
13 | pin, a group, or a list of pins or groups. This configuration can include the | ||
14 | mux function to select on those pin(s)/group(s), and various pin configuration | ||
15 | parameters, such as input, output, pull up, pull down... | ||
16 | |||
17 | The name of each subnode is not important; all subnodes should be enumerated | ||
18 | and processed purely based on their content. | ||
19 | |||
20 | Required subnode-properties: | ||
21 | - ste,pins : An array of strings. Each string contains the name of a pin or | ||
22 | group. | ||
23 | |||
24 | Optional subnode-properties: | ||
25 | - ste,function: A string containing the name of the function to mux to the | ||
26 | pin or group. | ||
27 | |||
28 | - generic pin configuration option to use. Example : | ||
29 | |||
30 | default_cfg { | ||
31 | ste,pins = "GPIO1"; | ||
32 | bias-disable; | ||
33 | }; | ||
34 | |||
35 | - ste,config: Handle of pin configuration node containing the generic | ||
36 | pinconfig options to use, as described in pinctrl-bindings.txt in | ||
37 | this directory. Example : | ||
38 | |||
39 | pcfg_bias_disable: pcfg_bias_disable { | ||
40 | bias-disable; | ||
41 | }; | ||
42 | |||
43 | default_cfg { | ||
44 | ste,pins = "GPIO1"; | ||
45 | ste.config = <&pcfg_bias_disable>; | ||
46 | }; | ||
47 | 13 | ||
48 | Example board file extract: | 14 | Example board file extract: |
49 | 15 | ||
@@ -54,11 +20,11 @@ Example board file extract: | |||
54 | sysclkreq2 { | 20 | sysclkreq2 { |
55 | sysclkreq2_default_mode: sysclkreq2_default { | 21 | sysclkreq2_default_mode: sysclkreq2_default { |
56 | default_mux { | 22 | default_mux { |
57 | ste,function = "sysclkreq"; | 23 | function = "sysclkreq"; |
58 | ste,pins = "sysclkreq2_d_1"; | 24 | groups = "sysclkreq2_d_1"; |
59 | }; | 25 | }; |
60 | default_cfg { | 26 | default_cfg { |
61 | ste,pins = "GPIO1"; | 27 | pins = "GPIO1"; |
62 | bias-disable; | 28 | bias-disable; |
63 | }; | 29 | }; |
64 | }; | 30 | }; |
@@ -66,11 +32,11 @@ Example board file extract: | |||
66 | sysclkreq3 { | 32 | sysclkreq3 { |
67 | sysclkreq3_default_mode: sysclkreq3_default { | 33 | sysclkreq3_default_mode: sysclkreq3_default { |
68 | default_mux { | 34 | default_mux { |
69 | ste,function = "sysclkreq"; | 35 | function = "sysclkreq"; |
70 | ste,pins = "sysclkreq3_d_1"; | 36 | groups = "sysclkreq3_d_1"; |
71 | }; | 37 | }; |
72 | default_cfg { | 38 | default_cfg { |
73 | ste,pins = "GPIO2"; | 39 | pins = "GPIO2"; |
74 | output-low; | 40 | output-low; |
75 | }; | 41 | }; |
76 | }; | 42 | }; |
@@ -78,11 +44,11 @@ Example board file extract: | |||
78 | gpio3 { | 44 | gpio3 { |
79 | gpio3_default_mode: gpio3_default { | 45 | gpio3_default_mode: gpio3_default { |
80 | default_mux { | 46 | default_mux { |
81 | ste,function = "gpio"; | 47 | function = "gpio"; |
82 | ste,pins = "gpio3_a_1"; | 48 | groups = "gpio3_a_1"; |
83 | }; | 49 | }; |
84 | default_cfg { | 50 | default_cfg { |
85 | ste,pins = "GPIO3"; | 51 | pins = "GPIO3"; |
86 | output-low; | 52 | output-low; |
87 | }; | 53 | }; |
88 | }; | 54 | }; |
@@ -90,11 +56,11 @@ Example board file extract: | |||
90 | sysclkreq6 { | 56 | sysclkreq6 { |
91 | sysclkreq6_default_mode: sysclkreq6_default { | 57 | sysclkreq6_default_mode: sysclkreq6_default { |
92 | default_mux { | 58 | default_mux { |
93 | ste,function = "sysclkreq"; | 59 | function = "sysclkreq"; |
94 | ste,pins = "sysclkreq6_d_1"; | 60 | groups = "sysclkreq6_d_1"; |
95 | }; | 61 | }; |
96 | default_cfg { | 62 | default_cfg { |
97 | ste,pins = "GPIO4"; | 63 | pins = "GPIO4"; |
98 | bias-disable; | 64 | bias-disable; |
99 | }; | 65 | }; |
100 | }; | 66 | }; |
@@ -102,11 +68,11 @@ Example board file extract: | |||
102 | pwmout1 { | 68 | pwmout1 { |
103 | pwmout1_default_mode: pwmout1_default { | 69 | pwmout1_default_mode: pwmout1_default { |
104 | default_mux { | 70 | default_mux { |
105 | ste,function = "pwmout"; | 71 | function = "pwmout"; |
106 | ste,pins = "pwmout1_d_1"; | 72 | groups = "pwmout1_d_1"; |
107 | }; | 73 | }; |
108 | default_cfg { | 74 | default_cfg { |
109 | ste,pins = "GPIO14"; | 75 | pins = "GPIO14"; |
110 | output-low; | 76 | output-low; |
111 | }; | 77 | }; |
112 | }; | 78 | }; |
@@ -114,11 +80,11 @@ Example board file extract: | |||
114 | pwmout2 { | 80 | pwmout2 { |
115 | pwmout2_default_mode: pwmout2_default { | 81 | pwmout2_default_mode: pwmout2_default { |
116 | pwmout2_default_mux { | 82 | pwmout2_default_mux { |
117 | ste,function = "pwmout"; | 83 | function = "pwmout"; |
118 | ste,pins = "pwmout2_d_1"; | 84 | groups = "pwmout2_d_1"; |
119 | }; | 85 | }; |
120 | pwmout2_default_cfg { | 86 | pwmout2_default_cfg { |
121 | ste,pins = "GPIO15"; | 87 | pins = "GPIO15"; |
122 | output-low; | 88 | output-low; |
123 | }; | 89 | }; |
124 | }; | 90 | }; |
@@ -126,11 +92,11 @@ Example board file extract: | |||
126 | pwmout3 { | 92 | pwmout3 { |
127 | pwmout3_default_mode: pwmout3_default { | 93 | pwmout3_default_mode: pwmout3_default { |
128 | pwmout3_default_mux { | 94 | pwmout3_default_mux { |
129 | ste,function = "pwmout"; | 95 | function = "pwmout"; |
130 | ste,pins = "pwmout3_d_1"; | 96 | groups = "pwmout3_d_1"; |
131 | }; | 97 | }; |
132 | pwmout3_default_cfg { | 98 | pwmout3_default_cfg { |
133 | ste,pins = "GPIO16"; | 99 | pins = "GPIO16"; |
134 | output-low; | 100 | output-low; |
135 | }; | 101 | }; |
136 | }; | 102 | }; |
@@ -139,15 +105,15 @@ Example board file extract: | |||
139 | 105 | ||
140 | adi1_default_mode: adi1_default { | 106 | adi1_default_mode: adi1_default { |
141 | adi1_default_mux { | 107 | adi1_default_mux { |
142 | ste,function = "adi1"; | 108 | function = "adi1"; |
143 | ste,pins = "adi1_d_1"; | 109 | groups = "adi1_d_1"; |
144 | }; | 110 | }; |
145 | adi1_default_cfg1 { | 111 | adi1_default_cfg1 { |
146 | ste,pins = "GPIO17","GPIO19","GPIO20"; | 112 | pins = "GPIO17","GPIO19","GPIO20"; |
147 | bias-disable; | 113 | bias-disable; |
148 | }; | 114 | }; |
149 | adi1_default_cfg2 { | 115 | adi1_default_cfg2 { |
150 | ste,pins = "GPIO18"; | 116 | pins = "GPIO18"; |
151 | output-low; | 117 | output-low; |
152 | }; | 118 | }; |
153 | }; | 119 | }; |
@@ -155,15 +121,15 @@ Example board file extract: | |||
155 | dmic12 { | 121 | dmic12 { |
156 | dmic12_default_mode: dmic12_default { | 122 | dmic12_default_mode: dmic12_default { |
157 | dmic12_default_mux { | 123 | dmic12_default_mux { |
158 | ste,function = "dmic"; | 124 | function = "dmic"; |
159 | ste,pins = "dmic12_d_1"; | 125 | groups = "dmic12_d_1"; |
160 | }; | 126 | }; |
161 | dmic12_default_cfg1 { | 127 | dmic12_default_cfg1 { |
162 | ste,pins = "GPIO27"; | 128 | pins = "GPIO27"; |
163 | output-low; | 129 | output-low; |
164 | }; | 130 | }; |
165 | dmic12_default_cfg2 { | 131 | dmic12_default_cfg2 { |
166 | ste,pins = "GPIO28"; | 132 | pins = "GPIO28"; |
167 | bias-disable; | 133 | bias-disable; |
168 | }; | 134 | }; |
169 | }; | 135 | }; |
@@ -171,15 +137,15 @@ Example board file extract: | |||
171 | dmic34 { | 137 | dmic34 { |
172 | dmic34_default_mode: dmic34_default { | 138 | dmic34_default_mode: dmic34_default { |
173 | dmic34_default_mux { | 139 | dmic34_default_mux { |
174 | ste,function = "dmic"; | 140 | function = "dmic"; |
175 | ste,pins = "dmic34_d_1"; | 141 | groups = "dmic34_d_1"; |
176 | }; | 142 | }; |
177 | dmic34_default_cfg1 { | 143 | dmic34_default_cfg1 { |
178 | ste,pins = "GPIO29"; | 144 | pins = "GPIO29"; |
179 | output-low; | 145 | output-low; |
180 | }; | 146 | }; |
181 | dmic34_default_cfg2 { | 147 | dmic34_default_cfg2 { |
182 | ste,pins = "GPIO30"; | 148 | pins = "GPIO30"; |
183 | bias-disable;{ | 149 | bias-disable;{ |
184 | 150 | ||
185 | }; | 151 | }; |
@@ -188,15 +154,15 @@ Example board file extract: | |||
188 | dmic56 { | 154 | dmic56 { |
189 | dmic56_default_mode: dmic56_default { | 155 | dmic56_default_mode: dmic56_default { |
190 | dmic56_default_mux { | 156 | dmic56_default_mux { |
191 | ste,function = "dmic"; | 157 | function = "dmic"; |
192 | ste,pins = "dmic56_d_1"; | 158 | groups = "dmic56_d_1"; |
193 | }; | 159 | }; |
194 | dmic56_default_cfg1 { | 160 | dmic56_default_cfg1 { |
195 | ste,pins = "GPIO31"; | 161 | pins = "GPIO31"; |
196 | output-low; | 162 | output-low; |
197 | }; | 163 | }; |
198 | dmic56_default_cfg2 { | 164 | dmic56_default_cfg2 { |
199 | ste,pins = "GPIO32"; | 165 | pins = "GPIO32"; |
200 | bias-disable; | 166 | bias-disable; |
201 | }; | 167 | }; |
202 | }; | 168 | }; |
@@ -204,11 +170,11 @@ Example board file extract: | |||
204 | sysclkreq5 { | 170 | sysclkreq5 { |
205 | sysclkreq5_default_mode: sysclkreq5_default { | 171 | sysclkreq5_default_mode: sysclkreq5_default { |
206 | sysclkreq5_default_mux { | 172 | sysclkreq5_default_mux { |
207 | ste,function = "sysclkreq"; | 173 | function = "sysclkreq"; |
208 | ste,pins = "sysclkreq5_d_1"; | 174 | groups = "sysclkreq5_d_1"; |
209 | }; | 175 | }; |
210 | sysclkreq5_default_cfg { | 176 | sysclkreq5_default_cfg { |
211 | ste,pins = "GPIO42"; | 177 | pins = "GPIO42"; |
212 | output-low; | 178 | output-low; |
213 | }; | 179 | }; |
214 | }; | 180 | }; |
@@ -216,11 +182,11 @@ Example board file extract: | |||
216 | batremn { | 182 | batremn { |
217 | batremn_default_mode: batremn_default { | 183 | batremn_default_mode: batremn_default { |
218 | batremn_default_mux { | 184 | batremn_default_mux { |
219 | ste,function = "batremn"; | 185 | function = "batremn"; |
220 | ste,pins = "batremn_d_1"; | 186 | groups = "batremn_d_1"; |
221 | }; | 187 | }; |
222 | batremn_default_cfg { | 188 | batremn_default_cfg { |
223 | ste,pins = "GPIO43"; | 189 | pins = "GPIO43"; |
224 | bias-disable; | 190 | bias-disable; |
225 | }; | 191 | }; |
226 | }; | 192 | }; |
@@ -228,11 +194,11 @@ Example board file extract: | |||
228 | service { | 194 | service { |
229 | service_default_mode: service_default { | 195 | service_default_mode: service_default { |
230 | service_default_mux { | 196 | service_default_mux { |
231 | ste,function = "service"; | 197 | function = "service"; |
232 | ste,pins = "service_d_1"; | 198 | groups = "service_d_1"; |
233 | }; | 199 | }; |
234 | service_default_cfg { | 200 | service_default_cfg { |
235 | ste,pins = "GPIO44"; | 201 | pins = "GPIO44"; |
236 | bias-disable; | 202 | bias-disable; |
237 | }; | 203 | }; |
238 | }; | 204 | }; |
@@ -240,13 +206,13 @@ Example board file extract: | |||
240 | pwrctrl0 { | 206 | pwrctrl0 { |
241 | pwrctrl0_default_mux: pwrctrl0_mux { | 207 | pwrctrl0_default_mux: pwrctrl0_mux { |
242 | pwrctrl0_default_mux { | 208 | pwrctrl0_default_mux { |
243 | ste,function = "pwrctrl"; | 209 | function = "pwrctrl"; |
244 | ste,pins = "pwrctrl0_d_1"; | 210 | groups = "pwrctrl0_d_1"; |
245 | }; | 211 | }; |
246 | }; | 212 | }; |
247 | pwrctrl0_default_mode: pwrctrl0_default { | 213 | pwrctrl0_default_mode: pwrctrl0_default { |
248 | pwrctrl0_default_cfg { | 214 | pwrctrl0_default_cfg { |
249 | ste,pins = "GPIO45"; | 215 | pins = "GPIO45"; |
250 | bias-disable; | 216 | bias-disable; |
251 | }; | 217 | }; |
252 | }; | 218 | }; |
@@ -254,13 +220,13 @@ Example board file extract: | |||
254 | pwrctrl1 { | 220 | pwrctrl1 { |
255 | pwrctrl1_default_mux: pwrctrl1_mux { | 221 | pwrctrl1_default_mux: pwrctrl1_mux { |
256 | pwrctrl1_default_mux { | 222 | pwrctrl1_default_mux { |
257 | ste,function = "pwrctrl"; | 223 | function = "pwrctrl"; |
258 | ste,pins = "pwrctrl1_d_1"; | 224 | groups = "pwrctrl1_d_1"; |
259 | }; | 225 | }; |
260 | }; | 226 | }; |
261 | pwrctrl1_default_mode: pwrctrl1_default { | 227 | pwrctrl1_default_mode: pwrctrl1_default { |
262 | pwrctrl1_default_cfg { | 228 | pwrctrl1_default_cfg { |
263 | ste,pins = "GPIO46"; | 229 | pins = "GPIO46"; |
264 | bias-disable; | 230 | bias-disable; |
265 | }; | 231 | }; |
266 | }; | 232 | }; |
@@ -268,11 +234,11 @@ Example board file extract: | |||
268 | pwmextvibra1 { | 234 | pwmextvibra1 { |
269 | pwmextvibra1_default_mode: pwmextvibra1_default { | 235 | pwmextvibra1_default_mode: pwmextvibra1_default { |
270 | pwmextvibra1_default_mux { | 236 | pwmextvibra1_default_mux { |
271 | ste,function = "pwmextvibra"; | 237 | function = "pwmextvibra"; |
272 | ste,pins = "pwmextvibra1_d_1"; | 238 | groups = "pwmextvibra1_d_1"; |
273 | }; | 239 | }; |
274 | pwmextvibra1_default_cfg { | 240 | pwmextvibra1_default_cfg { |
275 | ste,pins = "GPIO47"; | 241 | pins = "GPIO47"; |
276 | bias-disable; | 242 | bias-disable; |
277 | }; | 243 | }; |
278 | }; | 244 | }; |
@@ -280,11 +246,11 @@ Example board file extract: | |||
280 | pwmextvibra2 { | 246 | pwmextvibra2 { |
281 | pwmextvibra2_default_mode: pwmextvibra2_default { | 247 | pwmextvibra2_default_mode: pwmextvibra2_default { |
282 | pwmextvibra2_default_mux { | 248 | pwmextvibra2_default_mux { |
283 | ste,function = "pwmextvibra"; | 249 | function = "pwmextvibra"; |
284 | ste,pins = "pwmextvibra2_d_1"; | 250 | groups = "pwmextvibra2_d_1"; |
285 | }; | 251 | }; |
286 | pwmextvibra1_default_cfg { | 252 | pwmextvibra1_default_cfg { |
287 | ste,pins = "GPIO48"; | 253 | pins = "GPIO48"; |
288 | bias-disable; | 254 | bias-disable; |
289 | }; | 255 | }; |
290 | }; | 256 | }; |
@@ -292,11 +258,11 @@ Example board file extract: | |||
292 | gpio51 { | 258 | gpio51 { |
293 | gpio51_default_mode: gpio51_default { | 259 | gpio51_default_mode: gpio51_default { |
294 | gpio51_default_mux { | 260 | gpio51_default_mux { |
295 | ste,function = "gpio"; | 261 | function = "gpio"; |
296 | ste,pins = "gpio51_a_1"; | 262 | groups = "gpio51_a_1"; |
297 | }; | 263 | }; |
298 | gpio51_default_cfg { | 264 | gpio51_default_cfg { |
299 | ste,pins = "GPIO51"; | 265 | pins = "GPIO51"; |
300 | output-low; | 266 | output-low; |
301 | }; | 267 | }; |
302 | }; | 268 | }; |
@@ -304,11 +270,11 @@ Example board file extract: | |||
304 | gpio52 { | 270 | gpio52 { |
305 | gpio52_default_mode: gpio52_default { | 271 | gpio52_default_mode: gpio52_default { |
306 | gpio52_default_mux { | 272 | gpio52_default_mux { |
307 | ste,function = "gpio"; | 273 | function = "gpio"; |
308 | ste,pins = "gpio52_a_1"; | 274 | groups = "gpio52_a_1"; |
309 | }; | 275 | }; |
310 | gpio52_default_cfg { | 276 | gpio52_default_cfg { |
311 | ste,pins = "GPIO52"; | 277 | pins = "GPIO52"; |
312 | bias-pull-down; | 278 | bias-pull-down; |
313 | }; | 279 | }; |
314 | }; | 280 | }; |
@@ -316,11 +282,11 @@ Example board file extract: | |||
316 | gpio53 { | 282 | gpio53 { |
317 | gpio53_default_mode: gpio53_default { | 283 | gpio53_default_mode: gpio53_default { |
318 | gpio53_default_mux { | 284 | gpio53_default_mux { |
319 | ste,function = "gpio"; | 285 | function = "gpio"; |
320 | ste,pins = "gpio53_a_1"; | 286 | groups = "gpio53_a_1"; |
321 | }; | 287 | }; |
322 | gpio53_default_cfg { | 288 | gpio53_default_cfg { |
323 | ste,pins = "GPIO53"; | 289 | pins = "GPIO53"; |
324 | bias-pull-down; | 290 | bias-pull-down; |
325 | }; | 291 | }; |
326 | }; | 292 | }; |
@@ -328,11 +294,11 @@ Example board file extract: | |||
328 | gpio54 { | 294 | gpio54 { |
329 | gpio54_default_mode: gpio54_default { | 295 | gpio54_default_mode: gpio54_default { |
330 | gpio54_default_mux { | 296 | gpio54_default_mux { |
331 | ste,function = "gpio"; | 297 | function = "gpio"; |
332 | ste,pins = "gpio54_a_1"; | 298 | groups = "gpio54_a_1"; |
333 | }; | 299 | }; |
334 | gpio54_default_cfg { | 300 | gpio54_default_cfg { |
335 | ste,pins = "GPIO54"; | 301 | pins = "GPIO54"; |
336 | output-low; | 302 | output-low; |
337 | }; | 303 | }; |
338 | }; | 304 | }; |
@@ -340,11 +306,11 @@ Example board file extract: | |||
340 | pdmclkdat { | 306 | pdmclkdat { |
341 | pdmclkdat_default_mode: pdmclkdat_default { | 307 | pdmclkdat_default_mode: pdmclkdat_default { |
342 | pdmclkdat_default_mux { | 308 | pdmclkdat_default_mux { |
343 | ste,function = "pdm"; | 309 | function = "pdm"; |
344 | ste,pins = "pdmclkdat_d_1"; | 310 | groups = "pdmclkdat_d_1"; |
345 | }; | 311 | }; |
346 | pdmclkdat_default_cfg { | 312 | pdmclkdat_default_cfg { |
347 | ste,pins = "GPIO55", "GPIO56"; | 313 | pins = "GPIO55", "GPIO56"; |
348 | bias-disable; | 314 | bias-disable; |
349 | }; | 315 | }; |
350 | }; | 316 | }; |
diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt new file mode 100644 index 000000000000..88c80273da91 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt | |||
@@ -0,0 +1,13 @@ | |||
1 | OMAP Pinctrl definitions | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be one of: | ||
5 | "ti,omap2420-padconf" - OMAP2420 compatible pinctrl | ||
6 | "ti,omap2430-padconf" - OMAP2430 compatible pinctrl | ||
7 | "ti,omap3-padconf" - OMAP3 compatible pinctrl | ||
8 | "ti,omap4-padconf" - OMAP4 compatible pinctrl | ||
9 | "ti,omap5-padconf" - OMAP5 compatible pinctrl | ||
10 | "ti,dra7-padconf" - DRA7 compatible pinctrl | ||
11 | "ti,am437-padconf" - AM437x compatible pinctrl | ||
12 | |||
13 | See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details. | ||
diff --git a/Documentation/devicetree/bindings/power/power-controller.txt b/Documentation/devicetree/bindings/power/power-controller.txt new file mode 100644 index 000000000000..4f7a3bc9c407 --- /dev/null +++ b/Documentation/devicetree/bindings/power/power-controller.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | * Generic system power control capability | ||
2 | |||
3 | Power-management integrated circuits or miscellaneous hardware components are | ||
4 | sometimes able to control the system power. The device driver associated with these | ||
5 | components might need to define this capability, which tells the kernel that | ||
6 | it can be used to switch off the system. The corresponding device must have the | ||
7 | standard property "system-power-controller" in its device node. This property | ||
8 | marks the device as able to control the system power. In order to test if this | ||
9 | property is found programmatically, use the helper function | ||
10 | "of_device_is_system_power_controller" from of.h . | ||
11 | |||
12 | Example: | ||
13 | |||
14 | act8846: act8846@5 { | ||
15 | compatible = "active-semi,act8846"; | ||
16 | status = "okay"; | ||
17 | system-power-controller; | ||
18 | } | ||
diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt new file mode 100644 index 000000000000..98c16672ab5f --- /dev/null +++ b/Documentation/devicetree/bindings/power/power_domain.txt | |||
@@ -0,0 +1,49 @@ | |||
1 | * Generic PM domains | ||
2 | |||
3 | System on chip designs are often divided into multiple PM domains that can be | ||
4 | used for power gating of selected IP blocks for power saving by reduced leakage | ||
5 | current. | ||
6 | |||
7 | This device tree binding can be used to bind PM domain consumer devices with | ||
8 | their PM domains provided by PM domain providers. A PM domain provider can be | ||
9 | represented by any node in the device tree and can provide one or more PM | ||
10 | domains. A consumer node can refer to the provider by a phandle and a set of | ||
11 | phandle arguments (so called PM domain specifiers) of length specified by the | ||
12 | #power-domain-cells property in the PM domain provider node. | ||
13 | |||
14 | ==PM domain providers== | ||
15 | |||
16 | Required properties: | ||
17 | - #power-domain-cells : Number of cells in a PM domain specifier; | ||
18 | Typically 0 for nodes representing a single PM domain and 1 for nodes | ||
19 | providing multiple PM domains (e.g. power controllers), but can be any value | ||
20 | as specified by device tree binding documentation of particular provider. | ||
21 | |||
22 | Example: | ||
23 | |||
24 | power: power-controller@12340000 { | ||
25 | compatible = "foo,power-controller"; | ||
26 | reg = <0x12340000 0x1000>; | ||
27 | #power-domain-cells = <1>; | ||
28 | }; | ||
29 | |||
30 | The node above defines a power controller that is a PM domain provider and | ||
31 | expects one cell as its phandle argument. | ||
32 | |||
33 | ==PM domain consumers== | ||
34 | |||
35 | Required properties: | ||
36 | - power-domains : A phandle and PM domain specifier as defined by bindings of | ||
37 | the power controller specified by phandle. | ||
38 | |||
39 | Example: | ||
40 | |||
41 | leaky-device@12350000 { | ||
42 | compatible = "foo,i-leak-current"; | ||
43 | reg = <0x12350000 0x1000>; | ||
44 | power-domains = <&power 0>; | ||
45 | }; | ||
46 | |||
47 | The node above defines a typical PM domain consumer device, which is located | ||
48 | inside a PM domain with index 0 of a power controller represented by a node | ||
49 | with the label "power". | ||
diff --git a/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt new file mode 100644 index 000000000000..0c94c637f63b --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt | |||
@@ -0,0 +1,26 @@ | |||
1 | Binding for the LTC2952 PowerPath controller | ||
2 | |||
3 | This chip is used to externally trigger a system shut down. Once the trigger has | ||
4 | been sent, the chips' watchdog has to be reset to gracefully shut down. | ||
5 | If the Linux systems decides to shut down it powers off the platform via the | ||
6 | kill signal. | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - compatible: Must contain: "lltc,ltc2952" | ||
11 | - trigger-gpios: phandle + gpio-specifier for the GPIO connected to the | ||
12 | chip's trigger line | ||
13 | - watchdog-gpios: phandle + gpio-specifier for the GPIO connected to the | ||
14 | chip's watchdog line | ||
15 | - kill-gpios: phandle + gpio-specifier for the GPIO connected to the | ||
16 | chip's kill line | ||
17 | |||
18 | Example: | ||
19 | |||
20 | ltc2952 { | ||
21 | compatible = "lltc,ltc2952"; | ||
22 | |||
23 | trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; | ||
24 | watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; | ||
25 | kill-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/power/reset/st-reset.txt b/Documentation/devicetree/bindings/power/reset/st-reset.txt new file mode 100644 index 000000000000..809af54f02f3 --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/st-reset.txt | |||
@@ -0,0 +1,11 @@ | |||
1 | *Device-Tree bindings for ST SW reset functionality | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "st,<chip>-restart". | ||
5 | - st,syscfg: should be a phandle of the syscfg node. | ||
6 | |||
7 | Example node: | ||
8 | restart { | ||
9 | compatible = "st,stih416-restart"; | ||
10 | st,syscfg = <&syscfg_sbc>; | ||
11 | }; | ||
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt new file mode 100644 index 000000000000..11906316b43d --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt | |||
@@ -0,0 +1,23 @@ | |||
1 | Generic SYSCON mapped register reset driver | ||
2 | |||
3 | This is a generic reset driver using syscon to map the reset register. | ||
4 | The reset is generally performed with a write to the reset register | ||
5 | defined by the register map pointed by syscon reference plus the offset | ||
6 | with the mask defined in the reboot node. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: should contain "syscon-reboot" | ||
10 | - regmap: this is phandle to the register map node | ||
11 | - offset: offset in the register map for the reboot register (in bytes) | ||
12 | - mask: the reset value written to the reboot register (32 bit access) | ||
13 | |||
14 | Default will be little endian mode, 32 bit access only. | ||
15 | |||
16 | Examples: | ||
17 | |||
18 | reboot { | ||
19 | compatible = "syscon-reboot"; | ||
20 | regmap = <®mapnode>; | ||
21 | offset = <0x0>; | ||
22 | mask = <0x1>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.txt b/Documentation/devicetree/bindings/power/rockchip-io-domain.txt new file mode 100644 index 000000000000..6fbf6e7ecde6 --- /dev/null +++ b/Documentation/devicetree/bindings/power/rockchip-io-domain.txt | |||
@@ -0,0 +1,83 @@ | |||
1 | Rockchip SRAM for IO Voltage Domains: | ||
2 | ------------------------------------- | ||
3 | |||
4 | IO domain voltages on some Rockchip SoCs are variable but need to be | ||
5 | kept in sync between the regulators and the SoC using a special | ||
6 | register. | ||
7 | |||
8 | A specific example using rk3288: | ||
9 | - If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then | ||
10 | bit 7 of GRF_IO_VSEL needs to be 0. If the regulator hooked up to | ||
11 | that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1. | ||
12 | |||
13 | Said another way, this driver simply handles keeping bits in the SoC's | ||
14 | general register file (GRF) in sync with the actual value of a voltage | ||
15 | hooked up to the pins. | ||
16 | |||
17 | Note that this driver specifically doesn't include: | ||
18 | - any logic for deciding what voltage we should set regulators to | ||
19 | - any logic for deciding whether regulators (or internal SoC blocks) | ||
20 | should have power or not have power | ||
21 | |||
22 | If there were some other software that had the smarts of making | ||
23 | decisions about regulators, it would work in conjunction with this | ||
24 | driver. When that other software adjusted a regulator's voltage then | ||
25 | this driver would handle telling the SoC about it. A good example is | ||
26 | vqmmc for SD. In that case the dw_mmc driver simply is told about a | ||
27 | regulator. It changes the regulator between 3.3V and 1.8V at the | ||
28 | right time. This driver notices the change and makes sure that the | ||
29 | SoC is on the same page. | ||
30 | |||
31 | |||
32 | Required properties: | ||
33 | - compatible: should be one of: | ||
34 | - "rockchip,rk3188-io-voltage-domain" for rk3188 | ||
35 | - "rockchip,rk3288-io-voltage-domain" for rk3288 | ||
36 | - rockchip,grf: phandle to the syscon managing the "general register files" | ||
37 | |||
38 | |||
39 | You specify supplies using the standard regulator bindings by including | ||
40 | a phandle the the relevant regulator. All specified supplies must be able | ||
41 | to report their voltage. The IO Voltage Domain for any non-specified | ||
42 | supplies will be not be touched. | ||
43 | |||
44 | Possible supplies for rk3188: | ||
45 | - ap0-supply: The supply connected to AP0_VCC. | ||
46 | - ap1-supply: The supply connected to AP1_VCC. | ||
47 | - cif-supply: The supply connected to CIF_VCC. | ||
48 | - flash-supply: The supply connected to FLASH_VCC. | ||
49 | - lcdc0-supply: The supply connected to LCD0_VCC. | ||
50 | - lcdc1-supply: The supply connected to LCD1_VCC. | ||
51 | - vccio0-supply: The supply connected to VCCIO0. | ||
52 | - vccio1-supply: The supply connected to VCCIO1. | ||
53 | Sometimes also labeled VCCIO1 and VCCIO2. | ||
54 | |||
55 | Possible supplies for rk3288: | ||
56 | - audio-supply: The supply connected to APIO4_VDD. | ||
57 | - bb-supply: The supply connected to APIO5_VDD. | ||
58 | - dvp-supply: The supply connected to DVPIO_VDD. | ||
59 | - flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC | ||
60 | - flash1-supply: The supply connected to FLASH1_VDD. Also known as SDIO1. | ||
61 | - gpio30-supply: The supply connected to APIO1_VDD. | ||
62 | - gpio1830 The supply connected to APIO2_VDD. | ||
63 | - lcdc-supply: The supply connected to LCDC_VDD. | ||
64 | - sdcard-supply: The supply connected to SDMMC0_VDD. | ||
65 | - wifi-supply: The supply connected to APIO3_VDD. Also known as SDIO0. | ||
66 | |||
67 | |||
68 | Example: | ||
69 | |||
70 | io-domains { | ||
71 | compatible = "rockchip,rk3288-io-voltage-domain"; | ||
72 | rockchip,grf = <&grf>; | ||
73 | |||
74 | audio-supply = <&vcc18_codec>; | ||
75 | bb-supply = <&vcc33_io>; | ||
76 | dvp-supply = <&vcc_18>; | ||
77 | flash0-supply = <&vcc18_flashio>; | ||
78 | gpio1830-supply = <&vcc33_io>; | ||
79 | gpio30-supply = <&vcc33_pmuio>; | ||
80 | lcdc-supply = <&vcc33_lcd>; | ||
81 | sdcard-supply = <&vccio_sd>; | ||
82 | wifi-supply = <&vcc18_wl>; | ||
83 | }; | ||
diff --git a/Documentation/devicetree/bindings/power_supply/charger-manager.txt b/Documentation/devicetree/bindings/power_supply/charger-manager.txt index 2b33750e3db2..ec4fe9de3137 100644 --- a/Documentation/devicetree/bindings/power_supply/charger-manager.txt +++ b/Documentation/devicetree/bindings/power_supply/charger-manager.txt | |||
@@ -24,7 +24,7 @@ Optional properties : | |||
24 | - cm-thermal-zone : name of external thermometer's thermal zone | 24 | - cm-thermal-zone : name of external thermometer's thermal zone |
25 | - cm-battery-* : threshold battery temperature for charging | 25 | - cm-battery-* : threshold battery temperature for charging |
26 | -cold : critical cold temperature of battery for charging | 26 | -cold : critical cold temperature of battery for charging |
27 | -cold-in-minus : flag that cold temerature is in minus degree | 27 | -cold-in-minus : flag that cold temperature is in minus degrees |
28 | -hot : critical hot temperature of battery for charging | 28 | -hot : critical hot temperature of battery for charging |
29 | -temp-diff : temperature difference to allow recharging | 29 | -temp-diff : temperature difference to allow recharging |
30 | - cm-dis/charging-max = limits of charging duration | 30 | - cm-dis/charging-max = limits of charging duration |
diff --git a/Documentation/devicetree/bindings/power_supply/gpio-charger.txt b/Documentation/devicetree/bindings/power_supply/gpio-charger.txt new file mode 100644 index 000000000000..adbb5dc5b6e9 --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/gpio-charger.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | gpio-charger | ||
2 | |||
3 | Required properties : | ||
4 | - compatible : "gpio-charger" | ||
5 | - gpios : GPIO indicating the charger presence. | ||
6 | See GPIO binding in bindings/gpio/gpio.txt . | ||
7 | - charger-type : power supply type, one of | ||
8 | unknown | ||
9 | battery | ||
10 | ups | ||
11 | mains | ||
12 | usb-sdp (USB standard downstream port) | ||
13 | usb-dcp (USB dedicated charging port) | ||
14 | usb-cdp (USB charging downstream port) | ||
15 | usb-aca (USB accessory charger adapter) | ||
16 | |||
17 | Example: | ||
18 | |||
19 | usb_charger: charger { | ||
20 | compatible = "gpio-charger"; | ||
21 | charger-type = "usb-sdp"; | ||
22 | gpios = <&gpf0 2 0 0 0>; | ||
23 | } | ||
24 | |||
25 | battery { | ||
26 | power-supplies = <&usb_charger>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt b/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt new file mode 100644 index 000000000000..dc7c9bad63ea --- /dev/null +++ b/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt | |||
@@ -0,0 +1,23 @@ | |||
1 | i.mx6 Poweroff Driver | ||
2 | |||
3 | SNVS_LPCR in SNVS module can power off the whole system by pull | ||
4 | PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC. | ||
5 | If you don't want to use PMIC_ON_REQ as power on/off control, | ||
6 | please set status='disabled' to disable this driver. | ||
7 | |||
8 | Required Properties: | ||
9 | -compatible: "fsl,sec-v4.0-poweroff" | ||
10 | -reg: Specifies the physical address of the SNVS_LPCR register | ||
11 | |||
12 | Example: | ||
13 | snvs@020cc000 { | ||
14 | compatible = "fsl,sec-v4.0-mon", "simple-bus"; | ||
15 | #address-cells = <1>; | ||
16 | #size-cells = <1>; | ||
17 | ranges = <0 0x020cc000 0x4000>; | ||
18 | ..... | ||
19 | snvs_poweroff: snvs-poweroff@38 { | ||
20 | compatible = "fsl,sec-v4.0-poweroff"; | ||
21 | reg = <0x38 0x4>; | ||
22 | }; | ||
23 | } | ||
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt new file mode 100644 index 000000000000..edeea160ca39 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt | |||
@@ -0,0 +1,534 @@ | |||
1 | ============================================================================= | ||
2 | Freescale Frame Manager Device Bindings | ||
3 | |||
4 | CONTENTS | ||
5 | - FMan Node | ||
6 | - FMan Port Node | ||
7 | - FMan MURAM Node | ||
8 | - FMan dTSEC/XGEC/mEMAC Node | ||
9 | - FMan IEEE 1588 Node | ||
10 | - Example | ||
11 | |||
12 | ============================================================================= | ||
13 | FMan Node | ||
14 | |||
15 | DESCRIPTION | ||
16 | |||
17 | Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs, | ||
18 | etc.) the FMan node will have child nodes for each of them. | ||
19 | |||
20 | PROPERTIES | ||
21 | |||
22 | - compatible | ||
23 | Usage: required | ||
24 | Value type: <stringlist> | ||
25 | Definition: Must include "fsl,fman" | ||
26 | FMan version can be determined via FM_IP_REV_1 register in the | ||
27 | FMan block. The offset is 0xc4 from the beginning of the | ||
28 | Frame Processing Manager memory map (0xc3000 from the | ||
29 | beginning of the FMan node). | ||
30 | |||
31 | - cell-index | ||
32 | Usage: required | ||
33 | Value type: <u32> | ||
34 | Definition: Specifies the index of the FMan unit. | ||
35 | |||
36 | The cell-index value may be used by the SoC, to identify the | ||
37 | FMan unit in the SoC memory map. In the table bellow, | ||
38 | there's a description of the cell-index use in each SoC: | ||
39 | |||
40 | - P1023: | ||
41 | register[bit] FMan unit cell-index | ||
42 | ============================================================ | ||
43 | DEVDISR[1] 1 0 | ||
44 | |||
45 | - P2041, P3041, P4080 P5020, P5040: | ||
46 | register[bit] FMan unit cell-index | ||
47 | ============================================================ | ||
48 | DCFG_DEVDISR2[6] 1 0 | ||
49 | DCFG_DEVDISR2[14] 2 1 | ||
50 | (Second FM available only in P4080 and P5040) | ||
51 | |||
52 | - B4860, T1040, T2080, T4240: | ||
53 | register[bit] FMan unit cell-index | ||
54 | ============================================================ | ||
55 | DCFG_CCSR_DEVDISR2[24] 1 0 | ||
56 | DCFG_CCSR_DEVDISR2[25] 2 1 | ||
57 | (Second FM available only in T4240) | ||
58 | |||
59 | DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in | ||
60 | the specific SoC "Device Configuration/Pin Control" Memory | ||
61 | Map. | ||
62 | |||
63 | - reg | ||
64 | Usage: required | ||
65 | Value type: <prop-encoded-array> | ||
66 | Definition: A standard property. Specifies the offset of the | ||
67 | following configuration registers: | ||
68 | - BMI configuration registers. | ||
69 | - QMI configuration registers. | ||
70 | - DMA configuration registers. | ||
71 | - FPM configuration registers. | ||
72 | - FMan controller configuration registers. | ||
73 | |||
74 | - ranges | ||
75 | Usage: required | ||
76 | Value type: <prop-encoded-array> | ||
77 | Definition: A standard property. | ||
78 | |||
79 | - clocks | ||
80 | Usage: required | ||
81 | Value type: <prop-encoded-array> | ||
82 | Definition: phandle for the fman input clock. | ||
83 | |||
84 | - clock-names | ||
85 | usage: required | ||
86 | Value type: <stringlist> | ||
87 | Definition: "fmanclk" for the fman input clock. | ||
88 | |||
89 | - interrupts | ||
90 | Usage: required | ||
91 | Value type: <prop-encoded-array> | ||
92 | Definition: A pair of IRQs are specified in this property. | ||
93 | The first element is associated with the event interrupts and | ||
94 | the second element is associated with the error interrupts. | ||
95 | |||
96 | - fsl,qman-channel-range | ||
97 | Usage: required | ||
98 | Value type: <prop-encoded-array> | ||
99 | Definition: Specifies the range of the available dedicated | ||
100 | channels in the FMan. The first cell specifies the beginning | ||
101 | of the range and the second cell specifies the number of | ||
102 | channels. | ||
103 | Further information available at: | ||
104 | "Work Queue (WQ) Channel Assignments in the QMan" section | ||
105 | in DPAA Reference Manual. | ||
106 | |||
107 | - fsl,qman | ||
108 | - fsl,bman | ||
109 | Usage: required | ||
110 | Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt | ||
111 | |||
112 | ============================================================================= | ||
113 | FMan MURAM Node | ||
114 | |||
115 | DESCRIPTION | ||
116 | |||
117 | FMan Internal memory - shared between all the FMan modules. | ||
118 | It contains data structures that are common and written to or read by | ||
119 | the modules. | ||
120 | FMan internal memory is split into the following parts: | ||
121 | Packet buffering (Tx/Rx FIFOs) | ||
122 | Frames internal context | ||
123 | |||
124 | PROPERTIES | ||
125 | |||
126 | - compatible | ||
127 | Usage: required | ||
128 | Value type: <stringlist> | ||
129 | Definition: Must include "fsl,fman-muram" | ||
130 | |||
131 | - ranges | ||
132 | Usage: required | ||
133 | Value type: <prop-encoded-array> | ||
134 | Definition: A standard property. | ||
135 | Specifies the multi-user memory offset and the size within | ||
136 | the FMan. | ||
137 | |||
138 | EXAMPLE | ||
139 | |||
140 | muram@0 { | ||
141 | compatible = "fsl,fman-muram"; | ||
142 | ranges = <0 0x000000 0x28000>; | ||
143 | }; | ||
144 | |||
145 | ============================================================================= | ||
146 | FMan Port Node | ||
147 | |||
148 | DESCRIPTION | ||
149 | |||
150 | The Frame Manager (FMan) supports several types of hardware ports: | ||
151 | Ethernet receiver (RX) | ||
152 | Ethernet transmitter (TX) | ||
153 | Offline/Host command (O/H) | ||
154 | |||
155 | PROPERTIES | ||
156 | |||
157 | - compatible | ||
158 | Usage: required | ||
159 | Value type: <stringlist> | ||
160 | Definition: A standard property. | ||
161 | Must include one of the following: | ||
162 | - "fsl,fman-v2-port-oh" for FManV2 OH ports | ||
163 | - "fsl,fman-v2-port-rx" for FManV2 RX ports | ||
164 | - "fsl,fman-v2-port-tx" for FManV2 TX ports | ||
165 | - "fsl,fman-v3-port-oh" for FManV3 OH ports | ||
166 | - "fsl,fman-v3-port-rx" for FManV3 RX ports | ||
167 | - "fsl,fman-v3-port-tx" for FManV3 TX ports | ||
168 | |||
169 | - cell-index | ||
170 | Usage: required | ||
171 | Value type: <u32> | ||
172 | Definition: Specifies the hardware port id. | ||
173 | Each hardware port on the FMan has its own hardware PortID. | ||
174 | Super set of all hardware Port IDs available at FMan Reference | ||
175 | Manual under "FMan Hardware Ports in Freescale Devices" table. | ||
176 | |||
177 | Each hardware port is assigned a 4KB, port-specific page in | ||
178 | the FMan hardware port memory region (which is part of the | ||
179 | FMan memory map). The first 4 KB in the FMan hardware ports | ||
180 | memory region is used for what are called common registers. | ||
181 | The subsequent 63 4KB pages are allocated to the hardware | ||
182 | ports. | ||
183 | The page of a specific port is determined by the cell-index. | ||
184 | |||
185 | - reg | ||
186 | Usage: required | ||
187 | Value type: <prop-encoded-array> | ||
188 | Definition: There is one reg region describing the port | ||
189 | configuration registers. | ||
190 | |||
191 | EXAMPLE | ||
192 | |||
193 | port@a8000 { | ||
194 | cell-index = <0x28>; | ||
195 | compatible = "fsl,fman-v2-port-tx"; | ||
196 | reg = <0xa8000 0x1000>; | ||
197 | }; | ||
198 | |||
199 | port@88000 { | ||
200 | cell-index = <0x8>; | ||
201 | compatible = "fsl,fman-v2-port-rx"; | ||
202 | reg = <0x88000 0x1000>; | ||
203 | }; | ||
204 | |||
205 | port@81000 { | ||
206 | cell-index = <0x1>; | ||
207 | compatible = "fsl,fman-v2-port-oh"; | ||
208 | reg = <0x81000 0x1000>; | ||
209 | }; | ||
210 | |||
211 | ============================================================================= | ||
212 | FMan dTSEC/XGEC/mEMAC Node | ||
213 | |||
214 | DESCRIPTION | ||
215 | |||
216 | mEMAC/dTSEC/XGEC are the Ethernet network interfaces | ||
217 | |||
218 | PROPERTIES | ||
219 | |||
220 | - compatible | ||
221 | Usage: required | ||
222 | Value type: <stringlist> | ||
223 | Definition: A standard property. | ||
224 | Must include one of the following: | ||
225 | - "fsl,fman-dtsec" for dTSEC MAC | ||
226 | - "fsl,fman-xgec" for XGEC MAC | ||
227 | - "fsl,fman-memac for mEMAC MAC | ||
228 | |||
229 | - cell-index | ||
230 | Usage: required | ||
231 | Value type: <u32> | ||
232 | Definition: Specifies the MAC id. | ||
233 | |||
234 | The cell-index value may be used by the FMan or the SoC, to | ||
235 | identify the MAC unit in the FMan (or SoC) memory map. | ||
236 | In the tables bellow there's a description of the cell-index | ||
237 | use, there are two tables, one describes the use of cell-index | ||
238 | by the FMan, the second describes the use by the SoC: | ||
239 | |||
240 | 1. FMan Registers | ||
241 | |||
242 | FManV2: | ||
243 | register[bit] MAC cell-index | ||
244 | ============================================================ | ||
245 | FM_EPI[16] XGEC 8 | ||
246 | FM_EPI[16+n] dTSECn n-1 | ||
247 | FM_NPI[11+n] dTSECn n-1 | ||
248 | n = 1,..,5 | ||
249 | |||
250 | FManV3: | ||
251 | register[bit] MAC cell-index | ||
252 | ============================================================ | ||
253 | FM_EPI[16+n] mEMACn n-1 | ||
254 | FM_EPI[25] mEMAC10 9 | ||
255 | |||
256 | FM_NPI[11+n] mEMACn n-1 | ||
257 | FM_NPI[10] mEMAC10 9 | ||
258 | FM_NPI[11] mEMAC9 8 | ||
259 | n = 1,..8 | ||
260 | |||
261 | FM_EPI and FM_NPI are located in the FMan memory map. | ||
262 | |||
263 | 2. SoC registers: | ||
264 | |||
265 | - P2041, P3041, P4080 P5020, P5040: | ||
266 | register[bit] FMan MAC cell | ||
267 | Unit index | ||
268 | ============================================================ | ||
269 | DCFG_DEVDISR2[7] 1 XGEC 8 | ||
270 | DCFG_DEVDISR2[7+n] 1 dTSECn n-1 | ||
271 | DCFG_DEVDISR2[15] 2 XGEC 8 | ||
272 | DCFG_DEVDISR2[15+n] 2 dTSECn n-1 | ||
273 | n = 1,..5 | ||
274 | |||
275 | - T1040, T2080, T4240, B4860: | ||
276 | register[bit] FMan MAC cell | ||
277 | Unit index | ||
278 | ============================================================ | ||
279 | DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1 | ||
280 | DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1 | ||
281 | n = 1,..6,9,10 | ||
282 | |||
283 | EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in | ||
284 | the specific SoC "Device Configuration/Pin Control" Memory | ||
285 | Map. | ||
286 | |||
287 | - reg | ||
288 | Usage: required | ||
289 | Value type: <prop-encoded-array> | ||
290 | Definition: A standard property. | ||
291 | |||
292 | - fsl,fman-ports | ||
293 | Usage: required | ||
294 | Value type: <prop-encoded-array> | ||
295 | Definition: An array of two phandles - the first references is | ||
296 | the FMan RX port and the second is the TX port used by this | ||
297 | MAC. | ||
298 | |||
299 | - ptp-timer | ||
300 | Usage required | ||
301 | Value type: <phandle> | ||
302 | Definition: A phandle for 1EEE1588 timer. | ||
303 | |||
304 | EXAMPLE | ||
305 | |||
306 | fman1_tx28: port@a8000 { | ||
307 | cell-index = <0x28>; | ||
308 | compatible = "fsl,fman-v2-port-tx"; | ||
309 | reg = <0xa8000 0x1000>; | ||
310 | }; | ||
311 | |||
312 | fman1_rx8: port@88000 { | ||
313 | cell-index = <0x8>; | ||
314 | compatible = "fsl,fman-v2-port-rx"; | ||
315 | reg = <0x88000 0x1000>; | ||
316 | }; | ||
317 | |||
318 | ptp-timer: ptp_timer@fe000 { | ||
319 | compatible = "fsl,fman-ptp-timer"; | ||
320 | reg = <0xfe000 0x1000>; | ||
321 | }; | ||
322 | |||
323 | ethernet@e0000 { | ||
324 | compatible = "fsl,fman-dtsec"; | ||
325 | cell-index = <0>; | ||
326 | reg = <0xe0000 0x1000>; | ||
327 | fsl,fman-ports = <&fman1_rx8 &fman1_tx28>; | ||
328 | ptp-timer = <&ptp-timer>; | ||
329 | }; | ||
330 | |||
331 | ============================================================================ | ||
332 | FMan IEEE 1588 Node | ||
333 | |||
334 | DESCRIPTION | ||
335 | |||
336 | The FMan interface to support IEEE 1588 | ||
337 | |||
338 | |||
339 | PROPERTIES | ||
340 | |||
341 | - compatible | ||
342 | Usage: required | ||
343 | Value type: <stringlist> | ||
344 | Definition: A standard property. | ||
345 | Must include "fsl,fman-ptp-timer". | ||
346 | |||
347 | - reg | ||
348 | Usage: required | ||
349 | Value type: <prop-encoded-array> | ||
350 | Definition: A standard property. | ||
351 | |||
352 | EXAMPLE | ||
353 | |||
354 | ptp-timer@fe000 { | ||
355 | compatible = "fsl,fman-ptp-timer"; | ||
356 | reg = <0xfe000 0x1000>; | ||
357 | }; | ||
358 | |||
359 | ============================================================================= | ||
360 | Example | ||
361 | |||
362 | fman@400000 { | ||
363 | #address-cells = <1>; | ||
364 | #size-cells = <1>; | ||
365 | cell-index = <1>; | ||
366 | compatible = "fsl,fman" | ||
367 | ranges = <0 0x400000 0x100000>; | ||
368 | reg = <0x400000 0x100000>; | ||
369 | clocks = <&fman_clk>; | ||
370 | clock-names = "fmanclk"; | ||
371 | interrupts = < | ||
372 | 96 2 0 0 | ||
373 | 16 2 1 1>; | ||
374 | fsl,qman-channel-range = <0x40 0xc>; | ||
375 | |||
376 | muram@0 { | ||
377 | compatible = "fsl,fman-muram"; | ||
378 | reg = <0x0 0x28000>; | ||
379 | }; | ||
380 | |||
381 | port@81000 { | ||
382 | cell-index = <1>; | ||
383 | compatible = "fsl,fman-v2-port-oh"; | ||
384 | reg = <0x81000 0x1000>; | ||
385 | }; | ||
386 | |||
387 | port@82000 { | ||
388 | cell-index = <2>; | ||
389 | compatible = "fsl,fman-v2-port-oh"; | ||
390 | reg = <0x82000 0x1000>; | ||
391 | }; | ||
392 | |||
393 | port@83000 { | ||
394 | cell-index = <3>; | ||
395 | compatible = "fsl,fman-v2-port-oh"; | ||
396 | reg = <0x83000 0x1000>; | ||
397 | }; | ||
398 | |||
399 | port@84000 { | ||
400 | cell-index = <4>; | ||
401 | compatible = "fsl,fman-v2-port-oh"; | ||
402 | reg = <0x84000 0x1000>; | ||
403 | }; | ||
404 | |||
405 | port@85000 { | ||
406 | cell-index = <5>; | ||
407 | compatible = "fsl,fman-v2-port-oh"; | ||
408 | reg = <0x85000 0x1000>; | ||
409 | }; | ||
410 | |||
411 | port@86000 { | ||
412 | cell-index = <6>; | ||
413 | compatible = "fsl,fman-v2-port-oh"; | ||
414 | reg = <0x86000 0x1000>; | ||
415 | }; | ||
416 | |||
417 | fman1_rx_0x8: port@88000 { | ||
418 | cell-index = <0x8>; | ||
419 | compatible = "fsl,fman-v2-port-rx"; | ||
420 | reg = <0x88000 0x1000>; | ||
421 | }; | ||
422 | |||
423 | fman1_rx_0x9: port@89000 { | ||
424 | cell-index = <0x9>; | ||
425 | compatible = "fsl,fman-v2-port-rx"; | ||
426 | reg = <0x89000 0x1000>; | ||
427 | }; | ||
428 | |||
429 | fman1_rx_0xa: port@8a000 { | ||
430 | cell-index = <0xa>; | ||
431 | compatible = "fsl,fman-v2-port-rx"; | ||
432 | reg = <0x8a000 0x1000>; | ||
433 | }; | ||
434 | |||
435 | fman1_rx_0xb: port@8b000 { | ||
436 | cell-index = <0xb>; | ||
437 | compatible = "fsl,fman-v2-port-rx"; | ||
438 | reg = <0x8b000 0x1000>; | ||
439 | }; | ||
440 | |||
441 | fman1_rx_0xc: port@8c000 { | ||
442 | cell-index = <0xc>; | ||
443 | compatible = "fsl,fman-v2-port-rx"; | ||
444 | reg = <0x8c000 0x1000>; | ||
445 | }; | ||
446 | |||
447 | fman1_rx_0x10: port@90000 { | ||
448 | cell-index = <0x10>; | ||
449 | compatible = "fsl,fman-v2-port-rx"; | ||
450 | reg = <0x90000 0x1000>; | ||
451 | }; | ||
452 | |||
453 | fman1_tx_0x28: port@a8000 { | ||
454 | cell-index = <0x28>; | ||
455 | compatible = "fsl,fman-v2-port-tx"; | ||
456 | reg = <0xa8000 0x1000>; | ||
457 | }; | ||
458 | |||
459 | fman1_tx_0x29: port@a9000 { | ||
460 | cell-index = <0x29>; | ||
461 | compatible = "fsl,fman-v2-port-tx"; | ||
462 | reg = <0xa9000 0x1000>; | ||
463 | }; | ||
464 | |||
465 | fman1_tx_0x2a: port@aa000 { | ||
466 | cell-index = <0x2a>; | ||
467 | compatible = "fsl,fman-v2-port-tx"; | ||
468 | reg = <0xaa000 0x1000>; | ||
469 | }; | ||
470 | |||
471 | fman1_tx_0x2b: port@ab000 { | ||
472 | cell-index = <0x2b>; | ||
473 | compatible = "fsl,fman-v2-port-tx"; | ||
474 | reg = <0xab000 0x1000>; | ||
475 | }; | ||
476 | |||
477 | fman1_tx_0x2c: port@ac0000 { | ||
478 | cell-index = <0x2c>; | ||
479 | compatible = "fsl,fman-v2-port-tx"; | ||
480 | reg = <0xac000 0x1000>; | ||
481 | }; | ||
482 | |||
483 | fman1_tx_0x30: port@b0000 { | ||
484 | cell-index = <0x30>; | ||
485 | compatible = "fsl,fman-v2-port-tx"; | ||
486 | reg = <0xb0000 0x1000>; | ||
487 | }; | ||
488 | |||
489 | ethernet@e0000 { | ||
490 | compatible = "fsl,fman-dtsec"; | ||
491 | cell-index = <0>; | ||
492 | reg = <0xe0000 0x1000>; | ||
493 | fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>; | ||
494 | }; | ||
495 | |||
496 | ethernet@e2000 { | ||
497 | compatible = "fsl,fman-dtsec"; | ||
498 | cell-index = <1>; | ||
499 | reg = <0xe2000 0x1000>; | ||
500 | fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>; | ||
501 | }; | ||
502 | |||
503 | ethernet@e4000 { | ||
504 | compatible = "fsl,fman-dtsec"; | ||
505 | cell-index = <2>; | ||
506 | reg = <0xe4000 0x1000>; | ||
507 | fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>; | ||
508 | }; | ||
509 | |||
510 | ethernet@e6000 { | ||
511 | compatible = "fsl,fman-dtsec"; | ||
512 | cell-index = <3>; | ||
513 | reg = <0xe6000 0x1000>; | ||
514 | fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>; | ||
515 | }; | ||
516 | |||
517 | ethernet@e8000 { | ||
518 | compatible = "fsl,fman-dtsec"; | ||
519 | cell-index = <4>; | ||
520 | reg = <0xf0000 0x1000>; | ||
521 | fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>; | ||
522 | |||
523 | ethernet@f0000 { | ||
524 | cell-index = <8>; | ||
525 | compatible = "fsl,fman-xgec"; | ||
526 | reg = <0xf0000 0x1000>; | ||
527 | fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>; | ||
528 | }; | ||
529 | |||
530 | ptp-timer@fe000 { | ||
531 | compatible = "fsl,fman-ptp-timer"; | ||
532 | reg = <0xfe000 0x1000>; | ||
533 | }; | ||
534 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt new file mode 100644 index 000000000000..cfda0d57d302 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | |||
@@ -0,0 +1,29 @@ | |||
1 | Device-Tree bindings for Atmel's HLCDC (High-end LCD Controller) PWM driver | ||
2 | |||
3 | The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. | ||
4 | See ../mfd/atmel-hlcdc.txt for more details. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: value should be one of the following: | ||
8 | "atmel,hlcdc-pwm" | ||
9 | - pinctr-names: the pin control state names. Should contain "default". | ||
10 | - pinctrl-0: should contain the pinctrl states described by pinctrl | ||
11 | default. | ||
12 | - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells | ||
13 | bindings defined in pwm.txt in this directory. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | hlcdc: hlcdc@f0030000 { | ||
18 | compatible = "atmel,sama5d3-hlcdc"; | ||
19 | reg = <0xf0030000 0x2000>; | ||
20 | clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; | ||
21 | clock-names = "periph_clk","sys_clk", "slow_clk"; | ||
22 | |||
23 | hlcdc_pwm: hlcdc-pwm { | ||
24 | compatible = "atmel,hlcdc-pwm"; | ||
25 | pinctrl-names = "default"; | ||
26 | pinctrl-0 = <&pinctrl_lcd_pwm>; | ||
27 | #pwm-cells = <3>; | ||
28 | }; | ||
29 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt new file mode 100644 index 000000000000..fb6fb31bc4c4 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-bcm2835.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | BCM2835 PWM controller (Raspberry Pi controller) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "brcm,bcm2835-pwm" | ||
5 | - reg: physical base address and length of the controller's registers | ||
6 | - clock: This clock defines the base clock frequency of the PWM hardware | ||
7 | system, the period and the duty_cycle of the PWM signal is a multiple of | ||
8 | the base period. | ||
9 | - #pwm-cells: Should be 2. See pwm.txt in this directory for a description of | ||
10 | the cells format. | ||
11 | |||
12 | Examples: | ||
13 | |||
14 | pwm@2020c000 { | ||
15 | compatible = "brcm,bcm2835-pwm"; | ||
16 | reg = <0x2020c000 0x28>; | ||
17 | clocks = <&clk_pwm>; | ||
18 | #pwm-cells = <2>; | ||
19 | }; | ||
20 | |||
21 | clocks { | ||
22 | .... | ||
23 | clk_pwm: pwm { | ||
24 | compatible = "fixed-clock"; | ||
25 | reg = <3>; | ||
26 | #clock-cells = <0>; | ||
27 | clock-frequency = <9200000>; | ||
28 | }; | ||
29 | .... | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt index 0bda229a6171..3899d6a557c1 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt | |||
@@ -1,5 +1,20 @@ | |||
1 | Freescale FlexTimer Module (FTM) PWM controller | 1 | Freescale FlexTimer Module (FTM) PWM controller |
2 | 2 | ||
3 | The same FTM PWM device can have a different endianness on different SoCs. The | ||
4 | device tree provides a property to describing this so that an operating system | ||
5 | device driver can handle all variants of the device. Refer to the table below | ||
6 | for the endianness of the FTM PWM block as integrated into the existing SoCs: | ||
7 | |||
8 | SoC | FTM-PWM endianness | ||
9 | --------+------------------- | ||
10 | Vybrid | LE | ||
11 | LS1 | BE | ||
12 | LS2 | LE | ||
13 | |||
14 | Please see ../regmap/regmap.txt for more detail about how to specify endian | ||
15 | modes in device tree. | ||
16 | |||
17 | |||
3 | Required properties: | 18 | Required properties: |
4 | - compatible: Should be "fsl,vf610-ftm-pwm". | 19 | - compatible: Should be "fsl,vf610-ftm-pwm". |
5 | - reg: Physical base address and length of the controller's registers | 20 | - reg: Physical base address and length of the controller's registers |
@@ -16,7 +31,8 @@ Required properties: | |||
16 | - pinctrl-names: Must contain a "default" entry. | 31 | - pinctrl-names: Must contain a "default" entry. |
17 | - pinctrl-NNN: One property must exist for each entry in pinctrl-names. | 32 | - pinctrl-NNN: One property must exist for each entry in pinctrl-names. |
18 | See pinctrl/pinctrl-bindings.txt for details of the property values. | 33 | See pinctrl/pinctrl-bindings.txt for details of the property values. |
19 | 34 | - big-endian: Boolean property, required if the FTM PWM registers use a big- | |
35 | endian rather than little-endian layout. | ||
20 | 36 | ||
21 | Example: | 37 | Example: |
22 | 38 | ||
@@ -32,4 +48,5 @@ pwm0: pwm@40038000 { | |||
32 | <&clks VF610_CLK_FTM0_EXT_FIX_EN>; | 48 | <&clks VF610_CLK_FTM0_EXT_FIX_EN>; |
33 | pinctrl-names = "default"; | 49 | pinctrl-names = "default"; |
34 | pinctrl-0 = <&pinctrl_pwm0_1>; | 50 | pinctrl-0 = <&pinctrl_pwm0_1>; |
51 | big-endian; | ||
35 | }; | 52 | }; |
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt index d47d15a6a298..b8be3d09ee26 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt | |||
@@ -7,8 +7,8 @@ Required properties: | |||
7 | "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC | 7 | "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC |
8 | - reg: physical base address and length of the controller's registers | 8 | - reg: physical base address and length of the controller's registers |
9 | - clocks: phandle and clock specifier of the PWM reference clock | 9 | - clocks: phandle and clock specifier of the PWM reference clock |
10 | - #pwm-cells: should be 2. See pwm.txt in this directory for a | 10 | - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory |
11 | description of the cell format. | 11 | for a description of the cell format. |
12 | 12 | ||
13 | Example: | 13 | Example: |
14 | 14 | ||
diff --git a/Documentation/devicetree/bindings/regmap/regmap.txt b/Documentation/devicetree/bindings/regmap/regmap.txt new file mode 100644 index 000000000000..b494f8b8ef72 --- /dev/null +++ b/Documentation/devicetree/bindings/regmap/regmap.txt | |||
@@ -0,0 +1,47 @@ | |||
1 | Device-Tree binding for regmap | ||
2 | |||
3 | The endianness mode of CPU & Device scenarios: | ||
4 | Index Device Endianness properties | ||
5 | --------------------------------------------------- | ||
6 | 1 BE 'big-endian' | ||
7 | 2 LE 'little-endian' | ||
8 | |||
9 | For one device driver, which will run in different scenarios above | ||
10 | on different SoCs using the devicetree, we need one way to simplify | ||
11 | this. | ||
12 | |||
13 | Required properties: | ||
14 | - {big,little}-endian: these are boolean properties, if absent | ||
15 | meaning that the CPU and the Device are in the same endianness mode, | ||
16 | these properties are for register values and all the buffers only. | ||
17 | |||
18 | Examples: | ||
19 | Scenario 1 : CPU in LE mode & device in LE mode. | ||
20 | dev: dev@40031000 { | ||
21 | compatible = "name"; | ||
22 | reg = <0x40031000 0x1000>; | ||
23 | ... | ||
24 | }; | ||
25 | |||
26 | Scenario 2 : CPU in LE mode & device in BE mode. | ||
27 | dev: dev@40031000 { | ||
28 | compatible = "name"; | ||
29 | reg = <0x40031000 0x1000>; | ||
30 | ... | ||
31 | big-endian; | ||
32 | }; | ||
33 | |||
34 | Scenario 3 : CPU in BE mode & device in BE mode. | ||
35 | dev: dev@40031000 { | ||
36 | compatible = "name"; | ||
37 | reg = <0x40031000 0x1000>; | ||
38 | ... | ||
39 | }; | ||
40 | |||
41 | Scenario 4 : CPU in BE mode & device in LE mode. | ||
42 | dev: dev@40031000 { | ||
43 | compatible = "name"; | ||
44 | reg = <0x40031000 0x1000>; | ||
45 | ... | ||
46 | little-endian; | ||
47 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt index 865614b34d6f..dad6358074ac 100644 --- a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt +++ b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt | |||
@@ -5,6 +5,10 @@ Required properties: | |||
5 | - compatible: "active-semi,act8846" or "active-semi,act8865" | 5 | - compatible: "active-semi,act8846" or "active-semi,act8865" |
6 | - reg: I2C slave address | 6 | - reg: I2C slave address |
7 | 7 | ||
8 | Optional properties: | ||
9 | - system-power-controller: Telling whether or not this pmic is controlling | ||
10 | the system power. See Documentation/devicetree/bindings/power/power-controller.txt . | ||
11 | |||
8 | Any standard regulator properties can be used to configure the single regulator. | 12 | Any standard regulator properties can be used to configure the single regulator. |
9 | 13 | ||
10 | The valid names for regulators are: | 14 | The valid names for regulators are: |
diff --git a/Documentation/devicetree/bindings/regulator/da9210.txt b/Documentation/devicetree/bindings/regulator/da9210.txt index f120f229d67d..3297c53cb915 100644 --- a/Documentation/devicetree/bindings/regulator/da9210.txt +++ b/Documentation/devicetree/bindings/regulator/da9210.txt | |||
@@ -2,7 +2,7 @@ | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible: must be "diasemi,da9210" | 5 | - compatible: must be "dlg,da9210" |
6 | - reg: the i2c slave address of the regulator. It should be 0x68. | 6 | - reg: the i2c slave address of the regulator. It should be 0x68. |
7 | 7 | ||
8 | Any standard regulator properties can be used to configure the single da9210 | 8 | Any standard regulator properties can be used to configure the single da9210 |
@@ -11,7 +11,7 @@ DCDC. | |||
11 | Example: | 11 | Example: |
12 | 12 | ||
13 | da9210@68 { | 13 | da9210@68 { |
14 | compatible = "diasemi,da9210"; | 14 | compatible = "dlg,da9210"; |
15 | reg = <0x68>; | 15 | reg = <0x68>; |
16 | 16 | ||
17 | regulator-min-microvolt = <900000>; | 17 | regulator-min-microvolt = <900000>; |
diff --git a/Documentation/devicetree/bindings/regulator/da9211.txt b/Documentation/devicetree/bindings/regulator/da9211.txt new file mode 100644 index 000000000000..240019a82f9a --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/da9211.txt | |||
@@ -0,0 +1,63 @@ | |||
1 | * Dialog Semiconductor DA9211/DA9213 Voltage Regulator | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: "dlg,da9211" or "dlg,da9213". | ||
5 | - reg: I2C slave address, usually 0x68. | ||
6 | - interrupts: the interrupt outputs of the controller | ||
7 | - regulators: A node that houses a sub-node for each regulator within the | ||
8 | device. Each sub-node is identified using the node's name, with valid | ||
9 | values listed below. The content of each sub-node is defined by the | ||
10 | standard binding for regulators; see regulator.txt. | ||
11 | BUCKA and BUCKB. | ||
12 | |||
13 | Optional properties: | ||
14 | - Any optional property defined in regulator.txt | ||
15 | |||
16 | Example 1) DA9211 | ||
17 | |||
18 | pmic: da9211@68 { | ||
19 | compatible = "dlg,da9211"; | ||
20 | reg = <0x68>; | ||
21 | interrupts = <3 27>; | ||
22 | |||
23 | regulators { | ||
24 | BUCKA { | ||
25 | regulator-name = "VBUCKA"; | ||
26 | regulator-min-microvolt = < 300000>; | ||
27 | regulator-max-microvolt = <1570000>; | ||
28 | regulator-min-microamp = <2000000>; | ||
29 | regulator-max-microamp = <5000000>; | ||
30 | }; | ||
31 | BUCKB { | ||
32 | regulator-name = "VBUCKB"; | ||
33 | regulator-min-microvolt = < 300000>; | ||
34 | regulator-max-microvolt = <1570000>; | ||
35 | regulator-min-microamp = <2000000>; | ||
36 | regulator-max-microamp = <5000000>; | ||
37 | }; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | Example 2) DA92113 | ||
42 | pmic: da9213@68 { | ||
43 | compatible = "dlg,da9213"; | ||
44 | reg = <0x68>; | ||
45 | interrupts = <3 27>; | ||
46 | |||
47 | regulators { | ||
48 | BUCKA { | ||
49 | regulator-name = "VBUCKA"; | ||
50 | regulator-min-microvolt = < 300000>; | ||
51 | regulator-max-microvolt = <1570000>; | ||
52 | regulator-min-microamp = <3000000>; | ||
53 | regulator-max-microamp = <6000000>; | ||
54 | }; | ||
55 | BUCKB { | ||
56 | regulator-name = "VBUCKB"; | ||
57 | regulator-min-microvolt = < 300000>; | ||
58 | regulator-max-microvolt = <1570000>; | ||
59 | regulator-min-microamp = <3000000>; | ||
60 | regulator-max-microamp = <6000000>; | ||
61 | }; | ||
62 | }; | ||
63 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/fan53555.txt b/Documentation/devicetree/bindings/regulator/fan53555.txt new file mode 100644 index 000000000000..54a3f2c80e3a --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/fan53555.txt | |||
@@ -0,0 +1,23 @@ | |||
1 | Binding for Fairchild FAN53555 regulators | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: one of "fcs,fan53555", "silergy,syr827", "silergy,syr828" | ||
5 | - reg: I2C address | ||
6 | |||
7 | Optional properties: | ||
8 | - fcs,suspend-voltage-selector: declare which of the two available | ||
9 | voltage selector registers should be used for the suspend | ||
10 | voltage. The other one is used for the runtime voltage setting | ||
11 | Possible values are either <0> or <1> | ||
12 | - vin-supply: regulator supplying the vin pin | ||
13 | |||
14 | Example: | ||
15 | |||
16 | regulator@40 { | ||
17 | compatible = "fcs,fan53555"; | ||
18 | regulator-name = "fan53555"; | ||
19 | regulator-min-microvolt = <1000000>; | ||
20 | regulator-max-microvolt = <1800000>; | ||
21 | vin-supply = <&parent_reg>; | ||
22 | fcs,suspend-voltage-selector = <1>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/isl9305.txt b/Documentation/devicetree/bindings/regulator/isl9305.txt new file mode 100644 index 000000000000..a626fc1bbf0d --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/isl9305.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | Intersil ISL9305/ISL9305H voltage regulator | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: "isl,isl9305" or "isl,isl9305h" | ||
6 | - reg: I2C slave address, usually 0x68. | ||
7 | - regulators: A node that houses a sub-node for each regulator within the | ||
8 | device. Each sub-node is identified using the node's name, with valid | ||
9 | values being "dcd1", "dcd2", "ldo1" and "ldo2". The content of each sub-node | ||
10 | is defined by the standard binding for regulators; see regulator.txt. | ||
11 | - VINDCD1-supply: A phandle to a regulator node supplying VINDCD1. | ||
12 | VINDCD2-supply: A phandle to a regulator node supplying VINDCD2. | ||
13 | VINLDO1-supply: A phandle to a regulator node supplying VINLDO1. | ||
14 | VINLDO2-supply: A phandle to a regulator node supplying VINLDO2. | ||
15 | |||
16 | Optional properties: | ||
17 | - Per-regulator optional properties are defined in regulator.txt | ||
18 | |||
19 | Example | ||
20 | |||
21 | pmic: isl9305@68 { | ||
22 | compatible = "isl,isl9305"; | ||
23 | reg = <0x68>; | ||
24 | |||
25 | VINDCD1-supply = <&system_power>; | ||
26 | VINDCD2-supply = <&system_power>; | ||
27 | VINLDO1-supply = <&system_power>; | ||
28 | VINLDO2-supply = <&system_power>; | ||
29 | |||
30 | regulators { | ||
31 | dcd1 { | ||
32 | regulator-name = "VDD_DSP"; | ||
33 | regulator-always-on; | ||
34 | }; | ||
35 | }; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/max1586-regulator.txt b/Documentation/devicetree/bindings/regulator/max1586-regulator.txt new file mode 100644 index 000000000000..c050c1744cb8 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/max1586-regulator.txt | |||
@@ -0,0 +1,28 @@ | |||
1 | Maxim MAX1586 voltage regulator | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: must be "maxim,max1586" | ||
5 | - reg: I2C slave address, usually 0x14 | ||
6 | - v3-gain: integer specifying the V3 gain as per datasheet | ||
7 | (1 + R24/R25 + R24/185.5kOhm) | ||
8 | - any required generic properties defined in regulator.txt | ||
9 | |||
10 | Example: | ||
11 | |||
12 | i2c_master { | ||
13 | max1586@14 { | ||
14 | compatible = "maxim,max1586"; | ||
15 | reg = <0x14>; | ||
16 | v3-gain = <1000000>; | ||
17 | |||
18 | regulators { | ||
19 | vcc_core: v3 { | ||
20 | regulator-name = "vcc_core"; | ||
21 | regulator-compatible = "Output_V3"; | ||
22 | regulator-min-microvolt = <1000000>; | ||
23 | regulator-max-microvolt = <1705000>; | ||
24 | regulator-always-on; | ||
25 | }; | ||
26 | }; | ||
27 | }; | ||
28 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/max77802.txt b/Documentation/devicetree/bindings/regulator/max77802.txt new file mode 100644 index 000000000000..79e5476444f7 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/max77802.txt | |||
@@ -0,0 +1,88 @@ | |||
1 | Binding for Maxim MAX77802 regulators | ||
2 | |||
3 | This is a part of device tree bindings of MAX77802 multi-function device. | ||
4 | More information can be found in bindings/mfd/max77802.txt file. | ||
5 | |||
6 | The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout (LDO) | ||
7 | regulators that can be controlled over I2C. | ||
8 | |||
9 | Following properties should be present in main device node of the MFD chip. | ||
10 | |||
11 | Optional node: | ||
12 | - regulators : The regulators of max77802 have to be instantiated | ||
13 | under subnode named "regulators" using the following format. | ||
14 | |||
15 | regulator-name { | ||
16 | standard regulator constraints.... | ||
17 | }; | ||
18 | refer Documentation/devicetree/bindings/regulator/regulator.txt | ||
19 | |||
20 | The regulator node name should be initialized with a string to get matched | ||
21 | with their hardware counterparts as follow. The valid names are: | ||
22 | |||
23 | -LDOn : for LDOs, where n can lie in ranges 1-15, 17-21, 23-30 | ||
24 | and 32-35. | ||
25 | example: LDO1, LDO2, LDO35. | ||
26 | -BUCKn : for BUCKs, where n can lie in range 1 to 10. | ||
27 | example: BUCK1, BUCK5, BUCK10. | ||
28 | |||
29 | The max77802 regulator supports two different operating modes: Normal and Low | ||
30 | Power Mode. Some regulators support the modes to be changed at startup or by | ||
31 | the consumers during normal operation while others only support to change the | ||
32 | mode during system suspend. The standard regulator suspend states binding can | ||
33 | be used to configure the regulator operating mode. | ||
34 | |||
35 | The regulators that support the standard "regulator-initial-mode" property, | ||
36 | changing their mode during normal operation are: LDOs 1, 3, 20 and 21. | ||
37 | |||
38 | The possible values for "regulator-initial-mode" and "regulator-mode" are: | ||
39 | 1: Normal regulator voltage output mode. | ||
40 | 3: Low Power which reduces the quiescent current down to only 1uA | ||
41 | |||
42 | The list of valid modes are defined in the dt-bindings/clock/maxim,max77802.h | ||
43 | header and can be included by device tree source files. | ||
44 | |||
45 | The standard "regulator-mode" property can only be used for regulators that | ||
46 | support changing their mode to Low Power Mode during suspend. These regulators | ||
47 | are: BUCKs 2-4 and LDOs 1-35. Also, it only takes effect if the regulator has | ||
48 | been enabled for the given suspend state using "regulator-on-in-suspend" and | ||
49 | has not been disabled for that state using "regulator-off-in-suspend". | ||
50 | |||
51 | Example: | ||
52 | |||
53 | max77802@09 { | ||
54 | compatible = "maxim,max77802"; | ||
55 | interrupt-parent = <&wakeup_eint>; | ||
56 | interrupts = <26 0>; | ||
57 | reg = <0x09>; | ||
58 | #address-cells = <1>; | ||
59 | #size-cells = <0>; | ||
60 | |||
61 | regulators { | ||
62 | ldo1_reg: LDO1 { | ||
63 | regulator-name = "vdd_1v0"; | ||
64 | regulator-min-microvolt = <1000000>; | ||
65 | regulator-max-microvolt = <1000000>; | ||
66 | regulator-always-on; | ||
67 | regulator-initial-mode = <MAX77802_OPMODE_LP>; | ||
68 | }; | ||
69 | |||
70 | ldo11_reg: LDO11 { | ||
71 | regulator-name = "vdd_ldo11"; | ||
72 | regulator-min-microvolt = <1900000>; | ||
73 | regulator-max-microvolt = <1900000>; | ||
74 | regulator-always-on; | ||
75 | regulator-state-mem { | ||
76 | regulator-on-in-suspend; | ||
77 | regulator-mode = <MAX77802_OPMODE_LP>; | ||
78 | }; | ||
79 | }; | ||
80 | |||
81 | buck1_reg: BUCK1 { | ||
82 | regulator-name = "vdd_mif"; | ||
83 | regulator-min-microvolt = <950000>; | ||
84 | regulator-max-microvolt = <1300000>; | ||
85 | regulator-always-on; | ||
86 | regulator-boot-on; | ||
87 | }; | ||
88 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt new file mode 100644 index 000000000000..ce91f61feb12 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | pwm regulator bindings | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should be "pwm-regulator" | ||
5 | - pwms: OF device-tree PWM specification (see PWM binding pwm.txt) | ||
6 | - voltage-table: voltage and duty table, include 2 members in each set of | ||
7 | brackets, first one is voltage(unit: uv), the next is duty(unit: percent) | ||
8 | |||
9 | Any property defined as part of the core regulator binding defined in | ||
10 | regulator.txt can also be used. | ||
11 | |||
12 | Example: | ||
13 | pwm_regulator { | ||
14 | compatible = "pwm-regulator; | ||
15 | pwms = <&pwm1 0 8448 0>; | ||
16 | |||
17 | voltage-table = <1114000 0>, | ||
18 | <1095000 10>, | ||
19 | <1076000 20>, | ||
20 | <1056000 30>, | ||
21 | <1036000 40>, | ||
22 | <1016000 50>; | ||
23 | |||
24 | regulator-min-microvolt = <1016000>; | ||
25 | regulator-max-microvolt = <1114000>; | ||
26 | regulator-name = "vdd_logic"; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt index 86074334e342..abb26b58c83e 100644 --- a/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/Documentation/devicetree/bindings/regulator/regulator.txt | |||
@@ -19,6 +19,24 @@ Optional properties: | |||
19 | design requires. This property describes the total system ramp time | 19 | design requires. This property describes the total system ramp time |
20 | required due to the combination of internal ramping of the regulator itself, | 20 | required due to the combination of internal ramping of the regulator itself, |
21 | and board design issues such as trace capacitance and load on the supply. | 21 | and board design issues such as trace capacitance and load on the supply. |
22 | - regulator-state-mem sub-root node for Suspend-to-RAM mode | ||
23 | : suspend to memory, the device goes to sleep, but all data stored in memory, | ||
24 | only some external interrupt can wake the device. | ||
25 | - regulator-state-disk sub-root node for Suspend-to-DISK mode | ||
26 | : suspend to disk, this state operates similarly to Suspend-to-RAM, | ||
27 | but includes a final step of writing memory contents to disk. | ||
28 | - regulator-state-[mem/disk] node has following common properties: | ||
29 | - regulator-on-in-suspend: regulator should be on in suspend state. | ||
30 | - regulator-off-in-suspend: regulator should be off in suspend state. | ||
31 | - regulator-suspend-microvolt: regulator should be set to this voltage | ||
32 | in suspend. | ||
33 | - regulator-mode: operating mode in the given suspend state. | ||
34 | The set of possible operating modes depends on the capabilities of | ||
35 | every hardware so the valid modes are documented on each regulator | ||
36 | device tree binding document. | ||
37 | - regulator-initial-mode: initial operating mode. The set of possible operating | ||
38 | modes depends on the capabilities of every hardware so each device binding | ||
39 | documentation explains which values the regulator supports. | ||
22 | 40 | ||
23 | Deprecated properties: | 41 | Deprecated properties: |
24 | - regulator-compatible: If a regulator chip contains multiple | 42 | - regulator-compatible: If a regulator chip contains multiple |
@@ -34,6 +52,10 @@ Example: | |||
34 | regulator-max-microvolt = <2500000>; | 52 | regulator-max-microvolt = <2500000>; |
35 | regulator-always-on; | 53 | regulator-always-on; |
36 | vin-supply = <&vin>; | 54 | vin-supply = <&vin>; |
55 | |||
56 | regulator-state-mem { | ||
57 | regulator-on-in-suspend; | ||
58 | }; | ||
37 | }; | 59 | }; |
38 | 60 | ||
39 | Regulator Consumers: | 61 | Regulator Consumers: |
diff --git a/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt b/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt new file mode 100644 index 000000000000..f9acbc1f3c6b --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | SKY81452 voltage regulator | ||
2 | |||
3 | Required properties: | ||
4 | - regulator node named lout. | ||
5 | - any required generic properties defined in regulator.txt | ||
6 | |||
7 | Optional properties: | ||
8 | - any available generic properties defined in regulator.txt | ||
9 | |||
10 | Example: | ||
11 | |||
12 | regulator { | ||
13 | lout { | ||
14 | regulator-name = "sky81452-lout"; | ||
15 | regulator-min-microvolt = <4500000>; | ||
16 | regulator-max-microvolt = <8000000>; | ||
17 | }; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt b/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt new file mode 100644 index 000000000000..54ae9f747e45 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt | |||
@@ -0,0 +1,42 @@ | |||
1 | STMicroelectronics STi family Sysconfig Picophy SoftReset Controller | ||
2 | ============================================================================= | ||
3 | |||
4 | This binding describes a reset controller device that is used to enable and | ||
5 | disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in | ||
6 | the STi family SoC system configuration registers. | ||
7 | |||
8 | The actual action taken when softreset is asserted is hardware dependent. | ||
9 | However, when asserted it may not be possible to access the hardware's | ||
10 | registers and after an assert/deassert sequence the hardware's previous state | ||
11 | may no longer be valid. | ||
12 | |||
13 | Please refer to Documentation/devicetree/bindings/reset/reset.txt | ||
14 | for common reset controller binding usage. | ||
15 | |||
16 | Required properties: | ||
17 | - compatible: Should be "st,stih407-picophyreset" | ||
18 | - #reset-cells: 1, see below | ||
19 | |||
20 | Example: | ||
21 | |||
22 | picophyreset: picophyreset-controller { | ||
23 | compatible = "st,stih407-picophyreset"; | ||
24 | #reset-cells = <1>; | ||
25 | }; | ||
26 | |||
27 | Specifying picophyreset control of devices | ||
28 | ======================================= | ||
29 | |||
30 | Device nodes should specify the reset channel required in their "resets" | ||
31 | property, containing a phandle to the picophyreset device node and an | ||
32 | index specifying which channel to use, as described in | ||
33 | Documentation/devicetree/bindings/reset/reset.txt. | ||
34 | |||
35 | Example: | ||
36 | |||
37 | usb2_picophy0: usbpicophy@0 { | ||
38 | resets = <&picophyreset STIH407_PICOPHY0_RESET>; | ||
39 | }; | ||
40 | |||
41 | Macro definitions for the supported reset channels can be found in: | ||
42 | include/dt-bindings/reset-controller/stih407-resets.h | ||
diff --git a/Documentation/devicetree/bindings/rng/apm,rng.txt b/Documentation/devicetree/bindings/rng/apm,rng.txt new file mode 100644 index 000000000000..4dde4b06cdd9 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/apm,rng.txt | |||
@@ -0,0 +1,17 @@ | |||
1 | APM X-Gene SoC random number generator. | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "apm,xgene-rng" | ||
6 | - reg : specifies base physical address and size of the registers map | ||
7 | - clocks : phandle to clock-controller plus clock-specifier pair | ||
8 | - interrupts : specify the fault interrupt for the RNG device | ||
9 | |||
10 | Example: | ||
11 | |||
12 | rng: rng@10520000 { | ||
13 | compatible = "apm,xgene-rng"; | ||
14 | reg = <0x0 0x10520000 0x0 0x100>; | ||
15 | interrupts = <0x0 0x41 0x4>; | ||
16 | clocks = <&rngpkaclk 0>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt new file mode 100644 index 000000000000..6ae79d1843f3 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/atmel,at91sam9-rtc.txt | |||
@@ -0,0 +1,23 @@ | |||
1 | Atmel AT91SAM9260 Real Time Timer | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be: "atmel,at91sam9260-rtt" | ||
5 | - reg: should encode the memory region of the RTT controller | ||
6 | - interrupts: rtt alarm/event interrupt | ||
7 | - clocks: should contain the 32 KHz slow clk that will drive the RTT block. | ||
8 | - atmel,rtt-rtc-time-reg: should encode the GPBR register used to store | ||
9 | the time base when the RTT is used as an RTC. | ||
10 | The first cell should point to the GPBR node and the second one | ||
11 | encode the offset within the GPBR block (or in other words, the | ||
12 | GPBR register used to store the time base). | ||
13 | |||
14 | |||
15 | Example: | ||
16 | |||
17 | rtt@fffffd20 { | ||
18 | compatible = "atmel,at91sam9260-rtt"; | ||
19 | reg = <0xfffffd20 0x10>; | ||
20 | interrupts = <1 4 7>; | ||
21 | clocks = <&clk32k>; | ||
22 | atmel,rtt-rtc-time-reg = <&gpbr 0x0>; | ||
23 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt b/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt new file mode 100644 index 000000000000..916f57601a8f --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | * Dallas DS1339 I2C Serial Real-Time Clock | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should contain "dallas,ds1339". | ||
5 | - reg: I2C address for chip | ||
6 | |||
7 | Optional properties: | ||
8 | - trickle-resistor-ohms : Selected resistor for trickle charger | ||
9 | Values usable for ds1339 are 250, 2000, 4000 | ||
10 | Should be given if trickle charger should be enabled | ||
11 | - trickle-diode-disable : Do not use internal trickle charger diode | ||
12 | Should be given if internal trickle charger diode should be disabled | ||
13 | Example: | ||
14 | ds1339: rtc@68 { | ||
15 | compatible = "dallas,ds1339"; | ||
16 | trickle-resistor-ohms = <250>; | ||
17 | reg = <0x68>; | ||
18 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt index 5a0f02d34d95..4ba4dbd34289 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt +++ b/Documentation/devicetree/bindings/rtc/rtc-omap.txt | |||
@@ -5,11 +5,17 @@ Required properties: | |||
5 | - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family. | 5 | - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family. |
6 | - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family. | 6 | - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family. |
7 | This RTC IP has special WAKE-EN Register to enable | 7 | This RTC IP has special WAKE-EN Register to enable |
8 | Wakeup generation for event Alarm. | 8 | Wakeup generation for event Alarm. It can also be |
9 | used to control an external PMIC via the | ||
10 | pmic_power_en pin. | ||
9 | - reg: Address range of rtc register set | 11 | - reg: Address range of rtc register set |
10 | - interrupts: rtc timer, alarm interrupts in order | 12 | - interrupts: rtc timer, alarm interrupts in order |
11 | - interrupt-parent: phandle for the interrupt controller | 13 | - interrupt-parent: phandle for the interrupt controller |
12 | 14 | ||
15 | Optional properties: | ||
16 | - system-power-controller: whether the rtc is controlling the system power | ||
17 | through pmic_power_en | ||
18 | |||
13 | Example: | 19 | Example: |
14 | 20 | ||
15 | rtc@1c23000 { | 21 | rtc@1c23000 { |
@@ -18,4 +24,5 @@ rtc@1c23000 { | |||
18 | interrupts = <19 | 24 | interrupts = <19 |
19 | 19>; | 25 | 19>; |
20 | interrupt-parent = <&intc>; | 26 | interrupt-parent = <&intc>; |
27 | system-power-controller; | ||
21 | }; | 28 | }; |
diff --git a/Documentation/devicetree/bindings/rtc/rtc-opal.txt b/Documentation/devicetree/bindings/rtc/rtc-opal.txt new file mode 100644 index 000000000000..af87e5ecac54 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-opal.txt | |||
@@ -0,0 +1,16 @@ | |||
1 | IBM OPAL real-time clock | ||
2 | ------------------------ | ||
3 | |||
4 | Required properties: | ||
5 | - comapatible: Should be "ibm,opal-rtc" | ||
6 | |||
7 | Optional properties: | ||
8 | - has-tpo: Decides if the wakeup is supported or not. | ||
9 | |||
10 | Example: | ||
11 | rtc { | ||
12 | compatible = "ibm,opal-rtc"; | ||
13 | has-tpo; | ||
14 | phandle = <0x10000029>; | ||
15 | linux,phandle = <0x10000029>; | ||
16 | }; | ||
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt index 7ac7259fe9ea..ab757b84daa7 100644 --- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt | |||
@@ -3,7 +3,10 @@ | |||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: should be one of the following. | 4 | - compatible: should be one of the following. |
5 | * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc. | 5 | * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc. |
6 | * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc. | ||
7 | * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc. | ||
6 | * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. | 8 | * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc. |
9 | * "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc. | ||
7 | - reg: physical base address of the controller and length of memory mapped | 10 | - reg: physical base address of the controller and length of memory mapped |
8 | region. | 11 | region. |
9 | - interrupts: Two interrupt numbers to the cpu should be specified. First | 12 | - interrupts: Two interrupt numbers to the cpu should be specified. First |
diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt new file mode 100644 index 000000000000..f007e428a1ab --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt | |||
@@ -0,0 +1,17 @@ | |||
1 | * sun6i Real Time Clock | ||
2 | |||
3 | RTC controller for the Allwinner A31 | ||
4 | |||
5 | Required properties: | ||
6 | - compatible : Should be "allwinner,sun6i-a31-rtc" | ||
7 | - reg : physical base address of the controller and length of | ||
8 | memory mapped region. | ||
9 | - interrupts : IRQ lines for the RTC alarm 0 and alarm 1, in that order. | ||
10 | |||
11 | Example: | ||
12 | |||
13 | rtc: rtc@01f00000 { | ||
14 | compatible = "allwinner,sun6i-a31-rtc"; | ||
15 | reg = <0x01f00000 0x54>; | ||
16 | interrupts = <0 40 4>, <0 41 4>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt b/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt new file mode 100644 index 000000000000..5c52e5eef16d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | * BCM63xx UART | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible: "brcm,bcm6345-uart" | ||
6 | |||
7 | - reg: The base address of the UART register bank. | ||
8 | |||
9 | - interrupts: A single interrupt specifier. | ||
10 | |||
11 | - clocks: Clock driving the hardware; used to figure out the baud rate | ||
12 | divisor. | ||
13 | |||
14 | Example: | ||
15 | |||
16 | uart0: serial@14e00520 { | ||
17 | compatible = "brcm,bcm6345-uart"; | ||
18 | reg = <0x14e00520 0x18>; | ||
19 | interrupt-parent = <&periph_intc>; | ||
20 | interrupts = <2>; | ||
21 | clocks = <&periph_clk>; | ||
22 | }; | ||
23 | |||
24 | clocks { | ||
25 | periph_clk: periph_clk@0 { | ||
26 | compatible = "fixed-clock"; | ||
27 | #clock-cells = <0>; | ||
28 | clock-frequency = <54000000>; | ||
29 | }; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt index 12f3cf834deb..caaeb2583579 100644 --- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt +++ b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt | |||
@@ -8,7 +8,8 @@ Required properties: | |||
8 | - syscon: Phandle to SYSCON node, which contain UART control bits. | 8 | - syscon: Phandle to SYSCON node, which contain UART control bits. |
9 | 9 | ||
10 | Optional properties: | 10 | Optional properties: |
11 | - uart-use-ms: Indicate the UART has modem signal (DCD, DSR, CTS). | 11 | - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD |
12 | line respectively. | ||
12 | 13 | ||
13 | Note: Each UART port should have an alias correctly numbered | 14 | Note: Each UART port should have an alias correctly numbered |
14 | in "aliases" node. | 15 | in "aliases" node. |
@@ -24,5 +25,7 @@ Example: | |||
24 | interrupts = <12 13>; | 25 | interrupts = <12 13>; |
25 | clocks = <&clks 11>; | 26 | clocks = <&clks 11>; |
26 | syscon = <&syscon1>; | 27 | syscon = <&syscon1>; |
27 | uart-use-ms; | 28 | cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>; |
29 | dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>; | ||
30 | dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>; | ||
28 | }; | 31 | }; |
diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt index 59a40f18d551..7c408c87e613 100644 --- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt +++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt | |||
@@ -11,8 +11,13 @@ Required properties: | |||
11 | - dma-names: "rx" for RX channel, "tx" for TX channel. | 11 | - dma-names: "rx" for RX channel, "tx" for TX channel. |
12 | 12 | ||
13 | Optional properties: | 13 | Optional properties: |
14 | - fsl,uart-has-rtscts : Indicate the UART has RTS and CTS lines, | 14 | - fsl,uart-has-rtscts : Indicate the UART has RTS and CTS lines |
15 | for hardware flow control, | ||
15 | it also means you enable the DMA support for this UART. | 16 | it also means you enable the DMA support for this UART. |
17 | - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD | ||
18 | line respectively. It will use specified PIO instead of the peripheral | ||
19 | function pin for the USART feature. | ||
20 | If unsure, don't specify this property. | ||
16 | 21 | ||
17 | Example: | 22 | Example: |
18 | auart0: serial@8006a000 { | 23 | auart0: serial@8006a000 { |
@@ -21,6 +26,9 @@ auart0: serial@8006a000 { | |||
21 | interrupts = <112>; | 26 | interrupts = <112>; |
22 | dmas = <&dma_apbx 8>, <&dma_apbx 9>; | 27 | dmas = <&dma_apbx 8>, <&dma_apbx 9>; |
23 | dma-names = "rx", "tx"; | 28 | dma-names = "rx", "tx"; |
29 | cts-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; | ||
30 | dsr-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; | ||
31 | dcd-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; | ||
24 | }; | 32 | }; |
25 | 33 | ||
26 | Note: Each auart port should have an alias correctly numbered in "aliases" | 34 | Note: Each auart port should have an alias correctly numbered in "aliases" |
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt new file mode 100644 index 000000000000..48358a33ea7d --- /dev/null +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt | |||
@@ -0,0 +1,22 @@ | |||
1 | * Mediatek Universal Asynchronous Receiver/Transmitter (UART) | ||
2 | |||
3 | Required properties: | ||
4 | - compatible should contain: | ||
5 | * "mediatek,mt6589-uart" for MT6589 compatible UARTS | ||
6 | * "mediatek,mt6582-uart" for MT6582 compatible UARTS | ||
7 | * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577) | ||
8 | |||
9 | - reg: The base address of the UART register bank. | ||
10 | |||
11 | - interrupts: A single interrupt specifier. | ||
12 | |||
13 | - clocks: Clock driving the hardware. | ||
14 | |||
15 | Example: | ||
16 | |||
17 | uart0: serial@11006000 { | ||
18 | compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; | ||
19 | reg = <0x11006000 0x400>; | ||
20 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; | ||
21 | clocks = <&uart_clk>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/of-serial.txt b/Documentation/devicetree/bindings/serial/of-serial.txt index 77054772a8f4..b52b98234b9b 100644 --- a/Documentation/devicetree/bindings/serial/of-serial.txt +++ b/Documentation/devicetree/bindings/serial/of-serial.txt | |||
@@ -10,10 +10,12 @@ Required properties: | |||
10 | - "ns16850" | 10 | - "ns16850" |
11 | - "nvidia,tegra20-uart" | 11 | - "nvidia,tegra20-uart" |
12 | - "nxp,lpc3220-uart" | 12 | - "nxp,lpc3220-uart" |
13 | - "ralink,rt2880-uart" | ||
13 | - "ibm,qpace-nwp-serial" | 14 | - "ibm,qpace-nwp-serial" |
14 | - "altr,16550-FIFO32" | 15 | - "altr,16550-FIFO32" |
15 | - "altr,16550-FIFO64" | 16 | - "altr,16550-FIFO64" |
16 | - "altr,16550-FIFO128" | 17 | - "altr,16550-FIFO128" |
18 | - "fsl,16550-FIFO64" | ||
17 | - "serial" if the port type is unknown. | 19 | - "serial" if the port type is unknown. |
18 | - reg : offset and length of the register set for the device. | 20 | - reg : offset and length of the register set for the device. |
19 | - interrupts : should contain uart interrupt. | 21 | - interrupts : should contain uart interrupt. |
@@ -37,7 +39,6 @@ Optional properties: | |||
37 | - auto-flow-control: one way to enable automatic flow control support. The | 39 | - auto-flow-control: one way to enable automatic flow control support. The |
38 | driver is allowed to detect support for the capability even without this | 40 | driver is allowed to detect support for the capability even without this |
39 | property. | 41 | property. |
40 | - has-hw-flow-control: the hardware has flow control capability. | ||
41 | 42 | ||
42 | Example: | 43 | Example: |
43 | 44 | ||
diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt index 5d2e840ae65c..ba3ecb8cb5a1 100644 --- a/Documentation/devicetree/bindings/serial/pl011.txt +++ b/Documentation/devicetree/bindings/serial/pl011.txt | |||
@@ -6,12 +6,46 @@ Required properties: | |||
6 | - interrupts: exactly one interrupt specifier | 6 | - interrupts: exactly one interrupt specifier |
7 | 7 | ||
8 | Optional properties: | 8 | Optional properties: |
9 | - pinctrl: When present, must have one state named "sleep" | 9 | - pinctrl: |
10 | and one state named "default" | 10 | When present, must have one state named "default", |
11 | - clocks: When present, must refer to exactly one clock named | 11 | and may contain a second name named "sleep". The former |
12 | state sets up pins for ordinary operation whereas | ||
13 | the latter state will put the associated pins to sleep | ||
14 | when the UART is unused | ||
15 | - clocks: | ||
16 | When present, the first clock listed must correspond to | ||
17 | the clock named UARTCLK on the IP block, i.e. the clock | ||
18 | to the external serial line, whereas the second clock | ||
19 | must correspond to the PCLK clocking the internal logic | ||
20 | of the block. Just listing one clock (the first one) is | ||
21 | deprecated. | ||
22 | - clocks-names: | ||
23 | When present, the first clock listed must be named | ||
24 | "uartclk" and the second clock listed must be named | ||
12 | "apb_pclk" | 25 | "apb_pclk" |
13 | - dmas: When present, may have one or two dma channels. | 26 | - dmas: |
27 | When present, may have one or two dma channels. | ||
14 | The first one must be named "rx", the second one | 28 | The first one must be named "rx", the second one |
15 | must be named "tx". | 29 | must be named "tx". |
30 | - auto-poll: | ||
31 | Enables polling when using RX DMA. | ||
32 | - poll-rate-ms: | ||
33 | Rate at which poll occurs when auto-poll is set, | ||
34 | default 100ms. | ||
35 | - poll-timeout-ms: | ||
36 | Poll timeout when auto-poll is set, default | ||
37 | 3000ms. | ||
16 | 38 | ||
17 | See also bindings/arm/primecell.txt | 39 | See also bindings/arm/primecell.txt |
40 | |||
41 | Example: | ||
42 | |||
43 | uart@80120000 { | ||
44 | compatible = "arm,pl011", "arm,primecell"; | ||
45 | reg = <0x80120000 0x1000>; | ||
46 | interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; | ||
47 | dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>; | ||
48 | dma-names = "rx", "tx"; | ||
49 | clocks = <&foo_clk>, <&bar_clk>; | ||
50 | clock-names = "uartclk", "apb_pclk"; | ||
51 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt index ffa5b784c66e..a2114c217376 100644 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt | |||
@@ -27,27 +27,52 @@ Optional properties: | |||
27 | - dmas: Should contain dma specifiers for transmit and receive channels | 27 | - dmas: Should contain dma specifiers for transmit and receive channels |
28 | - dma-names: Should contain "tx" for transmit and "rx" for receive channels | 28 | - dma-names: Should contain "tx" for transmit and "rx" for receive channels |
29 | 29 | ||
30 | Note: Aliases may be defined to ensure the correct ordering of the UARTs. | ||
31 | The alias serialN will result in the UART being assigned port N. If any | ||
32 | serialN alias exists, then an alias must exist for each enabled UART. The | ||
33 | serialN aliases should be in a .dts file instead of in a .dtsi file. | ||
34 | |||
30 | Examples: | 35 | Examples: |
31 | 36 | ||
32 | A uartdm v1.4 device with dma capabilities. | 37 | - A uartdm v1.4 device with dma capabilities. |
33 | 38 | ||
34 | serial@f991e000 { | 39 | serial@f991e000 { |
35 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | 40 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
36 | reg = <0xf991e000 0x1000>; | 41 | reg = <0xf991e000 0x1000>; |
37 | interrupts = <0 108 0x0>; | 42 | interrupts = <0 108 0x0>; |
38 | clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; | 43 | clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; |
39 | clock-names = "core", "iface"; | 44 | clock-names = "core", "iface"; |
40 | dmas = <&dma0 0>, <&dma0 1>; | 45 | dmas = <&dma0 0>, <&dma0 1>; |
41 | dma-names = "tx", "rx"; | 46 | dma-names = "tx", "rx"; |
42 | }; | 47 | }; |
43 | 48 | ||
44 | A uartdm v1.3 device without dma capabilities and part of a GSBI complex. | 49 | - A uartdm v1.3 device without dma capabilities and part of a GSBI complex. |
45 | 50 | ||
46 | serial@19c40000 { | 51 | serial@19c40000 { |
47 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | 52 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
48 | reg = <0x19c40000 0x1000>, | 53 | reg = <0x19c40000 0x1000>, |
49 | <0x19c00000 0x1000>; | 54 | <0x19c00000 0x1000>; |
50 | interrupts = <0 195 0x0>; | 55 | interrupts = <0 195 0x0>; |
51 | clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; | 56 | clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; |
52 | clock-names = "core", "iface"; | 57 | clock-names = "core", "iface"; |
53 | }; | 58 | }; |
59 | |||
60 | - serialN alias. | ||
61 | |||
62 | aliases { | ||
63 | serial0 = &uarta; | ||
64 | serial1 = &uartc; | ||
65 | serial2 = &uartb; | ||
66 | }; | ||
67 | |||
68 | uarta: serial@12490000 { | ||
69 | status = "ok"; | ||
70 | }; | ||
71 | |||
72 | uartb: serial@16340000 { | ||
73 | status = "ok"; | ||
74 | }; | ||
75 | |||
76 | uartc: serial@1a240000 { | ||
77 | status = "ok"; | ||
78 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index b3556609a06f..ae73bb0e9ad9 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | |||
@@ -4,8 +4,7 @@ Required properties: | |||
4 | 4 | ||
5 | - compatible: Must contain one of the following: | 5 | - compatible: Must contain one of the following: |
6 | 6 | ||
7 | - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART. | 7 | - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART. |
8 | - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART. | ||
9 | - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. | 8 | - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART. |
10 | - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. | 9 | - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART. |
11 | - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. | 10 | - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART. |
@@ -20,6 +19,12 @@ Required properties: | |||
20 | - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART. | 19 | - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART. |
21 | - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART. | 20 | - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART. |
22 | - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART. | 21 | - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART. |
22 | - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART. | ||
23 | - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART. | ||
24 | - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART. | ||
25 | - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART. | ||
26 | - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART. | ||
27 | - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART. | ||
23 | - "renesas,scif" for generic SCIF compatible UART. | 28 | - "renesas,scif" for generic SCIF compatible UART. |
24 | - "renesas,scifa" for generic SCIFA compatible UART. | 29 | - "renesas,scifa" for generic SCIFA compatible UART. |
25 | - "renesas,scifb" for generic SCIFB compatible UART. | 30 | - "renesas,scifb" for generic SCIFB compatible UART. |
diff --git a/Documentation/devicetree/bindings/serial/sirf-uart.txt b/Documentation/devicetree/bindings/serial/sirf-uart.txt index a2dfc6522a91..3acdd969edf1 100644 --- a/Documentation/devicetree/bindings/serial/sirf-uart.txt +++ b/Documentation/devicetree/bindings/serial/sirf-uart.txt | |||
@@ -1,7 +1,9 @@ | |||
1 | * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * | 1 | * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : Should be "sirf,prima2-uart" or "sirf, prima2-usp-uart" | 4 | - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", |
5 | "sirf,marco-uart" or "sirf,marco-bt-uart" which means | ||
6 | uart located in BT module and used for BT. | ||
5 | - reg : Offset and length of the register set for the device | 7 | - reg : Offset and length of the register set for the device |
6 | - interrupts : Should contain uart interrupt | 8 | - interrupts : Should contain uart interrupt |
7 | - fifosize : Should define hardware rx/tx fifo size | 9 | - fifosize : Should define hardware rx/tx fifo size |
@@ -31,3 +33,15 @@ usp@b0090000 { | |||
31 | rts-gpios = <&gpio 15 0>; | 33 | rts-gpios = <&gpio 15 0>; |
32 | cts-gpios = <&gpio 46 0>; | 34 | cts-gpios = <&gpio 46 0>; |
33 | }; | 35 | }; |
36 | |||
37 | for uart use in BT module, | ||
38 | uart6: uart@11000000 { | ||
39 | cell-index = <6>; | ||
40 | compatible = "sirf,marco-bt-uart", "sirf,marco-uart"; | ||
41 | reg = <0x11000000 0x1000>; | ||
42 | interrupts = <0 100 0>; | ||
43 | clocks = <&clks 138>, <&clks 140>, <&clks 141>; | ||
44 | clock-names = "uart", "general", "noc"; | ||
45 | fifosize = <128>; | ||
46 | status = "disabled"; | ||
47 | } | ||
diff --git a/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt deleted file mode 100644 index 5feef1ef167d..000000000000 --- a/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | VIA/Wondermedia VT8500 UART Controller | ||
2 | ----------------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : "via,vt8500-uart" | ||
6 | - reg : Should contain 1 register ranges(address and length) | ||
7 | - interrupts : UART interrupt | ||
8 | - clocks : phandle to the uart source clock (usually a 24Mhz fixed clock) | ||
9 | |||
10 | Example: | ||
11 | |||
12 | uart@d8210000 { | ||
13 | compatible = "via,vt8500-uart"; | ||
14 | reg = <0xd8210000 0x1040>; | ||
15 | interrupts = <47>; | ||
16 | clocks = <&ref24>; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/vt8500-uart.txt b/Documentation/devicetree/bindings/serial/vt8500-uart.txt index 795c393d09c4..2b64e6107fb3 100644 --- a/Documentation/devicetree/bindings/serial/vt8500-uart.txt +++ b/Documentation/devicetree/bindings/serial/vt8500-uart.txt | |||
@@ -1,7 +1,8 @@ | |||
1 | * VIA VT8500 and WonderMedia WM8xxx UART Controller | 1 | * VIA VT8500 and WonderMedia WM8xxx UART Controller |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: should be "via,vt8500-uart" | 4 | - compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and |
5 | including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later) | ||
5 | 6 | ||
6 | - reg: base physical address of the controller and length of memory mapped | 7 | - reg: base physical address of the controller and length of memory mapped |
7 | region. | 8 | region. |
diff --git a/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt new file mode 100644 index 000000000000..2a00e14e11e0 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/bman-portals.txt | |||
@@ -0,0 +1,56 @@ | |||
1 | QorIQ DPAA Buffer Manager Portals Device Tree Binding | ||
2 | |||
3 | Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. | ||
4 | |||
5 | CONTENTS | ||
6 | |||
7 | - BMan Portal | ||
8 | - Example | ||
9 | |||
10 | BMan Portal Node | ||
11 | |||
12 | Portals are memory mapped interfaces to BMan that allow low-latency, lock-less | ||
13 | interaction by software running on processor cores, accelerators and network | ||
14 | interfaces with the BMan | ||
15 | |||
16 | PROPERTIES | ||
17 | |||
18 | - compatible | ||
19 | Usage: Required | ||
20 | Value type: <stringlist> | ||
21 | Definition: Must include "fsl,bman-portal-<hardware revision>" | ||
22 | May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal" | ||
23 | |||
24 | - reg | ||
25 | Usage: Required | ||
26 | Value type: <prop-encoded-array> | ||
27 | Definition: Two regions. The first is the cache-enabled region of | ||
28 | the portal. The second is the cache-inhibited region of | ||
29 | the portal | ||
30 | |||
31 | - interrupts | ||
32 | Usage: Required | ||
33 | Value type: <prop-encoded-array> | ||
34 | Definition: Standard property | ||
35 | |||
36 | EXAMPLE | ||
37 | |||
38 | The example below shows a (P4080) BMan portals container/bus node with two portals | ||
39 | |||
40 | bman-portals@ff4000000 { | ||
41 | #address-cells = <1>; | ||
42 | #size-cells = <1>; | ||
43 | compatible = "simple-bus"; | ||
44 | ranges = <0 0xf 0xf4000000 0x200000>; | ||
45 | |||
46 | bman-portal@0 { | ||
47 | compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; | ||
48 | reg = <0x0 0x4000>, <0x100000 0x1000>; | ||
49 | interrupts = <105 2 0 0>; | ||
50 | }; | ||
51 | bman-portal@4000 { | ||
52 | compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal"; | ||
53 | reg = <0x4000 0x4000>, <0x101000 0x1000>; | ||
54 | interrupts = <107 2 0 0>; | ||
55 | }; | ||
56 | }; | ||
diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt b/Documentation/devicetree/bindings/soc/fsl/bman.txt new file mode 100644 index 000000000000..9f80bf8709ac --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt | |||
@@ -0,0 +1,125 @@ | |||
1 | QorIQ DPAA Buffer Manager Device Tree Bindings | ||
2 | |||
3 | Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. | ||
4 | |||
5 | CONTENTS | ||
6 | |||
7 | - BMan Node | ||
8 | - BMan Private Memory Node | ||
9 | - Example | ||
10 | |||
11 | BMan Node | ||
12 | |||
13 | The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). | ||
14 | BMan supports hardware allocation and deallocation of buffers belonging to pools | ||
15 | originally created by software with configurable depletion thresholds. This | ||
16 | binding covers the CCSR space programming model | ||
17 | |||
18 | PROPERTIES | ||
19 | |||
20 | - compatible | ||
21 | Usage: Required | ||
22 | Value type: <stringlist> | ||
23 | Definition: Must include "fsl,bman" | ||
24 | May include "fsl,<SoC>-bman" | ||
25 | |||
26 | - reg | ||
27 | Usage: Required | ||
28 | Value type: <prop-encoded-array> | ||
29 | Definition: Registers region within the CCSR address space | ||
30 | |||
31 | The BMan revision information is located in the BMAN_IP_REV_1/2 registers which | ||
32 | are located at offsets 0xbf8 and 0xbfc | ||
33 | |||
34 | - interrupts | ||
35 | Usage: Required | ||
36 | Value type: <prop-encoded-array> | ||
37 | Definition: Standard property. The error interrupt | ||
38 | |||
39 | - fsl,liodn | ||
40 | Usage: See pamu.txt | ||
41 | Value type: <prop-encoded-array> | ||
42 | Definition: PAMU property used for static LIODN assignment | ||
43 | |||
44 | - fsl,iommu-parent | ||
45 | Usage: See pamu.txt | ||
46 | Value type: <phandle> | ||
47 | Definition: PAMU property used for dynamic LIODN assignment | ||
48 | |||
49 | For additional details about the PAMU/LIODN binding(s) see pamu.txt | ||
50 | |||
51 | Devices connected to a BMan instance via Direct Connect Portals (DCP) must link | ||
52 | to the respective BMan instance | ||
53 | |||
54 | - fsl,bman | ||
55 | Usage: Required | ||
56 | Value type: <prop-encoded-array> | ||
57 | Description: List of phandle and DCP index pairs, to the BMan instance | ||
58 | to which this device is connected via the DCP | ||
59 | |||
60 | BMan Private Memory Node | ||
61 | |||
62 | BMan requires a contiguous range of physical memory used for the backing store | ||
63 | for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as a | ||
64 | node under the /reserved-memory node | ||
65 | |||
66 | The BMan FBPR memory node must be named "bman-fbpr" | ||
67 | |||
68 | PROPERTIES | ||
69 | |||
70 | - compatible | ||
71 | Usage: required | ||
72 | Value type: <stringlist> | ||
73 | Definition: Must inclide "fsl,bman-fbpr" | ||
74 | |||
75 | The following constraints are relevant to the FBPR private memory: | ||
76 | - The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to | ||
77 | 16 GiB | ||
78 | - The alignment must be a muliptle of the memory size | ||
79 | |||
80 | The size of the FBPR must be chosen by observing the hardware features configured | ||
81 | via the Reset Configuration Word (RCW) and that are relevant to a specific board | ||
82 | (e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports, | ||
83 | etc.). The size configured in the DT must reflect the hardware capabilities and | ||
84 | not the specific needs of an application | ||
85 | |||
86 | For additional details about reserved memory regions see reserved-memory.txt | ||
87 | |||
88 | EXAMPLE | ||
89 | |||
90 | The example below shows a BMan FBPR dynamic allocation memory node | ||
91 | |||
92 | reserved-memory { | ||
93 | #address-cells = <2>; | ||
94 | #size-cells = <2>; | ||
95 | ranges; | ||
96 | |||
97 | bman_fbpr: bman-fbpr { | ||
98 | compatible = "fsl,bman-fbpr"; | ||
99 | alloc-ranges = <0 0 0xf 0xffffffff>; | ||
100 | size = <0 0x1000000>; | ||
101 | alignment = <0 0x1000000>; | ||
102 | }; | ||
103 | }; | ||
104 | |||
105 | The example below shows a (P4080) BMan CCSR-space node | ||
106 | |||
107 | crypto@300000 { | ||
108 | ... | ||
109 | fsl,bman = <&bman, 2>; | ||
110 | ... | ||
111 | }; | ||
112 | |||
113 | bman: bman@31a000 { | ||
114 | compatible = "fsl,bman"; | ||
115 | reg = <0x31a000 0x1000>; | ||
116 | interrupts = <16 2 1 2>; | ||
117 | fsl,liodn = <0x17>; | ||
118 | memory-region = <&bman_fbpr>; | ||
119 | }; | ||
120 | |||
121 | fman@400000 { | ||
122 | ... | ||
123 | fsl,bman = <&bman, 0>; | ||
124 | ... | ||
125 | }; | ||
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt new file mode 100644 index 000000000000..48c4dae5d6f9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/qman-portals.txt | |||
@@ -0,0 +1,154 @@ | |||
1 | QorIQ DPAA Queue Manager Portals Device Tree Binding | ||
2 | |||
3 | Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. | ||
4 | |||
5 | CONTENTS | ||
6 | |||
7 | - QMan Portal | ||
8 | - QMan Pool Channel | ||
9 | - Example | ||
10 | |||
11 | QMan Portal Node | ||
12 | |||
13 | Portals are memory mapped interfaces to QMan that allow low-latency, lock-less | ||
14 | interaction by software running on processor cores, accelerators and network | ||
15 | interfaces with the QMan | ||
16 | |||
17 | PROPERTIES | ||
18 | |||
19 | - compatible | ||
20 | Usage: Required | ||
21 | Value type: <stringlist> | ||
22 | Definition: Must include "fsl,qman-portal-<hardware revision>" | ||
23 | May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal" | ||
24 | |||
25 | - reg | ||
26 | Usage: Required | ||
27 | Value type: <prop-encoded-array> | ||
28 | Definition: Two regions. The first is the cache-enabled region of | ||
29 | the portal. The second is the cache-inhibited region of | ||
30 | the portal | ||
31 | |||
32 | - interrupts | ||
33 | Usage: Required | ||
34 | Value type: <prop-encoded-array> | ||
35 | Definition: Standard property | ||
36 | |||
37 | - fsl,liodn | ||
38 | Usage: See pamu.txt | ||
39 | Value type: <prop-encoded-array> | ||
40 | Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN | ||
41 | (FLIODN) | ||
42 | |||
43 | - fsl,iommu-parent | ||
44 | Usage: See pamu.txt | ||
45 | Value type: <phandle> | ||
46 | Definition: PAMU property used for dynamic LIODN assignment | ||
47 | |||
48 | For additional details about the PAMU/LIODN binding(s) see pamu.txt | ||
49 | |||
50 | - fsl,qman-channel-id | ||
51 | Usage: Required | ||
52 | Value type: <u32> | ||
53 | Definition: The hardware index of the channel. This can also be | ||
54 | determined by dividing any of the channel's 8 work queue | ||
55 | IDs by 8 | ||
56 | |||
57 | In addition to these properties the qman-portals should have sub-nodes to | ||
58 | represent the HW devices/portals that are connected to the software portal | ||
59 | described here | ||
60 | |||
61 | The currently supported sub-nodes are: | ||
62 | * fman0 | ||
63 | * fman1 | ||
64 | * pme | ||
65 | * crypto | ||
66 | |||
67 | These subnodes should have the following properties: | ||
68 | |||
69 | - fsl,liodn | ||
70 | Usage: See pamu.txt | ||
71 | Value type: <prop-encoded-array> | ||
72 | Definition: PAMU property used for static LIODN assignment | ||
73 | |||
74 | - fsl,iommu-parent | ||
75 | Usage: See pamu.txt | ||
76 | Value type: <phandle> | ||
77 | Definition: PAMU property used for dynamic LIODN assignment | ||
78 | |||
79 | - dev-handle | ||
80 | Usage: Required | ||
81 | Value type: <phandle> | ||
82 | Definition: The phandle to the particular hardware device that this | ||
83 | portal is connected to. | ||
84 | |||
85 | DPAA QMan Pool Channel Nodes | ||
86 | |||
87 | Pool Channels are defined with the following properties. | ||
88 | |||
89 | PROPERTIES | ||
90 | |||
91 | - compatible | ||
92 | Usage: Required | ||
93 | Value type: <stringlist> | ||
94 | Definition: Must include "fsl,qman-pool-channel" | ||
95 | May include "fsl,<SoC>-qman-pool-channel" | ||
96 | |||
97 | - fsl,qman-channel-id | ||
98 | Usage: Required | ||
99 | Value type: <u32> | ||
100 | Definition: The hardware index of the channel. This can also be | ||
101 | determined by dividing any of the channel's 8 work queue | ||
102 | IDs by 8 | ||
103 | |||
104 | EXAMPLE | ||
105 | |||
106 | The example below shows a (P4080) QMan portals container/bus node with two portals | ||
107 | |||
108 | qman-portals@ff4200000 { | ||
109 | #address-cells = <1>; | ||
110 | #size-cells = <1>; | ||
111 | compatible = "simple-bus"; | ||
112 | ranges = <0 0xf 0xf4200000 0x200000>; | ||
113 | |||
114 | qman-portal@0 { | ||
115 | compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; | ||
116 | reg = <0 0x4000>, <0x100000 0x1000>; | ||
117 | interrupts = <104 2 0 0>; | ||
118 | fsl,liodn = <1 2>; | ||
119 | fsl,qman-channel-id = <0>; | ||
120 | |||
121 | fman0 { | ||
122 | fsl,liodn = <0x21>; | ||
123 | dev-handle = <&fman0>; | ||
124 | }; | ||
125 | fman1 { | ||
126 | fsl,liodn = <0xa1>; | ||
127 | dev-handle = <&fman1>; | ||
128 | }; | ||
129 | crypto { | ||
130 | fsl,liodn = <0x41 0x66>; | ||
131 | dev-handle = <&crypto>; | ||
132 | }; | ||
133 | }; | ||
134 | qman-portal@4000 { | ||
135 | compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal"; | ||
136 | reg = <0x4000 0x4000>, <0x101000 0x1000>; | ||
137 | interrupts = <106 2 0 0>; | ||
138 | fsl,liodn = <3 4>; | ||
139 | fsl,qman-channel-id = <1>; | ||
140 | |||
141 | fman0 { | ||
142 | fsl,liodn = <0x22>; | ||
143 | dev-handle = <&fman0>; | ||
144 | }; | ||
145 | fman1 { | ||
146 | fsl,liodn = <0xa2>; | ||
147 | dev-handle = <&fman1>; | ||
148 | }; | ||
149 | crypto { | ||
150 | fsl,liodn = <0x42 0x67>; | ||
151 | dev-handle = <&crypto>; | ||
152 | }; | ||
153 | }; | ||
154 | }; | ||
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt b/Documentation/devicetree/bindings/soc/fsl/qman.txt new file mode 100644 index 000000000000..063e3a0b9d04 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt | |||
@@ -0,0 +1,165 @@ | |||
1 | QorIQ DPAA Queue Manager Device Tree Binding | ||
2 | |||
3 | Copyright (C) 2008 - 2014 Freescale Semiconductor Inc. | ||
4 | |||
5 | CONTENTS | ||
6 | |||
7 | - QMan Node | ||
8 | - QMan Private Memory Nodes | ||
9 | - Example | ||
10 | |||
11 | QMan Node | ||
12 | |||
13 | The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan | ||
14 | supports queuing and QoS scheduling of frames to CPUs, network interfaces and | ||
15 | DPAA logic modules, maintains packet ordering within flows. Besides providing | ||
16 | flow-level queuing, is also responsible for congestion management functions such | ||
17 | as RED/WRED, congestion notifications and tail discards. This binding covers the | ||
18 | CCSR space programming model | ||
19 | |||
20 | PROPERTIES | ||
21 | |||
22 | - compatible | ||
23 | Usage: Required | ||
24 | Value type: <stringlist> | ||
25 | Definition: Must include "fsl,qman" | ||
26 | May include "fsl,<SoC>-qman" | ||
27 | |||
28 | - reg | ||
29 | Usage: Required | ||
30 | Value type: <prop-encoded-array> | ||
31 | Definition: Registers region within the CCSR address space | ||
32 | |||
33 | The QMan revision information is located in the QMAN_IP_REV_1/2 registers which | ||
34 | are located at offsets 0xbf8 and 0xbfc | ||
35 | |||
36 | - interrupts | ||
37 | Usage: Required | ||
38 | Value type: <prop-encoded-array> | ||
39 | Definition: Standard property. The error interrupt | ||
40 | |||
41 | - fsl,liodn | ||
42 | Usage: See pamu.txt | ||
43 | Value type: <prop-encoded-array> | ||
44 | Definition: PAMU property used for static LIODN assignment | ||
45 | |||
46 | - fsl,iommu-parent | ||
47 | Usage: See pamu.txt | ||
48 | Value type: <phandle> | ||
49 | Definition: PAMU property used for dynamic LIODN assignment | ||
50 | |||
51 | For additional details about the PAMU/LIODN binding(s) see pamu.txt | ||
52 | |||
53 | - clocks | ||
54 | Usage: See clock-bindings.txt and qoriq-clock.txt | ||
55 | Value type: <prop-encoded-array> | ||
56 | Definition: Reference input clock. Its frequency is half of the | ||
57 | platform clock | ||
58 | |||
59 | Devices connected to a QMan instance via Direct Connect Portals (DCP) must link | ||
60 | to the respective QMan instance | ||
61 | |||
62 | - fsl,qman | ||
63 | Usage: Required | ||
64 | Value type: <prop-encoded-array> | ||
65 | Description: List of phandle and DCP index pairs, to the QMan instance | ||
66 | to which this device is connected via the DCP | ||
67 | |||
68 | QMan Private Memory Nodes | ||
69 | |||
70 | QMan requires two contiguous range of physical memory used for the backing store | ||
71 | for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR). | ||
72 | This memory is reserved/allocated as a nodes under the /reserved-memory node | ||
73 | |||
74 | The QMan FQD memory node must be named "qman-fqd" | ||
75 | |||
76 | PROPERTIES | ||
77 | |||
78 | - compatible | ||
79 | Usage: required | ||
80 | Value type: <stringlist> | ||
81 | Definition: Must inclide "fsl,qman-fqd" | ||
82 | |||
83 | The QMan PFDR memory node must be named "qman-pfdr" | ||
84 | |||
85 | PROPERTIES | ||
86 | |||
87 | - compatible | ||
88 | Usage: required | ||
89 | Value type: <stringlist> | ||
90 | Definition: Must inclide "fsl,qman-pfdr" | ||
91 | |||
92 | The following constraints are relevant to the FQD and PFDR private memory: | ||
93 | - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to | ||
94 | 1 GiB | ||
95 | - The alignment must be a muliptle of the memory size | ||
96 | |||
97 | The size of the FQD and PFDP must be chosen by observing the hardware features | ||
98 | configured via the Reset Configuration Word (RCW) and that are relevant to a | ||
99 | specific board (e.g. number of MAC(s) pinned-out, number of offline/host command | ||
100 | FMan ports, etc.). The size configured in the DT must reflect the hardware | ||
101 | capabilities and not the specific needs of an application | ||
102 | |||
103 | For additional details about reserved memory regions see reserved-memory.txt | ||
104 | |||
105 | EXAMPLE | ||
106 | |||
107 | The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes | ||
108 | |||
109 | reserved-memory { | ||
110 | #address-cells = <2>; | ||
111 | #size-cells = <2>; | ||
112 | ranges; | ||
113 | |||
114 | qman_fqd: qman-fqd { | ||
115 | compatible = "fsl,qman-fqd"; | ||
116 | alloc-ranges = <0 0 0xf 0xffffffff>; | ||
117 | size = <0 0x400000>; | ||
118 | alignment = <0 0x400000>; | ||
119 | }; | ||
120 | qman_pfdr: qman-pfdr { | ||
121 | compatible = "fsl,qman-pfdr"; | ||
122 | alloc-ranges = <0 0 0xf 0xffffffff>; | ||
123 | size = <0 0x2000000>; | ||
124 | alignment = <0 0x2000000>; | ||
125 | }; | ||
126 | }; | ||
127 | |||
128 | The example below shows a (P4080) QMan CCSR-space node | ||
129 | |||
130 | clockgen: global-utilities@e1000 { | ||
131 | ... | ||
132 | sysclk: sysclk { | ||
133 | ... | ||
134 | }; | ||
135 | ... | ||
136 | platform_pll: platform-pll@c00 { | ||
137 | #clock-cells = <1>; | ||
138 | reg = <0xc00 0x4>; | ||
139 | compatible = "fsl,qoriq-platform-pll-1.0"; | ||
140 | clocks = <&sysclk>; | ||
141 | clock-output-names = "platform-pll", "platform-pll-div2"; | ||
142 | }; | ||
143 | ... | ||
144 | }; | ||
145 | |||
146 | crypto@300000 { | ||
147 | ... | ||
148 | fsl,qman = <&qman, 2>; | ||
149 | ... | ||
150 | }; | ||
151 | |||
152 | qman: qman@318000 { | ||
153 | compatible = "fsl,qman"; | ||
154 | reg = <0x318000 0x1000>; | ||
155 | interrupts = <16 2 1 3> | ||
156 | fsl,liodn = <0x16>; | ||
157 | memory-region = <&qman_fqd &qman_pfdr>; | ||
158 | clocks = <&platform_pll 1>; | ||
159 | }; | ||
160 | |||
161 | fman@400000 { | ||
162 | ... | ||
163 | fsl,qman = <&qman, 0>; | ||
164 | ... | ||
165 | }; | ||
diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt new file mode 100644 index 000000000000..337c4ea5c57b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt | |||
@@ -0,0 +1,111 @@ | |||
1 | Keystone Navigator DMA Controller | ||
2 | |||
3 | This document explains the device tree bindings for the packet dma | ||
4 | on keystone devices. The Keystone Navigator DMA driver sets up the dma | ||
5 | channels and flows for the QMSS(Queue Manager SubSystem) who triggers | ||
6 | the actual data movements across clients using destination queues. Every | ||
7 | client modules like NETCP(Network Coprocessor), SRIO(Serial Rapid IO), | ||
8 | CRYPTO Engines etc has its own instance of dma hardware. QMSS has also | ||
9 | an internal packet DMA module which is used as an infrastructure DMA | ||
10 | with zero copy. | ||
11 | |||
12 | Navigator DMA cloud layout: | ||
13 | ------------------ | ||
14 | | Navigator DMAs | | ||
15 | ------------------ | ||
16 | | | ||
17 | |-> DMA instance #0 | ||
18 | | | ||
19 | |-> DMA instance #1 | ||
20 | . | ||
21 | . | ||
22 | | | ||
23 | |-> DMA instance #n | ||
24 | |||
25 | Navigator DMA properties: | ||
26 | Required properties: | ||
27 | - compatible: Should be "ti,keystone-navigator-dma" | ||
28 | - clocks: phandle to dma instances clocks. The clock handles can be as | ||
29 | many as the dma instances. The order should be maintained as per | ||
30 | the dma instances. | ||
31 | - ti,navigator-cloud-address: Should contain base address for the multi-core | ||
32 | navigator cloud and number of addresses depends on SOC integration | ||
33 | configuration.. Navigator cloud global address needs to be programmed | ||
34 | into DMA and the DMA uses it as the physical addresses to reach queue | ||
35 | managers. Note that these addresses though points to queue managers, | ||
36 | they are relevant only from DMA perspective. The QMSS may not choose to | ||
37 | use them since it has a different address space view to reach all | ||
38 | its components. | ||
39 | |||
40 | DMA instance properties: | ||
41 | Required properties: | ||
42 | - reg: Should contain register location and length of the following dma | ||
43 | register regions. Register regions should be specified in the following | ||
44 | order. | ||
45 | - Global control register region (global). | ||
46 | - Tx DMA channel configuration register region (txchan). | ||
47 | - Rx DMA channel configuration register region (rxchan). | ||
48 | - Tx DMA channel Scheduler configuration register region (txsched). | ||
49 | - Rx DMA flow configuration register region (rxflow). | ||
50 | |||
51 | Optional properties: | ||
52 | - reg-names: Names for the register regions. | ||
53 | - ti,enable-all: Enable all DMA channels vs clients opening specific channels | ||
54 | what they need. This property is useful for the userspace fast path | ||
55 | case where the linux drivers enables the channels used by userland | ||
56 | stack. | ||
57 | - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for | ||
58 | infrastructure transfers. | ||
59 | - ti,rx-retry-timeout: Number of dma cycles to wait before retry on buffer | ||
60 | starvation. | ||
61 | |||
62 | Example: | ||
63 | |||
64 | knav_dmas: knav_dmas@0 { | ||
65 | compatible = "ti,keystone-navigator-dma"; | ||
66 | clocks = <&papllclk>, <&clkxge>; | ||
67 | #address-cells = <1>; | ||
68 | #size-cells = <1>; | ||
69 | ranges; | ||
70 | ti,navigator-cloud-address = <0x23a80000 0x23a90000 | ||
71 | 0x23aa0000 0x23ab0000>; | ||
72 | |||
73 | dma_gbe: dma_gbe@0 { | ||
74 | reg = <0x2004000 0x100>, | ||
75 | <0x2004400 0x120>, | ||
76 | <0x2004800 0x300>, | ||
77 | <0x2004c00 0x120>, | ||
78 | <0x2005000 0x400>; | ||
79 | reg-names = "global", "txchan", "rxchan", | ||
80 | "txsched", "rxflow"; | ||
81 | }; | ||
82 | |||
83 | dma_xgbe: dma_xgbe@0 { | ||
84 | reg = <0x2fa1000 0x100>, | ||
85 | <0x2fa1400 0x200>, | ||
86 | <0x2fa1800 0x200>, | ||
87 | <0x2fa1c00 0x200>, | ||
88 | <0x2fa2000 0x400>; | ||
89 | reg-names = "global", "txchan", "rxchan", | ||
90 | "txsched", "rxflow"; | ||
91 | }; | ||
92 | }; | ||
93 | |||
94 | Navigator DMA client: | ||
95 | Required properties: | ||
96 | - ti,navigator-dmas: List of one or more DMA specifiers, each consisting of | ||
97 | - A phandle pointing to DMA instance node | ||
98 | - A DMA channel number as a phandle arg. | ||
99 | - ti,navigator-dma-names: Contains dma channel name for each DMA specifier in | ||
100 | the 'ti,navigator-dmas' property. | ||
101 | |||
102 | Example: | ||
103 | |||
104 | netcp: netcp@2090000 { | ||
105 | .. | ||
106 | ti,navigator-dmas = <&dma_gbe 22>, | ||
107 | <&dma_gbe 23>, | ||
108 | <&dma_gbe 8>; | ||
109 | ti,navigator-dma-names = "netrx0", "netrx1", "nettx"; | ||
110 | .. | ||
111 | }; | ||
diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt new file mode 100644 index 000000000000..d8e8cdb733f9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt | |||
@@ -0,0 +1,232 @@ | |||
1 | * Texas Instruments Keystone Navigator Queue Management SubSystem driver | ||
2 | |||
3 | The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of | ||
4 | the main hardware sub system which forms the backbone of the Keystone | ||
5 | multi-core Navigator. QMSS consist of queue managers, packed-data structure | ||
6 | processors(PDSP), linking RAM, descriptor pools and infrastructure | ||
7 | Packet DMA. | ||
8 | The Queue Manager is a hardware module that is responsible for accelerating | ||
9 | management of the packet queues. Packets are queued/de-queued by writing or | ||
10 | reading descriptor address to a particular memory mapped location. The PDSPs | ||
11 | perform QMSS related functions like accumulation, QoS, or event management. | ||
12 | Linking RAM registers are used to link the descriptors which are stored in | ||
13 | descriptor RAM. Descriptor RAM is configurable as internal or external memory. | ||
14 | The QMSS driver manages the PDSP setups, linking RAM regions, | ||
15 | queue pool management (allocation, push, pop and notify) and descriptor | ||
16 | pool management. | ||
17 | |||
18 | |||
19 | Required properties: | ||
20 | - compatible : Must be "ti,keystone-navigator-qmss"; | ||
21 | - clocks : phandle to the reference clock for this device. | ||
22 | - queue-range : <start number> total range of queue numbers for the device. | ||
23 | - linkram0 : <address size> for internal link ram, where size is the total | ||
24 | link ram entries. | ||
25 | - linkram1 : <address size> for external link ram, where size is the total | ||
26 | external link ram entries. If the address is specified as "0" | ||
27 | driver will allocate memory. | ||
28 | - qmgrs : child node describing the individual queue managers on the | ||
29 | SoC. On keystone 1 devices there should be only one node. | ||
30 | On keystone 2 devices there can be more than 1 node. | ||
31 | -- managed-queues : the actual queues managed by each queue manager | ||
32 | instance, specified as <"base queue #" "# of queues">. | ||
33 | -- reg : Address and size of the register set for the device. | ||
34 | Register regions should be specified in the following | ||
35 | order | ||
36 | - Queue Peek region. | ||
37 | - Queue status RAM. | ||
38 | - Queue configuration region. | ||
39 | - Descriptor memory setup region. | ||
40 | - Queue Management/Queue Proxy region for queue Push. | ||
41 | - Queue Management/Queue Proxy region for queue Pop. | ||
42 | - queue-pools : child node classifying the queue ranges into pools. | ||
43 | Queue ranges are grouped into 3 type of pools: | ||
44 | - qpend : pool of qpend(interruptible) queues | ||
45 | - general-purpose : pool of general queues, primarly used | ||
46 | as free descriptor queues or the | ||
47 | transmit DMA queues. | ||
48 | - accumulator : pool of queues on PDSP accumulator channel | ||
49 | Each range can have the following properties: | ||
50 | -- qrange : number of queues to use per queue range, specified as | ||
51 | <"base queue #" "# of queues">. | ||
52 | -- interrupts : Optional property to specify the interrupt mapping | ||
53 | for interruptible queues. The driver additionaly sets | ||
54 | the interrupt affinity hint based on the cpu mask. | ||
55 | -- qalloc-by-id : Optional property to specify that the queues in this | ||
56 | range can only be allocated by queue id. | ||
57 | -- accumulator : Accumulator channel specification. Any of the PDSPs in | ||
58 | QMSS can be loaded with the accumulator firmware. The | ||
59 | accumulator firmware’s job is to poll a select number of | ||
60 | queues looking for descriptors that have been pushed | ||
61 | into them. Descriptors are popped from the queue and | ||
62 | placed in a buffer provided by the host. When the list | ||
63 | becomes full or a programmed time period expires, the | ||
64 | accumulator triggers an interrupt to the host to read | ||
65 | the buffer for descriptor information. This firmware | ||
66 | comes in 16, 32, and 48 channel builds. Each of these | ||
67 | channels can be configured to monitor 32 contiguous | ||
68 | queues. Accumulator channel property is specified as: | ||
69 | <pdsp-id, channel, entries, pacing mode, latency> | ||
70 | pdsp-id : QMSS PDSP running accumulator firmware | ||
71 | on which the channel has to be | ||
72 | configured | ||
73 | channel : Accumulator channel number | ||
74 | entries : Size of the accumulator descriptor list | ||
75 | pacing mode : Interrupt pacing mode | ||
76 | 0 : None, i.e interrupt on list full only | ||
77 | 1 : Time delay since last interrupt | ||
78 | 2 : Time delay since first new packet | ||
79 | 3 : Time delay since last new packet | ||
80 | latency : time to delay the interrupt, specified | ||
81 | in microseconds. | ||
82 | -- multi-queue : Optional property to specify that the channel has to | ||
83 | monitor upto 32 queues starting at the base queue #. | ||
84 | - descriptor-regions : child node describing the memory regions for keystone | ||
85 | navigator packet DMA descriptors. The memory for | ||
86 | descriptors will be allocated by the driver. | ||
87 | -- id : region number in QMSS. | ||
88 | -- region-spec : specifies the number of descriptors in the | ||
89 | region, specified as | ||
90 | <"# of descriptors" "descriptor size">. | ||
91 | -- link-index : start index, i.e. index of the first | ||
92 | descriptor in the region. | ||
93 | |||
94 | Optional properties: | ||
95 | - dma-coherent : Present if DMA operations are coherent. | ||
96 | - pdsps : child node describing the PDSP configuration. | ||
97 | -- firmware : firmware to be loaded on the PDSP. | ||
98 | -- id : the qmss pdsp that will run the firmware. | ||
99 | -- reg : Address and size of the register set for the PDSP. | ||
100 | Register regions should be specified in the following | ||
101 | order | ||
102 | - PDSP internal RAM region. | ||
103 | - PDSP control/status region registers. | ||
104 | - QMSS interrupt distributor registers. | ||
105 | - PDSP command interface region. | ||
106 | |||
107 | Example: | ||
108 | |||
109 | qmss: qmss@2a40000 { | ||
110 | compatible = "ti,keystone-qmss"; | ||
111 | dma-coherent; | ||
112 | #address-cells = <1>; | ||
113 | #size-cells = <1>; | ||
114 | clocks = <&chipclk13>; | ||
115 | ranges; | ||
116 | queue-range = <0 0x4000>; | ||
117 | linkram0 = <0x100000 0x8000>; | ||
118 | linkram1 = <0x0 0x10000>; | ||
119 | |||
120 | qmgrs { | ||
121 | #address-cells = <1>; | ||
122 | #size-cells = <1>; | ||
123 | ranges; | ||
124 | qmgr0 { | ||
125 | managed-queues = <0 0x2000>; | ||
126 | reg = <0x2a40000 0x20000>, | ||
127 | <0x2a06000 0x400>, | ||
128 | <0x2a02000 0x1000>, | ||
129 | <0x2a03000 0x1000>, | ||
130 | <0x23a80000 0x20000>, | ||
131 | <0x2a80000 0x20000>; | ||
132 | }; | ||
133 | |||
134 | qmgr1 { | ||
135 | managed-queues = <0x2000 0x2000>; | ||
136 | reg = <0x2a60000 0x20000>, | ||
137 | <0x2a06400 0x400>, | ||
138 | <0x2a04000 0x1000>, | ||
139 | <0x2a05000 0x1000>, | ||
140 | <0x23aa0000 0x20000>, | ||
141 | <0x2aa0000 0x20000>; | ||
142 | }; | ||
143 | }; | ||
144 | queue-pools { | ||
145 | qpend { | ||
146 | qpend-0 { | ||
147 | qrange = <658 8>; | ||
148 | interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04 | ||
149 | 0 43 0xf04 0 44 0xf04 0 45 0xf04 | ||
150 | 0 46 0xf04 0 47 0xf04>; | ||
151 | }; | ||
152 | qpend-1 { | ||
153 | qrange = <8704 16>; | ||
154 | interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04 | ||
155 | 0 51 0xf04 0 52 0xf04 0 53 0xf04 | ||
156 | 0 54 0xf04 0 55 0xf04 0 56 0xf04 | ||
157 | 0 57 0xf04 0 58 0xf04 0 59 0xf04 | ||
158 | 0 60 0xf04 0 61 0xf04 0 62 0xf04 | ||
159 | 0 63 0xf04>; | ||
160 | qalloc-by-id; | ||
161 | }; | ||
162 | qpend-2 { | ||
163 | qrange = <8720 16>; | ||
164 | interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04 | ||
165 | 0 59 0xf04 0 68 0xf04 0 69 0xf04 | ||
166 | 0 70 0xf04 0 71 0xf04 0 72 0xf04 | ||
167 | 0 73 0xf04 0 74 0xf04 0 75 0xf04 | ||
168 | 0 76 0xf04 0 77 0xf04 0 78 0xf04 | ||
169 | 0 79 0xf04>; | ||
170 | }; | ||
171 | }; | ||
172 | general-purpose { | ||
173 | gp-0 { | ||
174 | qrange = <4000 64>; | ||
175 | }; | ||
176 | netcp-tx { | ||
177 | qrange = <640 9>; | ||
178 | qalloc-by-id; | ||
179 | }; | ||
180 | }; | ||
181 | accumulator { | ||
182 | acc-0 { | ||
183 | qrange = <128 32>; | ||
184 | accumulator = <0 36 16 2 50>; | ||
185 | interrupts = <0 215 0xf01>; | ||
186 | multi-queue; | ||
187 | qalloc-by-id; | ||
188 | }; | ||
189 | acc-1 { | ||
190 | qrange = <160 32>; | ||
191 | accumulator = <0 37 16 2 50>; | ||
192 | interrupts = <0 216 0xf01>; | ||
193 | multi-queue; | ||
194 | }; | ||
195 | acc-2 { | ||
196 | qrange = <192 32>; | ||
197 | accumulator = <0 38 16 2 50>; | ||
198 | interrupts = <0 217 0xf01>; | ||
199 | multi-queue; | ||
200 | }; | ||
201 | acc-3 { | ||
202 | qrange = <224 32>; | ||
203 | accumulator = <0 39 16 2 50>; | ||
204 | interrupts = <0 218 0xf01>; | ||
205 | multi-queue; | ||
206 | }; | ||
207 | }; | ||
208 | }; | ||
209 | descriptor-regions { | ||
210 | #address-cells = <1>; | ||
211 | #size-cells = <1>; | ||
212 | ranges; | ||
213 | region-12 { | ||
214 | id = <12>; | ||
215 | region-spec = <8192 128>; /* num_desc desc_size */ | ||
216 | link-index = <0x4000>; | ||
217 | }; | ||
218 | }; | ||
219 | pdsps { | ||
220 | #address-cells = <1>; | ||
221 | #size-cells = <1>; | ||
222 | ranges; | ||
223 | pdsp0@0x2a10000 { | ||
224 | firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw"; | ||
225 | reg = <0x2a10000 0x1000>, | ||
226 | <0x2a0f000 0x100>, | ||
227 | <0x2a0c000 0x3c8>, | ||
228 | <0x2a20000 0x4000>; | ||
229 | id = <0>; | ||
230 | }; | ||
231 | }; | ||
232 | }; /* qmss */ | ||
diff --git a/Documentation/devicetree/bindings/sound/adi,ssm2602.txt b/Documentation/devicetree/bindings/sound/adi,ssm2602.txt new file mode 100644 index 000000000000..3b3302fe399b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/adi,ssm2602.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices | ||
2 | |||
3 | SSM2602 support both I2C and SPI as the configuration interface, | ||
4 | the selection is made by the MODE strap-in pin. | ||
5 | SSM2603 and SSM2604 only support I2C as the configuration interface. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604" | ||
10 | |||
11 | - reg : the I2C address of the device for I2C, the chip select | ||
12 | number for SPI. | ||
13 | |||
14 | Example: | ||
15 | |||
16 | ssm2602: ssm2602@1a { | ||
17 | compatible = "adi,ssm2602"; | ||
18 | reg = <0x1a>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/arndale.txt b/Documentation/devicetree/bindings/sound/arndale.txt new file mode 100644 index 000000000000..0e76946385ae --- /dev/null +++ b/Documentation/devicetree/bindings/sound/arndale.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | Audio Binding for Arndale boards | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Can be the following, | ||
5 | "samsung,arndale-rt5631" | ||
6 | |||
7 | - samsung,audio-cpu: The phandle of the Samsung I2S controller | ||
8 | - samsung,audio-codec: The phandle of the audio codec | ||
9 | |||
10 | Optional: | ||
11 | - samsung,model: The name of the sound-card | ||
12 | |||
13 | Arndale Boards has many audio daughter cards, one of them is | ||
14 | rt5631/alc5631. Below example shows audio bindings for rt5631/ | ||
15 | alc5631 based codec. | ||
16 | |||
17 | Example: | ||
18 | |||
19 | sound { | ||
20 | compatible = "samsung,arndale-rt5631"; | ||
21 | |||
22 | samsung,audio-cpu = <&i2s0> | ||
23 | samsung,audio-codec = <&rt5631>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/cs35l32.txt b/Documentation/devicetree/bindings/sound/cs35l32.txt new file mode 100644 index 000000000000..1417d3f5cc22 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cs35l32.txt | |||
@@ -0,0 +1,62 @@ | |||
1 | CS35L32 audio CODEC | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : "cirrus,cs35l32" | ||
6 | |||
7 | - reg : the I2C address of the device for I2C. Address is determined by the level | ||
8 | of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41. | ||
9 | |||
10 | - VA-supply, VP-supply : power supplies for the device, | ||
11 | as covered in Documentation/devicetree/bindings/regulator/regulator.txt. | ||
12 | |||
13 | Optional properties: | ||
14 | |||
15 | - reset-gpios : a GPIO spec for the reset pin. If specified, it will be | ||
16 | deasserted before communication to the codec starts. | ||
17 | |||
18 | - cirrus,boost-manager : Boost voltage control. | ||
19 | 0 = Automatically managed. Boost-converter output voltage is the higher | ||
20 | of the two: Class G or adaptive LED voltage. | ||
21 | 1 = Automatically managed irrespective of audio, adapting for low-power | ||
22 | dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode | ||
23 | if LEDs are OFF (VBST = VP). | ||
24 | 2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP). | ||
25 | 3 = Boost voltage fixed at 5 V. | ||
26 | |||
27 | - cirrus,sdout-datacfg : Data configuration for dual CS35L32 applications only. | ||
28 | Determines the data packed in a two-CS35L32 configuration. | ||
29 | 0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0]. | ||
30 | 1 = Left/right channels VMON[11:0], IMON[11:0], STATUS. | ||
31 | 2 = (Default) left/right channels VMON[15:0], IMON [15:0]. | ||
32 | 3 = Left/right channels VPMON[7:0], STATUS. | ||
33 | |||
34 | - cirrus,sdout-share : SDOUT sharing. Determines whether one or two CS35L32 | ||
35 | devices are on board sharing SDOUT. | ||
36 | 0 = (Default) One IC. | ||
37 | 1 = Two IC's. | ||
38 | |||
39 | - cirrus,battery-recovery : Low battery nominal recovery threshold, rising VP. | ||
40 | 0 = 3.1V | ||
41 | 1 = 3.2V | ||
42 | 2 = 3.3V (Default) | ||
43 | 3 = 3.4V | ||
44 | |||
45 | - cirrus,battery-threshold : Low battery nominal threshold, falling VP. | ||
46 | 0 = 3.1V | ||
47 | 1 = 3.2V | ||
48 | 2 = 3.3V | ||
49 | 3 = 3.4V (Default) | ||
50 | 4 = 3.5V | ||
51 | 5 = 3.6V | ||
52 | |||
53 | Example: | ||
54 | |||
55 | codec: codec@40 { | ||
56 | compatible = "cirrus,cs35l32"; | ||
57 | reg = <0x40>; | ||
58 | reset-gpios = <&gpio 10 0>; | ||
59 | cirrus,boost-manager = <0x03>; | ||
60 | cirrus,sdout-datacfg = <0x02>; | ||
61 | VA-supply = <®_audio>; | ||
62 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt index 60ca07996458..46bc9829c71a 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.txt | |||
@@ -32,7 +32,7 @@ Optional properties: | |||
32 | - rx-num-evt : FIFO levels. | 32 | - rx-num-evt : FIFO levels. |
33 | - sram-size-playback : size of sram to be allocated during playback | 33 | - sram-size-playback : size of sram to be allocated during playback |
34 | - sram-size-capture : size of sram to be allocated during capture | 34 | - sram-size-capture : size of sram to be allocated during capture |
35 | - interrupts : Interrupt numbers for McASP, currently not used by the driver | 35 | - interrupts : Interrupt numbers for McASP |
36 | - interrupt-names : Known interrupt names are "tx" and "rx" | 36 | - interrupt-names : Known interrupt names are "tx" and "rx" |
37 | - pinctrl-0: Should specify pin control group used for this controller. | 37 | - pinctrl-0: Should specify pin control group used for this controller. |
38 | - pinctrl-names: Should contain only one value - "default", for more details | 38 | - pinctrl-names: Should contain only one value - "default", for more details |
diff --git a/Documentation/devicetree/bindings/sound/es8328.txt b/Documentation/devicetree/bindings/sound/es8328.txt new file mode 100644 index 000000000000..30ea8a318ae9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/es8328.txt | |||
@@ -0,0 +1,38 @@ | |||
1 | Everest ES8328 audio CODEC | ||
2 | |||
3 | This device supports both I2C and SPI. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "everest,es8328" | ||
8 | - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V | ||
9 | - AVDD-supply : Regulator providing analog supply voltage 3.3V | ||
10 | - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V | ||
11 | - IPVDD-supply : Regulator providing analog output voltage 3.3V | ||
12 | - clocks : A 22.5792 or 11.2896 MHz clock | ||
13 | - reg : the I2C address of the device for I2C, the chip select number for SPI | ||
14 | |||
15 | Pins on the device (for linking into audio routes): | ||
16 | |||
17 | * LOUT1 | ||
18 | * LOUT2 | ||
19 | * ROUT1 | ||
20 | * ROUT2 | ||
21 | * LINPUT1 | ||
22 | * RINPUT1 | ||
23 | * LINPUT2 | ||
24 | * RINPUT2 | ||
25 | * Mic Bias | ||
26 | |||
27 | |||
28 | Example: | ||
29 | |||
30 | codec: es8328@11 { | ||
31 | compatible = "everest,es8328"; | ||
32 | DVDD-supply = <®_3p3v>; | ||
33 | AVDD-supply = <®_3p3v>; | ||
34 | PVDD-supply = <®_3p3v>; | ||
35 | HPVDD-supply = <®_3p3v>; | ||
36 | clocks = <&clks 169>; | ||
37 | reg = <0x11>; | ||
38 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt b/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt index 0d7985c864af..6dfa88c4dc1e 100644 --- a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt +++ b/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt | |||
@@ -1,11 +1,16 @@ | |||
1 | Audio complex for Eukrea boards with tlv320aic23 codec. | 1 | Audio complex for Eukrea boards with tlv320aic23 codec. |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "eukrea,asoc-tlv320" | 4 | |
5 | - eukrea,model : The user-visible name of this sound complex. | 5 | - compatible : "eukrea,asoc-tlv320" |
6 | - ssi-controller : The phandle of the SSI controller. | 6 | |
7 | - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX). | 7 | - eukrea,model : The user-visible name of this sound complex. |
8 | - fsl,mux-ext-port : The external port of the i.MX audio muxer. | 8 | |
9 | - ssi-controller : The phandle of the SSI controller. | ||
10 | |||
11 | - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX). | ||
12 | |||
13 | - fsl,mux-ext-port : The external port of the i.MX audio muxer. | ||
9 | 14 | ||
10 | Note: The AUDMUX port numbering should start at 1, which is consistent with | 15 | Note: The AUDMUX port numbering should start at 1, which is consistent with |
11 | hardware manual. | 16 | hardware manual. |
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt index aeb8c4a0b88d..d3b6b5f48010 100644 --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt | |||
@@ -7,36 +7,39 @@ other DSPs. It has up to six transmitters and four receivers. | |||
7 | 7 | ||
8 | Required properties: | 8 | Required properties: |
9 | 9 | ||
10 | - compatible : Compatible list, must contain "fsl,imx35-esai". | 10 | - compatible : Compatible list, must contain "fsl,imx35-esai" or |
11 | "fsl,vf610-esai" | ||
11 | 12 | ||
12 | - reg : Offset and length of the register set for the device. | 13 | - reg : Offset and length of the register set for the device. |
13 | 14 | ||
14 | - interrupts : Contains the spdif interrupt. | 15 | - interrupts : Contains the spdif interrupt. |
15 | 16 | ||
16 | - dmas : Generic dma devicetree binding as described in | 17 | - dmas : Generic dma devicetree binding as described in |
17 | Documentation/devicetree/bindings/dma/dma.txt. | 18 | Documentation/devicetree/bindings/dma/dma.txt. |
18 | 19 | ||
19 | - dma-names : Two dmas have to be defined, "tx" and "rx". | 20 | - dma-names : Two dmas have to be defined, "tx" and "rx". |
20 | 21 | ||
21 | - clocks: Contains an entry for each entry in clock-names. | 22 | - clocks : Contains an entry for each entry in clock-names. |
22 | 23 | ||
23 | - clock-names : Includes the following entries: | 24 | - clock-names : Includes the following entries: |
24 | "core" The core clock used to access registers | 25 | "core" The core clock used to access registers |
25 | "extal" The esai baud clock for esai controller used to derive | 26 | "extal" The esai baud clock for esai controller used to |
26 | HCK, SCK and FS. | 27 | derive HCK, SCK and FS. |
27 | "fsys" The system clock derived from ahb clock used to derive | 28 | "fsys" The system clock derived from ahb clock used to |
28 | HCK, SCK and FS. | 29 | derive HCK, SCK and FS. |
29 | 30 | ||
30 | - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs. | 31 | - fsl,fifo-depth : The number of elements in the transmit and receive |
31 | This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM]. | 32 | FIFOs. This number is the maximum allowed value for |
33 | TFCR[TFWM] or RFCR[RFWM]. | ||
32 | 34 | ||
33 | - fsl,esai-synchronous: This is a boolean property. If present, indicating | 35 | - fsl,esai-synchronous: This is a boolean property. If present, indicating |
34 | that ESAI would work in the synchronous mode, which means all the settings | 36 | that ESAI would work in the synchronous mode, which |
35 | for Receiving would be duplicated from Transmition related registers. | 37 | means all the settings for Receiving would be |
38 | duplicated from Transmition related registers. | ||
36 | 39 | ||
37 | - big-endian : If this property is absent, the native endian mode will | 40 | - big-endian : If this property is absent, the native endian mode |
38 | be in use as default, or the big endian mode will be in use for all the | 41 | will be in use as default, or the big endian mode |
39 | device registers. | 42 | will be in use for all the device registers. |
40 | 43 | ||
41 | Example: | 44 | Example: |
42 | 45 | ||
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index 3e9e82c8eab3..b5ee32ee3706 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt | |||
@@ -6,32 +6,31 @@ a fibre cable. | |||
6 | 6 | ||
7 | Required properties: | 7 | Required properties: |
8 | 8 | ||
9 | - compatible : Compatible list, must contain "fsl,imx35-spdif". | 9 | - compatible : Compatible list, must contain "fsl,imx35-spdif". |
10 | 10 | ||
11 | - reg : Offset and length of the register set for the device. | 11 | - reg : Offset and length of the register set for the device. |
12 | 12 | ||
13 | - interrupts : Contains the spdif interrupt. | 13 | - interrupts : Contains the spdif interrupt. |
14 | 14 | ||
15 | - dmas : Generic dma devicetree binding as described in | 15 | - dmas : Generic dma devicetree binding as described in |
16 | Documentation/devicetree/bindings/dma/dma.txt. | 16 | Documentation/devicetree/bindings/dma/dma.txt. |
17 | 17 | ||
18 | - dma-names : Two dmas have to be defined, "tx" and "rx". | 18 | - dma-names : Two dmas have to be defined, "tx" and "rx". |
19 | 19 | ||
20 | - clocks : Contains an entry for each entry in clock-names. | 20 | - clocks : Contains an entry for each entry in clock-names. |
21 | 21 | ||
22 | - clock-names : Includes the following entries: | 22 | - clock-names : Includes the following entries: |
23 | "core" The core clock of spdif controller | 23 | "core" The core clock of spdif controller. |
24 | "rxtx<0-7>" Clock source list for tx and rx clock. | 24 | "rxtx<0-7>" Clock source list for tx and rx clock. |
25 | This clock list should be identical to | 25 | This clock list should be identical to the source |
26 | the source list connecting to the spdif | 26 | list connecting to the spdif clock mux in "SPDIF |
27 | clock mux in "SPDIF Transceiver Clock | 27 | Transceiver Clock Diagram" of SoC reference manual. |
28 | Diagram" of SoC reference manual. It | 28 | It can also be referred to TxClk_Source bit of |
29 | can also be referred to TxClk_Source | 29 | register SPDIF_STC. |
30 | bit of register SPDIF_STC. | ||
31 | 30 | ||
32 | - big-endian : If this property is absent, the native endian mode will | 31 | - big-endian : If this property is absent, the native endian mode |
33 | be in use as default, or the big endian mode will be in use for all the | 32 | will be in use as default, or the big endian mode |
34 | device registers. | 33 | will be in use for all the device registers. |
35 | 34 | ||
36 | Example: | 35 | Example: |
37 | 36 | ||
diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt index 3aa4a8f528f4..5b76be45d18b 100644 --- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt +++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt | |||
@@ -58,13 +58,7 @@ Optional properties: | |||
58 | Documentation/devicetree/bindings/dma/dma.txt. | 58 | Documentation/devicetree/bindings/dma/dma.txt. |
59 | - dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq | 59 | - dma-names: Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq |
60 | is not defined. | 60 | is not defined. |
61 | - fsl,mode: The operating mode for the SSI interface. | 61 | - fsl,mode: The operating mode for the AC97 interface only. |
62 | "i2s-slave" - I2S mode, SSI is clock slave | ||
63 | "i2s-master" - I2S mode, SSI is clock master | ||
64 | "lj-slave" - left-justified mode, SSI is clock slave | ||
65 | "lj-master" - l.j. mode, SSI is clock master | ||
66 | "rj-slave" - right-justified mode, SSI is clock slave | ||
67 | "rj-master" - r.j., SSI is clock master | ||
68 | "ac97-slave" - AC97 mode, SSI is clock slave | 62 | "ac97-slave" - AC97 mode, SSI is clock slave |
69 | "ac97-master" - AC97 mode, SSI is clock master | 63 | "ac97-master" - AC97 mode, SSI is clock master |
70 | 64 | ||
diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt new file mode 100644 index 000000000000..a96774c194c8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt | |||
@@ -0,0 +1,82 @@ | |||
1 | Freescale Generic ASoC Sound Card with ASRC support | ||
2 | |||
3 | The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale | ||
4 | SoCs connecting with external CODECs. | ||
5 | |||
6 | The idea of this generic sound card is a bit like ASoC Simple Card. However, | ||
7 | for Freescale SoCs (especially those released in recent years), most of them | ||
8 | have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And | ||
9 | this is a specific feature that might be painstakingly controlled and merged | ||
10 | into the Simple Card. | ||
11 | |||
12 | So having this generic sound card allows all Freescale SoC users to benefit | ||
13 | from the simplification of a new card support and the capability of the wide | ||
14 | sample rates support through ASRC. | ||
15 | |||
16 | Note: The card is initially designed for those sound cards who use I2S and | ||
17 | PCM DAI formats. However, it'll be also possible to support those non | ||
18 | I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as long | ||
19 | as the driver has been properly upgraded. | ||
20 | |||
21 | |||
22 | The compatible list for this generic sound card currently: | ||
23 | "fsl,imx-audio-cs42888" | ||
24 | |||
25 | "fsl,imx-audio-wm8962" | ||
26 | (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt) | ||
27 | |||
28 | "fsl,imx-audio-sgtl5000" | ||
29 | (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) | ||
30 | |||
31 | Required properties: | ||
32 | |||
33 | - compatible : Contains one of entries in the compatible list. | ||
34 | |||
35 | - model : The user-visible name of this sound complex | ||
36 | |||
37 | - audio-cpu : The phandle of an CPU DAI controller | ||
38 | |||
39 | - audio-codec : The phandle of an audio codec | ||
40 | |||
41 | - audio-routing : A list of the connections between audio components. | ||
42 | Each entry is a pair of strings, the first being the | ||
43 | connection's sink, the second being the connection's | ||
44 | source. There're a few pre-designed board connectors: | ||
45 | * Line Out Jack | ||
46 | * Line In Jack | ||
47 | * Headphone Jack | ||
48 | * Mic Jack | ||
49 | * Ext Spk | ||
50 | * AMIC (stands for Analog Microphone Jack) | ||
51 | * DMIC (stands for Digital Microphone Jack) | ||
52 | |||
53 | Note: The "Mic Jack" and "AMIC" are redundant while | ||
54 | coexsiting in order to support the old bindings | ||
55 | of wm8962 and sgtl5000. | ||
56 | |||
57 | Optional properties: | ||
58 | |||
59 | - audio-asrc : The phandle of ASRC. It can be absent if there's no | ||
60 | need to add ASRC support via DPCM. | ||
61 | |||
62 | Example: | ||
63 | sound-cs42888 { | ||
64 | compatible = "fsl,imx-audio-cs42888"; | ||
65 | model = "cs42888-audio"; | ||
66 | audio-cpu = <&esai>; | ||
67 | audio-asrc = <&asrc>; | ||
68 | audio-codec = <&cs42888>; | ||
69 | audio-routing = | ||
70 | "Line Out Jack", "AOUT1L", | ||
71 | "Line Out Jack", "AOUT1R", | ||
72 | "Line Out Jack", "AOUT2L", | ||
73 | "Line Out Jack", "AOUT2R", | ||
74 | "Line Out Jack", "AOUT3L", | ||
75 | "Line Out Jack", "AOUT3R", | ||
76 | "Line Out Jack", "AOUT4L", | ||
77 | "Line Out Jack", "AOUT4R", | ||
78 | "AIN1L", "Line In Jack", | ||
79 | "AIN1R", "Line In Jack", | ||
80 | "AIN2L", "Line In Jack", | ||
81 | "AIN2R", "Line In Jack"; | ||
82 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 0f4e23828190..044e5d76e2dd 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt | |||
@@ -5,25 +5,55 @@ which provides a synchronous audio interface that supports fullduplex | |||
5 | serial interfaces with frame synchronization such as I2S, AC97, TDM, and | 5 | serial interfaces with frame synchronization such as I2S, AC97, TDM, and |
6 | codec/DSP interfaces. | 6 | codec/DSP interfaces. |
7 | 7 | ||
8 | |||
9 | Required properties: | 8 | Required properties: |
10 | - compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai". | 9 | |
11 | - reg: Offset and length of the register set for the device. | 10 | - compatible : Compatible list, contains "fsl,vf610-sai" or |
12 | - clocks: Must contain an entry for each entry in clock-names. | 11 | "fsl,imx6sx-sai". |
13 | - clock-names : Must include the "bus" for register access and "mclk1" "mclk2" | 12 | |
14 | "mclk3" for bit clock and frame clock providing. | 13 | - reg : Offset and length of the register set for the device. |
15 | - dmas : Generic dma devicetree binding as described in | 14 | |
16 | Documentation/devicetree/bindings/dma/dma.txt. | 15 | - clocks : Must contain an entry for each entry in clock-names. |
17 | - dma-names : Two dmas have to be defined, "tx" and "rx". | 16 | |
18 | - pinctrl-names: Must contain a "default" entry. | 17 | - clock-names : Must include the "bus" for register access and |
19 | - pinctrl-NNN: One property must exist for each entry in pinctrl-names. | 18 | "mclk1", "mclk2", "mclk3" for bit clock and frame |
20 | See ../pinctrl/pinctrl-bindings.txt for details of the property values. | 19 | clock providing. |
21 | - big-endian-regs: If this property is absent, the little endian mode will | 20 | - dmas : Generic dma devicetree binding as described in |
22 | be in use as default, or the big endian mode will be in use for all the | 21 | Documentation/devicetree/bindings/dma/dma.txt. |
23 | device registers. | 22 | |
24 | - big-endian-data: If this property is absent, the little endian mode will | 23 | - dma-names : Two dmas have to be defined, "tx" and "rx". |
25 | be in use as default, or the big endian mode will be in use for all the | 24 | |
26 | fifo data. | 25 | - pinctrl-names : Must contain a "default" entry. |
26 | |||
27 | - pinctrl-NNN : One property must exist for each entry in | ||
28 | pinctrl-names. See ../pinctrl/pinctrl-bindings.txt | ||
29 | for details of the property values. | ||
30 | |||
31 | - big-endian : Boolean property, required if all the FTM_PWM | ||
32 | registers are big-endian rather than little-endian. | ||
33 | |||
34 | - lsb-first : Configures whether the LSB or the MSB is transmitted | ||
35 | first for the fifo data. If this property is absent, | ||
36 | the MSB is transmitted first as default, or the LSB | ||
37 | is transmitted first. | ||
38 | |||
39 | - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating | ||
40 | that SAI will work in the synchronous mode (sync Tx | ||
41 | with Rx) which means both the transimitter and the | ||
42 | receiver will send and receive data by following | ||
43 | receiver's bit clocks and frame sync clocks. | ||
44 | |||
45 | - fsl,sai-asynchronous: This is a boolean property. If present, indicating | ||
46 | that SAI will work in the asynchronous mode, which | ||
47 | means both transimitter and receiver will send and | ||
48 | receive data by following their own bit clocks and | ||
49 | frame sync clocks separately. | ||
50 | |||
51 | Note: | ||
52 | - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the | ||
53 | default synchronous mode (sync Rx with Tx) will be used, which means both | ||
54 | transimitter and receiver will send and receive data by following clocks | ||
55 | of transimitter. | ||
56 | - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. | ||
27 | 57 | ||
28 | Example: | 58 | Example: |
29 | sai2: sai@40031000 { | 59 | sai2: sai@40031000 { |
@@ -38,6 +68,6 @@ sai2: sai@40031000 { | |||
38 | dma-names = "tx", "rx"; | 68 | dma-names = "tx", "rx"; |
39 | dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, | 69 | dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, |
40 | <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; | 70 | <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; |
41 | big-endian-regs; | 71 | big-endian; |
42 | big-endian-data; | 72 | lsb-first; |
43 | }; | 73 | }; |
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt b/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt new file mode 100644 index 000000000000..07b68ab206fb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt | |||
@@ -0,0 +1,60 @@ | |||
1 | Freescale i.MX audio complex with ES8328 codec | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "fsl,imx-audio-es8328" | ||
5 | - model : The user-visible name of this sound complex | ||
6 | - ssi-controller : The phandle of the i.MX SSI controller | ||
7 | - jack-gpio : Optional GPIO for headphone jack | ||
8 | - audio-amp-supply : Power regulator for speaker amps | ||
9 | - audio-codec : The phandle of the ES8328 audio codec | ||
10 | - audio-routing : A list of the connections between audio components. | ||
11 | Each entry is a pair of strings, the first being the | ||
12 | connection's sink, the second being the connection's | ||
13 | source. Valid names could be power supplies, ES8328 | ||
14 | pins, and the jacks on the board: | ||
15 | |||
16 | Power supplies: | ||
17 | * audio-amp | ||
18 | |||
19 | ES8328 pins: | ||
20 | * LOUT1 | ||
21 | * LOUT2 | ||
22 | * ROUT1 | ||
23 | * ROUT2 | ||
24 | * LINPUT1 | ||
25 | * LINPUT2 | ||
26 | * RINPUT1 | ||
27 | * RINPUT2 | ||
28 | * Mic PGA | ||
29 | |||
30 | Board connectors: | ||
31 | * Headphone | ||
32 | * Speaker | ||
33 | * Mic Jack | ||
34 | - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) | ||
35 | - mux-ext-port : The external port of the i.MX audio muxer (AUDMIX) | ||
36 | |||
37 | Note: The AUDMUX port numbering should start at 1, which is consistent with | ||
38 | hardware manual. | ||
39 | |||
40 | Example: | ||
41 | |||
42 | sound { | ||
43 | compatible = "fsl,imx-audio-es8328"; | ||
44 | model = "imx-audio-es8328"; | ||
45 | ssi-controller = <&ssi1>; | ||
46 | audio-codec = <&codec>; | ||
47 | jack-gpio = <&gpio5 15 0>; | ||
48 | audio-amp-supply = <®_audio_amp>; | ||
49 | audio-routing = | ||
50 | "Speaker", "LOUT2", | ||
51 | "Speaker", "ROUT2", | ||
52 | "Speaker", "audio-amp", | ||
53 | "Headphone", "ROUT1", | ||
54 | "Headphone", "LOUT1", | ||
55 | "LINPUT1", "Mic Jack", | ||
56 | "RINPUT1", "Mic Jack", | ||
57 | "Mic Jack", "Mic Bias"; | ||
58 | mux-int-port = <1>; | ||
59 | mux-ext-port = <3>; | ||
60 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt index e4acdd891e49..2f89db88fd57 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt | |||
@@ -1,33 +1,40 @@ | |||
1 | Freescale i.MX audio complex with SGTL5000 codec | 1 | Freescale i.MX audio complex with SGTL5000 codec |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "fsl,imx-audio-sgtl5000" | 4 | |
5 | - model : The user-visible name of this sound complex | 5 | - compatible : "fsl,imx-audio-sgtl5000" |
6 | - ssi-controller : The phandle of the i.MX SSI controller | 6 | |
7 | - audio-codec : The phandle of the SGTL5000 audio codec | 7 | - model : The user-visible name of this sound complex |
8 | - audio-routing : A list of the connections between audio components. | 8 | |
9 | Each entry is a pair of strings, the first being the connection's sink, | 9 | - ssi-controller : The phandle of the i.MX SSI controller |
10 | the second being the connection's source. Valid names could be power | 10 | |
11 | supplies, SGTL5000 pins, and the jacks on the board: | 11 | - audio-codec : The phandle of the SGTL5000 audio codec |
12 | 12 | ||
13 | Power supplies: | 13 | - audio-routing : A list of the connections between audio components. |
14 | * Mic Bias | 14 | Each entry is a pair of strings, the first being the |
15 | 15 | connection's sink, the second being the connection's | |
16 | SGTL5000 pins: | 16 | source. Valid names could be power supplies, SGTL5000 |
17 | * MIC_IN | 17 | pins, and the jacks on the board: |
18 | * LINE_IN | 18 | |
19 | * HP_OUT | 19 | Power supplies: |
20 | * LINE_OUT | 20 | * Mic Bias |
21 | 21 | ||
22 | Board connectors: | 22 | SGTL5000 pins: |
23 | * Mic Jack | 23 | * MIC_IN |
24 | * Line In Jack | 24 | * LINE_IN |
25 | * Headphone Jack | 25 | * HP_OUT |
26 | * Line Out Jack | 26 | * LINE_OUT |
27 | * Ext Spk | 27 | |
28 | 28 | Board connectors: | |
29 | - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) | 29 | * Mic Jack |
30 | - mux-ext-port : The external port of the i.MX audio muxer | 30 | * Line In Jack |
31 | * Headphone Jack | ||
32 | * Line Out Jack | ||
33 | * Ext Spk | ||
34 | |||
35 | - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) | ||
36 | |||
37 | - mux-ext-port : The external port of the i.MX audio muxer | ||
31 | 38 | ||
32 | Note: The AUDMUX port numbering should start at 1, which is consistent with | 39 | Note: The AUDMUX port numbering should start at 1, which is consistent with |
33 | hardware manual. | 40 | hardware manual. |
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt index 7d13479f9c3c..da84a442ccea 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt +++ b/Documentation/devicetree/bindings/sound/imx-audio-spdif.txt | |||
@@ -2,23 +2,25 @@ Freescale i.MX audio complex with S/PDIF transceiver | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | 4 | ||
5 | - compatible : "fsl,imx-audio-spdif" | 5 | - compatible : "fsl,imx-audio-spdif" |
6 | 6 | ||
7 | - model : The user-visible name of this sound complex | 7 | - model : The user-visible name of this sound complex |
8 | 8 | ||
9 | - spdif-controller : The phandle of the i.MX S/PDIF controller | 9 | - spdif-controller : The phandle of the i.MX S/PDIF controller |
10 | 10 | ||
11 | 11 | ||
12 | Optional properties: | 12 | Optional properties: |
13 | 13 | ||
14 | - spdif-out : This is a boolean property. If present, the transmitting | 14 | - spdif-out : This is a boolean property. If present, the |
15 | function of S/PDIF will be enabled, indicating there's a physical | 15 | transmitting function of S/PDIF will be enabled, |
16 | S/PDIF out connector/jack on the board or it's connecting to some | 16 | indicating there's a physical S/PDIF out connector |
17 | other IP block, such as an HDMI encoder/display-controller. | 17 | or jack on the board or it's connecting to some |
18 | other IP block, such as an HDMI encoder or | ||
19 | display-controller. | ||
18 | 20 | ||
19 | - spdif-in : This is a boolean property. If present, the receiving | 21 | - spdif-in : This is a boolean property. If present, the receiving |
20 | function of S/PDIF will be enabled, indicating there's a physical | 22 | function of S/PDIF will be enabled, indicating there |
21 | S/PDIF in connector/jack on the board. | 23 | is a physical S/PDIF in connector/jack on the board. |
22 | 24 | ||
23 | * Note: At least one of these two properties should be set in the DT binding. | 25 | * Note: At least one of these two properties should be set in the DT binding. |
24 | 26 | ||
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt index f49450a87890..acea71bee34f 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt | |||
@@ -1,25 +1,32 @@ | |||
1 | Freescale i.MX audio complex with WM8962 codec | 1 | Freescale i.MX audio complex with WM8962 codec |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "fsl,imx-audio-wm8962" | 4 | |
5 | - model : The user-visible name of this sound complex | 5 | - compatible : "fsl,imx-audio-wm8962" |
6 | - ssi-controller : The phandle of the i.MX SSI controller | 6 | |
7 | - audio-codec : The phandle of the WM8962 audio codec | 7 | - model : The user-visible name of this sound complex |
8 | - audio-routing : A list of the connections between audio components. | 8 | |
9 | Each entry is a pair of strings, the first being the connection's sink, | 9 | - ssi-controller : The phandle of the i.MX SSI controller |
10 | the second being the connection's source. Valid names could be power | 10 | |
11 | supplies, WM8962 pins, and the jacks on the board: | 11 | - audio-codec : The phandle of the WM8962 audio codec |
12 | 12 | ||
13 | Power supplies: | 13 | - audio-routing : A list of the connections between audio components. |
14 | * Mic Bias | 14 | Each entry is a pair of strings, the first being the |
15 | 15 | connection's sink, the second being the connection's | |
16 | Board connectors: | 16 | source. Valid names could be power supplies, WM8962 |
17 | * Mic Jack | 17 | pins, and the jacks on the board: |
18 | * Headphone Jack | 18 | |
19 | * Ext Spk | 19 | Power supplies: |
20 | 20 | * Mic Bias | |
21 | - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) | 21 | |
22 | - mux-ext-port : The external port of the i.MX audio muxer | 22 | Board connectors: |
23 | * Mic Jack | ||
24 | * Headphone Jack | ||
25 | * Ext Spk | ||
26 | |||
27 | - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) | ||
28 | |||
29 | - mux-ext-port : The external port of the i.MX audio muxer | ||
23 | 30 | ||
24 | Note: The AUDMUX port numbering should start at 1, which is consistent with | 31 | Note: The AUDMUX port numbering should start at 1, which is consistent with |
25 | hardware manual. | 32 | hardware manual. |
diff --git a/Documentation/devicetree/bindings/sound/imx-audmux.txt b/Documentation/devicetree/bindings/sound/imx-audmux.txt index f88a00e54c63..b30a737e209e 100644 --- a/Documentation/devicetree/bindings/sound/imx-audmux.txt +++ b/Documentation/devicetree/bindings/sound/imx-audmux.txt | |||
@@ -1,18 +1,24 @@ | |||
1 | Freescale Digital Audio Mux (AUDMUX) device | 1 | Freescale Digital Audio Mux (AUDMUX) device |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "fsl,imx21-audmux" for AUDMUX version firstly used on i.MX21, | 4 | |
5 | or "fsl,imx31-audmux" for the version firstly used on i.MX31. | 5 | - compatible : "fsl,imx21-audmux" for AUDMUX version firstly used |
6 | - reg : Should contain AUDMUX registers location and length | 6 | on i.MX21, or "fsl,imx31-audmux" for the version |
7 | firstly used on i.MX31. | ||
8 | |||
9 | - reg : Should contain AUDMUX registers location and length. | ||
7 | 10 | ||
8 | An initial configuration can be setup using child nodes. | 11 | An initial configuration can be setup using child nodes. |
9 | 12 | ||
10 | Required properties of optional child nodes: | 13 | Required properties of optional child nodes: |
11 | - fsl,audmux-port : Integer of the audmux port that is configured by this | 14 | |
12 | child node. | 15 | - fsl,audmux-port : Integer of the audmux port that is configured by this |
13 | - fsl,port-config : List of configuration options for the specific port. For | 16 | child node. |
14 | imx31-audmux and above, it is a list of tuples <ptcr pdcr>. For | 17 | |
15 | imx21-audmux it is a list of pcr values. | 18 | - fsl,port-config : List of configuration options for the specific port. |
19 | For imx31-audmux and above, it is a list of tuples | ||
20 | <ptcr pdcr>. For imx21-audmux it is a list of pcr | ||
21 | values. | ||
16 | 22 | ||
17 | Example: | 23 | Example: |
18 | 24 | ||
diff --git a/Documentation/devicetree/bindings/sound/max98090.txt b/Documentation/devicetree/bindings/sound/max98090.txt index c454e67f54bb..aa802a274520 100644 --- a/Documentation/devicetree/bindings/sound/max98090.txt +++ b/Documentation/devicetree/bindings/sound/max98090.txt | |||
@@ -16,6 +16,8 @@ Optional properties: | |||
16 | 16 | ||
17 | - clock-names: Should be "mclk" | 17 | - clock-names: Should be "mclk" |
18 | 18 | ||
19 | - maxim,dmic-freq: Frequency at which to clock DMIC | ||
20 | |||
19 | Pins on the device (for linking into audio routes): | 21 | Pins on the device (for linking into audio routes): |
20 | 22 | ||
21 | * MIC1 | 23 | * MIC1 |
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt index 9c7c55c71370..c949abc2992f 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt | |||
@@ -25,6 +25,7 @@ Required properties: | |||
25 | 25 | ||
26 | Optional properties: | 26 | Optional properties: |
27 | - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in | 27 | - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in |
28 | - nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in | ||
28 | 29 | ||
29 | Example: | 30 | Example: |
30 | 31 | ||
diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.txt b/Documentation/devicetree/bindings/sound/renesas,fsi.txt index c5be003f413e..0d0ab51105b0 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.txt +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.txt | |||
@@ -1,11 +1,16 @@ | |||
1 | Renesas FSI | 1 | Renesas FSI |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "renesas,sh_fsi2" or "renesas,sh_fsi" | 4 | - compatible : "renesas,fsi2-<soctype>", |
5 | "renesas,sh_fsi2" or "renesas,sh_fsi" as | ||
6 | fallback. | ||
7 | Examples with soctypes are: | ||
8 | - "renesas,fsi2-r8a7740" (R-Mobile A1) | ||
9 | - "renesas,fsi2-sh73a0" (SH-Mobile AG5) | ||
5 | - reg : Should contain the register physical address and length | 10 | - reg : Should contain the register physical address and length |
6 | - interrupts : Should contain FSI interrupt | 11 | - interrupts : Should contain FSI interrupt |
7 | 12 | ||
8 | - fsia,spdif-connection : FSI is connected by S/PDFI | 13 | - fsia,spdif-connection : FSI is connected by S/PDIF |
9 | - fsia,stream-mode-support : FSI supports 16bit stream mode. | 14 | - fsia,stream-mode-support : FSI supports 16bit stream mode. |
10 | - fsia,use-internal-clock : FSI uses internal clock when master mode. | 15 | - fsia,use-internal-clock : FSI uses internal clock when master mode. |
11 | 16 | ||
diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt index aa697abf337e..2dd690bc19cc 100644 --- a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt +++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt | |||
@@ -1,8 +1,12 @@ | |||
1 | Renesas R-Car sound | 1 | Renesas R-Car sound |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "renesas,rcar_sound-gen1" if generation1 | 4 | - compatible : "renesas,rcar_sound-<soctype>", fallbacks |
5 | "renesas,rcar_sound-gen1" if generation1, and | ||
5 | "renesas,rcar_sound-gen2" if generation2 | 6 | "renesas,rcar_sound-gen2" if generation2 |
7 | Examples with soctypes are: | ||
8 | - "renesas,rcar_sound-r8a7790" (R-Car H2) | ||
9 | - "renesas,rcar_sound-r8a7791" (R-Car M2-W) | ||
6 | - reg : Should contain the register physical address. | 10 | - reg : Should contain the register physical address. |
7 | required register is | 11 | required register is |
8 | SRU/ADG/SSI if generation1 | 12 | SRU/ADG/SSI if generation1 |
@@ -35,9 +39,9 @@ DAI subnode properties: | |||
35 | 39 | ||
36 | Example: | 40 | Example: |
37 | 41 | ||
38 | rcar_sound: rcar_sound@0xffd90000 { | 42 | rcar_sound: rcar_sound@ec500000 { |
39 | #sound-dai-cells = <1>; | 43 | #sound-dai-cells = <1>; |
40 | compatible = "renesas,rcar_sound-gen2"; | 44 | compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; |
41 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | 45 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
42 | <0 0xec5a0000 0 0x100>, /* ADG */ | 46 | <0 0xec5a0000 0 0x100>, /* ADG */ |
43 | <0 0xec540000 0 0x1000>, /* SSIU */ | 47 | <0 0xec540000 0 0x1000>, /* SSIU */ |
diff --git a/Documentation/devicetree/bindings/sound/rt5631.txt b/Documentation/devicetree/bindings/sound/rt5631.txt new file mode 100644 index 000000000000..92b986ca337b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt5631.txt | |||
@@ -0,0 +1,48 @@ | |||
1 | ALC5631/RT5631 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "realtek,alc5631" or "realtek,rt5631" | ||
8 | |||
9 | - reg : the I2C address of the device. | ||
10 | |||
11 | Pins on the device (for linking into audio routes): | ||
12 | |||
13 | * SPK_OUT_R_P | ||
14 | * SPK_OUT_R_N | ||
15 | * SPK_OUT_L_P | ||
16 | * SPK_OUT_L_N | ||
17 | * HP_OUT_L | ||
18 | * HP_OUT_R | ||
19 | * AUX_OUT2_LP | ||
20 | * AUX_OUT2_RN | ||
21 | * AUX_OUT1_LP | ||
22 | * AUX_OUT1_RN | ||
23 | * AUX_IN_L_JD | ||
24 | * AUX_IN_R_JD | ||
25 | * MONO_IN_P | ||
26 | * MONO_IN_N | ||
27 | * MIC1_P | ||
28 | * MIC1_N | ||
29 | * MIC2_P | ||
30 | * MIC2_N | ||
31 | * MONO_OUT_P | ||
32 | * MONO_OUT_N | ||
33 | * MICBIAS1 | ||
34 | * MICBIAS2 | ||
35 | |||
36 | Example: | ||
37 | |||
38 | alc5631: alc5631@1a { | ||
39 | compatible = "realtek,alc5631"; | ||
40 | reg = <0x1a>; | ||
41 | }; | ||
42 | |||
43 | or | ||
44 | |||
45 | rt5631: rt5631@1a { | ||
46 | compatible = "realtek,rt5631"; | ||
47 | reg = <0x1a>; | ||
48 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/rt5677.txt b/Documentation/devicetree/bindings/sound/rt5677.txt new file mode 100644 index 000000000000..740ff771aa8b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/rt5677.txt | |||
@@ -0,0 +1,76 @@ | |||
1 | RT5677 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "realtek,rt5677". | ||
8 | |||
9 | - reg : The I2C address of the device. | ||
10 | |||
11 | - interrupts : The CODEC's interrupt output. | ||
12 | |||
13 | - gpio-controller : Indicates this device is a GPIO controller. | ||
14 | |||
15 | - #gpio-cells : Should be two. The first cell is the pin number and the | ||
16 | second cell is used to specify optional parameters (currently unused). | ||
17 | |||
18 | Optional properties: | ||
19 | |||
20 | - realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin. | ||
21 | |||
22 | - realtek,in1-differential | ||
23 | - realtek,in2-differential | ||
24 | - realtek,lout1-differential | ||
25 | - realtek,lout2-differential | ||
26 | - realtek,lout3-differential | ||
27 | Boolean. Indicate MIC1/2 input and LOUT1/2/3 outputs are differential, | ||
28 | rather than single-ended. | ||
29 | |||
30 | - realtek,gpio-config | ||
31 | Array of six 8bit elements that configures GPIO. | ||
32 | 0 - floating (reset value) | ||
33 | 1 - pull down | ||
34 | 2 - pull up | ||
35 | |||
36 | - realtek,jd1-gpio | ||
37 | Configures GPIO Mic Jack detection 1. | ||
38 | Select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively. | ||
39 | |||
40 | - realtek,jd2-gpio | ||
41 | - realtek,jd3-gpio | ||
42 | Configures GPIO Mic Jack detection 2 and 3. | ||
43 | Select 0 ~ 3 as OFF, GPIO4, GPIO5 and GPIO6 respectively. | ||
44 | |||
45 | Pins on the device (for linking into audio routes): | ||
46 | |||
47 | * IN1P | ||
48 | * IN1N | ||
49 | * IN2P | ||
50 | * IN2N | ||
51 | * MICBIAS1 | ||
52 | * DMIC1 | ||
53 | * DMIC2 | ||
54 | * DMIC3 | ||
55 | * DMIC4 | ||
56 | * LOUT1 | ||
57 | * LOUT2 | ||
58 | * LOUT3 | ||
59 | |||
60 | Example: | ||
61 | |||
62 | rt5677 { | ||
63 | compatible = "realtek,rt5677"; | ||
64 | reg = <0x2c>; | ||
65 | interrupt-parent = <&gpio>; | ||
66 | interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; | ||
67 | |||
68 | gpio-controller; | ||
69 | #gpio-cells = <2>; | ||
70 | |||
71 | realtek,pow-ldo2-gpio = | ||
72 | <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; | ||
73 | realtek,in1-differential = "true"; | ||
74 | realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; /* pull up GPIO6 */ | ||
75 | realtek,jd2-gpio = <3>; /* Enables Jack detection for GPIO6 */ | ||
76 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt index 7386d444ada1..d188296bb6ec 100644 --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt | |||
@@ -6,10 +6,17 @@ Required SoC Specific Properties: | |||
6 | - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. | 6 | - samsung,s3c6410-i2s: for 8/16/24bit stereo I2S. |
7 | - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with | 7 | - samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with |
8 | secondary fifo, s/w reset control and internal mux for root clk src. | 8 | secondary fifo, s/w reset control and internal mux for root clk src. |
9 | - samsung,exynos5420-i2s: for 8/16/24bit multichannel(7.1) I2S with | 9 | - samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for |
10 | secondary fifo, s/w reset control, internal mux for root clk src and | 10 | playback, sterio channel capture, secondary fifo using internal |
11 | TDM support. TDM (Time division multiplexing) is to allow transfer of | 11 | or external dma, s/w reset control, internal mux for root clk src |
12 | multiple channel audio data on single data line. | 12 | and 7.1 channel TDM support for playback. TDM (Time division multiplexing) |
13 | is to allow transfer of multiple channel audio data on single data line. | ||
14 | - samsung,exynos7-i2s: with all the available features of exynos5 i2s, | ||
15 | exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo | ||
16 | with only external dma and more no.of root clk sampling frequencies. | ||
17 | - samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports | ||
18 | stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with | ||
19 | slightly modified bit offsets. | ||
13 | 20 | ||
14 | - reg: physical base address of the controller and length of memory mapped | 21 | - reg: physical base address of the controller and length of memory mapped |
15 | region. | 22 | region. |
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt index 955df60a118c..0e5e4eb3ef1b 100644 --- a/Documentation/devicetree/bindings/sound/sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt | |||
@@ -7,10 +7,33 @@ Required properties: | |||
7 | 7 | ||
8 | - clocks : the clock provider of SYS_MCLK | 8 | - clocks : the clock provider of SYS_MCLK |
9 | 9 | ||
10 | - micbias-resistor-k-ohms : the bias resistor to be used in kOmhs | ||
11 | The resistor can take values of 2k, 4k or 8k. | ||
12 | If set to 0 it will be off. | ||
13 | If this node is not mentioned or if the value is unknown, then | ||
14 | micbias resistor is set to 4K. | ||
15 | |||
16 | - micbias-voltage-m-volts : the bias voltage to be used in mVolts | ||
17 | The voltage can take values from 1.25V to 3V by 250mV steps | ||
18 | If this node is not mentionned or the value is unknown, then | ||
19 | the value is set to 1.25V. | ||
20 | |||
21 | - VDDA-supply : the regulator provider of VDDA | ||
22 | |||
23 | - VDDIO-supply: the regulator provider of VDDIO | ||
24 | |||
25 | Optional properties: | ||
26 | |||
27 | - VDDD-supply : the regulator provider of VDDD | ||
28 | |||
10 | Example: | 29 | Example: |
11 | 30 | ||
12 | codec: sgtl5000@0a { | 31 | codec: sgtl5000@0a { |
13 | compatible = "fsl,sgtl5000"; | 32 | compatible = "fsl,sgtl5000"; |
14 | reg = <0x0a>; | 33 | reg = <0x0a>; |
15 | clocks = <&clks 150>; | 34 | clocks = <&clks 150>; |
35 | micbias-resistor-k-ohms = <2>; | ||
36 | micbias-voltage-m-volts = <2250>; | ||
37 | VDDA-supply = <®_3p3v>; | ||
38 | VDDIO-supply = <®_3p3v>; | ||
16 | }; | 39 | }; |
diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt index c2e9841dfce4..c3cba600bf11 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.txt +++ b/Documentation/devicetree/bindings/sound/simple-card.txt | |||
@@ -17,6 +17,10 @@ Optional properties: | |||
17 | source. | 17 | source. |
18 | - simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec | 18 | - simple-audio-card,mclk-fs : Multiplication factor between stream rate and codec |
19 | mclk. | 19 | mclk. |
20 | - simple-audio-card,hp-det-gpio : Reference to GPIO that signals when | ||
21 | headphones are attached. | ||
22 | - simple-audio-card,mic-det-gpio : Reference to GPIO that signals when | ||
23 | a microphone is attached. | ||
20 | 24 | ||
21 | Optional subnodes: | 25 | Optional subnodes: |
22 | 26 | ||
diff --git a/Documentation/devicetree/bindings/sound/ssm4567.txt b/Documentation/devicetree/bindings/sound/ssm4567.txt new file mode 100644 index 000000000000..ec3d9e7004b5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ssm4567.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | Analog Devices SSM4567 audio amplifier | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | - compatible : Must be "adi,ssm4567" | ||
7 | - reg : the I2C address of the device. This will either be 0x34 (LR_SEL/ADDR connected to AGND), | ||
8 | 0x35 (LR_SEL/ADDR connected to IOVDD) or 0x36 (LR_SEL/ADDR open). | ||
9 | |||
10 | Example: | ||
11 | |||
12 | ssm4567: ssm4567@34 { | ||
13 | compatible = "adi,ssm4567"; | ||
14 | reg = <0x34>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/st,sta350.txt b/Documentation/devicetree/bindings/sound/st,sta350.txt index b7e71bf5caf4..307398ef2317 100644 --- a/Documentation/devicetree/bindings/sound/st,sta350.txt +++ b/Documentation/devicetree/bindings/sound/st,sta350.txt | |||
@@ -33,7 +33,7 @@ Optional properties: | |||
33 | 0: Channel 1 | 33 | 0: Channel 1 |
34 | 1: Channel 2 | 34 | 1: Channel 2 |
35 | 2: Channel 3 | 35 | 2: Channel 3 |
36 | If parameter is missing, channel 1 is choosen. | 36 | If parameter is missing, channel 1 is chosen. |
37 | This properties have to be specified as '/bits/ 8' values. | 37 | This properties have to be specified as '/bits/ 8' values. |
38 | 38 | ||
39 | - st,thermal-warning-recover: | 39 | - st,thermal-warning-recover: |
diff --git a/Documentation/devicetree/bindings/sound/ts3a227e.txt b/Documentation/devicetree/bindings/sound/ts3a227e.txt new file mode 100644 index 000000000000..e8bf23eb1803 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ts3a227e.txt | |||
@@ -0,0 +1,26 @@ | |||
1 | Texas Instruments TS3A227E | ||
2 | Autonomous Audio Accessory Detection and Configuration Switch | ||
3 | |||
4 | The TS3A227E detect headsets of 3-ring and 4-ring standards and | ||
5 | switches automatically to route the microphone correctly. It also | ||
6 | handles key press detection in accordance with the Android audio | ||
7 | headset specification v1.0. | ||
8 | |||
9 | Required properties: | ||
10 | |||
11 | - compatible: Should contain "ti,ts3a227e". | ||
12 | - reg: The i2c address. Should contain <0x3b>. | ||
13 | - interrupt-parent: The parent interrupt controller | ||
14 | - interrupts: Interrupt number for /INT pin from the 227e | ||
15 | |||
16 | |||
17 | Examples: | ||
18 | |||
19 | i2c { | ||
20 | ts3a227e@3b { | ||
21 | compatible = "ti,ts3a227e"; | ||
22 | reg = <0x3b>; | ||
23 | interrupt-parent = <&gpio>; | ||
24 | interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | ||
25 | }; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/sound/wm8960.txt b/Documentation/devicetree/bindings/sound/wm8960.txt new file mode 100644 index 000000000000..2deb8a3da9c5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/wm8960.txt | |||
@@ -0,0 +1,31 @@ | |||
1 | WM8960 audio CODEC | ||
2 | |||
3 | This device supports I2C only. | ||
4 | |||
5 | Required properties: | ||
6 | |||
7 | - compatible : "wlf,wm8960" | ||
8 | |||
9 | - reg : the I2C address of the device. | ||
10 | |||
11 | Optional properties: | ||
12 | - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of | ||
13 | R24 (Additional control 2) gets set, indicating that ADCLRC and DACLRC pins | ||
14 | will be disabled only when ADC (Left and Right) and DAC (Left and Right) | ||
15 | are disabled. | ||
16 | When wm8960 works on synchronize mode and DACLRC pin is used to supply | ||
17 | frame clock, it will no frame clock for captrue unless enable DAC to enable | ||
18 | DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue. | ||
19 | |||
20 | - wlf,capless: This is a boolean property. If present, OUT3 pin will be | ||
21 | enabled and disabled together with HP_L and HP_R pins in response to jack | ||
22 | detect events. | ||
23 | |||
24 | Example: | ||
25 | |||
26 | codec: wm8960@1a { | ||
27 | compatible = "wlf,wm8960"; | ||
28 | reg = <0x1a>; | ||
29 | |||
30 | wlf,shared-lrclk; | ||
31 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 4256a6df9b79..aad527b357a0 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt | |||
@@ -7,6 +7,9 @@ Required properties: | |||
7 | - interrupts : Should contain CSPI/eCSPI interrupt | 7 | - interrupts : Should contain CSPI/eCSPI interrupt |
8 | - fsl,spi-num-chipselects : Contains the number of the chipselect | 8 | - fsl,spi-num-chipselects : Contains the number of the chipselect |
9 | - cs-gpios : Specifies the gpio pins to be used for chipselects. | 9 | - cs-gpios : Specifies the gpio pins to be used for chipselects. |
10 | - dmas: DMA specifiers for tx and rx dma. See the DMA client binding, | ||
11 | Documentation/devicetree/bindings/dma/dma.txt | ||
12 | - dma-names: DMA request names should include "tx" and "rx" if present. | ||
10 | 13 | ||
11 | Example: | 14 | Example: |
12 | 15 | ||
@@ -19,4 +22,6 @@ ecspi@70010000 { | |||
19 | fsl,spi-num-chipselects = <2>; | 22 | fsl,spi-num-chipselects = <2>; |
20 | cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */ | 23 | cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */ |
21 | <&gpio3 25 0>; /* GPIO3_25 */ | 24 | <&gpio3 25 0>; /* GPIO3_25 */ |
25 | dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; | ||
26 | dma-names = "rx", "tx"; | ||
22 | }; | 27 | }; |
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index f24baf3b6cc1..d11c3721e7cd 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt | |||
@@ -6,8 +6,17 @@ Required properties: | |||
6 | "renesas,sh-mobile-msiof" for SH Mobile series. | 6 | "renesas,sh-mobile-msiof" for SH Mobile series. |
7 | Examples with soctypes are: | 7 | Examples with soctypes are: |
8 | "renesas,msiof-r8a7790" (R-Car H2) | 8 | "renesas,msiof-r8a7790" (R-Car H2) |
9 | "renesas,msiof-r8a7791" (R-Car M2) | 9 | "renesas,msiof-r8a7791" (R-Car M2-W) |
10 | - reg : Offset and length of the register set for the device | 10 | "renesas,msiof-r8a7792" (R-Car V2H) |
11 | "renesas,msiof-r8a7793" (R-Car M2-N) | ||
12 | "renesas,msiof-r8a7794" (R-Car E2) | ||
13 | - reg : A list of offsets and lengths of the register sets for | ||
14 | the device. | ||
15 | If only one register set is present, it is to be used | ||
16 | by both the CPU and the DMA engine. | ||
17 | If two register sets are present, the first is to be | ||
18 | used by the CPU, and the second is to be used by the | ||
19 | DMA engine. | ||
11 | - interrupt-parent : The phandle for the interrupt controller that | 20 | - interrupt-parent : The phandle for the interrupt controller that |
12 | services interrupts for this device | 21 | services interrupts for this device |
13 | - interrupts : Interrupt specifier | 22 | - interrupts : Interrupt specifier |
@@ -17,12 +26,16 @@ Required properties: | |||
17 | Optional properties: | 26 | Optional properties: |
18 | - clocks : Must contain a reference to the functional clock. | 27 | - clocks : Must contain a reference to the functional clock. |
19 | - num-cs : Total number of chip-selects (default is 1) | 28 | - num-cs : Total number of chip-selects (default is 1) |
29 | - dmas : Must contain a list of two references to DMA | ||
30 | specifiers, one for transmission, and one for | ||
31 | reception. | ||
32 | - dma-names : Must contain a list of two DMA names, "tx" and "rx". | ||
20 | 33 | ||
21 | Optional properties, deprecated for soctype-specific bindings: | 34 | Optional properties, deprecated for soctype-specific bindings: |
22 | - renesas,tx-fifo-size : Overrides the default tx fifo size given in words | 35 | - renesas,tx-fifo-size : Overrides the default tx fifo size given in words |
23 | (default is 64) | 36 | (default is 64) |
24 | - renesas,rx-fifo-size : Overrides the default rx fifo size given in words | 37 | - renesas,rx-fifo-size : Overrides the default rx fifo size given in words |
25 | (default is 64, or 256 on R-Car H2 and M2) | 38 | (default is 64, or 256 on R-Car Gen2) |
26 | 39 | ||
27 | Pinctrl properties might be needed, too. See | 40 | Pinctrl properties might be needed, too. See |
28 | Documentation/devicetree/bindings/pinctrl/renesas,*. | 41 | Documentation/devicetree/bindings/pinctrl/renesas,*. |
@@ -31,9 +44,11 @@ Example: | |||
31 | 44 | ||
32 | msiof0: spi@e6e20000 { | 45 | msiof0: spi@e6e20000 { |
33 | compatible = "renesas,msiof-r8a7791"; | 46 | compatible = "renesas,msiof-r8a7791"; |
34 | reg = <0 0xe6e20000 0 0x0064>; | 47 | reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; |
35 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; | 48 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
36 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; | 49 | clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; |
50 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; | ||
51 | dma-names = "tx", "rx"; | ||
37 | #address-cells = <1>; | 52 | #address-cells = <1>; |
38 | #size-cells = <0>; | 53 | #size-cells = <0>; |
39 | status = "disabled"; | 54 | status = "disabled"; |
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt index f80887bca0d6..12ecfe9e3599 100644 --- a/Documentation/devicetree/bindings/spi/spi-davinci.txt +++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt | |||
@@ -1,5 +1,10 @@ | |||
1 | Davinci SPI controller device bindings | 1 | Davinci SPI controller device bindings |
2 | 2 | ||
3 | Links on DM: | ||
4 | Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf | ||
5 | dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf | ||
6 | OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf | ||
7 | |||
3 | Required properties: | 8 | Required properties: |
4 | - #address-cells: number of cells required to define a chip select | 9 | - #address-cells: number of cells required to define a chip select |
5 | address on the SPI bus. Should be set to 1. | 10 | address on the SPI bus. Should be set to 1. |
@@ -24,6 +29,30 @@ Optional: | |||
24 | cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; | 29 | cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; |
25 | where first three are internal CS and last two are GPIO CS. | 30 | where first three are internal CS and last two are GPIO CS. |
26 | 31 | ||
32 | Optional properties for slave devices: | ||
33 | SPI slave nodes can contain the following properties. | ||
34 | Not all SPI Peripherals from Texas Instruments support this. | ||
35 | Please check SPI peripheral documentation for a device before using these. | ||
36 | |||
37 | - ti,spi-wdelay : delay between transmission of words | ||
38 | (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module | ||
39 | clock periods. | ||
40 | |||
41 | delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period | ||
42 | |||
43 | Below is timing diagram which shows functional meaning of | ||
44 | "ti,spi-wdelay" parameter. | ||
45 | |||
46 | +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ | ||
47 | SPI_CLK | | | | | | | | | | | | | | | | | ||
48 | +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +- | ||
49 | |||
50 | SPI_SOMI/SIMO+-----------------+ +----------- | ||
51 | +----------+ word1 +---------------------------+word2 | ||
52 | +-----------------+ +----------- | ||
53 | WDELAY | ||
54 | <--------------------------> | ||
55 | |||
27 | Example of a NOR flash slave device (n25q032) connected to DaVinci | 56 | Example of a NOR flash slave device (n25q032) connected to DaVinci |
28 | SPI controller device over the SPI bus. | 57 | SPI controller device over the SPI bus. |
29 | 58 | ||
@@ -43,6 +72,7 @@ spi0:spi@20BF0000 { | |||
43 | compatible = "st,m25p32"; | 72 | compatible = "st,m25p32"; |
44 | spi-max-frequency = <25000000>; | 73 | spi-max-frequency = <25000000>; |
45 | reg = <0>; | 74 | reg = <0>; |
75 | ti,spi-wdelay = <8>; | ||
46 | 76 | ||
47 | partition@0 { | 77 | partition@0 { |
48 | label = "u-boot-spl"; | 78 | label = "u-boot-spl"; |
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index 5376de40f10b..cbbe16ed3874 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | |||
@@ -10,7 +10,12 @@ Required properties: | |||
10 | - pinctrl-names: must contain a "default" entry. | 10 | - pinctrl-names: must contain a "default" entry. |
11 | - spi-num-chipselects : the number of the chipselect signals. | 11 | - spi-num-chipselects : the number of the chipselect signals. |
12 | - bus-num : the slave chip chipselect signal number. | 12 | - bus-num : the slave chip chipselect signal number. |
13 | - big-endian : if DSPI modudle is big endian, the bool will be set in node. | 13 | |
14 | Optional property: | ||
15 | - big-endian: If present the dspi device's registers are implemented | ||
16 | in big endian mode, otherwise in native mode(same with CPU), for more | ||
17 | detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. | ||
18 | |||
14 | Example: | 19 | Example: |
15 | 20 | ||
16 | dspi0@4002c000 { | 21 | dspi0@4002c000 { |
diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.txt b/Documentation/devicetree/bindings/spi/spi-gpio.txt index 8a824be15754..a95603bcf6ff 100644 --- a/Documentation/devicetree/bindings/spi/spi-gpio.txt +++ b/Documentation/devicetree/bindings/spi/spi-gpio.txt | |||
@@ -8,8 +8,10 @@ Required properties: | |||
8 | - gpio-sck: GPIO spec for the SCK line to use | 8 | - gpio-sck: GPIO spec for the SCK line to use |
9 | - gpio-miso: GPIO spec for the MISO line to use | 9 | - gpio-miso: GPIO spec for the MISO line to use |
10 | - gpio-mosi: GPIO spec for the MOSI line to use | 10 | - gpio-mosi: GPIO spec for the MOSI line to use |
11 | - cs-gpios: GPIOs to use for chipselect lines | 11 | - cs-gpios: GPIOs to use for chipselect lines. |
12 | - num-chipselects: number of chipselect lines | 12 | Not needed if num-chipselects = <0>. |
13 | - num-chipselects: Number of chipselect lines. Should be <0> if a single device | ||
14 | with no chip select is connected. | ||
13 | 15 | ||
14 | Example: | 16 | Example: |
15 | 17 | ||
diff --git a/Documentation/devicetree/bindings/spi/spi-img-spfi.txt b/Documentation/devicetree/bindings/spi/spi-img-spfi.txt new file mode 100644 index 000000000000..c7dd50fb8eb2 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-img-spfi.txt | |||
@@ -0,0 +1,37 @@ | |||
1 | IMG Synchronous Peripheral Flash Interface (SPFI) controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must be "img,spfi". | ||
5 | - reg: Must contain the base address and length of the SPFI registers. | ||
6 | - interrupts: Must contain the SPFI interrupt. | ||
7 | - clocks: Must contain an entry for each entry in clock-names. | ||
8 | See ../clock/clock-bindings.txt for details. | ||
9 | - clock-names: Must include the following entries: | ||
10 | - spfi: SPI operating clock | ||
11 | - sys: SPI system interface clock | ||
12 | - dmas: Must contain an entry for each entry in dma-names. | ||
13 | See ../dma/dma.txt for details. | ||
14 | - dma-names: Must include the following entries: | ||
15 | - rx | ||
16 | - tx | ||
17 | - #address-cells: Must be 1. | ||
18 | - #size-cells: Must be 0. | ||
19 | |||
20 | Optional properties: | ||
21 | - img,supports-quad-mode: Should be set if the interface supports quad mode | ||
22 | SPI transfers. | ||
23 | |||
24 | Example: | ||
25 | |||
26 | spi@18100f00 { | ||
27 | compatible = "img,spfi"; | ||
28 | reg = <0x18100f00 0x100>; | ||
29 | interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>; | ||
30 | clocks = <&spi_clk>, <&system_clk>; | ||
31 | clock-names = "spfi", "sys"; | ||
32 | dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>; | ||
33 | dma-names = "rx", "tx"; | ||
34 | |||
35 | #address-cells = <1>; | ||
36 | #size-cells = <0>; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt new file mode 100644 index 000000000000..bb52a86f3365 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-meson.txt | |||
@@ -0,0 +1,22 @@ | |||
1 | Amlogic Meson SPI controllers | ||
2 | |||
3 | * SPIFC (SPI Flash Controller) | ||
4 | |||
5 | The Meson SPIFC is a controller optimized for communication with SPI | ||
6 | NOR memories, without DMA support and a 64-byte unified transmit / | ||
7 | receive buffer. | ||
8 | |||
9 | Required properties: | ||
10 | - compatible: should be "amlogic,meson6-spifc" | ||
11 | - reg: physical base address and length of the controller registers | ||
12 | - clocks: phandle of the input clock for the baud rate generator | ||
13 | - #address-cells: should be 1 | ||
14 | - #size-cells: should be 0 | ||
15 | |||
16 | spi@c1108c80 { | ||
17 | compatible = "amlogic,meson6-spifc"; | ||
18 | reg = <0xc1108c80 0x80>; | ||
19 | clocks = <&clk81>; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <0>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt index a3ff50fc76fb..50c3a3de61c1 100644 --- a/Documentation/devicetree/bindings/spi/spi-orion.txt +++ b/Documentation/devicetree/bindings/spi/spi-orion.txt | |||
@@ -1,7 +1,7 @@ | |||
1 | Marvell Orion SPI device | 1 | Marvell Orion SPI device |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : should be "marvell,orion-spi". | 4 | - compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi". |
5 | - reg : offset and length of the register set for the device | 5 | - reg : offset and length of the register set for the device |
6 | - cell-index : Which of multiple SPI controllers is this. | 6 | - cell-index : Which of multiple SPI controllers is this. |
7 | Optional properties: | 7 | Optional properties: |
diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt index d57d82a74054..8f4169f63936 100644 --- a/Documentation/devicetree/bindings/spi/spi-rspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt | |||
@@ -11,7 +11,10 @@ Required properties: | |||
11 | - "renesas,rspi-sh7757" (SH) | 11 | - "renesas,rspi-sh7757" (SH) |
12 | - "renesas,rspi-r7s72100" (RZ/A1H) | 12 | - "renesas,rspi-r7s72100" (RZ/A1H) |
13 | - "renesas,qspi-r8a7790" (R-Car H2) | 13 | - "renesas,qspi-r8a7790" (R-Car H2) |
14 | - "renesas,qspi-r8a7791" (R-Car M2) | 14 | - "renesas,qspi-r8a7791" (R-Car M2-W) |
15 | - "renesas,qspi-r8a7792" (R-Car V2H) | ||
16 | - "renesas,qspi-r8a7793" (R-Car M2-N) | ||
17 | - "renesas,qspi-r8a7794" (R-Car E2) | ||
15 | - reg : Address start and address range size of the device | 18 | - reg : Address start and address range size of the device |
16 | - interrupts : A list of interrupt-specifiers, one for each entry in | 19 | - interrupts : A list of interrupt-specifiers, one for each entry in |
17 | interrupt-names. | 20 | interrupt-names. |
@@ -30,6 +33,9 @@ Required properties: | |||
30 | 33 | ||
31 | Optional properties: | 34 | Optional properties: |
32 | - clocks : Must contain a reference to the functional clock. | 35 | - clocks : Must contain a reference to the functional clock. |
36 | - dmas : Must contain a list of two references to DMA specifiers, | ||
37 | one for transmission, and one for reception. | ||
38 | - dma-names : Must contain a list of two DMA names, "tx" and "rx". | ||
33 | 39 | ||
34 | Pinctrl properties might be needed, too. See | 40 | Pinctrl properties might be needed, too. See |
35 | Documentation/devicetree/bindings/pinctrl/renesas,*. | 41 | Documentation/devicetree/bindings/pinctrl/renesas,*. |
@@ -58,4 +64,6 @@ Examples: | |||
58 | num-cs = <1>; | 64 | num-cs = <1>; |
59 | #address-cells = <1>; | 65 | #address-cells = <1>; |
60 | #size-cells = <0>; | 66 | #size-cells = <0>; |
67 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; | ||
68 | dma-names = "tx", "rx"; | ||
61 | }; | 69 | }; |
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt index 1e8a8578148f..6dbdeb3c361a 100644 --- a/Documentation/devicetree/bindings/spi/spi-samsung.txt +++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt | |||
@@ -9,7 +9,7 @@ Required SoC Specific Properties: | |||
9 | - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms | 9 | - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms |
10 | - samsung,s3c6410-spi: for s3c6410 platforms | 10 | - samsung,s3c6410-spi: for s3c6410 platforms |
11 | - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms | 11 | - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms |
12 | - samsung,exynos4210-spi: for exynos4 and exynos5 platforms | 12 | - samsung,exynos7-spi: for exynos7 platforms |
13 | 13 | ||
14 | - reg: physical base address of the controller and length of memory mapped | 14 | - reg: physical base address of the controller and length of memory mapped |
15 | region. | 15 | region. |
diff --git a/Documentation/devicetree/bindings/submitting-patches.txt b/Documentation/devicetree/bindings/submitting-patches.txt index 042a0273b8ba..b7ba01ad1426 100644 --- a/Documentation/devicetree/bindings/submitting-patches.txt +++ b/Documentation/devicetree/bindings/submitting-patches.txt | |||
@@ -12,6 +12,9 @@ I. For patch submitters | |||
12 | 12 | ||
13 | devicetree@vger.kernel.org | 13 | devicetree@vger.kernel.org |
14 | 14 | ||
15 | 3) The Documentation/ portion of the patch should come in the series before | ||
16 | the code implementing the binding. | ||
17 | |||
15 | II. For kernel maintainers | 18 | II. For kernel maintainers |
16 | 19 | ||
17 | 1) If you aren't comfortable reviewing a given binding, reply to it and ask | 20 | 1) If you aren't comfortable reviewing a given binding, reply to it and ask |
diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt index 4cf024929a3f..4698e0edc205 100644 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/armada-thermal.txt | |||
@@ -5,17 +5,9 @@ Required properties: | |||
5 | - compatible: Should be set to one of the following: | 5 | - compatible: Should be set to one of the following: |
6 | marvell,armada370-thermal | 6 | marvell,armada370-thermal |
7 | marvell,armada375-thermal | 7 | marvell,armada375-thermal |
8 | marvell,armada375-z1-thermal | ||
9 | marvell,armada380-thermal | 8 | marvell,armada380-thermal |
10 | marvell,armadaxp-thermal | 9 | marvell,armadaxp-thermal |
11 | 10 | ||
12 | Note: As the name suggests, "marvell,armada375-z1-thermal" | ||
13 | applies for the SoC Z1 stepping only. On such stepping | ||
14 | some quirks need to be done and the register offset differs | ||
15 | from the one in the A0 stepping. | ||
16 | The operating system may auto-detect the SoC stepping and | ||
17 | update the compatible and register offsets at runtime. | ||
18 | |||
19 | - reg: Device's register space. | 11 | - reg: Device's register space. |
20 | Two entries are expected, see the examples below. | 12 | Two entries are expected, see the examples below. |
21 | The first one is required for the sensor register; | 13 | The first one is required for the sensor register; |
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt index 1f0f67234a91..3c67bd50aa10 100644 --- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt | |||
@@ -1,7 +1,10 @@ | |||
1 | * Temperature Monitor (TEMPMON) on Freescale i.MX SoCs | 1 | * Temperature Monitor (TEMPMON) on Freescale i.MX SoCs |
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible : "fsl,imx6q-thermal" | 4 | - compatible : "fsl,imx6q-tempmon" for i.MX6Q, "fsl,imx6sx-tempmon" for i.MX6SX. |
5 | i.MX6SX has two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC, | ||
6 | when temperature is below than low threshold, IRQ_LOW will be triggered, when temperature | ||
7 | is higher than panic threshold, system will auto reboot by SRC module. | ||
5 | - fsl,tempmon : phandle pointer to system controller that contains TEMPMON | 8 | - fsl,tempmon : phandle pointer to system controller that contains TEMPMON |
6 | control registers, e.g. ANATOP on imx6q. | 9 | control registers, e.g. ANATOP on imx6q. |
7 | - fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON | 10 | - fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON |
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt index 0ef00be44b01..43404b197933 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt | |||
@@ -7,7 +7,10 @@ Required properties: | |||
7 | - "renesas,thermal-r8a73a4" (R-Mobile AP6) | 7 | - "renesas,thermal-r8a73a4" (R-Mobile AP6) |
8 | - "renesas,thermal-r8a7779" (R-Car H1) | 8 | - "renesas,thermal-r8a7779" (R-Car H1) |
9 | - "renesas,thermal-r8a7790" (R-Car H2) | 9 | - "renesas,thermal-r8a7790" (R-Car H2) |
10 | - "renesas,thermal-r8a7791" (R-Car M2) | 10 | - "renesas,thermal-r8a7791" (R-Car M2-W) |
11 | - "renesas,thermal-r8a7792" (R-Car V2H) | ||
12 | - "renesas,thermal-r8a7793" (R-Car M2-N) | ||
13 | - "renesas,thermal-r8a7794" (R-Car E2) | ||
11 | - reg : Address range of the thermal registers. | 14 | - reg : Address range of the thermal registers. |
12 | The 1st reg will be recognized as common register | 15 | The 1st reg will be recognized as common register |
13 | if it has "interrupts". | 16 | if it has "interrupts". |
diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt new file mode 100644 index 000000000000..ef802de4957a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | |||
@@ -0,0 +1,68 @@ | |||
1 | * Temperature Sensor ADC (TSADC) on rockchip SoCs | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : "rockchip,rk3288-tsadc" | ||
5 | - reg : physical base address of the controller and length of memory mapped | ||
6 | region. | ||
7 | - interrupts : The interrupt number to the cpu. The interrupt specifier format | ||
8 | depends on the interrupt controller. | ||
9 | - clocks : Must contain an entry for each entry in clock-names. | ||
10 | - clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for | ||
11 | the peripheral clock. | ||
12 | - resets : Must contain an entry for each entry in reset-names. | ||
13 | See ../reset/reset.txt for details. | ||
14 | - reset-names : Must include the name "tsadc-apb". | ||
15 | - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description. | ||
16 | - rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value. | ||
17 | - rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO. | ||
18 | - rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW | ||
19 | 1:HIGH. | ||
20 | |||
21 | Exiample: | ||
22 | tsadc: tsadc@ff280000 { | ||
23 | compatible = "rockchip,rk3288-tsadc"; | ||
24 | reg = <0xff280000 0x100>; | ||
25 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | ||
26 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; | ||
27 | clock-names = "tsadc", "apb_pclk"; | ||
28 | resets = <&cru SRST_TSADC>; | ||
29 | reset-names = "tsadc-apb"; | ||
30 | pinctrl-names = "default"; | ||
31 | pinctrl-0 = <&otp_out>; | ||
32 | #thermal-sensor-cells = <1>; | ||
33 | rockchip,hw-tshut-temp = <95000>; | ||
34 | rockchip,hw-tshut-mode = <0>; | ||
35 | rockchip,hw-tshut-polarity = <0>; | ||
36 | }; | ||
37 | |||
38 | Example: referring to thermal sensors: | ||
39 | thermal-zones { | ||
40 | cpu_thermal: cpu_thermal { | ||
41 | polling-delay-passive = <1000>; /* milliseconds */ | ||
42 | polling-delay = <5000>; /* milliseconds */ | ||
43 | |||
44 | /* sensor ID */ | ||
45 | thermal-sensors = <&tsadc 1>; | ||
46 | |||
47 | trips { | ||
48 | cpu_alert0: cpu_alert { | ||
49 | temperature = <70000>; /* millicelsius */ | ||
50 | hysteresis = <2000>; /* millicelsius */ | ||
51 | type = "passive"; | ||
52 | }; | ||
53 | cpu_crit: cpu_crit { | ||
54 | temperature = <90000>; /* millicelsius */ | ||
55 | hysteresis = <2000>; /* millicelsius */ | ||
56 | type = "critical"; | ||
57 | }; | ||
58 | }; | ||
59 | |||
60 | cooling-maps { | ||
61 | map0 { | ||
62 | trip = <&cpu_alert0>; | ||
63 | cooling-device = | ||
64 | <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | ||
65 | }; | ||
66 | }; | ||
67 | }; | ||
68 | }; | ||
diff --git a/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt new file mode 100644 index 000000000000..ecf3ed76cd46 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/tegra-soctherm.txt | |||
@@ -0,0 +1,53 @@ | |||
1 | Tegra124 SOCTHERM thermal management system | ||
2 | |||
3 | The SOCTHERM IP block contains thermal sensors, support for polled | ||
4 | or interrupt-based thermal monitoring, CPU and GPU throttling based | ||
5 | on temperature trip points, and handling external overcurrent | ||
6 | notifications. It is also used to manage emergency shutdown in an | ||
7 | overheating situation. | ||
8 | |||
9 | Required properties : | ||
10 | - compatible : "nvidia,tegra124-soctherm". | ||
11 | - reg : Should contain 1 entry: | ||
12 | - SOCTHERM register set | ||
13 | - interrupts : Defines the interrupt used by SOCTHERM | ||
14 | - clocks : Must contain an entry for each entry in clock-names. | ||
15 | See ../clocks/clock-bindings.txt for details. | ||
16 | - clock-names : Must include the following entries: | ||
17 | - tsensor | ||
18 | - soctherm | ||
19 | - resets : Must contain an entry for each entry in reset-names. | ||
20 | See ../reset/reset.txt for details. | ||
21 | - reset-names : Must include the following entries: | ||
22 | - soctherm | ||
23 | - #thermal-sensor-cells : Should be 1. See ./thermal.txt for a description | ||
24 | of this property. See <dt-bindings/thermal/tegra124-soctherm.h> for a | ||
25 | list of valid values when referring to thermal sensors. | ||
26 | |||
27 | |||
28 | Example : | ||
29 | |||
30 | soctherm@0,700e2000 { | ||
31 | compatible = "nvidia,tegra124-soctherm"; | ||
32 | reg = <0x0 0x700e2000 0x0 0x1000>; | ||
33 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | ||
34 | clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, | ||
35 | <&tegra_car TEGRA124_CLK_SOC_THERM>; | ||
36 | clock-names = "tsensor", "soctherm"; | ||
37 | resets = <&tegra_car 78>; | ||
38 | reset-names = "soctherm"; | ||
39 | |||
40 | #thermal-sensor-cells = <1>; | ||
41 | }; | ||
42 | |||
43 | Example: referring to thermal sensors : | ||
44 | |||
45 | thermal-zones { | ||
46 | cpu { | ||
47 | polling-delay-passive = <1000>; | ||
48 | polling-delay = <1000>; | ||
49 | |||
50 | thermal-sensors = | ||
51 | <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; | ||
52 | }; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt new file mode 100644 index 000000000000..a092053f7902 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt | |||
@@ -0,0 +1,15 @@ | |||
1 | Amlogic Meson6 SoCs Timer Controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "amlogic,meson6-timer" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | - interrupts : The interrupt of the first timer | ||
8 | |||
9 | Example: | ||
10 | |||
11 | timer@c1109940 { | ||
12 | compatible = "amlogic,meson6-timer"; | ||
13 | reg = <0xc1109940 0x14>; | ||
14 | interrupts = <0 10 1>; | ||
15 | }; | ||
diff --git a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt index f455182b1086..e9c78ce880e6 100644 --- a/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt +++ b/Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt | |||
@@ -2,8 +2,10 @@ Marvell Armada 370 and Armada XP Timers | |||
2 | --------------------------------------- | 2 | --------------------------------------- |
3 | 3 | ||
4 | Required properties: | 4 | Required properties: |
5 | - compatible: Should be either "marvell,armada-370-timer" or | 5 | - compatible: Should be one of the following |
6 | "marvell,armada-xp-timer" as appropriate. | 6 | "marvell,armada-370-timer", |
7 | "marvell,armada-375-timer", | ||
8 | "marvell,armada-xp-timer". | ||
7 | - interrupts: Should contain the list of Global Timer interrupts and | 9 | - interrupts: Should contain the list of Global Timer interrupts and |
8 | then local timer interrupts | 10 | then local timer interrupts |
9 | - reg: Should contain location and length for timers register. First | 11 | - reg: Should contain location and length for timers register. First |
@@ -13,7 +15,8 @@ Required properties: | |||
13 | Clocks required for compatible = "marvell,armada-370-timer": | 15 | Clocks required for compatible = "marvell,armada-370-timer": |
14 | - clocks : Must contain a single entry describing the clock input | 16 | - clocks : Must contain a single entry describing the clock input |
15 | 17 | ||
16 | Clocks required for compatible = "marvell,armada-xp-timer": | 18 | Clocks required for compatibles = "marvell,armada-xp-timer", |
19 | "marvell,armada-375-timer": | ||
17 | - clocks : Must contain an entry for each entry in clock-names. | 20 | - clocks : Must contain an entry for each entry in clock-names. |
18 | - clock-names : Must include the following entries: | 21 | - clock-names : Must include the following entries: |
19 | "nbclk" (L2/coherency fabric clock), | 22 | "nbclk" (L2/coherency fabric clock), |
diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index a17418b0ece3..1a05c1b243c1 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt | |||
@@ -11,15 +11,47 @@ datasheets. | |||
11 | 11 | ||
12 | Required Properties: | 12 | Required Properties: |
13 | 13 | ||
14 | - compatible: must contain one of the following. | 14 | - compatible: must contain one or more of the following: |
15 | - "renesas,cmt-32" for the 32-bit CMT | 15 | - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT |
16 | (CMT0) | ||
17 | - "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT | ||
18 | (CMT0) | ||
19 | - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT | ||
20 | (CMT0) | ||
21 | - "renesas,cmt-32" for all 32-bit CMT without fast clock support | ||
16 | (CMT0 on sh7372, sh73a0 and r8a7740) | 22 | (CMT0 on sh7372, sh73a0 and r8a7740) |
17 | - "renesas,cmt-32-fast" for the 32-bit CMT with fast clock support | 23 | This is a fallback for the above renesas,cmt-32-* entries. |
24 | |||
25 | - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast | ||
26 | clock support (CMT[234]) | ||
27 | - "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast | ||
28 | clock support (CMT[234]) | ||
29 | - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast | ||
30 | clock support (CMT[234]) | ||
31 | - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support | ||
18 | (CMT[234] on sh7372, sh73a0 and r8a7740) | 32 | (CMT[234] on sh7372, sh73a0 and r8a7740) |
19 | - "renesas,cmt-48" for the 48-bit CMT | 33 | This is a fallback for the above renesas,cmt-32-fast-* entries. |
34 | |||
35 | - "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT | ||
36 | (CMT1) | ||
37 | - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT | ||
38 | (CMT1) | ||
39 | - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT | ||
40 | (CMT1) | ||
41 | - "renesas,cmt-48" for all non-second generation 48-bit CMT | ||
20 | (CMT1 on sh7372, sh73a0 and r8a7740) | 42 | (CMT1 on sh7372, sh73a0 and r8a7740) |
21 | - "renesas,cmt-48-gen2" for the second generation 48-bit CMT | 43 | This is a fallback for the above renesas,cmt-48-* entries. |
44 | |||
45 | - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT | ||
46 | (CMT[01]) | ||
47 | - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT | ||
48 | (CMT[01]) | ||
49 | - "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT | ||
50 | (CMT[01]) | ||
51 | - "renesas,cmt-48-gen2" for all second generation 48-bit CMT | ||
22 | (CMT[01] on r8a73a4, r8a7790 and r8a7791) | 52 | (CMT[01] on r8a73a4, r8a7790 and r8a7791) |
53 | This is a fallback for the renesas,cmt-48-r8a73a4, | ||
54 | renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries. | ||
23 | 55 | ||
24 | - reg: base address and length of the registers block for the timer module. | 56 | - reg: base address and length of the registers block for the timer module. |
25 | - interrupts: interrupt-specifier for the timer, one per channel. | 57 | - interrupts: interrupt-specifier for the timer, one per channel. |
@@ -36,7 +68,7 @@ Example: R8A7790 (R-Car H2) CMT0 node | |||
36 | them channels 0 and 1 in the documentation. | 68 | them channels 0 and 1 in the documentation. |
37 | 69 | ||
38 | cmt0: timer@ffca0000 { | 70 | cmt0: timer@ffca0000 { |
39 | compatible = "renesas,cmt-48-gen2"; | 71 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
40 | reg = <0 0xffca0000 0 0x1004>; | 72 | reg = <0 0xffca0000 0 0x1004>; |
41 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | 73 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, |
42 | <0 142 IRQ_TYPE_LEVEL_HIGH>; | 74 | <0 142 IRQ_TYPE_LEVEL_HIGH>; |
diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt index 917453f826bc..ba0a34d97eb8 100644 --- a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt +++ b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt | |||
@@ -1,4 +1,4 @@ | |||
1 | * Renesas R-Car Multi-Function Timer Pulse Unit 2 (MTU2) | 1 | * Renesas Multi-Function Timer Pulse Unit 2 (MTU2) |
2 | 2 | ||
3 | The MTU2 is a multi-purpose, multi-channel timer/counter with configurable | 3 | The MTU2 is a multi-purpose, multi-channel timer/counter with configurable |
4 | clock inputs and programmable compare match. | 4 | clock inputs and programmable compare match. |
@@ -8,7 +8,10 @@ are independent. The MTU2 hardware supports five channels indexed from 0 to 4. | |||
8 | 8 | ||
9 | Required Properties: | 9 | Required Properties: |
10 | 10 | ||
11 | - compatible: must contain "renesas,mtu2" | 11 | - compatible: must be one or more of the following: |
12 | - "renesas,mtu2-r7s72100" for the r7s72100 MTU2 | ||
13 | - "renesas,mtu2" for any MTU2 | ||
14 | This is a fallback for the above renesas,mtu2-* entries | ||
12 | 15 | ||
13 | - reg: base address and length of the registers block for the timer module. | 16 | - reg: base address and length of the registers block for the timer module. |
14 | 17 | ||
@@ -26,7 +29,7 @@ Required Properties: | |||
26 | Example: R7S72100 (RZ/A1H) MTU2 node | 29 | Example: R7S72100 (RZ/A1H) MTU2 node |
27 | 30 | ||
28 | mtu2: timer@fcff0000 { | 31 | mtu2: timer@fcff0000 { |
29 | compatible = "renesas,mtu2"; | 32 | compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; |
30 | reg = <0xfcff0000 0x400>; | 33 | reg = <0xfcff0000 0x400>; |
31 | interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>, | 34 | interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>, |
32 | <0 146 IRQ_TYPE_LEVEL_HIGH>, | 35 | <0 146 IRQ_TYPE_LEVEL_HIGH>, |
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 425d0c5f4aee..cd5f20bf2582 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt | |||
@@ -1,4 +1,4 @@ | |||
1 | * Renesas R-Car Timer Unit (TMU) | 1 | * Renesas R-Mobile/R-Car Timer Unit (TMU) |
2 | 2 | ||
3 | The TMU is a 32-bit timer/counter with configurable clock inputs and | 3 | The TMU is a 32-bit timer/counter with configurable clock inputs and |
4 | programmable compare match. | 4 | programmable compare match. |
@@ -8,7 +8,12 @@ are independent. The TMU hardware supports up to three channels. | |||
8 | 8 | ||
9 | Required Properties: | 9 | Required Properties: |
10 | 10 | ||
11 | - compatible: must contain "renesas,tmu" | 11 | - compatible: must contain one or more of the following: |
12 | - "renesas,tmu-r8a7740" for the r8a7740 TMU | ||
13 | - "renesas,tmu-r8a7778" for the r8a7778 TMU | ||
14 | - "renesas,tmu-r8a7779" for the r8a7779 TMU | ||
15 | - "renesas,tmu" for any TMU. | ||
16 | This is a fallback for the above renesas,tmu-* entries | ||
12 | 17 | ||
13 | - reg: base address and length of the registers block for the timer module. | 18 | - reg: base address and length of the registers block for the timer module. |
14 | 19 | ||
@@ -27,7 +32,7 @@ Optional Properties: | |||
27 | Example: R8A7779 (R-Car H1) TMU0 node | 32 | Example: R8A7779 (R-Car H1) TMU0 node |
28 | 33 | ||
29 | tmu0: timer@ffd80000 { | 34 | tmu0: timer@ffd80000 { |
30 | compatible = "renesas,tmu"; | 35 | compatible = "renesas,tmu-r8a7779", "renesas,tmu"; |
31 | reg = <0xffd80000 0x30>; | 36 | reg = <0xffd80000 0x30>; |
32 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, | 37 | interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, |
33 | <0 33 IRQ_TYPE_LEVEL_HIGH>, | 38 | <0 33 IRQ_TYPE_LEVEL_HIGH>, |
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt index 20468b2a7516..53579197eca2 100644 --- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt +++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | |||
@@ -8,9 +8,50 @@ Required properties: | |||
8 | - interrupts : <interrupt mapping for UFS host controller IRQ> | 8 | - interrupts : <interrupt mapping for UFS host controller IRQ> |
9 | - reg : <registers mapping> | 9 | - reg : <registers mapping> |
10 | 10 | ||
11 | Optional properties: | ||
12 | - vdd-hba-supply : phandle to UFS host controller supply regulator node | ||
13 | - vcc-supply : phandle to VCC supply regulator node | ||
14 | - vccq-supply : phandle to VCCQ supply regulator node | ||
15 | - vccq2-supply : phandle to VCCQ2 supply regulator node | ||
16 | - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V | ||
17 | or 2.7-3.6V. This boolean property when set, specifies | ||
18 | to use low voltage range of 1.7-1.95V. Note for external | ||
19 | UFS cards this property is invalid and valid VCC range is | ||
20 | always 2.7-3.6V. | ||
21 | - vcc-max-microamp : specifies max. load that can be drawn from vcc supply | ||
22 | - vccq-max-microamp : specifies max. load that can be drawn from vccq supply | ||
23 | - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply | ||
24 | - <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator | ||
25 | |||
26 | - clocks : List of phandle and clock specifier pairs | ||
27 | - clock-names : List of clock input name strings sorted in the same | ||
28 | order as the clocks property. | ||
29 | - freq-table-hz : Array of <min max> operating frequencies stored in the same | ||
30 | order as the clocks property. If this property is not | ||
31 | defined or a value in the array is "0" then it is assumed | ||
32 | that the frequency is set by the parent clock or a | ||
33 | fixed rate clock source. | ||
34 | |||
35 | Note: If above properties are not defined it can be assumed that the supply | ||
36 | regulators or clocks are always on. | ||
37 | |||
11 | Example: | 38 | Example: |
12 | ufshc@0xfc598000 { | 39 | ufshc@0xfc598000 { |
13 | compatible = "jedec,ufs-1.1"; | 40 | compatible = "jedec,ufs-1.1"; |
14 | reg = <0xfc598000 0x800>; | 41 | reg = <0xfc598000 0x800>; |
15 | interrupts = <0 28 0>; | 42 | interrupts = <0 28 0>; |
43 | |||
44 | vdd-hba-supply = <&xxx_reg0>; | ||
45 | vdd-hba-fixed-regulator; | ||
46 | vcc-supply = <&xxx_reg1>; | ||
47 | vcc-supply-1p8; | ||
48 | vccq-supply = <&xxx_reg2>; | ||
49 | vccq2-supply = <&xxx_reg3>; | ||
50 | vcc-max-microamp = 500000; | ||
51 | vccq-max-microamp = 200000; | ||
52 | vccq2-max-microamp = 200000; | ||
53 | |||
54 | clocks = <&core 0>, <&ref 0>, <&iface 0>; | ||
55 | clock-names = "core_clk", "ref_clk", "iface_clk"; | ||
56 | freq-table-hz = <100000000 200000000>, <0 0>, <0 0>; | ||
16 | }; | 57 | }; |
diff --git a/Documentation/devicetree/bindings/unittest.txt b/Documentation/devicetree/bindings/unittest.txt new file mode 100644 index 000000000000..0f92a22fddfa --- /dev/null +++ b/Documentation/devicetree/bindings/unittest.txt | |||
@@ -0,0 +1,14 @@ | |||
1 | * OF selftest platform device | ||
2 | |||
3 | ** selftest | ||
4 | |||
5 | Required properties: | ||
6 | - compatible: must be "selftest" | ||
7 | |||
8 | All other properties are optional. | ||
9 | |||
10 | Example: | ||
11 | selftest { | ||
12 | compatible = "selftest"; | ||
13 | status = "okay"; | ||
14 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt index 1bae71e9ad47..38a548001e3a 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt | |||
@@ -19,6 +19,7 @@ Optional properties: | |||
19 | - disable-over-current: disable over current detect | 19 | - disable-over-current: disable over current detect |
20 | - external-vbus-divider: enables off-chip resistor divider for Vbus | 20 | - external-vbus-divider: enables off-chip resistor divider for Vbus |
21 | - maximum-speed: limit the maximum connection speed to "full-speed". | 21 | - maximum-speed: limit the maximum connection speed to "full-speed". |
22 | - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts | ||
22 | 23 | ||
23 | Examples: | 24 | Examples: |
24 | usb@02184000 { /* USB OTG */ | 25 | usb@02184000 { /* USB OTG */ |
@@ -30,4 +31,5 @@ usb@02184000 { /* USB OTG */ | |||
30 | disable-over-current; | 31 | disable-over-current; |
31 | external-vbus-divider; | 32 | external-vbus-divider; |
32 | maximum-speed = "full-speed"; | 33 | maximum-speed = "full-speed"; |
34 | tpl-support; | ||
33 | }; | 35 | }; |
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt new file mode 100644 index 000000000000..27f8b1e5ee46 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | * USB2 ChipIdea USB controller for ci13xxx | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should be "chipidea,usb2" | ||
5 | - reg: base address and length of the registers | ||
6 | - interrupts: interrupt for the USB controller | ||
7 | |||
8 | Optional properties: | ||
9 | - clocks: reference to the USB clock | ||
10 | - phys: reference to the USB PHY | ||
11 | - phy-names: should be "usb-phy" | ||
12 | - vbus-supply: reference to the VBUS regulator | ||
13 | |||
14 | Example: | ||
15 | |||
16 | usb@f7ed0000 { | ||
17 | compatible = "chipidea,usb2"; | ||
18 | reg = <0xf7ed0000 0x10000>; | ||
19 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | ||
20 | clocks = <&chip CLKID_USB0>; | ||
21 | phys = <&usb_phy0>; | ||
22 | phy-names = "usb-phy"; | ||
23 | vbus-supply = <®_usb0_vbus>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index 467ddd15d40c..482f815363ef 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt | |||
@@ -4,6 +4,9 @@ Platform DesignWare HS OTG USB 2.0 controller | |||
4 | Required properties: | 4 | Required properties: |
5 | - compatible : One of: | 5 | - compatible : One of: |
6 | - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. | 6 | - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC. |
7 | - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc; | ||
8 | - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc; | ||
9 | - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; | ||
7 | - snps,dwc2: A generic DWC2 USB controller with default parameters. | 10 | - snps,dwc2: A generic DWC2 USB controller with default parameters. |
8 | - reg : Should contain 1 register range (address and length) | 11 | - reg : Should contain 1 register range (address and length) |
9 | - interrupts : Should contain 1 interrupt | 12 | - interrupts : Should contain 1 interrupt |
@@ -15,6 +18,8 @@ Optional properties: | |||
15 | - phys: phy provider specifier | 18 | - phys: phy provider specifier |
16 | - phy-names: shall be "usb2-phy" | 19 | - phy-names: shall be "usb2-phy" |
17 | Refer to phy/phy-bindings.txt for generic phy consumer properties | 20 | Refer to phy/phy-bindings.txt for generic phy consumer properties |
21 | - dr_mode: shall be one of "host", "peripheral" and "otg" | ||
22 | Refer to usb/generic.txt | ||
18 | 23 | ||
19 | Example: | 24 | Example: |
20 | 25 | ||
diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt new file mode 100644 index 000000000000..f9d70252bbb2 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-st.txt | |||
@@ -0,0 +1,68 @@ | |||
1 | ST DWC3 glue logic | ||
2 | |||
3 | This file documents the parameters for the dwc3-st driver. | ||
4 | This driver controls the glue logic used to configure the dwc3 core on | ||
5 | STiH407 based platforms. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : must be "st,stih407-dwc3" | ||
9 | - reg : glue logic base address and USB syscfg ctrl register offset | ||
10 | - reg-names : should be "reg-glue" and "syscfg-reg" | ||
11 | - st,syscon : should be phandle to system configuration node which | ||
12 | encompasses the glue registers | ||
13 | - resets : list of phandle and reset specifier pairs. There should be two entries, one | ||
14 | for the powerdown and softreset lines of the usb3 IP | ||
15 | - reset-names : list of reset signal names. Names should be "powerdown" and "softreset" | ||
16 | See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt | ||
17 | See: Documentation/devicetree/bindings/reset/reset.txt | ||
18 | |||
19 | - #address-cells, #size-cells : should be '1' if the device has sub-nodes | ||
20 | with 'reg' property | ||
21 | |||
22 | - pinctl-names : A pinctrl state named "default" must be defined | ||
23 | See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt | ||
24 | |||
25 | - pinctrl-0 : Pin control group | ||
26 | See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt | ||
27 | |||
28 | - ranges : allows valid 1:1 translation between child's address space and | ||
29 | parent's address space | ||
30 | |||
31 | Sub-nodes: | ||
32 | The dwc3 core should be added as subnode to ST DWC3 glue as shown in the | ||
33 | example below. The DT binding details of dwc3 can be found in: | ||
34 | Documentation/devicetree/bindings/usb/dwc3.txt | ||
35 | |||
36 | NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value | ||
37 | is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host" | ||
38 | or "device". | ||
39 | |||
40 | [1] Documentation/devicetree/bindings/usb/generic.txt | ||
41 | |||
42 | Example: | ||
43 | |||
44 | st_dwc3: dwc3@8f94000 { | ||
45 | status = "disabled"; | ||
46 | compatible = "st,stih407-dwc3"; | ||
47 | reg = <0x08f94000 0x1000>, <0x110 0x4>; | ||
48 | reg-names = "reg-glue", "syscfg-reg"; | ||
49 | st,syscfg = <&syscfg_core>; | ||
50 | resets = <&powerdown STIH407_USB3_POWERDOWN>, | ||
51 | <&softreset STIH407_MIPHY2_SOFTRESET>; | ||
52 | reset-names = "powerdown", | ||
53 | "softreset"; | ||
54 | #address-cells = <1>; | ||
55 | #size-cells = <1>; | ||
56 | pinctrl-names = "default"; | ||
57 | pinctrl-0 = <&pinctrl_usb3>; | ||
58 | ranges; | ||
59 | |||
60 | dwc3: dwc3@9900000 { | ||
61 | compatible = "snps,dwc3"; | ||
62 | reg = <0x09900000 0x100000>; | ||
63 | interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; | ||
64 | dr_mode = "host"; | ||
65 | phys-names = "usb2-phy", "usb3-phy"; | ||
66 | phys = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>; | ||
67 | }; | ||
68 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 471366d6a129..cd7f0454e13a 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt | |||
@@ -14,6 +14,29 @@ Optional properties: | |||
14 | - phys: from the *Generic PHY* bindings | 14 | - phys: from the *Generic PHY* bindings |
15 | - phy-names: from the *Generic PHY* bindings | 15 | - phy-names: from the *Generic PHY* bindings |
16 | - tx-fifo-resize: determines if the FIFO *has* to be reallocated. | 16 | - tx-fifo-resize: determines if the FIFO *has* to be reallocated. |
17 | - snps,disable_scramble_quirk: true when SW should disable data scrambling. | ||
18 | Only really useful for FPGA builds. | ||
19 | - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled | ||
20 | - snps,lpm-nyet-threshold: LPM NYET threshold | ||
21 | - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk | ||
22 | - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk | ||
23 | - snps,req_p1p2p3_quirk: when set, the core will always request for | ||
24 | P1/P2/P3 transition sequence. | ||
25 | - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain | ||
26 | amount of 8B10B errors occur. | ||
27 | - snps,del_phy_power_chg_quirk: when set core will delay PHY power change | ||
28 | from P0 to P1/P2/P3. | ||
29 | - snps,lfps_filter_quirk: when set core will filter LFPS reception. | ||
30 | - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start | ||
31 | Polling LFPS after RX.Detect. | ||
32 | - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value. | ||
33 | - snps,tx_de_emphasis: the value driven to the PHY is controlled by the | ||
34 | LTSSM during USB3 Compliance mode. | ||
35 | - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy. | ||
36 | - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy. | ||
37 | - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal | ||
38 | utmi_l1_suspend_n, false when asserts utmi_sleep_n | ||
39 | - snps,hird-threshold: HIRD threshold | ||
17 | 40 | ||
18 | This is usually a subnode to DWC3 glue to which it is connected. | 41 | This is usually a subnode to DWC3 glue to which it is connected. |
19 | 42 | ||
diff --git a/Documentation/devicetree/bindings/usb/ehci-st.txt b/Documentation/devicetree/bindings/usb/ehci-st.txt new file mode 100644 index 000000000000..fb45fa5770bb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ehci-st.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | ST USB EHCI controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : must be "st,st-ehci-300x" | ||
5 | - reg : physical base addresses of the controller and length of memory mapped | ||
6 | region | ||
7 | - interrupts : one EHCI interrupt should be described here | ||
8 | - pinctrl-names : a pinctrl state named "default" must be defined | ||
9 | - pinctrl-0 : phandle referencing pin configuration of the USB controller | ||
10 | See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt | ||
11 | - clocks : phandle list of usb clocks | ||
12 | - clock-names : should be "ic" for interconnect clock and "clk48" | ||
13 | See: Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
14 | |||
15 | - phys : phandle for the PHY device | ||
16 | - phy-names : should be "usb" | ||
17 | - resets : phandle + reset specifier pairs to the powerdown and softreset lines | ||
18 | of the USB IP | ||
19 | - reset-names : should be "power" and "softreset" | ||
20 | See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt | ||
21 | See: Documentation/devicetree/bindings/reset/reset.txt | ||
22 | |||
23 | Example: | ||
24 | |||
25 | ehci1: usb@0xfe203e00 { | ||
26 | compatible = "st,st-ehci-300x"; | ||
27 | reg = <0xfe203e00 0x100>; | ||
28 | interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>; | ||
29 | pinctrl-names = "default"; | ||
30 | pinctrl-0 = <&pinctrl_usb1>; | ||
31 | clocks = <&clk_s_a1_ls 0>; | ||
32 | phys = <&usb2_phy>; | ||
33 | phy-names = "usb"; | ||
34 | status = "okay"; | ||
35 | |||
36 | resets = <&powerdown STIH416_USB1_POWERDOWN>, | ||
37 | <&softreset STIH416_USB1_SOFTRESET>; | ||
38 | reset-names = "power", "softreset"; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index a3b5990d0f2c..9b4dbe3b2acc 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt | |||
@@ -82,8 +82,10 @@ Example: | |||
82 | 82 | ||
83 | DWC3 | 83 | DWC3 |
84 | Required properties: | 84 | Required properties: |
85 | - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3 | 85 | - compatible: should be one of the following - |
86 | controller. | 86 | "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on |
87 | Exynos5250/5420. | ||
88 | "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. | ||
87 | - #address-cells, #size-cells : should be '1' if the device has sub-nodes | 89 | - #address-cells, #size-cells : should be '1' if the device has sub-nodes |
88 | with 'reg' property. | 90 | with 'reg' property. |
89 | - ranges: allows valid 1:1 translation between child's address space and | 91 | - ranges: allows valid 1:1 translation between child's address space and |
diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt index 96681c93b86d..379b84a567cc 100644 --- a/Documentation/devicetree/bindings/usb/mxs-phy.txt +++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt | |||
@@ -5,6 +5,7 @@ Required properties: | |||
5 | * "fsl,imx23-usbphy" for imx23 and imx28 | 5 | * "fsl,imx23-usbphy" for imx23 and imx28 |
6 | * "fsl,imx6q-usbphy" for imx6dq and imx6dl | 6 | * "fsl,imx6q-usbphy" for imx6dq and imx6dl |
7 | * "fsl,imx6sl-usbphy" for imx6sl | 7 | * "fsl,imx6sl-usbphy" for imx6sl |
8 | * "fsl,vf610-usbphy" for Vybrid vf610 | ||
8 | * "fsl,imx6sx-usbphy" for imx6sx | 9 | * "fsl,imx6sx-usbphy" for imx6sx |
9 | "fsl,imx23-usbphy" is still a fallback for other strings | 10 | "fsl,imx23-usbphy" is still a fallback for other strings |
10 | - reg: Should contain registers location and length | 11 | - reg: Should contain registers location and length |
diff --git a/Documentation/devicetree/bindings/usb/ohci-st.txt b/Documentation/devicetree/bindings/usb/ohci-st.txt new file mode 100644 index 000000000000..6d8393748da2 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ohci-st.txt | |||
@@ -0,0 +1,37 @@ | |||
1 | ST USB OHCI controller | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : must be "st,st-ohci-300x" | ||
6 | - reg : physical base addresses of the controller and length of memory mapped | ||
7 | region | ||
8 | - interrupts : one OHCI controller interrupt should be described here | ||
9 | - clocks : phandle list of usb clocks | ||
10 | - clock-names : should be "ic" for interconnect clock and "clk48" | ||
11 | See: Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
12 | |||
13 | - phys : phandle for the PHY device | ||
14 | - phy-names : should be "usb" | ||
15 | |||
16 | - resets : phandle to the powerdown and reset controller for the USB IP | ||
17 | - reset-names : should be "power" and "softreset". | ||
18 | See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt | ||
19 | See: Documentation/devicetree/bindings/reset/reset.txt | ||
20 | |||
21 | Example: | ||
22 | |||
23 | ohci0: usb@0xfe1ffc00 { | ||
24 | compatible = "st,st-ohci-300x"; | ||
25 | reg = <0xfe1ffc00 0x100>; | ||
26 | interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; | ||
27 | clocks = <&clk_s_a1_ls 0>, | ||
28 | <&clockgen_b0 0>; | ||
29 | clock-names = "ic", "clk48"; | ||
30 | phys = <&usb2_phy>; | ||
31 | phy-names = "usb"; | ||
32 | status = "okay"; | ||
33 | |||
34 | resets = <&powerdown STIH416_USB0_POWERDOWN>, | ||
35 | <&softreset STIH416_USB0_SOFTRESET>; | ||
36 | reset-names = "power", "softreset"; | ||
37 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/pxa-usb.txt b/Documentation/devicetree/bindings/usb/pxa-usb.txt index 79729a948d5a..9c331799b87c 100644 --- a/Documentation/devicetree/bindings/usb/pxa-usb.txt +++ b/Documentation/devicetree/bindings/usb/pxa-usb.txt | |||
@@ -29,3 +29,25 @@ Example: | |||
29 | marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ | 29 | marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ |
30 | }; | 30 | }; |
31 | 31 | ||
32 | UDC | ||
33 | |||
34 | Required properties: | ||
35 | - compatible: Should be "marvell,pxa270-udc" for USB controllers | ||
36 | used in device mode. | ||
37 | - reg: usb device MMIO address space | ||
38 | - interrupts: single interrupt generated by the UDC IP | ||
39 | - clocks: input clock of the UDC IP (see clock-bindings.txt) | ||
40 | |||
41 | Optional properties: | ||
42 | - gpios: | ||
43 | - gpio activated to control the USB D+ pullup (see gpio.txt) | ||
44 | |||
45 | Example: | ||
46 | |||
47 | pxa27x_udc: udc@40600000 { | ||
48 | compatible = "marvell,pxa270-udc"; | ||
49 | reg = <0x40600000 0x10000>; | ||
50 | interrupts = <11>; | ||
51 | clocks = <&pxa2xx_clks 11>; | ||
52 | gpios = <&gpio 22 GPIO_ACTIVE_LOW>; | ||
53 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt new file mode 100644 index 000000000000..ca164e71dd50 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt | |||
@@ -0,0 +1,66 @@ | |||
1 | Qualcomm SuperSpeed DWC3 USB SoC controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: should contain "qcom,dwc3" | ||
5 | - clocks: A list of phandle + clock-specifier pairs for the | ||
6 | clocks listed in clock-names | ||
7 | - clock-names: Should contain the following: | ||
8 | "core" Master/Core clock, have to be >= 125 MHz for SS | ||
9 | operation and >= 60MHz for HS operation | ||
10 | |||
11 | Optional clocks: | ||
12 | "iface" System bus AXI clock. Not present on all platforms | ||
13 | "sleep" Sleep clock, used when USB3 core goes into low | ||
14 | power mode (U3). | ||
15 | |||
16 | Required child node: | ||
17 | A child node must exist to represent the core DWC3 IP block. The name of | ||
18 | the node is not important. The content of the node is defined in dwc3.txt. | ||
19 | |||
20 | Phy documentation is provided in the following places: | ||
21 | Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt | ||
22 | |||
23 | Example device nodes: | ||
24 | |||
25 | hs_phy: phy@100f8800 { | ||
26 | compatible = "qcom,dwc3-hs-usb-phy"; | ||
27 | reg = <0x100f8800 0x30>; | ||
28 | clocks = <&gcc USB30_0_UTMI_CLK>; | ||
29 | clock-names = "ref"; | ||
30 | #phy-cells = <0>; | ||
31 | |||
32 | status = "ok"; | ||
33 | }; | ||
34 | |||
35 | ss_phy: phy@100f8830 { | ||
36 | compatible = "qcom,dwc3-ss-usb-phy"; | ||
37 | reg = <0x100f8830 0x30>; | ||
38 | clocks = <&gcc USB30_0_MASTER_CLK>; | ||
39 | clock-names = "ref"; | ||
40 | #phy-cells = <0>; | ||
41 | |||
42 | status = "ok"; | ||
43 | }; | ||
44 | |||
45 | usb3_0: usb30@0 { | ||
46 | compatible = "qcom,dwc3"; | ||
47 | #address-cells = <1>; | ||
48 | #size-cells = <1>; | ||
49 | clocks = <&gcc USB30_0_MASTER_CLK>; | ||
50 | clock-names = "core"; | ||
51 | |||
52 | ranges; | ||
53 | |||
54 | status = "ok"; | ||
55 | |||
56 | dwc3@10000000 { | ||
57 | compatible = "snps,dwc3"; | ||
58 | reg = <0x10000000 0xcd00>; | ||
59 | interrupts = <0 205 0x4>; | ||
60 | phys = <&hs_phy>, <&ss_phy>; | ||
61 | phy-names = "usb2-phy", "usb3-phy"; | ||
62 | tx-fifo-resize; | ||
63 | dr_mode = "host"; | ||
64 | }; | ||
65 | }; | ||
66 | |||
diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt new file mode 100644 index 000000000000..b08c903f8668 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | Renesas Electronics USBHS driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Must contain one of the following: | ||
5 | - "renesas,usbhs-r8a7790" | ||
6 | - "renesas,usbhs-r8a7791" | ||
7 | - reg: Base address and length of the register for the USBHS | ||
8 | - interrupts: Interrupt specifier for the USBHS | ||
9 | - clocks: A list of phandle + clock specifier pairs | ||
10 | |||
11 | Optional properties: | ||
12 | - renesas,buswait: Integer to use BUSWAIT register | ||
13 | - renesas,enable-gpio: A gpio specifier to check GPIO determining if USB | ||
14 | function should be enabled | ||
15 | - phys: phandle + phy specifier pair | ||
16 | - phy-names: must be "usb" | ||
17 | |||
18 | Example: | ||
19 | usbhs: usb@e6590000 { | ||
20 | compatible = "renesas,usbhs-r8a7790"; | ||
21 | reg = <0 0xe6590000 0 0x100>; | ||
22 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | ||
23 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/usb/udc-xilinx.txt b/Documentation/devicetree/bindings/usb/udc-xilinx.txt new file mode 100644 index 000000000000..47b4e397a08d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/udc-xilinx.txt | |||
@@ -0,0 +1,18 @@ | |||
1 | Xilinx USB2 device controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : Should be "xlnx,usb2-device-4.00.a" | ||
5 | - reg : Physical base address and size of the USB2 | ||
6 | device registers map. | ||
7 | - interrupts : Should contain single irq line of USB2 device | ||
8 | controller | ||
9 | - xlnx,has-builtin-dma : if DMA is included | ||
10 | |||
11 | Example: | ||
12 | axi-usb2-device@42e00000 { | ||
13 | compatible = "xlnx,usb2-device-4.00.a"; | ||
14 | interrupts = <0x0 0x39 0x1>; | ||
15 | reg = <0x42e00000 0x10000>; | ||
16 | xlnx,has-builtin-dma; | ||
17 | }; | ||
18 | |||
diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt index b968a1aea995..19233b7365e1 100644 --- a/Documentation/devicetree/bindings/usb/usb-ohci.txt +++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt | |||
@@ -9,6 +9,8 @@ Optional properties: | |||
9 | - big-endian-regs : boolean, set this for hcds with big-endian registers | 9 | - big-endian-regs : boolean, set this for hcds with big-endian registers |
10 | - big-endian-desc : boolean, set this for hcds with big-endian descriptors | 10 | - big-endian-desc : boolean, set this for hcds with big-endian descriptors |
11 | - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc | 11 | - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc |
12 | - no-big-frame-no : boolean, set if frame_no lives in bits [15:0] of HCCA | ||
13 | - num-ports : u32, to override the detected port count | ||
12 | - clocks : a list of phandle + clock specifier pairs | 14 | - clocks : a list of phandle + clock specifier pairs |
13 | - phys : phandle + phy specifier pair | 15 | - phys : phandle + phy specifier pair |
14 | - phy-names : "usb" | 16 | - phy-names : "usb" |
diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt index 221ac0dbc678..52493b1480e2 100644 --- a/Documentation/devicetree/bindings/usb/usb3503.txt +++ b/Documentation/devicetree/bindings/usb/usb3503.txt | |||
@@ -8,8 +8,8 @@ Optional properties: | |||
8 | if I2C is used. | 8 | if I2C is used. |
9 | - connect-gpios: Should specify GPIO for connect. | 9 | - connect-gpios: Should specify GPIO for connect. |
10 | - disabled-ports: Should specify the ports unused. | 10 | - disabled-ports: Should specify the ports unused. |
11 | '1' or '2' or '3' are availe for this property to describe the port | 11 | '1' or '2' or '3' are available for this property to describe the port |
12 | number. 1~3 property values are possible to be desribed. | 12 | number. 1~3 property values are possible to be described. |
13 | Do not describe this property if all ports have to be enabled. | 13 | Do not describe this property if all ports have to be enabled. |
14 | - intn-gpios: Should specify GPIO for interrupt. | 14 | - intn-gpios: Should specify GPIO for interrupt. |
15 | - reset-gpios: Should specify GPIO for reset. | 15 | - reset-gpios: Should specify GPIO for reset. |
diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt index 97ce94e1a6cc..c101a4b17131 100644 --- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt | |||
@@ -4,6 +4,7 @@ Required properties: | |||
4 | - #index-cells: Cells used to descibe usb controller index. Should be <1> | 4 | - #index-cells: Cells used to descibe usb controller index. Should be <1> |
5 | - compatible: Should be one of below: | 5 | - compatible: Should be one of below: |
6 | "fsl,imx6q-usbmisc" for imx6q | 6 | "fsl,imx6q-usbmisc" for imx6q |
7 | "fsl,vf610-usbmisc" for Vybrid vf610 | ||
7 | - reg: Should contain registers location and length | 8 | - reg: Should contain registers location and length |
8 | 9 | ||
9 | Examples: | 10 | Examples: |
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index e6469ec7a90e..b1df0ad1306c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt | |||
@@ -14,6 +14,7 @@ allwinner Allwinner Technology Co., Ltd. | |||
14 | altr Altera Corp. | 14 | altr Altera Corp. |
15 | amcc Applied Micro Circuits Corporation (APM, formally AMCC) | 15 | amcc Applied Micro Circuits Corporation (APM, formally AMCC) |
16 | amd Advanced Micro Devices (AMD), Inc. | 16 | amd Advanced Micro Devices (AMD), Inc. |
17 | amlogic Amlogic, Inc. | ||
17 | ams AMS AG | 18 | ams AMS AG |
18 | amstaos AMS-Taos Inc. | 19 | amstaos AMS-Taos Inc. |
19 | apm Applied Micro Circuits Corporation (APM) | 20 | apm Applied Micro Circuits Corporation (APM) |
@@ -29,36 +30,47 @@ calxeda Calxeda | |||
29 | capella Capella Microsystems, Inc | 30 | capella Capella Microsystems, Inc |
30 | cavium Cavium, Inc. | 31 | cavium Cavium, Inc. |
31 | cdns Cadence Design Systems Inc. | 32 | cdns Cadence Design Systems Inc. |
33 | chipidea Chipidea, Inc | ||
32 | chrp Common Hardware Reference Platform | 34 | chrp Common Hardware Reference Platform |
33 | chunghwa Chunghwa Picture Tubes Ltd. | 35 | chunghwa Chunghwa Picture Tubes Ltd. |
34 | cirrus Cirrus Logic, Inc. | 36 | cirrus Cirrus Logic, Inc. |
37 | cnm Chips&Media, Inc. | ||
35 | cortina Cortina Systems, Inc. | 38 | cortina Cortina Systems, Inc. |
36 | crystalfontz Crystalfontz America, Inc. | 39 | crystalfontz Crystalfontz America, Inc. |
37 | dallas Maxim Integrated Products (formerly Dallas Semiconductor) | 40 | dallas Maxim Integrated Products (formerly Dallas Semiconductor) |
38 | davicom DAVICOM Semiconductor, Inc. | 41 | davicom DAVICOM Semiconductor, Inc. |
39 | denx Denx Software Engineering | 42 | denx Denx Software Engineering |
40 | digi Digi International Inc. | 43 | digi Digi International Inc. |
44 | digilent Diglent, Inc. | ||
45 | dlg Dialog Semiconductor | ||
41 | dlink D-Link Corporation | 46 | dlink D-Link Corporation |
42 | dmo Data Modul AG | 47 | dmo Data Modul AG |
43 | ebv EBV Elektronik | 48 | ebv EBV Elektronik |
44 | edt Emerging Display Technologies | 49 | edt Emerging Display Technologies |
45 | elan Elan Microelectronic Corp. | 50 | elan Elan Microelectronic Corp. |
46 | emmicro EM Microelectronic | 51 | emmicro EM Microelectronic |
52 | energymicro Silicon Laboratories (formerly Energy Micro AS) | ||
47 | epcos EPCOS AG | 53 | epcos EPCOS AG |
48 | epfl Ecole Polytechnique Fédérale de Lausanne | 54 | epfl Ecole Polytechnique Fédérale de Lausanne |
49 | epson Seiko Epson Corp. | 55 | epson Seiko Epson Corp. |
50 | est ESTeem Wireless Modems | 56 | est ESTeem Wireless Modems |
51 | eukrea Eukréa Electromatique | 57 | eukrea Eukréa Electromatique |
58 | everest Everest Semiconductor Co. Ltd. | ||
52 | excito Excito | 59 | excito Excito |
60 | fcs Fairchild Semiconductor | ||
53 | fsl Freescale Semiconductor | 61 | fsl Freescale Semiconductor |
54 | GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. | 62 | GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. |
55 | gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. | 63 | gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. |
64 | geniatech Geniatech, Inc. | ||
56 | globalscale Globalscale Technologies, Inc. | 65 | globalscale Globalscale Technologies, Inc. |
57 | gmt Global Mixed-mode Technology, Inc. | 66 | gmt Global Mixed-mode Technology, Inc. |
58 | google Google, Inc. | 67 | google Google, Inc. |
59 | gumstix Gumstix, Inc. | 68 | gumstix Gumstix, Inc. |
69 | gw Gateworks Corporation | ||
70 | hannstar HannStar Display Corporation | ||
60 | haoyu Haoyu Microelectronic Co. Ltd. | 71 | haoyu Haoyu Microelectronic Co. Ltd. |
61 | hisilicon Hisilicon Limited. | 72 | hisilicon Hisilicon Limited. |
73 | hit Hitachi Ltd. | ||
62 | honeywell Honeywell | 74 | honeywell Honeywell |
63 | hp Hewlett Packard | 75 | hp Hewlett Packard |
64 | i2se I2SE GmbH | 76 | i2se I2SE GmbH |
@@ -66,9 +78,11 @@ ibm International Business Machines (IBM) | |||
66 | idt Integrated Device Technologies, Inc. | 78 | idt Integrated Device Technologies, Inc. |
67 | iom Iomega Corporation | 79 | iom Iomega Corporation |
68 | img Imagination Technologies Ltd. | 80 | img Imagination Technologies Ltd. |
81 | innolux Innolux Corporation | ||
69 | intel Intel Corporation | 82 | intel Intel Corporation |
70 | intercontrol Inter Control Group | 83 | intercontrol Inter Control Group |
71 | isee ISEE 2007 S.L. | 84 | isee ISEE 2007 S.L. |
85 | isil Intersil (deprecated, use isl) | ||
72 | isl Intersil | 86 | isl Intersil |
73 | karo Ka-Ro electronics GmbH | 87 | karo Ka-Ro electronics GmbH |
74 | keymile Keymile GmbH | 88 | keymile Keymile GmbH |
@@ -82,11 +96,15 @@ lltc Linear Technology Corporation | |||
82 | marvell Marvell Technology Group Ltd. | 96 | marvell Marvell Technology Group Ltd. |
83 | maxim Maxim Integrated Products | 97 | maxim Maxim Integrated Products |
84 | mediatek MediaTek Inc. | 98 | mediatek MediaTek Inc. |
99 | merrii Merrii Technology Co., Ltd. | ||
85 | micrel Micrel Inc. | 100 | micrel Micrel Inc. |
86 | microchip Microchip Technology Inc. | 101 | microchip Microchip Technology Inc. |
102 | micron Micron Technology Inc. | ||
103 | mitsubishi Mitsubishi Electric Corporation | ||
87 | mosaixtech Mosaix Technologies, Inc. | 104 | mosaixtech Mosaix Technologies, Inc. |
88 | moxa Moxa | 105 | moxa Moxa |
89 | mpl MPL AG | 106 | mpl MPL AG |
107 | mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) | ||
90 | mundoreader Mundo Reader S.L. | 108 | mundoreader Mundo Reader S.L. |
91 | murata Murata Manufacturing Co., Ltd. | 109 | murata Murata Manufacturing Co., Ltd. |
92 | mxicy Macronix International Co., Ltd. | 110 | mxicy Macronix International Co., Ltd. |
@@ -101,6 +119,7 @@ nxp NXP Semiconductors | |||
101 | onnn ON Semiconductor Corp. | 119 | onnn ON Semiconductor Corp. |
102 | opencores OpenCores.org | 120 | opencores OpenCores.org |
103 | panasonic Panasonic Corporation | 121 | panasonic Panasonic Corporation |
122 | pericom Pericom Technology Inc. | ||
104 | phytec PHYTEC Messtechnik GmbH | 123 | phytec PHYTEC Messtechnik GmbH |
105 | picochip Picochip Ltd | 124 | picochip Picochip Ltd |
106 | plathome Plat'Home Co., Ltd. | 125 | plathome Plat'Home Co., Ltd. |
@@ -118,6 +137,7 @@ renesas Renesas Electronics Corporation | |||
118 | ricoh Ricoh Co. Ltd. | 137 | ricoh Ricoh Co. Ltd. |
119 | rockchip Fuzhou Rockchip Electronics Co., Ltd | 138 | rockchip Fuzhou Rockchip Electronics Co., Ltd |
120 | samsung Samsung Semiconductor | 139 | samsung Samsung Semiconductor |
140 | sandisk Sandisk Corporation | ||
121 | sbs Smart Battery System | 141 | sbs Smart Battery System |
122 | schindler Schindler | 142 | schindler Schindler |
123 | seagate Seagate Technology PLC | 143 | seagate Seagate Technology PLC |
@@ -125,21 +145,26 @@ sil Silicon Image | |||
125 | silabs Silicon Laboratories | 145 | silabs Silicon Laboratories |
126 | simtek | 146 | simtek |
127 | sii Seiko Instruments, Inc. | 147 | sii Seiko Instruments, Inc. |
148 | silergy Silergy Corp. | ||
128 | sirf SiRF Technology, Inc. | 149 | sirf SiRF Technology, Inc. |
150 | sitronix Sitronix Technology Corporation | ||
129 | smsc Standard Microsystems Corporation | 151 | smsc Standard Microsystems Corporation |
130 | snps Synopsys, Inc. | 152 | snps Synopsys, Inc. |
131 | solidrun SolidRun | 153 | solidrun SolidRun |
154 | sony Sony Corporation | ||
132 | spansion Spansion Inc. | 155 | spansion Spansion Inc. |
133 | st STMicroelectronics | 156 | st STMicroelectronics |
134 | ste ST-Ericsson | 157 | ste ST-Ericsson |
135 | stericsson ST-Ericsson | 158 | stericsson ST-Ericsson |
136 | synology Synology, Inc. | 159 | synology Synology, Inc. |
160 | tbs TBS Technologies | ||
161 | thine THine Electronics, Inc. | ||
137 | ti Texas Instruments | 162 | ti Texas Instruments |
138 | tlm Trusted Logic Mobility | 163 | tlm Trusted Logic Mobility |
139 | toradex Toradex AG | 164 | toradex Toradex AG |
140 | toshiba Toshiba Corporation | 165 | toshiba Toshiba Corporation |
141 | toumaz Toumaz | 166 | toumaz Toumaz |
142 | usi Universal Scientifc Industrial Co., Ltd. | 167 | usi Universal Scientific Industrial Co., Ltd. |
143 | v3 V3 Semiconductor | 168 | v3 V3 Semiconductor |
144 | variscite Variscite Ltd. | 169 | variscite Variscite Ltd. |
145 | via VIA Technologies, Inc. | 170 | via VIA Technologies, Inc. |
@@ -148,6 +173,7 @@ winbond Winbond Electronics corp. | |||
148 | wlf Wolfson Microelectronics | 173 | wlf Wolfson Microelectronics |
149 | wm Wondermedia Technologies, Inc. | 174 | wm Wondermedia Technologies, Inc. |
150 | xes Extreme Engineering Solutions (X-ES) | 175 | xes Extreme Engineering Solutions (X-ES) |
176 | xillybus Xillybus Ltd. | ||
151 | xlnx Xilinx | 177 | xlnx Xilinx |
152 | zyxel ZyXEL Communications Corp. | 178 | zyxel ZyXEL Communications Corp. |
153 | zarlink Zarlink Semiconductor | 179 | zarlink Zarlink Semiconductor |
diff --git a/Documentation/devicetree/bindings/video/adi,adv7123.txt b/Documentation/devicetree/bindings/video/adi,adv7123.txt new file mode 100644 index 000000000000..a6b2b2b8f3d9 --- /dev/null +++ b/Documentation/devicetree/bindings/video/adi,adv7123.txt | |||
@@ -0,0 +1,50 @@ | |||
1 | Analog Device ADV7123 Video DAC | ||
2 | ------------------------------- | ||
3 | |||
4 | The ADV7123 is a digital-to-analog converter that outputs VGA signals from a | ||
5 | parallel video input. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible: Should be "adi,adv7123" | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - psave-gpios: Power save control GPIO | ||
14 | |||
15 | Required nodes: | ||
16 | |||
17 | The ADV7123 has two video ports. Their connections are modeled using the OF | ||
18 | graph bindings specified in Documentation/devicetree/bindings/graph.txt. | ||
19 | |||
20 | - Video port 0 for DPI input | ||
21 | - Video port 1 for VGA output | ||
22 | |||
23 | |||
24 | Example | ||
25 | ------- | ||
26 | |||
27 | adv7123: encoder@0 { | ||
28 | compatible = "adi,adv7123"; | ||
29 | |||
30 | ports { | ||
31 | #address-cells = <1>; | ||
32 | #size-cells = <0>; | ||
33 | |||
34 | port@0 { | ||
35 | reg = <0>; | ||
36 | |||
37 | adv7123_in: endpoint@0 { | ||
38 | remote-endpoint = <&dpi_out>; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | port@1 { | ||
43 | reg = <1>; | ||
44 | |||
45 | adv7123_out: endpoint@0 { | ||
46 | remote-endpoint = <&vga_connector_in>; | ||
47 | }; | ||
48 | }; | ||
49 | }; | ||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/adi,adv7511.txt b/Documentation/devicetree/bindings/video/adi,adv7511.txt new file mode 100644 index 000000000000..96c25ee01501 --- /dev/null +++ b/Documentation/devicetree/bindings/video/adi,adv7511.txt | |||
@@ -0,0 +1,88 @@ | |||
1 | Analog Device ADV7511(W)/13 HDMI Encoders | ||
2 | ----------------------------------------- | ||
3 | |||
4 | The ADV7511, ADV7511W and ADV7513 are HDMI audio and video transmitters | ||
5 | compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, | ||
6 | S/PDIF, CEC and HDCP. | ||
7 | |||
8 | Required properties: | ||
9 | |||
10 | - compatible: Should be one of "adi,adv7511", "adi,adv7511w" or "adi,adv7513" | ||
11 | - reg: I2C slave address | ||
12 | |||
13 | The ADV7511 supports a large number of input data formats that differ by their | ||
14 | color depth, color format, clock mode, bit justification and random | ||
15 | arrangement of components on the data bus. The combination of the following | ||
16 | properties describe the input and map directly to the video input tables of the | ||
17 | ADV7511 datasheet that document all the supported combinations. | ||
18 | |||
19 | - adi,input-depth: Number of bits per color component at the input (8, 10 or | ||
20 | 12). | ||
21 | - adi,input-colorspace: The input color space, one of "rgb", "yuv422" or | ||
22 | "yuv444". | ||
23 | - adi,input-clock: The input clock type, one of "1x" (one clock cycle per | ||
24 | pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel, | ||
25 | data driven on both edges). | ||
26 | |||
27 | The following input format properties are required except in "rgb 1x" and | ||
28 | "yuv444 1x" modes, in which case they must not be specified. | ||
29 | |||
30 | - adi,input-style: The input components arrangement variant (1, 2 or 3), as | ||
31 | listed in the input format tables in the datasheet. | ||
32 | - adi,input-justification: The input bit justification ("left", "evenly", | ||
33 | "right"). | ||
34 | |||
35 | Optional properties: | ||
36 | |||
37 | - interrupts: Specifier for the ADV7511 interrupt | ||
38 | - pd-gpios: Specifier for the GPIO connected to the power down signal | ||
39 | |||
40 | - adi,clock-delay: Video data clock delay relative to the pixel clock, in ps | ||
41 | (-1200 ps .. 1600 ps). Defaults to no delay. | ||
42 | - adi,embedded-sync: The input uses synchronization signals embedded in the | ||
43 | data stream (similar to BT.656). Defaults to separate H/V synchronization | ||
44 | signals. | ||
45 | |||
46 | Required nodes: | ||
47 | |||
48 | The ADV7511 has two video ports. Their connections are modelled using the OF | ||
49 | graph bindings specified in Documentation/devicetree/bindings/graph.txt. | ||
50 | |||
51 | - Video port 0 for the RGB or YUV input | ||
52 | - Video port 1 for the HDMI output | ||
53 | |||
54 | |||
55 | Example | ||
56 | ------- | ||
57 | |||
58 | adv7511w: hdmi@39 { | ||
59 | compatible = "adi,adv7511w"; | ||
60 | reg = <39>; | ||
61 | interrupt-parent = <&gpio3>; | ||
62 | interrupts = <29 IRQ_TYPE_EDGE_FALLING>; | ||
63 | |||
64 | adi,input-depth = <8>; | ||
65 | adi,input-colorspace = "rgb"; | ||
66 | adi,input-clock = "1x"; | ||
67 | adi,input-style = <1>; | ||
68 | adi,input-justification = "evenly"; | ||
69 | |||
70 | ports { | ||
71 | #address-cells = <1>; | ||
72 | #size-cells = <0>; | ||
73 | |||
74 | port@0 { | ||
75 | reg = <0>; | ||
76 | adv7511w_in: endpoint { | ||
77 | remote-endpoint = <&dpi_out>; | ||
78 | }; | ||
79 | }; | ||
80 | |||
81 | port@1 { | ||
82 | reg = <1>; | ||
83 | adv7511_out: endpoint { | ||
84 | remote-endpoint = <&hdmi_connector_in>; | ||
85 | }; | ||
86 | }; | ||
87 | }; | ||
88 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt index b75af94a5e52..f059dd0b3d28 100644 --- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt +++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt | |||
@@ -20,6 +20,9 @@ Required nodes: | |||
20 | - default-mode: a videomode within the display with timing parameters | 20 | - default-mode: a videomode within the display with timing parameters |
21 | as specified below. | 21 | as specified below. |
22 | 22 | ||
23 | Optional properties: | ||
24 | - lcd-supply: Regulator for LCD supply voltage. | ||
25 | |||
23 | Example: | 26 | Example: |
24 | 27 | ||
25 | fb0: fb@0x00500000 { | 28 | fb0: fb@0x00500000 { |
@@ -39,8 +42,8 @@ Atmel LCDC Display | |||
39 | ----------------------------------------------------- | 42 | ----------------------------------------------------- |
40 | Required properties (as per of_videomode_helper): | 43 | Required properties (as per of_videomode_helper): |
41 | 44 | ||
42 | - atmel,dmacon: dma controler configuration | 45 | - atmel,dmacon: dma controller configuration |
43 | - atmel,lcdcon2: lcd controler configuration | 46 | - atmel,lcdcon2: lcd controller configuration |
44 | - atmel,guard-time: lcd guard time (Delay in frame periods) | 47 | - atmel,guard-time: lcd guard time (Delay in frame periods) |
45 | - bits-per-pixel: lcd panel bit-depth. | 48 | - bits-per-pixel: lcd panel bit-depth. |
46 | 49 | ||
diff --git a/Documentation/devicetree/bindings/video/backlight/lp855x.txt b/Documentation/devicetree/bindings/video/backlight/lp855x.txt index 96e83a56048e..0a3ecbc3a1b9 100644 --- a/Documentation/devicetree/bindings/video/backlight/lp855x.txt +++ b/Documentation/devicetree/bindings/video/backlight/lp855x.txt | |||
@@ -12,6 +12,7 @@ Optional properties: | |||
12 | - pwm-period: PWM period value. Set only PWM input mode used (u32) | 12 | - pwm-period: PWM period value. Set only PWM input mode used (u32) |
13 | - rom-addr: Register address of ROM area to be updated (u8) | 13 | - rom-addr: Register address of ROM area to be updated (u8) |
14 | - rom-val: Register value to be updated (u8) | 14 | - rom-val: Register value to be updated (u8) |
15 | - power-supply: Regulator which controls the 3V rail | ||
15 | 16 | ||
16 | Example: | 17 | Example: |
17 | 18 | ||
@@ -56,6 +57,7 @@ Example: | |||
56 | backlight@2c { | 57 | backlight@2c { |
57 | compatible = "ti,lp8557"; | 58 | compatible = "ti,lp8557"; |
58 | reg = <0x2c>; | 59 | reg = <0x2c>; |
60 | power-supply = <&backlight_vdd>; | ||
59 | 61 | ||
60 | dev-ctrl = /bits/ 8 <0x41>; | 62 | dev-ctrl = /bits/ 8 <0x41>; |
61 | init-brt = /bits/ 8 <0x0a>; | 63 | init-brt = /bits/ 8 <0x0a>; |
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 31036c667d54..ca2b4aacd9af 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt | |||
@@ -2,7 +2,9 @@ Exynos MIPI DSI Master | |||
2 | 2 | ||
3 | Required properties: | 3 | Required properties: |
4 | - compatible: value should be one of the following | 4 | - compatible: value should be one of the following |
5 | "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */ | ||
5 | "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ | 6 | "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */ |
7 | "samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */ | ||
6 | "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ | 8 | "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */ |
7 | - reg: physical base address and length of the registers set for the device | 9 | - reg: physical base address and length of the registers set for the device |
8 | - interrupts: should contain DSI interrupt | 10 | - interrupts: should contain DSI interrupt |
diff --git a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt index 0329f60d431e..8c8c2f4e4c3f 100644 --- a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt +++ b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt | |||
@@ -20,7 +20,7 @@ Optional properties: | |||
20 | register is not modified as recommended by the datasheet. | 20 | register is not modified as recommended by the datasheet. |
21 | - fsl,lpccr: Contrast Control Register value. This property provides the | 21 | - fsl,lpccr: Contrast Control Register value. This property provides the |
22 | default value for the contrast control register. | 22 | default value for the contrast control register. |
23 | If that property is ommited, the register is zeroed. | 23 | If that property is omitted, the register is zeroed. |
24 | - fsl,lscr1: LCDC Sharp Configuration Register value. | 24 | - fsl,lscr1: LCDC Sharp Configuration Register value. |
25 | 25 | ||
26 | Example: | 26 | Example: |
diff --git a/Documentation/devicetree/bindings/video/renesas,du.txt b/Documentation/devicetree/bindings/video/renesas,du.txt new file mode 100644 index 000000000000..5102830f2760 --- /dev/null +++ b/Documentation/devicetree/bindings/video/renesas,du.txt | |||
@@ -0,0 +1,84 @@ | |||
1 | * Renesas R-Car Display Unit (DU) | ||
2 | |||
3 | Required Properties: | ||
4 | |||
5 | - compatible: must be one of the following. | ||
6 | - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU | ||
7 | - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU | ||
8 | - "renesas,du-r8a7791" for R8A7791 (R-Car M2) compatible DU | ||
9 | |||
10 | - reg: A list of base address and length of each memory resource, one for | ||
11 | each entry in the reg-names property. | ||
12 | - reg-names: Name of the memory resources. The DU requires one memory | ||
13 | resource for the DU core (named "du") and one memory resource for each | ||
14 | LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical | ||
15 | index). | ||
16 | |||
17 | - interrupt-parent: phandle of the parent interrupt controller. | ||
18 | - interrupts: Interrupt specifiers for the DU interrupts. | ||
19 | |||
20 | - clocks: A list of phandles + clock-specifier pairs, one for each entry in | ||
21 | the clock-names property. | ||
22 | - clock-names: Name of the clocks. This property is model-dependent. | ||
23 | - R8A7779 uses a single functional clock. The clock doesn't need to be | ||
24 | named. | ||
25 | - R8A7790 and R8A7791 use one functional clock per channel and one clock | ||
26 | per LVDS encoder. The functional clocks must be named "du.x" with "x" | ||
27 | being the channel numerical index. The LVDS clocks must be named | ||
28 | "lvds.x" with "x" being the LVDS encoder numerical index. | ||
29 | |||
30 | Required nodes: | ||
31 | |||
32 | The connections to the DU output video ports are modeled using the OF graph | ||
33 | bindings specified in Documentation/devicetree/bindings/graph.txt. | ||
34 | |||
35 | The following table lists for each supported model the port number | ||
36 | corresponding to each DU output. | ||
37 | |||
38 | Port 0 Port1 Port2 | ||
39 | ----------------------------------------------------------------------------- | ||
40 | R8A7779 (H1) DPAD 0 DPAD 1 - | ||
41 | R8A7790 (H2) DPAD LVDS 0 LVDS 1 | ||
42 | R8A7791 (M2) DPAD LVDS 0 - | ||
43 | |||
44 | |||
45 | Example: R8A7790 (R-Car H2) DU | ||
46 | |||
47 | du: du@feb00000 { | ||
48 | compatible = "renesas,du-r8a7790"; | ||
49 | reg = <0 0xfeb00000 0 0x70000>, | ||
50 | <0 0xfeb90000 0 0x1c>, | ||
51 | <0 0xfeb94000 0 0x1c>; | ||
52 | reg-names = "du", "lvds.0", "lvds.1"; | ||
53 | interrupt-parent = <&gic>; | ||
54 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | ||
55 | <0 268 IRQ_TYPE_LEVEL_HIGH>, | ||
56 | <0 269 IRQ_TYPE_LEVEL_HIGH>; | ||
57 | clocks = <&mstp7_clks R8A7790_CLK_DU0>, | ||
58 | <&mstp7_clks R8A7790_CLK_DU1>, | ||
59 | <&mstp7_clks R8A7790_CLK_DU2>, | ||
60 | <&mstp7_clks R8A7790_CLK_LVDS0>, | ||
61 | <&mstp7_clks R8A7790_CLK_LVDS1>; | ||
62 | clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; | ||
63 | |||
64 | ports { | ||
65 | #address-cells = <1>; | ||
66 | #size-cells = <0>; | ||
67 | |||
68 | port@0 { | ||
69 | reg = <0>; | ||
70 | du_out_rgb: endpoint { | ||
71 | }; | ||
72 | }; | ||
73 | port@1 { | ||
74 | reg = <1>; | ||
75 | du_out_lvds0: endpoint { | ||
76 | }; | ||
77 | }; | ||
78 | port@2 { | ||
79 | reg = <2>; | ||
80 | du_out_lvds1: endpoint { | ||
81 | }; | ||
82 | }; | ||
83 | }; | ||
84 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/rockchip-drm.txt b/Documentation/devicetree/bindings/video/rockchip-drm.txt new file mode 100644 index 000000000000..7fff582495a2 --- /dev/null +++ b/Documentation/devicetree/bindings/video/rockchip-drm.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | Rockchip DRM master device | ||
2 | ================================ | ||
3 | |||
4 | The Rockchip DRM master device is a virtual device needed to list all | ||
5 | vop devices or other display interface nodes that comprise the | ||
6 | graphics subsystem. | ||
7 | |||
8 | Required properties: | ||
9 | - compatible: Should be "rockchip,display-subsystem" | ||
10 | - ports: Should contain a list of phandles pointing to display interface port | ||
11 | of vop devices. vop definitions as defined in | ||
12 | Documentation/devicetree/bindings/video/rockchip-vop.txt | ||
13 | |||
14 | example: | ||
15 | |||
16 | display-subsystem { | ||
17 | compatible = "rockchip,display-subsystem"; | ||
18 | ports = <&vopl_out>, <&vopb_out>; | ||
19 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/rockchip-vop.txt b/Documentation/devicetree/bindings/video/rockchip-vop.txt new file mode 100644 index 000000000000..d15351f2313d --- /dev/null +++ b/Documentation/devicetree/bindings/video/rockchip-vop.txt | |||
@@ -0,0 +1,58 @@ | |||
1 | device-tree bindings for rockchip soc display controller (vop) | ||
2 | |||
3 | VOP (Visual Output Processor) is the Display Controller for the Rockchip | ||
4 | series of SoCs which transfers the image data from a video memory | ||
5 | buffer to an external LCD interface. | ||
6 | |||
7 | Required properties: | ||
8 | - compatible: value should be one of the following | ||
9 | "rockchip,rk3288-vop"; | ||
10 | |||
11 | - interrupts: should contain a list of all VOP IP block interrupts in the | ||
12 | order: VSYNC, LCD_SYSTEM. The interrupt specifier | ||
13 | format depends on the interrupt controller used. | ||
14 | |||
15 | - clocks: must include clock specifiers corresponding to entries in the | ||
16 | clock-names property. | ||
17 | |||
18 | - clock-names: Must contain | ||
19 | aclk_vop: for ddr buffer transfer. | ||
20 | hclk_vop: for ahb bus to R/W the phy regs. | ||
21 | dclk_vop: pixel clock. | ||
22 | |||
23 | - resets: Must contain an entry for each entry in reset-names. | ||
24 | See ../reset/reset.txt for details. | ||
25 | - reset-names: Must include the following entries: | ||
26 | - axi | ||
27 | - ahb | ||
28 | - dclk | ||
29 | |||
30 | - iommus: required a iommu node | ||
31 | |||
32 | - port: A port node with endpoint definitions as defined in | ||
33 | Documentation/devicetree/bindings/media/video-interfaces.txt. | ||
34 | |||
35 | Example: | ||
36 | SoC specific DT entry: | ||
37 | vopb: vopb@ff930000 { | ||
38 | compatible = "rockchip,rk3288-vop"; | ||
39 | reg = <0xff930000 0x19c>; | ||
40 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | ||
41 | clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; | ||
42 | clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; | ||
43 | resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; | ||
44 | reset-names = "axi", "ahb", "dclk"; | ||
45 | iommus = <&vopb_mmu>; | ||
46 | vopb_out: port { | ||
47 | #address-cells = <1>; | ||
48 | #size-cells = <0>; | ||
49 | vopb_out_edp: endpoint@0 { | ||
50 | reg = <0>; | ||
51 | remote-endpoint=<&edp_in_vopb>; | ||
52 | }; | ||
53 | vopb_out_hdmi: endpoint@1 { | ||
54 | reg = <1>; | ||
55 | remote-endpoint=<&hdmi_in_vopb>; | ||
56 | }; | ||
57 | }; | ||
58 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt index ecc899b9817b..cf1af6371021 100644 --- a/Documentation/devicetree/bindings/video/samsung-fimd.txt +++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt | |||
@@ -9,7 +9,9 @@ Required properties: | |||
9 | "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ | 9 | "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ |
10 | "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ | 10 | "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ |
11 | "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ | 11 | "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ |
12 | "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */ | ||
12 | "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ | 13 | "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ |
14 | "samsung,exynos4415-fimd"; /* for Exynos4415 SoC */ | ||
13 | "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ | 15 | "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ |
14 | 16 | ||
15 | - reg: physical base address and length of the FIMD registers set. | 17 | - reg: physical base address and length of the FIMD registers set. |
diff --git a/Documentation/devicetree/bindings/video/simple-framebuffer-sunxi.txt b/Documentation/devicetree/bindings/video/simple-framebuffer-sunxi.txt new file mode 100644 index 000000000000..c46ba641a1df --- /dev/null +++ b/Documentation/devicetree/bindings/video/simple-framebuffer-sunxi.txt | |||
@@ -0,0 +1,33 @@ | |||
1 | Sunxi specific Simple Framebuffer bindings | ||
2 | |||
3 | This binding documents sunxi specific extensions to the simple-framebuffer | ||
4 | bindings. The sunxi simplefb u-boot code relies on the devicetree containing | ||
5 | pre-populated simplefb nodes. | ||
6 | |||
7 | These extensions are intended so that u-boot can select the right node based | ||
8 | on which pipeline is being used. As such they are solely intended for | ||
9 | firmware / bootloader use, and the OS should ignore them. | ||
10 | |||
11 | Required properties: | ||
12 | - compatible: "allwinner,simple-framebuffer" | ||
13 | - allwinner,pipeline, one of: | ||
14 | "de_be0-lcd0" | ||
15 | "de_be1-lcd1" | ||
16 | "de_be0-lcd0-hdmi" | ||
17 | "de_be1-lcd1-hdmi" | ||
18 | |||
19 | Example: | ||
20 | |||
21 | chosen { | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <1>; | ||
24 | ranges; | ||
25 | |||
26 | framebuffer@0 { | ||
27 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | ||
28 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | ||
29 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | ||
30 | <&ahb_gates 44>; | ||
31 | status = "disabled"; | ||
32 | }; | ||
33 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/simple-framebuffer.txt b/Documentation/devicetree/bindings/video/simple-framebuffer.txt index 70c26f3a5b9a..4474ef6e0b95 100644 --- a/Documentation/devicetree/bindings/video/simple-framebuffer.txt +++ b/Documentation/devicetree/bindings/video/simple-framebuffer.txt | |||
@@ -1,8 +1,40 @@ | |||
1 | Simple Framebuffer | 1 | Simple Framebuffer |
2 | 2 | ||
3 | A simple frame-buffer describes a raw memory region that may be rendered to, | 3 | A simple frame-buffer describes a frame-buffer setup by firmware or |
4 | with the assumption that the display hardware has already been set up to scan | 4 | the bootloader, with the assumption that the display hardware has already |
5 | out from that buffer. | 5 | been set up to scan out from the memory pointed to by the reg property. |
6 | |||
7 | Since simplefb nodes represent runtime information they must be sub-nodes of | ||
8 | the chosen node (*). Simplefb nodes must be named "framebuffer@<address>". | ||
9 | |||
10 | If the devicetree contains nodes for the display hardware used by a simplefb, | ||
11 | then the simplefb node must contain a property called "display", which | ||
12 | contains a phandle pointing to the primary display hw node, so that the OS | ||
13 | knows which simplefb to disable when handing over control to a driver for the | ||
14 | real hardware. The bindings for the hw nodes must specify which node is | ||
15 | considered the primary node. | ||
16 | |||
17 | It is advised to add display# aliases to help the OS determine how to number | ||
18 | things. If display# aliases are used, then if the simplefb node contains a | ||
19 | "display" property then the /aliases/display# path must point to the display | ||
20 | hw node the "display" property points to, otherwise it must point directly | ||
21 | to the simplefb node. | ||
22 | |||
23 | If a simplefb node represents the preferred console for user interaction, | ||
24 | then the chosen node's stdout-path property should point to it, or to the | ||
25 | primary display hw node, as with display# aliases. If display aliases are | ||
26 | used then it should be set to the alias instead. | ||
27 | |||
28 | It is advised that devicetree files contain pre-filled, disabled framebuffer | ||
29 | nodes, so that the firmware only needs to update the mode information and | ||
30 | enable them. This way if e.g. later on support for more display clocks get | ||
31 | added, the simplefb nodes will already contain this info and the firmware | ||
32 | does not need to be updated. | ||
33 | |||
34 | If pre-filled framebuffer nodes are used, the firmware may need extra | ||
35 | information to find the right node. In that case an extra platform specific | ||
36 | compatible and platform specific properties should be used and documented, | ||
37 | see e.g. simple-framebuffer-sunxi.txt . | ||
6 | 38 | ||
7 | Required properties: | 39 | Required properties: |
8 | - compatible: "simple-framebuffer" | 40 | - compatible: "simple-framebuffer" |
@@ -14,13 +46,41 @@ Required properties: | |||
14 | - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). | 46 | - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). |
15 | - a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). | 47 | - a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). |
16 | 48 | ||
49 | Optional properties: | ||
50 | - clocks : List of clocks used by the framebuffer. Clocks listed here | ||
51 | are expected to already be configured correctly. The OS must | ||
52 | ensure these clocks are not modified or disabled while the | ||
53 | simple framebuffer remains active. | ||
54 | - display : phandle pointing to the primary display hardware node | ||
55 | |||
17 | Example: | 56 | Example: |
18 | 57 | ||
19 | framebuffer { | 58 | aliases { |
59 | display0 = &lcdc0; | ||
60 | } | ||
61 | |||
62 | chosen { | ||
63 | framebuffer0: framebuffer@1d385000 { | ||
20 | compatible = "simple-framebuffer"; | 64 | compatible = "simple-framebuffer"; |
21 | reg = <0x1d385000 (1600 * 1200 * 2)>; | 65 | reg = <0x1d385000 (1600 * 1200 * 2)>; |
22 | width = <1600>; | 66 | width = <1600>; |
23 | height = <1200>; | 67 | height = <1200>; |
24 | stride = <(1600 * 2)>; | 68 | stride = <(1600 * 2)>; |
25 | format = "r5g6b5"; | 69 | format = "r5g6b5"; |
70 | clocks = <&ahb_gates 36>, <&ahb_gates 43>, <&ahb_gates 44>; | ||
71 | display = <&lcdc0>; | ||
72 | }; | ||
73 | stdout-path = "display0"; | ||
74 | }; | ||
75 | |||
76 | soc@01c00000 { | ||
77 | lcdc0: lcdc@1c0c000 { | ||
78 | compatible = "allwinner,sun4i-a10-lcdc"; | ||
79 | ... | ||
26 | }; | 80 | }; |
81 | }; | ||
82 | |||
83 | |||
84 | *) Older devicetree files may have a compatible = "simple-framebuffer" node | ||
85 | in a different place, operating systems must first enumerate any compatible | ||
86 | nodes found under chosen and then check for other compatible nodes. | ||
diff --git a/Documentation/devicetree/bindings/video/thine,thc63lvdm83d b/Documentation/devicetree/bindings/video/thine,thc63lvdm83d new file mode 100644 index 000000000000..527e236e9a2a --- /dev/null +++ b/Documentation/devicetree/bindings/video/thine,thc63lvdm83d | |||
@@ -0,0 +1,50 @@ | |||
1 | THine Electronics THC63LVDM83D LVDS serializer | ||
2 | ---------------------------------------------- | ||
3 | |||
4 | The THC63LVDM83D is an LVDS serializer designed to support pixel data | ||
5 | transmission between a host and a flat panel. | ||
6 | |||
7 | Required properties: | ||
8 | |||
9 | - compatible: Should be "thine,thc63lvdm83d" | ||
10 | |||
11 | Optional properties: | ||
12 | |||
13 | - pwdn-gpios: Power down control GPIO | ||
14 | |||
15 | Required nodes: | ||
16 | |||
17 | The THC63LVDM83D has two video ports. Their connections are modeled using the | ||
18 | OFgraph bindings specified in Documentation/devicetree/bindings/graph.txt. | ||
19 | |||
20 | - Video port 0 for CMOS/TTL input | ||
21 | - Video port 1 for LVDS output | ||
22 | |||
23 | |||
24 | Example | ||
25 | ------- | ||
26 | |||
27 | lvds_enc: encoder@0 { | ||
28 | compatible = "thine,thc63lvdm83d"; | ||
29 | |||
30 | ports { | ||
31 | #address-cells = <1>; | ||
32 | #size-cells = <0>; | ||
33 | |||
34 | port@0 { | ||
35 | reg = <0>; | ||
36 | |||
37 | lvds_enc_in: endpoint@0 { | ||
38 | remote-endpoint = <&rgb_out>; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | port@1 { | ||
43 | reg = <1>; | ||
44 | |||
45 | lvds_enc_out: endpoint@0 { | ||
46 | remote-endpoint = <&panel_in>; | ||
47 | }; | ||
48 | }; | ||
49 | }; | ||
50 | }; | ||
diff --git a/Documentation/devicetree/bindings/video/vga-connector.txt b/Documentation/devicetree/bindings/video/vga-connector.txt new file mode 100644 index 000000000000..c727f298e7ad --- /dev/null +++ b/Documentation/devicetree/bindings/video/vga-connector.txt | |||
@@ -0,0 +1,36 @@ | |||
1 | VGA Connector | ||
2 | ============= | ||
3 | |||
4 | Required properties: | ||
5 | |||
6 | - compatible: "vga-connector" | ||
7 | |||
8 | Optional properties: | ||
9 | |||
10 | - label: a symbolic name for the connector corresponding to a hardware label | ||
11 | - ddc-i2c-bus: phandle to the I2C bus that is connected to VGA DDC | ||
12 | |||
13 | Required nodes: | ||
14 | |||
15 | The VGA connector internal connections are modeled using the OF graph bindings | ||
16 | specified in Documentation/devicetree/bindings/graph.txt. | ||
17 | |||
18 | The VGA connector has a single port that must be connected to a video source | ||
19 | port. | ||
20 | |||
21 | |||
22 | Example | ||
23 | ------- | ||
24 | |||
25 | vga0: connector@0 { | ||
26 | compatible = "vga-connector"; | ||
27 | label = "vga"; | ||
28 | |||
29 | ddc-i2c-bus = <&i2c3>; | ||
30 | |||
31 | port { | ||
32 | vga_connector_in: endpoint { | ||
33 | remote-endpoint = <&adv7123_out>; | ||
34 | }; | ||
35 | }; | ||
36 | }; | ||
diff --git a/Documentation/devicetree/bindings/w1/omap-hdq.txt b/Documentation/devicetree/bindings/w1/omap-hdq.txt new file mode 100644 index 000000000000..fef794741bd1 --- /dev/null +++ b/Documentation/devicetree/bindings/w1/omap-hdq.txt | |||
@@ -0,0 +1,17 @@ | |||
1 | * OMAP HDQ One wire bus master controller | ||
2 | |||
3 | Required properties: | ||
4 | - compatible : should be "ti,omap3-1w" | ||
5 | - reg : Address and length of the register set for the device | ||
6 | - interrupts : interrupt line. | ||
7 | - ti,hwmods : "hdq1w" | ||
8 | |||
9 | Example: | ||
10 | |||
11 | - From omap3.dtsi | ||
12 | hdqw1w: 1w@480b2000 { | ||
13 | compatible = "ti,omap3-1w"; | ||
14 | reg = <0x480b2000 0x1000>; | ||
15 | interrupts = <58>; | ||
16 | ti,hwmods = "hdq1w"; | ||
17 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt new file mode 100644 index 000000000000..c3a36ee45552 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | Zynq Watchdog Device Tree Bindings | ||
2 | ------------------------------------------- | ||
3 | |||
4 | Required properties: | ||
5 | - compatible : Should be "cdns,wdt-r1p2". | ||
6 | - clocks : This is pclk (APB clock). | ||
7 | - interrupts : This is wd_irq - watchdog timeout interrupt. | ||
8 | - interrupt-parent : Must be core interrupt controller. | ||
9 | |||
10 | Optional properties | ||
11 | - reset-on-timeout : If this property exists, then a reset is done | ||
12 | when watchdog times out. | ||
13 | - timeout-sec : Watchdog timeout value (in seconds). | ||
14 | |||
15 | Example: | ||
16 | watchdog@f8005000 { | ||
17 | compatible = "cdns,wdt-r1p2"; | ||
18 | clocks = <&clkc 45>; | ||
19 | interrupt-parent = <&intc>; | ||
20 | interrupts = <0 9 1>; | ||
21 | reg = <0xf8005000 0x1000>; | ||
22 | reset-on-timeout; | ||
23 | timeout-sec = <10>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt index e52ba2da868c..8dab6fd024aa 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt | |||
@@ -7,7 +7,8 @@ Required properties: | |||
7 | 7 | ||
8 | Optional property: | 8 | Optional property: |
9 | - big-endian: If present the watchdog device's registers are implemented | 9 | - big-endian: If present the watchdog device's registers are implemented |
10 | in big endian mode, otherwise in little mode. | 10 | in big endian mode, otherwise in native mode(same with CPU), for more |
11 | detail please see: Documentation/devicetree/bindings/regmap/regmap.txt. | ||
11 | 12 | ||
12 | Examples: | 13 | Examples: |
13 | 14 | ||
diff --git a/Documentation/devicetree/bindings/watchdog/marvel.txt b/Documentation/devicetree/bindings/watchdog/marvel.txt index 97223fddb7bd..858ed9221ac4 100644 --- a/Documentation/devicetree/bindings/watchdog/marvel.txt +++ b/Documentation/devicetree/bindings/watchdog/marvel.txt | |||
@@ -17,6 +17,18 @@ For "marvell,armada-375-wdt" and "marvell,armada-380-wdt": | |||
17 | - reg : A third entry is mandatory and should contain the | 17 | - reg : A third entry is mandatory and should contain the |
18 | shared mask/unmask RSTOUT address. | 18 | shared mask/unmask RSTOUT address. |
19 | 19 | ||
20 | Clocks required for compatibles = "marvell,orion-wdt", | ||
21 | "marvell,armada-370-wdt": | ||
22 | - clocks : Must contain a single entry describing the clock input | ||
23 | |||
24 | Clocks required for compatibles = "marvell,armada-xp-wdt" | ||
25 | "marvell,armada-375-wdt" | ||
26 | "marvell,armada-380-wdt": | ||
27 | - clocks : Must contain an entry for each entry in clock-names. | ||
28 | - clock-names : Must include the following entries: | ||
29 | "nbclk" (L2/coherency fabric clock), | ||
30 | "fixed" (Reference 25 MHz fixed-clock). | ||
31 | |||
20 | Optional properties: | 32 | Optional properties: |
21 | 33 | ||
22 | - interrupts : Contains the IRQ for watchdog expiration | 34 | - interrupts : Contains the IRQ for watchdog expiration |
@@ -30,4 +42,5 @@ Example: | |||
30 | interrupts = <3>; | 42 | interrupts = <3>; |
31 | timeout-sec = <10>; | 43 | timeout-sec = <10>; |
32 | status = "okay"; | 44 | status = "okay"; |
45 | clocks = <&gate_clk 7>; | ||
33 | }; | 46 | }; |
diff --git a/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt new file mode 100644 index 000000000000..9200fc2d508c --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt | |||
@@ -0,0 +1,13 @@ | |||
1 | Meson SoCs Watchdog timer | ||
2 | |||
3 | Required properties: | ||
4 | |||
5 | - compatible : should be "amlogic,meson6-wdt" | ||
6 | - reg : Specifies base physical address and size of the registers. | ||
7 | |||
8 | Example: | ||
9 | |||
10 | wdt: watchdog@c1109900 { | ||
11 | compatible = "amlogic,meson6-wdt"; | ||
12 | reg = <0xc1109900 0x8>; | ||
13 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt new file mode 100644 index 000000000000..4726924d034e --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt | |||
@@ -0,0 +1,24 @@ | |||
1 | Qualcomm Krait Processor Sub-system (KPSS) Watchdog | ||
2 | --------------------------------------------------- | ||
3 | |||
4 | Required properties : | ||
5 | - compatible : shall contain only one of the following: | ||
6 | |||
7 | "qcom,kpss-wdt-msm8960" | ||
8 | "qcom,kpss-wdt-apq8064" | ||
9 | "qcom,kpss-wdt-ipq8064" | ||
10 | |||
11 | - reg : shall contain base register location and length | ||
12 | - clocks : shall contain the input clock | ||
13 | |||
14 | Optional properties : | ||
15 | - timeout-sec : shall contain the default watchdog timeout in seconds, | ||
16 | if unset, the default timeout is 30 seconds | ||
17 | |||
18 | Example: | ||
19 | watchdog@208a038 { | ||
20 | compatible = "qcom,kpss-wdt-ipq8064"; | ||
21 | reg = <0x0208a038 0x40>; | ||
22 | clocks = <&sleep_clk>; | ||
23 | timeout-sec = <10>; | ||
24 | }; | ||
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt index cfff37511aac..8f3d96af81d7 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt | |||
@@ -9,6 +9,7 @@ Required properties: | |||
9 | (a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs | 9 | (a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs |
10 | (b) "samsung,exynos5250-wdt" for Exynos5250 | 10 | (b) "samsung,exynos5250-wdt" for Exynos5250 |
11 | (c) "samsung,exynos5420-wdt" for Exynos5420 | 11 | (c) "samsung,exynos5420-wdt" for Exynos5420 |
12 | (c) "samsung,exynos7-wdt" for Exynos7 | ||
12 | 13 | ||
13 | - reg : base physical address of the controller and length of memory mapped | 14 | - reg : base physical address of the controller and length of memory mapped |
14 | region. | 15 | region. |
diff --git a/Documentation/devicetree/bindings/staging/xillybus.txt b/Documentation/devicetree/bindings/xillybus/xillybus.txt index 9e316dc2e40f..9e316dc2e40f 100644 --- a/Documentation/devicetree/bindings/staging/xillybus.txt +++ b/Documentation/devicetree/bindings/xillybus/xillybus.txt | |||
diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt index 1f013bd0d320..77685185cf3b 100644 --- a/Documentation/devicetree/booting-without-of.txt +++ b/Documentation/devicetree/booting-without-of.txt | |||
@@ -51,6 +51,8 @@ Table of Contents | |||
51 | 51 | ||
52 | VIII - Specifying device power management information (sleep property) | 52 | VIII - Specifying device power management information (sleep property) |
53 | 53 | ||
54 | IX - Specifying dma bus information | ||
55 | |||
54 | Appendix A - Sample SOC node for MPC8540 | 56 | Appendix A - Sample SOC node for MPC8540 |
55 | 57 | ||
56 | 58 | ||
@@ -1332,6 +1334,57 @@ reasonably grouped in this manner, then create a virtual sleep controller | |||
1332 | (similar to an interrupt nexus, except that defining a standardized | 1334 | (similar to an interrupt nexus, except that defining a standardized |
1333 | sleep-map should wait until its necessity is demonstrated). | 1335 | sleep-map should wait until its necessity is demonstrated). |
1334 | 1336 | ||
1337 | IX - Specifying dma bus information | ||
1338 | |||
1339 | Some devices may have DMA memory range shifted relatively to the beginning of | ||
1340 | RAM, or even placed outside of kernel RAM. For example, the Keystone 2 SoC | ||
1341 | worked in LPAE mode with 4G memory has: | ||
1342 | - RAM range: [0x8 0000 0000, 0x8 FFFF FFFF] | ||
1343 | - DMA range: [ 0x8000 0000, 0xFFFF FFFF] | ||
1344 | and DMA range is aliased into first 2G of RAM in HW. | ||
1345 | |||
1346 | In such cases, DMA addresses translation should be performed between CPU phys | ||
1347 | and DMA addresses. The "dma-ranges" property is intended to be used | ||
1348 | for describing the configuration of such system in DT. | ||
1349 | |||
1350 | In addition, each DMA master device on the DMA bus may or may not support | ||
1351 | coherent DMA operations. The "dma-coherent" property is intended to be used | ||
1352 | for identifying devices supported coherent DMA operations in DT. | ||
1353 | |||
1354 | * DMA Bus master | ||
1355 | Optional property: | ||
1356 | - dma-ranges: <prop-encoded-array> encoded as arbitrary number of triplets of | ||
1357 | (child-bus-address, parent-bus-address, length). Each triplet specified | ||
1358 | describes a contiguous DMA address range. | ||
1359 | The dma-ranges property is used to describe the direct memory access (DMA) | ||
1360 | structure of a memory-mapped bus whose device tree parent can be accessed | ||
1361 | from DMA operations originating from the bus. It provides a means of | ||
1362 | defining a mapping or translation between the physical address space of | ||
1363 | the bus and the physical address space of the parent of the bus. | ||
1364 | (for more information see ePAPR specification) | ||
1365 | |||
1366 | * DMA Bus child | ||
1367 | Optional property: | ||
1368 | - dma-ranges: <empty> value. if present - It means that DMA addresses | ||
1369 | translation has to be enabled for this device. | ||
1370 | - dma-coherent: Present if dma operations are coherent | ||
1371 | |||
1372 | Example: | ||
1373 | soc { | ||
1374 | compatible = "ti,keystone","simple-bus"; | ||
1375 | ranges = <0x0 0x0 0x0 0xc0000000>; | ||
1376 | dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; | ||
1377 | |||
1378 | [...] | ||
1379 | |||
1380 | usb: usb@2680000 { | ||
1381 | compatible = "ti,keystone-dwc3"; | ||
1382 | |||
1383 | [...] | ||
1384 | dma-coherent; | ||
1385 | }; | ||
1386 | }; | ||
1387 | |||
1335 | Appendix A - Sample SOC node for MPC8540 | 1388 | Appendix A - Sample SOC node for MPC8540 |
1336 | ======================================== | 1389 | ======================================== |
1337 | 1390 | ||
diff --git a/Documentation/devicetree/dynamic-resolution-notes.txt b/Documentation/devicetree/dynamic-resolution-notes.txt new file mode 100644 index 000000000000..083d23262abe --- /dev/null +++ b/Documentation/devicetree/dynamic-resolution-notes.txt | |||
@@ -0,0 +1,25 @@ | |||
1 | Device Tree Dynamic Resolver Notes | ||
2 | ---------------------------------- | ||
3 | |||
4 | This document describes the implementation of the in-kernel | ||
5 | Device Tree resolver, residing in drivers/of/resolver.c and is a | ||
6 | companion document to Documentation/devicetree/dt-object-internal.txt[1] | ||
7 | |||
8 | How the resolver works | ||
9 | ---------------------- | ||
10 | |||
11 | The resolver is given as an input an arbitrary tree compiled with the | ||
12 | proper dtc option and having a /plugin/ tag. This generates the | ||
13 | appropriate __fixups__ & __local_fixups__ nodes as described in [1]. | ||
14 | |||
15 | In sequence the resolver works by the following steps: | ||
16 | |||
17 | 1. Get the maximum device tree phandle value from the live tree + 1. | ||
18 | 2. Adjust all the local phandles of the tree to resolve by that amount. | ||
19 | 3. Using the __local__fixups__ node information adjust all local references | ||
20 | by the same amount. | ||
21 | 4. For each property in the __fixups__ node locate the node it references | ||
22 | in the live tree. This is the label used to tag the node. | ||
23 | 5. Retrieve the phandle of the target of the fixup. | ||
24 | 6. For each fixup in the property locate the node:property:offset location | ||
25 | and replace it with the phandle value. | ||
diff --git a/Documentation/devicetree/of_selftest.txt b/Documentation/devicetree/of_selftest.txt index 3a2f54d07fc5..57a808b588bf 100644 --- a/Documentation/devicetree/of_selftest.txt +++ b/Documentation/devicetree/of_selftest.txt | |||
@@ -63,18 +63,17 @@ struct device_node { | |||
63 | struct device_node *parent; | 63 | struct device_node *parent; |
64 | struct device_node *child; | 64 | struct device_node *child; |
65 | struct device_node *sibling; | 65 | struct device_node *sibling; |
66 | struct device_node *allnext; /* next in list of all nodes */ | ||
67 | ... | 66 | ... |
68 | }; | 67 | }; |
69 | 68 | ||
70 | Figure 1, describes a generic structure of machine’s un-flattened device tree | 69 | Figure 1, describes a generic structure of machine's un-flattened device tree |
71 | considering only child and sibling pointers. There exists another pointer, | 70 | considering only child and sibling pointers. There exists another pointer, |
72 | *parent, that is used to traverse the tree in the reverse direction. So, at | 71 | *parent, that is used to traverse the tree in the reverse direction. So, at |
73 | a particular level the child node and all the sibling nodes will have a parent | 72 | a particular level the child node and all the sibling nodes will have a parent |
74 | pointer pointing to a common node (e.g. child1, sibling2, sibling3, sibling4’s | 73 | pointer pointing to a common node (e.g. child1, sibling2, sibling3, sibling4's |
75 | parent points to root node) | 74 | parent points to root node) |
76 | 75 | ||
77 | root (‘/’) | 76 | root ('/') |
78 | | | 77 | | |
79 | child1 -> sibling2 -> sibling3 -> sibling4 -> null | 78 | child1 -> sibling2 -> sibling3 -> sibling4 -> null |
80 | | | | | | 79 | | | | | |
@@ -99,12 +98,6 @@ child11 -> sibling12 -> sibling13 -> sibling14 -> null | |||
99 | Figure 1: Generic structure of un-flattened device tree | 98 | Figure 1: Generic structure of un-flattened device tree |
100 | 99 | ||
101 | 100 | ||
102 | *allnext: it is used to link all the nodes of DT into a list. So, for the | ||
103 | above tree the list would be as follows: | ||
104 | |||
105 | root->child1->child11->sibling12->sibling13->child131->sibling14->sibling2-> | ||
106 | child21->sibling22->sibling23->sibling3->child31->sibling32->sibling4->null | ||
107 | |||
108 | Before executing OF selftest, it is required to attach the test data to | 101 | Before executing OF selftest, it is required to attach the test data to |
109 | machine's device tree (if present). So, when selftest_data_add() is called, | 102 | machine's device tree (if present). So, when selftest_data_add() is called, |
110 | at first it reads the flattened device tree data linked into the kernel image | 103 | at first it reads the flattened device tree data linked into the kernel image |
@@ -113,8 +106,8 @@ via the following kernel symbols: | |||
113 | __dtb_testcases_begin - address marking the start of test data blob | 106 | __dtb_testcases_begin - address marking the start of test data blob |
114 | __dtb_testcases_end - address marking the end of test data blob | 107 | __dtb_testcases_end - address marking the end of test data blob |
115 | 108 | ||
116 | Secondly, it calls of_fdt_unflatten_device_tree() to unflatten the flattened | 109 | Secondly, it calls of_fdt_unflatten_tree() to unflatten the flattened |
117 | blob. And finally, if the machine’s device tree (i.e live tree) is present, | 110 | blob. And finally, if the machine's device tree (i.e live tree) is present, |
118 | then it attaches the unflattened test data tree to the live tree, else it | 111 | then it attaches the unflattened test data tree to the live tree, else it |
119 | attaches itself as a live device tree. | 112 | attaches itself as a live device tree. |
120 | 113 | ||
@@ -122,7 +115,7 @@ attach_node_and_children() uses of_attach_node() to attach the nodes into the | |||
122 | live tree as explained below. To explain the same, the test data tree described | 115 | live tree as explained below. To explain the same, the test data tree described |
123 | in Figure 2 is attached to the live tree described in Figure 1. | 116 | in Figure 2 is attached to the live tree described in Figure 1. |
124 | 117 | ||
125 | root (‘/’) | 118 | root ('/') |
126 | | | 119 | | |
127 | testcase-data | 120 | testcase-data |
128 | | | 121 | | |
@@ -131,15 +124,10 @@ root (‘/’) | |||
131 | test-child01 null null null | 124 | test-child01 null null null |
132 | 125 | ||
133 | 126 | ||
134 | allnext list: | ||
135 | |||
136 | root->testcase-data->test-child0->test-child01->test-sibling1->test-sibling2 | ||
137 | ->test-sibling3->null | ||
138 | |||
139 | Figure 2: Example test data tree to be attached to live tree. | 127 | Figure 2: Example test data tree to be attached to live tree. |
140 | 128 | ||
141 | According to the scenario above, the live tree is already present so it isn’t | 129 | According to the scenario above, the live tree is already present so it isn't |
142 | required to attach the root(‘/’) node. All other nodes are attached by calling | 130 | required to attach the root('/') node. All other nodes are attached by calling |
143 | of_attach_node() on each node. | 131 | of_attach_node() on each node. |
144 | 132 | ||
145 | In the function of_attach_node(), the new node is attached as the child of the | 133 | In the function of_attach_node(), the new node is attached as the child of the |
@@ -148,7 +136,7 @@ replaces the current child and turns it into its sibling. So, when the testcase | |||
148 | data node is attached to the live tree above (Figure 1), the final structure is | 136 | data node is attached to the live tree above (Figure 1), the final structure is |
149 | as shown in Figure 3. | 137 | as shown in Figure 3. |
150 | 138 | ||
151 | root (‘/’) | 139 | root ('/') |
152 | | | 140 | | |
153 | testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null | 141 | testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null |
154 | | | | | | | 142 | | | | | | |
@@ -170,7 +158,7 @@ testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null | |||
170 | null | 158 | null |
171 | ----------------------------------------------------------------------- | 159 | ----------------------------------------------------------------------- |
172 | 160 | ||
173 | root (‘/’) | 161 | root ('/') |
174 | | | 162 | | |
175 | testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null | 163 | testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null |
176 | | | | | | | 164 | | | | | | |
@@ -191,8 +179,8 @@ test-child0 the test-sibling1 is attached that pushes the child node | |||
191 | as mentioned above. | 179 | as mentioned above. |
192 | 180 | ||
193 | If a duplicate node is found (i.e. if a node with same full_name property is | 181 | If a duplicate node is found (i.e. if a node with same full_name property is |
194 | already present in the live tree), then the node isn’t attached rather its | 182 | already present in the live tree), then the node isn't attached rather its |
195 | properties are updated to the live tree’s node by calling the function | 183 | properties are updated to the live tree's node by calling the function |
196 | update_node_properties(). | 184 | update_node_properties(). |
197 | 185 | ||
198 | 186 | ||
@@ -204,8 +192,6 @@ detached and then moving up the parent nodes are removed, and eventually the | |||
204 | whole tree). selftest_data_remove() calls detach_node_and_children() that uses | 192 | whole tree). selftest_data_remove() calls detach_node_and_children() that uses |
205 | of_detach_node() to detach the nodes from the live device tree. | 193 | of_detach_node() to detach the nodes from the live device tree. |
206 | 194 | ||
207 | To detach a node, of_detach_node() first updates all_next linked list, by | 195 | To detach a node, of_detach_node() either updates the child pointer of given |
208 | attaching the previous node’s allnext to current node’s allnext pointer. And | 196 | node's parent to its sibling or attaches the previous sibling to the given |
209 | then, it either updates the child pointer of given node’s parent to its | 197 | node's sibling, as appropriate. That is it :) |
210 | sibling or attaches the previous sibling to the given node’s sibling, as | ||
211 | appropriate. That is it :) | ||
diff --git a/Documentation/devicetree/overlay-notes.txt b/Documentation/devicetree/overlay-notes.txt new file mode 100644 index 000000000000..30ae758e3eef --- /dev/null +++ b/Documentation/devicetree/overlay-notes.txt | |||
@@ -0,0 +1,133 @@ | |||
1 | Device Tree Overlay Notes | ||
2 | ------------------------- | ||
3 | |||
4 | This document describes the implementation of the in-kernel | ||
5 | device tree overlay functionality residing in drivers/of/overlay.c and is a | ||
6 | companion document to Documentation/devicetree/dt-object-internal.txt[1] & | ||
7 | Documentation/devicetree/dynamic-resolution-notes.txt[2] | ||
8 | |||
9 | How overlays work | ||
10 | ----------------- | ||
11 | |||
12 | A Device Tree's overlay purpose is to modify the kernel's live tree, and | ||
13 | have the modification affecting the state of the the kernel in a way that | ||
14 | is reflecting the changes. | ||
15 | Since the kernel mainly deals with devices, any new device node that result | ||
16 | in an active device should have it created while if the device node is either | ||
17 | disabled or removed all together, the affected device should be deregistered. | ||
18 | |||
19 | Lets take an example where we have a foo board with the following base tree | ||
20 | which is taken from [1]. | ||
21 | |||
22 | ---- foo.dts ----------------------------------------------------------------- | ||
23 | /* FOO platform */ | ||
24 | / { | ||
25 | compatible = "corp,foo"; | ||
26 | |||
27 | /* shared resources */ | ||
28 | res: res { | ||
29 | }; | ||
30 | |||
31 | /* On chip peripherals */ | ||
32 | ocp: ocp { | ||
33 | /* peripherals that are always instantiated */ | ||
34 | peripheral1 { ... }; | ||
35 | } | ||
36 | }; | ||
37 | ---- foo.dts ----------------------------------------------------------------- | ||
38 | |||
39 | The overlay bar.dts, when loaded (and resolved as described in [2]) should | ||
40 | |||
41 | ---- bar.dts ----------------------------------------------------------------- | ||
42 | /plugin/; /* allow undefined label references and record them */ | ||
43 | / { | ||
44 | .... /* various properties for loader use; i.e. part id etc. */ | ||
45 | fragment@0 { | ||
46 | target = <&ocp>; | ||
47 | __overlay__ { | ||
48 | /* bar peripheral */ | ||
49 | bar { | ||
50 | compatible = "corp,bar"; | ||
51 | ... /* various properties and child nodes */ | ||
52 | } | ||
53 | }; | ||
54 | }; | ||
55 | }; | ||
56 | ---- bar.dts ----------------------------------------------------------------- | ||
57 | |||
58 | result in foo+bar.dts | ||
59 | |||
60 | ---- foo+bar.dts ------------------------------------------------------------- | ||
61 | /* FOO platform + bar peripheral */ | ||
62 | / { | ||
63 | compatible = "corp,foo"; | ||
64 | |||
65 | /* shared resources */ | ||
66 | res: res { | ||
67 | }; | ||
68 | |||
69 | /* On chip peripherals */ | ||
70 | ocp: ocp { | ||
71 | /* peripherals that are always instantiated */ | ||
72 | peripheral1 { ... }; | ||
73 | |||
74 | /* bar peripheral */ | ||
75 | bar { | ||
76 | compatible = "corp,bar"; | ||
77 | ... /* various properties and child nodes */ | ||
78 | } | ||
79 | } | ||
80 | }; | ||
81 | ---- foo+bar.dts ------------------------------------------------------------- | ||
82 | |||
83 | As a result of the the overlay, a new device node (bar) has been created | ||
84 | so a bar platform device will be registered and if a matching device driver | ||
85 | is loaded the device will be created as expected. | ||
86 | |||
87 | Overlay in-kernel API | ||
88 | -------------------------------- | ||
89 | |||
90 | The API is quite easy to use. | ||
91 | |||
92 | 1. Call of_overlay_create() to create and apply an overlay. The return value | ||
93 | is a cookie identifying this overlay. | ||
94 | |||
95 | 2. Call of_overlay_destroy() to remove and cleanup the overlay previously | ||
96 | created via the call to of_overlay_create(). Removal of an overlay that | ||
97 | is stacked by another will not be permitted. | ||
98 | |||
99 | Finally, if you need to remove all overlays in one-go, just call | ||
100 | of_overlay_destroy_all() which will remove every single one in the correct | ||
101 | order. | ||
102 | |||
103 | Overlay DTS Format | ||
104 | ------------------ | ||
105 | |||
106 | The DTS of an overlay should have the following format: | ||
107 | |||
108 | { | ||
109 | /* ignored properties by the overlay */ | ||
110 | |||
111 | fragment@0 { /* first child node */ | ||
112 | |||
113 | target=<phandle>; /* phandle target of the overlay */ | ||
114 | or | ||
115 | target-path="/path"; /* target path of the overlay */ | ||
116 | |||
117 | __overlay__ { | ||
118 | property-a; /* add property-a to the target */ | ||
119 | node-a { /* add to an existing, or create a node-a */ | ||
120 | ... | ||
121 | }; | ||
122 | }; | ||
123 | } | ||
124 | fragment@1 { /* second child node */ | ||
125 | ... | ||
126 | }; | ||
127 | /* more fragments follow */ | ||
128 | } | ||
129 | |||
130 | Using the non-phandle based target method allows one to use a base DT which does | ||
131 | not contain a __symbols__ node, i.e. it was not compiled with the -@ option. | ||
132 | The __symbols__ node is only required for the target=<phandle> method, since it | ||
133 | contains the information required to map from a phandle to a tree location. | ||
diff --git a/Documentation/devicetree/todo.txt b/Documentation/devicetree/todo.txt index c3cf0659bd19..b5139d1de811 100644 --- a/Documentation/devicetree/todo.txt +++ b/Documentation/devicetree/todo.txt | |||
@@ -2,7 +2,6 @@ Todo list for devicetree: | |||
2 | 2 | ||
3 | === General structure === | 3 | === General structure === |
4 | - Switch from custom lists to (h)list_head for nodes and properties structure | 4 | - Switch from custom lists to (h)list_head for nodes and properties structure |
5 | - Remove of_allnodes list and iterate using list of child nodes alone | ||
6 | 5 | ||
7 | === CONFIG_OF_DYNAMIC === | 6 | === CONFIG_OF_DYNAMIC === |
8 | - Switch to RCU for tree updates and get rid of global spinlock | 7 | - Switch to RCU for tree updates and get rid of global spinlock |