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-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt9
1 files changed, 8 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index bcc30bac6831..70558c3f3682 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -5,14 +5,21 @@ Required properties:
5 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572, 5 first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on 6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
7 the parent type. 7 the parent type.
8
8- reg : should contain the address and the length of the shared message 9- reg : should contain the address and the length of the shared message
9 interrupt register set. 10 interrupt register set.
11
10- msi-available-ranges: use <start count> style section to define which 12- msi-available-ranges: use <start count> style section to define which
11 msi interrupt can be used in the 256 msi interrupts. This property is 13 msi interrupt can be used in the 256 msi interrupts. This property is
12 optional, without this, all the 256 MSI interrupts can be used. 14 optional, without this, all the 256 MSI interrupts can be used.
15 Each available range must begin and end on a multiple of 32 (i.e.
16 no splitting an individual MSI register or the associated PIC interrupt).
17
13- interrupts : each one of the interrupts here is one entry per 32 MSIs, 18- interrupts : each one of the interrupts here is one entry per 32 MSIs,
14 and routed to the host interrupt controller. the interrupts should 19 and routed to the host interrupt controller. the interrupts should
15 be set as edge sensitive. 20 be set as edge sensitive. If msi-available-ranges is present, only
21 the interrupts that correspond to available ranges shall be present.
22
16- interrupt-parent: the phandle for the interrupt controller 23- interrupt-parent: the phandle for the interrupt controller
17 that services interrupts for this device. for 83xx cpu, the interrupts 24 that services interrupts for this device. for 83xx cpu, the interrupts
18 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed 25 are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed