198 files changed, 5993 insertions, 165 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000000000000..d0ce01da5c59
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
+Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
+The EDAC accesses a range of registers in the SDRAM controller.
+Required properties:
+- compatible : should contain "altr,sdram-edac";
+- altr,sdr-syscon : phandle of the sdr module
+- interrupts : Should contain the SDRAM ECC IRQ in the
+        appropriate format for the IRQ controller.
+Example:
+        sdramedac {
+                compatible = "altr,sdram-edac";
+                altr,sdr-syscon = <&sdr>;
+                interrupts = <0 39 4>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
new file mode 100644
index 000000000000..7eece72b1a35
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -0,0 +1,8 @@
+Amlogic MesonX device tree bindings
+-------------------------------------------
+Boards with the Amlogic Meson6 SoC shall have the following properties:
+Required root node property:
+compatible = "amlogic,meson6";
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 16f60b41c147..562cda9d86d9 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -1,6 +1,43 @@
 Atmel AT91 device tree bindings.
 ================================
+Boards with a SoC of the Atmel AT91 or SMART family shall have the following
+properties:
+Required root node properties:
+compatible: must be one of:
+ * "atmel,at91rm9200"
+ * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
+   the specific SoC family or compatible:
+    o "atmel,at91sam9260"
+    o "atmel,at91sam9261"
+    o "atmel,at91sam9263"
+    o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
+      SoC compatible:
+       - "atmel,at91sam9g15"
+       - "atmel,at91sam9g25"
+       - "atmel,at91sam9g35"
+       - "atmel,at91sam9x25"
+       - "atmel,at91sam9x35"
+    o "atmel,at91sam9g20"
+    o "atmel,at91sam9g45"
+    o "atmel,at91sam9n12"
+    o "atmel,at91sam9rl"
+ * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
+   SoC family:
+    o "atmel,sama5d3" shall be extended with the specific SoC compatible:
+       - "atmel,sama5d31"
+       - "atmel,sama5d33"
+       - "atmel,sama5d34"
+       - "atmel,sama5d35"
+       - "atmel,sama5d36"
+    o "atmel,sama5d4" shall be extended with the specific SoC compatible:
+       - "atmel,sama5d41"
+       - "atmel,sama5d42"
+       - "atmel,sama5d43"
+       - "atmel,sama5d44"
 PIT Timer required properties:
 - compatible: Should be "atmel,at91sam9260-pit"
 - reg: Should contain registers location and length
@@ -61,8 +98,8 @@ RAMC SDRAM/DDR Controller required properties:
 - compatible: Should be "atmel,at91rm9200-sdramc",
                        "atmel,at91sam9260-sdramc",
                        "atmel,at91sam9g45-ddramc",
+                        "atmel,sama5d3-ddramc",
 - reg: Should contain registers location and length
-  For at91sam9263 and at91sam9g45 you must specify 2 entries.
 Examples:
@@ -71,12 +108,6 @@ Examples:
                reg = <0xffffe800 0x200>;
        };
-        ramc0: ramc@ffffe400 {
-                compatible = "atmel,at91sam9g45-ddramc";
-                reg = <0xffffe400 0x200
-                       0xffffe600 0x200>;
-        };
 SHDWC Shutdown Controller
 required properties:
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
new file mode 100644
index 000000000000..bd49987a8812
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
@@ -0,0 +1,9 @@
+Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
+-----------------------------------------------------------
+Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
+following properties:
+Required root node property:
+compatible: should be "brcm,bcm63138"
diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
new file mode 100644
index 000000000000..6f63a5866902
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
@@ -0,0 +1,10 @@
+Cavium Thunder platform device tree bindings
+--------------------------------------------
+Boards with Cavium's Thunder SoC shall have following properties.
+Root Node
+---------
+Required root node properties:
+  - compatible = "cavium,thunder-88xx";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 298e2f6b33c6..fc446347ab6d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -166,6 +166,7 @@ nodes to be present and contain the properties described below.
                            "arm,cortex-r5"
                            "arm,cortex-r7"
                            "brcm,brahma-b15"
+                            "cavium,thunder"
                            "faraday,fa526"
                            "intel,sa110"
                            "intel,sa1100"
@@ -219,6 +220,12 @@ nodes to be present and contain the properties described below.
                Value type: <phandle>
                Definition: Specifies the ACC[2] node associated with this CPU.
+        - cpu-idle-states
+                Usage: Optional
+                Value type: <prop-encoded-array>
+                Definition:
+                        # List of phandles to idle state nodes supported
+                          by this cpu [3].
 Example 1 (dual-cluster big.LITTLE system 32-bit):
@@ -415,3 +422,5 @@ cpus {
 --
 [1] arm/msm/qcom,saw2.txt
 [2] arm/msm/qcom,kpss-acc.txt
+[3] ARM Linux kernel documentation - idle states bindings
+    Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 8b4f7b7fe88b..abde1ea8a119 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -8,6 +8,8 @@ Required Properties:
    * samsung,exynos4210-pd - for exynos4210 type power domain.
 - reg: physical base address of the controller and length of memory mapped
    region.
+- #power-domain-cells: number of cells in power domain specifier;
+    must be 0.
 Optional Properties:
 - clocks: List of clock handles. The parent clocks of the input clocks to the
@@ -29,6 +31,7 @@ Example:
        lcd0: power-domain-lcd0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023C00 0x10>;
+                #power-domain-cells = <0>;
        };
        mfc_pd: power-domain@10044060 {
@@ -37,12 +40,8 @@ Example:
                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
                        <&clock CLK_MOUT_USER_ACLK333>;
                clock-names = "oscclk", "pclk0", "clk0";
+                #power-domain-cells = <0>;
        };
-Example of the node using power domain:
+See Documentation/devicetree/bindings/power/power_domain.txt for description
+of consumer-side bindings.
-        node {
-                /* ... */
-                samsung,power-domain = <&lcd0>;
-                /* ... */
-        };
diff --git a/Documentation/devicetree/bindings/arm/geniatech.txt b/Documentation/devicetree/bindings/arm/geniatech.txt
new file mode 100644
index 000000000000..74ccba40b73b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/geniatech.txt
@@ -0,0 +1,5 @@
+Geniatech platforms device tree bindings
+-------------------------------------------
+Geniatech ATV1200
+    - compatible = "geniatech,atv1200"
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 934f00025cc4..f717c7b48603 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -5,6 +5,11 @@ Hi4511 Board
 Required root node properties:
        - compatible = "hisilicon,hi3620-hi4511";
+HiP04 D01 Board
+Required root node properties:
+        - compatible = "hisilicon,hip04-d01";
 Hisilicon system controller
 Required properties:
@@ -55,3 +60,21 @@ Example:
                compatible = "hisilicon,pctrl";
                reg = <0xfca09000 0x1000>;
        };
+-----------------------------------------------------------------------
+Fabric:
+Required Properties:
+- compatible: "hisilicon,hip04-fabric";
+- reg: Address and size of Fabric
+-----------------------------------------------------------------------
+Bootwrapper boot method (software protocol on SMP):
+Required Properties:
+- compatible: "hisilicon,hip04-bootwrapper";
+- boot-method: Address and size of boot method.
+  [0]: bootwrapper physical address
+  [1]: bootwrapper size
+  [2]: relocation physical address
+  [3]: relocation size
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
new file mode 100644
index 000000000000..37375c7f3ccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -0,0 +1,679 @@
+==========================================
+ARM idle states binding description
+==========================================
+==========================================
+1 - Introduction
+==========================================
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OS PM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+According to the Server Base System Architecture document (SBSA, [3]), the
+power states an ARM CPU can be put into are identified by the following list:
+- Running
+- Idle_standby
+- Idle_retention
+- Sleep
+- Off
+The power states described in the SBSA document define the basic CPU states on
+top of which ARM platforms implement power management schemes that allow an OS
+PM implementation to put the processor in different idle states (which include
+states listed above; "off" state is not an idle state since it does not have
+wake-up capabilities, hence it is not considered in this document).
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OS PM
+code so that it can build the required tables and use them at runtime.
+The device tree binding definition for ARM idle states is the subject of this
+document.
+===========================================
+2 - idle-states definitions
+===========================================
+Idle states are characterized for a specific system through a set of
+timing and energy related properties, that underline the HW behaviour
+triggered upon idle states entry and exit.
+The following diagram depicts the CPU execution phases and related timing
+properties required to enter and exit an idle state:
+..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
+            |          |           |          |          |
+            |<------ entry ------->|
+            |       latency        |
+                                              |<- exit ->|
+                                              |  latency |
+            |<-------- min-residency -------->|
+                       |<-------  wakeup-latency ------->|
+                Diagram 1: CPU idle state execution phases
+EXEC:   Normal CPU execution.
+PREP:   Preparation phase before committing the hardware to idle mode
+        like cache flushing. This is abortable on pending wake-up
+        event conditions. The abort latency is assumed to be negligible
+        (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
+        goes back to EXEC. This phase is optional. If not abortable,
+        this should be included in the ENTRY phase instead.
+ENTRY:  The hardware is committed to idle mode. This period must run
+        to completion up to IDLE before anything else can happen.
+IDLE:   This is the actual energy-saving idle period. This may last
+        between 0 and infinite time, until a wake-up event occurs.
+EXIT:   Period during which the CPU is brought back to operational
+        mode (EXEC).
+entry-latency: Worst case latency required to enter the idle state. The
+exit-latency may be guaranteed only after entry-latency has passed.
+min-residency: Minimum period, including preparation and entry, for a given
+idle state to be worthwhile energywise.
+wakeup-latency: Maximum delay between the signaling of a wake-up event and the
+CPU being able to execute normal code again. If not specified, this is assumed
+to be entry-latency + exit-latency.
+These timing parameters can be used by an OS in different circumstances.
+An idle CPU requires the expected min-residency time to select the most
+appropriate idle state based on the expected expiry time of the next IRQ
+(ie wake-up) that causes the CPU to return to the EXEC phase.
+An operating system scheduler may need to compute the shortest wake-up delay
+for CPUs in the system by detecting how long will it take to get a CPU out
+of an idle state, eg:
+wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
+In other words, the scheduler can make its scheduling decision by selecting
+(eg waking-up) the CPU with the shortest wake-up latency.
+The wake-up latency must take into account the entry latency if that period
+has not expired. The abortable nature of the PREP period can be ignored
+if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
+the worst case since it depends on the CPU operating conditions, ie caches
+state).
+An OS has to reliably probe the wakeup-latency since some devices can enforce
+latency constraints guarantees to work properly, so the OS has to detect the
+worst case wake-up latency it can incur if a CPU is allowed to enter an
+idle state, and possibly to prevent that to guarantee reliable device
+functioning.
+The min-residency time parameter deserves further explanation since it is
+expressed in time units but must factor in energy consumption coefficients.
+The energy consumption of a cpu when it enters a power state can be roughly
+characterised by the following graph:
+               |
+               |
+               |
+           e   |
+           n   |                                      /---
+           e   |                               /------
+           r   |                        /------
+           g   |                  /-----
+           y   |           /------
+               |       ----
+               |      /|
+               |     / |
+               |    /  |
+               |   /   |
+               |  /    |
+               | /     |
+               |/      |
+          -----|-------+----------------------------------
+              0|       1                              time(ms)
+                Graph 1: Energy vs time example
+The graph is split in two parts delimited by time 1ms on the X-axis.
+The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
+and denotes the energy costs incurred whilst entering and leaving the idle
+state.
+The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
+shallower slope and essentially represents the energy consumption of the idle
+state.
+min-residency is defined for a given idle state as the minimum expected
+residency time for a state (inclusive of preparation and entry) after
+which choosing that state become the most energy efficient option. A good
+way to visualise this, is by taking the same graph above and comparing some
+states energy consumptions plots.
+For sake of simplicity, let's consider a system with two idle states IDLE1,
+and IDLE2:
+          |
+          |
+          |
+          |                                                  /-- IDLE1
+       e  |                                              /---
+       n  |                                         /----
+       e  |                                     /---
+       r  |                                /-----/--------- IDLE2
+       g  |                    /-------/---------
+       y  |        ------------    /---|
+          |       /           /----    |
+          |      /        /---         |
+          |     /    /----             |
+          |    / /---                  |
+          |   ---                      |
+          |  /                         |
+          | /                          |
+          |/                           |                  time
+       ---/----------------------------+------------------------
+          |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
+                                       |
+                                IDLE2-min-residency
+                Graph 2: idle states min-residency example
+In graph 2 above, that takes into account idle states entry/exit energy
+costs, it is clear that if the idle state residency time (ie time till next
+wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
+choice energywise.
+This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
+than IDLE2.
+However, the lower power consumption (ie shallower energy curve slope) of idle
+state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
+efficient.
+The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
+shallower states in a system with multiple idle states) is defined
+IDLE2-min-residency and corresponds to the time when energy consumption of
+IDLE1 and IDLE2 states breaks even.
+The definitions provided in this section underpin the idle states
+properties specification that is the subject of the following sections.
+===========================================
+3 - idle-states node
+===========================================
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node [1] and provides a container where the
+processor idle states, defined as device tree nodes, are listed.
+- idle-states node
+        Usage: Optional - On ARM systems, it is a container of processor idle
+                          states nodes. If the system does not provide CPU
+                          power management capabilities or the processor just
+                          supports idle_standby an idle-states node is not
+                          required.
+        Description: idle-states node is a container node, where its
+                     subnodes describe the CPU idle states.
+        Node name must be "idle-states".
+        The idle-states node's parent node must be the cpus node.
+        The idle-states node's child nodes can be:
+        - one or more state nodes
+        Any other configuration is considered invalid.
+        An idle-states node defines the following properties:
+        - entry-method
+                Value type: <stringlist>
+                Usage and definition depend on ARM architecture version.
+                        # On ARM v8 64-bit this property is required and must
+                          be one of:
+                           - "psci" (see bindings in [2])
+                        # On ARM 32-bit systems this property is optional
+The nodes describing the idle states (state) can only be defined within the
+idle-states node, any other configuration is considered invalid and therefore
+must be ignored.
+===========================================
+4 - state node
+===========================================
+A state node represents an idle state description and must be defined as
+follows:
+- state node
+        Description: must be child of the idle-states node
+        The state node name shall follow standard device tree naming
+        rules ([5], 2.2.1 "Node names"), in particular state nodes which
+        are siblings within a single common parent must be given a unique name.
+        The idle state entered by executing the wfi instruction (idle_standby
+        SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+        must not be listed.
+        With the definitions provided above, the following list represents
+        the valid properties for a state node:
+        - compatible
+                Usage: Required
+                Value type: <stringlist>
+                Definition: Must be "arm,idle-state".
+        - local-timer-stop
+                Usage: See definition
+                Value type: <none>
+                Definition: if present the CPU local timer control logic is
+                            lost on state entry, otherwise it is retained.
+        - entry-latency-us
+                Usage: Required
+                Value type: <prop-encoded-array>
+                Definition: u32 value representing worst case latency in
+                            microseconds required to enter the idle state.
+                            The exit-latency-us duration may be guaranteed
+                            only after entry-latency-us has passed.
+        - exit-latency-us
+                Usage: Required
+                Value type: <prop-encoded-array>
+                Definition: u32 value representing worst case latency
+                            in microseconds required to exit the idle state.
+        - min-residency-us
+                Usage: Required
+                Value type: <prop-encoded-array>
+                Definition: u32 value representing minimum residency duration
+                            in microseconds, inclusive of preparation and
+                            entry, for this idle state to be considered
+                            worthwhile energy wise (refer to section 2 of
+                            this document for a complete description).
+        - wakeup-latency-us:
+                Usage: Optional
+                Value type: <prop-encoded-array>
+                Definition: u32 value representing maximum delay between the
+                            signaling of a wake-up event and the CPU being
+                            able to execute normal code again. If omitted,
+                            this is assumed to be equal to:
+                                entry-latency-us + exit-latency-us
+                            It is important to supply this value on systems
+                            where the duration of PREP phase (see diagram 1,
+                            section 2) is non-neglibigle.
+                            In such systems entry-latency-us + exit-latency-us
+                            will exceed wakeup-latency-us by this duration.
+        In addition to the properties listed above, a state node may require
+        additional properties specifics to the entry-method defined in the
+        idle-states node, please refer to the entry-method bindings
+        documentation for properties definitions.
+===========================================
+4 - Examples
+===========================================
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+cpus {
+        #size-cells = <0>;
+        #address-cells = <2>;
+        CPU0: cpu@0 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x0>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU1: cpu@1 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x1>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU2: cpu@100 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x100>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU3: cpu@101 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x101>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU4: cpu@10000 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x10000>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU5: cpu@10001 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x10001>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU6: cpu@10100 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x10100>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU7: cpu@10101 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a57";
+                reg = <0x0 0x10101>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+                                   &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU8: cpu@100000000 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x0>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU9: cpu@100000001 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x1>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU10: cpu@100000100 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x100>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU11: cpu@100000101 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x101>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU12: cpu@100010000 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x10000>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU13: cpu@100010001 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x10001>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU14: cpu@100010100 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x10100>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        CPU15: cpu@100010101 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a53";
+                reg = <0x1 0x10101>;
+                enable-method = "psci";
+                cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+                                   &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+        };
+        idle-states {
+                entry-method = "arm,psci";
+                CPU_RETENTION_0_0: cpu-retention-0-0 {
+                        compatible = "arm,idle-state";
+                        arm,psci-suspend-param = <0x0010000>;
+                        entry-latency-us = <20>;
+                        exit-latency-us = <40>;
+                        min-residency-us = <80>;
+                };
+                CLUSTER_RETENTION_0: cluster-retention-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        arm,psci-suspend-param = <0x1010000>;
+                        entry-latency-us = <50>;
+                        exit-latency-us = <100>;
+                        min-residency-us = <250>;
+                        wakeup-latency-us = <130>;
+                };
+                CPU_SLEEP_0_0: cpu-sleep-0-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        arm,psci-suspend-param = <0x0010000>;
+                        entry-latency-us = <250>;
+                        exit-latency-us = <500>;
+                        min-residency-us = <950>;
+                };
+                CLUSTER_SLEEP_0: cluster-sleep-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        arm,psci-suspend-param = <0x1010000>;
+                        entry-latency-us = <600>;
+                        exit-latency-us = <1100>;
+                        min-residency-us = <2700>;
+                        wakeup-latency-us = <1500>;
+                };
+                CPU_RETENTION_1_0: cpu-retention-1-0 {
+                        compatible = "arm,idle-state";
+                        arm,psci-suspend-param = <0x0010000>;
+                        entry-latency-us = <20>;
+                        exit-latency-us = <40>;
+                        min-residency-us = <90>;
+                };
+                CLUSTER_RETENTION_1: cluster-retention-1 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        arm,psci-suspend-param = <0x1010000>;
+                        entry-latency-us = <50>;
+                        exit-latency-us = <100>;
+                        min-residency-us = <270>;
+                        wakeup-latency-us = <100>;
+                };
+                CPU_SLEEP_1_0: cpu-sleep-1-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        arm,psci-suspend-param = <0x0010000>;
+                        entry-latency-us = <70>;
+                        exit-latency-us = <100>;
+                        min-residency-us = <300>;
+                        wakeup-latency-us = <150>;
+                };
+                CLUSTER_SLEEP_1: cluster-sleep-1 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        arm,psci-suspend-param = <0x1010000>;
+                        entry-latency-us = <500>;
+                        exit-latency-us = <1200>;
+                        min-residency-us = <3500>;
+                        wakeup-latency-us = <1300>;
+                };
+        };
+};
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+cpus {
+        #size-cells = <0>;
+        #address-cells = <1>;
+        CPU0: cpu@0 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a15";
+                reg = <0x0>;
+                cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU1: cpu@1 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a15";
+                reg = <0x1>;
+                cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU2: cpu@2 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a15";
+                reg = <0x2>;
+                cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU3: cpu@3 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a15";
+                reg = <0x3>;
+                cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+        };
+        CPU4: cpu@100 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a7";
+                reg = <0x100>;
+                cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+        };
+        CPU5: cpu@101 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a7";
+                reg = <0x101>;
+                cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+        };
+        CPU6: cpu@102 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a7";
+                reg = <0x102>;
+                cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+        };
+        CPU7: cpu@103 {
+                device_type = "cpu";
+                compatible = "arm,cortex-a7";
+                reg = <0x103>;
+                cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+        };
+        idle-states {
+                CPU_SLEEP_0_0: cpu-sleep-0-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        entry-latency-us = <200>;
+                        exit-latency-us = <100>;
+                        min-residency-us = <400>;
+                        wakeup-latency-us = <250>;
+                };
+                CLUSTER_SLEEP_0: cluster-sleep-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        entry-latency-us = <500>;
+                        exit-latency-us = <1500>;
+                        min-residency-us = <2500>;
+                        wakeup-latency-us = <1700>;
+                };
+                CPU_SLEEP_1_0: cpu-sleep-1-0 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        entry-latency-us = <300>;
+                        exit-latency-us = <500>;
+                        min-residency-us = <900>;
+                        wakeup-latency-us = <600>;
+                };
+                CLUSTER_SLEEP_1: cluster-sleep-1 {
+                        compatible = "arm,idle-state";
+                        local-timer-stop;
+                        entry-latency-us = <800>;
+                        exit-latency-us = <2000>;
+                        min-residency-us = <6500>;
+                        wakeup-latency-us = <2300>;
+                };
+        };
+};
+===========================================
+5 - References
+===========================================
+[1] ARM Linux Kernel documentation - CPUs bindings
+    Documentation/devicetree/bindings/arm/cpus.txt
+[2] ARM Linux Kernel documentation - PSCI bindings
+    Documentation/devicetree/bindings/arm/psci.txt
+[3] ARM Server Base System Architecture (SBSA)
+    http://infocenter.arm.com/help/index.jsp
+[4] ARM Architecture Reference Manuals
+    http://infocenter.arm.com/help/index.jsp
+[5] ePAPR standard
+    https://www.power.org/documentation/epapr-version-1-1/
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index af527ee111c2..292ef7ca3058 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -2,6 +2,10 @@
 ARM cores often have a separate level 2 cache controller. There are various
 implementations of the L2 cache controller with compatible programming models.
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the ePAPR v1.1 specification which can be found at:
+https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
 The ARM L2 cache representation in the device tree should be done as follows:
 Required properties:
@@ -44,6 +48,12 @@ Optional properties:
  I/O coherent mode. Valid only when the arm,pl310-cache compatible
  string is used.
 - interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+  if this is not specified, the line size is assumed to be equal to the
+  cache block size
 - cache-id-part: cache id part number to be used if it is not present
  on hardware
 - wt-override: If present then L2 is forced to Write through mode
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index d6ac71f37314..fa252261dfaf 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -6,3 +6,9 @@ Required root node property:
 compatible: must contain "mediatek,mt6589"
+Supported boards:
+- bq Aquaris5 smart phone:
+    Required root node properties:
+      - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
index 83f405bde138..763695db2bd9 100644
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -10,6 +10,9 @@ Required properties:
               Should be "ti,omap5-mpu" for OMAP5
 - ti,hwmods: "mpu"
+Optional properties:
+- sram: Phandle to the ocmcram node
 Examples:
 - For an OMAP5 SMP system:
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 0edc90305dfe..ddd9bcdf889c 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -85,6 +85,18 @@ SoCs:
 - DRA722
  compatible = "ti,dra722", "ti,dra72", "ti,dra7"
+- AM5728
+  compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
+- AM5726
+  compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7"
+- AM5718
+  compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"
+- AM5716
+  compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7"
 - AM4372
  compatible = "ti,am4372", "ti,am43"
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
index b4a58f39223c..5aa40ede0e99 100644
--- a/Documentation/devicetree/bindings/arm/psci.txt
+++ b/Documentation/devicetree/bindings/arm/psci.txt
@@ -50,6 +50,16 @@ Main node optional properties:
 - migrate       : Function ID for MIGRATE operation
+Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
+state nodes, as per bindings in [1]) must specify the following properties:
+- arm,psci-suspend-param
+                Usage: Required for state nodes[1] if the corresponding
+                       idle-states node entry-method property is set
+                       to "psci".
+                Value type: <u32>
+                Definition: power_state parameter to pass to the PSCI
+                            suspend call.
 Example:
@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
                migrate         = <0x95c10003>;
        };
 Case 2: PSCI v0.2 only
        psci {
@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
                ...
        };
+[1] Kernel documentation - ARM idle states bindings
+    Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index adc61b095bd1..709efaa30841 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -11,13 +11,25 @@ New driver handles the following
 Required properties:
 - compatible:           Must be "samsung,exynos-adc-v1"
-                                for exynos4412/5250 controllers.
+                                for exynos4412/5250 and s5pv210 controllers.
                        Must be "samsung,exynos-adc-v2" for
                                future controllers.
                        Must be "samsung,exynos3250-adc" for
                                controllers compatible with ADC of Exynos3250.
- reg:                  Contains ADC register address range (base address and
+                        Must be "samsung,s3c2410-adc" for
-                        length) and the address of the phy enable register.
+                                the ADC in s3c2410 and compatibles
+                        Must be "samsung,s3c2416-adc" for
+                                the ADC in s3c2416 and compatibles
+                        Must be "samsung,s3c2440-adc" for
+                                the ADC in s3c2440 and compatibles
+                        Must be "samsung,s3c2443-adc" for
+                                the ADC in s3c2443 and compatibles
+                        Must be "samsung,s3c6410-adc" for
+                                the ADC in s3c6410 and compatibles
+- reg:                  List of ADC register address range
+                        - The base address and range of ADC register
+                        - The base address and range of ADC_PHY register (every
+                          SoC except for s3c24xx/s3c64xx ADC)
 - interrupts:           Contains the interrupt information for the timer. The
                        format is being dependent on which interrupt controller
                        the Samsung device uses.
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
new file mode 100644
index 000000000000..51147cb5c036
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -0,0 +1,71 @@
+Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
+--------------------------------------------------------------------
+SoCs:
+  - Emma Mobile EV2
+    compatible = "renesas,emev2"
+  - RZ/A1H (R7S72100)
+    compatible = "renesas,r7s72100"
+  - SH-Mobile AP4 (R8A73720/SH7372)
+    compatible = "renesas,sh7372"
+  - SH-Mobile AG5 (R8A73A00/SH73A0)
+    compatible = "renesas,sh73a0"
+  - R-Mobile APE6 (R8A73A40)
+    compatible = "renesas,r8a73a4"
+  - R-Mobile A1 (R8A77400)
+    compatible = "renesas,r8a7740"
+  - R-Car M1A (R8A77781)
+    compatible = "renesas,r8a7778"
+  - R-Car H1 (R8A77790)
+    compatible = "renesas,r8a7779"
+  - R-Car H2 (R8A77900)
+    compatible = "renesas,r8a7790"
+  - R-Car M2-W (R8A77910)
+    compatible = "renesas,r8a7791"
+  - R-Car V2H (R8A77920)
+    compatible = "renesas,r8a7792"
+  - R-Car M2-N (R8A77930)
+    compatible = "renesas,r8a7793"
+  - R-Car E2 (R8A77940)
+    compatible = "renesas,r8a7794"
+Boards:
+  - Alt
+    compatible = "renesas,alt", "renesas,r8a7794"
+  - APE6-EVM
+    compatible = "renesas,ape6evm", "renesas,r8a73a4"
+  - APE6-EVM - Reference Device Tree Implementation
+    compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
+  - Atmark Techno Armadillo-800 EVA
+    compatible = "renesas,armadillo800eva"
+  - BOCK-W
+    compatible = "renesas,bockw", "renesas,r8a7778"
+  - BOCK-W - Reference Device Tree Implementation
+    compatible = "renesas,bockw-reference", "renesas,r8a7778"
+  - Genmai (RTK772100BC00000BR)
+    compatible = "renesas,genmai", "renesas,r7s72100"
+  - Gose
+    compatible = "renesas,gose", "renesas,r8a7793"
+  - Henninger
+    compatible = "renesas,henninger", "renesas,r8a7791"
+  - Koelsch (RTP0RC7791SEB00010S)
+    compatible = "renesas,koelsch", "renesas,r8a7791"
+  - Kyoto Microcomputer Co. KZM-A9-Dual
+    compatible = "renesas,kzm9d", "renesas,emev2"
+  - Kyoto Microcomputer Co. KZM-A9-GT
+    compatible = "renesas,kzm9g", "renesas,sh73a0"
+  - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
+    compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
+  - Lager (RTP0RC7790SEB00010S)
+    compatible = "renesas,lager", "renesas,r8a7790"
+  - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
+    compatible = "renesas,mackerel"
+  - Marzen
+    compatible = "renesas,marzen", "renesas,r8a7779"
+Note: Reference Device Tree Implementations are temporary implementations
+      to ease the migration from platform devices to Device Tree, and are
+      intended to be removed in the future.
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
new file mode 100644
index 000000000000..ccf0adddc820
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra Flow Controller
+Required properties:
+- compatible: Should be "nvidia,tegra<chip>-flowctrl"
+- reg: Should contain one register range (address and length)
+Example:
+        flow-controller@60007000 {
+                compatible = "nvidia,tegra20-flowctrl";
+                reg = <0x60007000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/ata/qcom-sata.txt b/Documentation/devicetree/bindings/ata/qcom-sata.txt
new file mode 100644
index 000000000000..094de91cd9fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/qcom-sata.txt
@@ -0,0 +1,48 @@
+* Qualcomm AHCI SATA Controller
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+Required properties:
+- compatible            : compatible list, must contain "generic-ahci"
+- interrupts            : <interrupt mapping for SATA IRQ>
+- reg                   : <registers mapping>
+- phys                  : Must contain exactly one entry as specified
+                          in phy-bindings.txt
+- phy-names             : Must be "sata-phy"
+Required properties for "qcom,ipq806x-ahci" compatible:
+- clocks                : Must contain an entry for each entry in clock-names.
+- clock-names           : Shall be:
+                                "slave_iface" - Fabric port AHB clock for SATA
+                                "iface" - AHB clock
+                                "core" - core clock
+                                "rxoob" - RX out-of-band clock
+                                "pmalive" - Power Module Alive clock
+- assigned-clocks       : Shall be:
+                                SATA_RXOOB_CLK
+                                SATA_PMALIVE_CLK
+- assigned-clock-rates  : Shall be:
+                                100Mhz (100000000) for SATA_RXOOB_CLK
+                                100Mhz (100000000) for SATA_PMALIVE_CLK
+Example:
+        sata@29000000 {
+                compatible = "qcom,ipq806x-ahci", "generic-ahci";
+                reg = <0x29000000 0x180>;
+                interrupts = <0 209 0x0>;
+                clocks = <&gcc SFAB_SATA_S_H_CLK>,
+                         <&gcc SATA_H_CLK>,
+                         <&gcc SATA_A_CLK>,
+                         <&gcc SATA_RXOOB_CLK>,
+                         <&gcc SATA_PMALIVE_CLK>;
+                clock-names = "slave_iface", "iface", "core",
+                                "rxoob", "pmalive";
+                assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
+                assigned-clock-rates = <100000000>, <100000000>;
+                phys = <&sata_phy>;
+                phy-names = "sata-phy";
+        };
diff --git a/Documentation/devicetree/bindings/bus/bcma.txt b/Documentation/devicetree/bindings/bus/bcma.txt
new file mode 100644
index 000000000000..62a48348ac15
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/bcma.txt
@@ -0,0 +1,32 @@
+Driver for ARM AXI Bus with Broadcom Plugins (bcma)
+Required properties:
+- compatible : brcm,bus-axi
+- reg : iomem address range of chipcommon core
+The cores on the AXI bus are automatically detected by bcma with the
+memory ranges they are using and they get registered afterwards.
+The top-level axi bus may contain children representing attached cores
+(devices). This is needed since some hardware details can't be auto
+detected (e.g. IRQ numbers). Also some of the cores may be responsible
+for extra things, e.g. ChipCommon providing access to the GPIO chip.
+Example:
+        axi@18000000 {
+                compatible = "brcm,bus-axi";
+                reg = <0x18000000 0x1000>;
+                ranges = <0x00000000 0x18000000 0x00100000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                chipcommon {
+                        reg = <0x00000000 0x1000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt
index ecc69520bcea..11f5f95f571b 100644
--- a/Documentation/devicetree/bindings/clock/arm-integrator.txt
+++ b/Documentation/devicetree/bindings/clock/arm-integrator.txt
@@ -1,6 +1,6 @@
 Clock bindings for ARM Integrator and Versatile Core Module clocks
-Auxilary Oscillator Clock
+Auxiliary Oscillator Clock
 This is a configurable clock fed from a 24 MHz chrystal,
 used for generating e.g. video clocks. It is located on the
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index b3d544ca522a..7a4d4926f44e 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -74,6 +74,9 @@ Required properties:
        "atmel,at91sam9x5-clk-utmi":
                at91 utmi clock
+        "atmel,sama5d4-clk-h32mx":
+                at91 h32mx clock
 Required properties for SCKC node:
 - reg : defines the IO memory reserved for the SCKC.
 - #size-cells : shall be 0 (reg is used to encode clk id).
@@ -447,3 +450,14 @@ For example:
                #clock-cells = <0>;
                clocks = <&main>;
        };
+Required properties for 32 bits bus Matrix clock (h32mx clock):
+- #clock-cells : from common clock binding; shall be set to 0.
+- clocks : shall be the master clock source phandle.
+For example:
+        h32ck: h32mxck {
+                #clock-cells = <0>;
+                compatible = "atmel,sama5d4-clk-h32mx";
+                clocks = <&mck>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
index aadc9c59e2d1..f57d9dd9ea85 100644
--- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt
@@ -7,6 +7,8 @@ Required Properties:
 - compatible: should be one of the following.
  - "samsung,exynos3250-cmu" - controller compatible with Exynos3250 SoC.
+  - "samsung,exynos3250-cmu-dmc" - controller compatible with
+    Exynos3250 SoC for Dynamic Memory Controller domain.
 - reg: physical base address of the controller and length of memory mapped
  region.
@@ -20,7 +22,7 @@ All available clocks are defined as preprocessor macros in
 dt-bindings/clock/exynos3250.h header and can be used in device
 tree sources.
-Example 1: An example of a clock controller node is listed below.
+Example 1: Examples of clock controller nodes are listed below.
        cmu: clock-controller@10030000 {
                compatible = "samsung,exynos3250-cmu";
@@ -28,6 +30,12 @@ Example 1: An example of a clock controller node is listed below.
                #clock-cells = <1>;
        };
+        cmu_dmc: clock-controller@105C0000 {
+                compatible = "samsung,exynos3250-cmu-dmc";
+                reg = <0x105C0000 0x2000>;
+                #clock-cells = <1>;
+        };
 Example 2: UART controller node that consumes the clock generated by the clock
           controller. Refer to the standard clock bindings for information
           about 'clocks' and 'clock-names' property.
diff --git a/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
new file mode 100644
index 000000000000..d3379ff9b84b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
@@ -0,0 +1,21 @@
+Binding for simple gpio gated clock.
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Required properties:
+- compatible : shall be "gpio-gate-clock".
+- #clock-cells : from common clock binding; shall be set to 0.
+- enable-gpios : GPIO reference for enabling and disabling the clock.
+Optional properties:
+- clocks: Maximum of one parent clock is supported.
+Example:
+        clock {
+                compatible = "gpio-gate-clock";
+                clocks = <&parentclk>;
+                #clock-cells = <0>;
+                enable-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/maxim,max77686.txt b/Documentation/devicetree/bindings/clock/maxim,max77686.txt
index 96ce71bbd745..9c40739a661a 100644
--- a/Documentation/devicetree/bindings/clock/maxim,max77686.txt
+++ b/Documentation/devicetree/bindings/clock/maxim,max77686.txt
@@ -9,13 +9,21 @@ The MAX77686 contains three 32.768khz clock outputs that can be controlled
 Following properties should be presend in main device node of the MFD chip.
 Required properties:
- #clock-cells: simple one-cell clock specifier format is used, where the
-  only cell is used as an index of the clock inside the provider. Following
+- #clock-cells: from common clock binding; shall be set to 1.
-  indices are allowed:
+Optional properties:
+- clock-output-names: From common clock binding.
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Following indices are allowed:
    - 0: 32khz_ap clock,
    - 1: 32khz_cp clock,
    - 2: 32khz_pmic clock.
+Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77686.h
+header and can be used in device tree sources.
 Example: Node of the MFD chip
        max77686: max77686@09 {
@@ -34,5 +42,5 @@ Example: Clock consumer node
                compatible = "bar,foo";
                /* ... */
                clock-names = "my-clock";
-                clocks = <&max77686 2>;
+                clocks = <&max77686 MAX77686_CLK_PMIC>;
        };
diff --git a/Documentation/devicetree/bindings/clock/maxim,max77802.txt b/Documentation/devicetree/bindings/clock/maxim,max77802.txt
new file mode 100644
index 000000000000..c6dc7835f06c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/maxim,max77802.txt
@@ -0,0 +1,44 @@
+Binding for Maxim MAX77802 32k clock generator block
+This is a part of device tree bindings of MAX77802 multi-function device.
+More information can be found in bindings/mfd/max77802.txt file.
+The MAX77802 contains two 32.768khz clock outputs that can be controlled
+(gated/ungated) over I2C.
+Following properties should be present in main device node of the MFD chip.
+Required properties:
+- #clock-cells: From common clock binding; shall be set to 1.
+Optional properties:
+- clock-output-names: From common clock binding.
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Following indices are allowed:
+     - 0: 32khz_ap clock,
+     - 1: 32khz_cp clock.
+Clocks are defined as preprocessor macros in dt-bindings/clock/maxim,max77802.h
+header and can be used in device tree sources.
+Example: Node of the MFD chip
+        max77802: max77802@09 {
+                compatible = "maxim,max77802";
+                interrupt-parent = <&wakeup_eint>;
+                interrupts = <26 0>;
+                reg = <0x09>;
+                #clock-cells = <1>;
+                /* ... */
+        };
+Example: Clock consumer node
+        foo@0 {
+                compatible = "bar,foo";
+                /* ... */
+                clock-names = "my-clock";
+                clocks = <&max77802 MAX77802_CLK_32K_AP>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/pxa-clock.txt b/Documentation/devicetree/bindings/clock/pxa-clock.txt
new file mode 100644
index 000000000000..4b4a9024bd99
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/pxa-clock.txt
@@ -0,0 +1,16 @@
+* Clock bindings for Marvell PXA chips
+Required properties:
+- compatible: Should be "marvell,pxa-clocks"
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell (see include/.../pxa-clock.h).
+Examples:
+pxa2xx_clks: pxa2xx_clks@41300004 {
+        compatible = "marvell,pxa-clocks";
+        #clock-cells = <1>;
+        status = "okay";
+};
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 8a92b5fb3540..a5f52238c80d 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -11,9 +11,12 @@ Required Properties:
  - compatible: Must be one of the following
    - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
+    - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
    - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks
+    - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
+    - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
    - "renesas,cpg-mstp-clock" for generic MSTP gate clocks
  - reg: Base address and length of the I/O mapped registers used by the MSTP
    clocks. The first register is the clock control register and is mandatory.
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 7b41c2fe54db..e6ad35b894f9 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -8,6 +8,7 @@ Required Properties:
  - compatible: Must be one of
    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
+    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG
  - reg: Base address and length of the memory resource used by the CPG
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d3a5c3c6d677..ed116df9c3e7 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -46,7 +46,11 @@ Required properties:
        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
        "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
+        "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
+        "allwinner,sun4i-a10-mmc-output-clk" - for the MMC output clock on A10
+        "allwinner,sun4i-a10-mmc-sample-clk" - for the MMC sample clock on A10
        "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
+        "allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
        "allwinner,sun7i-a20-out-clk" - for the external output clocks
        "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
        "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
index 366690cb86a3..e41c98ffbccb 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt
@@ -1,8 +1,8 @@
-Generic CPU0 cpufreq driver
+Generic cpufreq driver
-It is a generic cpufreq driver for CPU0 frequency management.  It
+It is a generic DT based cpufreq driver for frequency management.  It supports
-supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
+both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share
-systems which share clock and voltage across all CPUs.
+clock and voltage across all CPUs.
 Both required and optional properties listed below must be defined
 under node /cpus/cpu@0.
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
index c0a20cd972e3..baf8a3c1b469 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
@@ -1,5 +1,5 @@
 SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
-Currently Freescale powerpc chip C29X is embeded with SEC 6.
+Currently Freescale powerpc chip C29X is embedded with SEC 6.
 SEC 6 device tree binding include:
   -SEC 6 Node
   -Job Ring Node
diff --git a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt b/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
index 9f1d750d76de..61bca509d7b9 100644
--- a/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
+++ b/Documentation/devicetree/bindings/dma/rcar-audmapp.txt
@@ -16,9 +16,9 @@ Example:
 * DMA client
 Required properties:
- dmas:         a list of <[DMA multiplexer phandle] [SRS/DRS value]> pairs,
+- dmas:         a list of <[DMA multiplexer phandle] [SRS << 8 | DRS]> pairs.
-                where SRS/DRS values are fixed handles, specified in the SoC
+                where SRS/DRS are specified in the SoC manual.
-                manual as the value that would be written into the PDMACHCR.
+                It will be written into PDMACHCR as high 16-bit parts.
 - dma-names:    a list of DMA channel names, one per "dmas" entry
 Example:
diff --git a/Documentation/devicetree/bindings/drm/tilcdc/panel.txt b/Documentation/devicetree/bindings/drm/tilcdc/panel.txt
index 9301c330d1a6..4ab9e2300907 100644
--- a/Documentation/devicetree/bindings/drm/tilcdc/panel.txt
+++ b/Documentation/devicetree/bindings/drm/tilcdc/panel.txt
@@ -18,6 +18,10 @@ Required properties:
   Documentation/devicetree/bindings/video/display-timing.txt for display
   timing binding details.
+Optional properties:
+- backlight: phandle of the backlight device attached to the panel
+- enable-gpios: GPIO pin to enable or disable the panel
 Recommended properties:
 - pinctrl-names, pinctrl-0: the pincontrol settings to configure
   muxing properly for pins that connect to TFP410 device
@@ -29,6 +33,9 @@ Example:
                compatible = "ti,tilcdc,panel";
                pinctrl-names = "default";
                pinctrl-0 = <&bone_lcd3_cape_lcd_pins>;
+                backlight = <&backlight>;
+                enable-gpios = <&gpio3 19 0>;
                panel-info {
                        ac-bias           = <255>;
                        ac-bias-intrpt    = <0>;
diff --git a/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt b/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt
new file mode 100644
index 000000000000..6dede7d11532
--- /dev/null
+++ b/Documentation/devicetree/bindings/extcon/extcon-rt8973a.txt
@@ -0,0 +1,25 @@
+* Richtek RT8973A - Micro USB Switch device
+The Richtek RT8973A is Micro USB Switch with OVP and I2C interface. The RT8973A
+is a USB port accessory detector and switch that is optimized to protect low
+voltage system from abnormal high input voltage (up to 28V) and supports high
+speed USB operation. Also, RT8973A support 'auto-configuration' mode.
+If auto-configuration mode is enabled, RT8973A would control internal h/w patch
+for USB D-/D+ switching.
+Required properties:
+- compatible: Should be "richtek,rt8973a-muic"
+- reg: Specifies the I2C slave address of the MUIC block. It should be 0x14
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from rt8973a are delivered to.
+- interrupts: Interrupt specifiers for detection interrupt sources.
+Example:
+        rt8973a@14 {
+                compatible = "richtek,rt8973a-muic";
+                interrupt-parent = <&gpx1>;
+                interrupts = <5 0>;
+                reg = <0x14>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
new file mode 100644
index 000000000000..6c7e6c7302f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt
@@ -0,0 +1,39 @@
+Keystone 2 DSP GPIO controller bindings
+HOST OS userland running on ARM can send interrupts to DSP cores using
+the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
+This is one of the component used by the IPC mechanism used on Keystone SOCs.
+For example TCI6638K2K SoC has 8 DSP GPIO controllers:
+ - 8 for C66x CorePacx CPUs 0-7
+Keystone 2 DSP GPIO controller has specific features:
+- each GPIO can be configured only as output pin;
+- setting GPIO value to 1 causes IRQ generation on target DSP core;
+- reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
+  pending.
+Required Properties:
+- compatible: should be "ti,keystone-dsp-gpio"
+- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
+  access device state control registers and the offset of device's specific
+  registers within device state control registers range.
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be 2.
+Please refer to gpio.txt in this directory for details of the common GPIO
+bindings used by client devices.
+Example:
+        dspgpio0: keystone_dsp_gpio@02620240 {
+                compatible = "ti,keystone-dsp-gpio";
+                ti,syscon-dev = <&devctrl 0x240>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        dsp0: dsp0 {
+                compatible = "linux,rproc-user";
+                ...
+                kick-gpio = <&dspgpio0 27>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
new file mode 100644
index 000000000000..b9a42f294dd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt
@@ -0,0 +1,39 @@
+* NXP PCA953x I2C GPIO multiplexer
+Required properties:
+ - compatible: Has to contain one of the following:
+        nxp,pca9505
+        nxp,pca9534
+        nxp,pca9535
+        nxp,pca9536
+        nxp,pca9537
+        nxp,pca9538
+        nxp,pca9539
+        nxp,pca9554
+        nxp,pca9555
+        nxp,pca9556
+        nxp,pca9557
+        nxp,pca9574
+        nxp,pca9575
+        nxp,pca9698
+        maxim,max7310
+        maxim,max7312
+        maxim,max7313
+        maxim,max7315
+        ti,pca6107
+        ti,tca6408
+        ti,tca6416
+        ti,tca6424
+        exar,xra1202
+Example:
+        gpio@20 {
+                compatible = "nxp,pca9505";
+                reg = <0x20>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pca9505>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-restart.txt b/Documentation/devicetree/bindings/gpio/gpio-restart.txt
new file mode 100644
index 000000000000..af3701bc15c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-restart.txt
@@ -0,0 +1,54 @@
+Drive a GPIO line that can be used to restart the system from a restart
+handler.
+This binding supports level and edge triggered reset.  At driver load
+time, the driver will request the given gpio line and install a restart
+handler. If the optional properties 'open-source' is not found, the GPIO line
+will be driven in the inactive state.  Otherwise its not driven until
+the restart is initiated.
+When the system is restarted, the restart handler will be invoked in
+priority order.  The gpio is configured as an output, and driven active,
+triggering a level triggered reset condition. This will also cause an
+inactive->active edge condition, triggering positive edge triggered
+reset. After a delay specified by active-delay, the GPIO is set to
+inactive, thus causing an active->inactive edge, triggering negative edge
+triggered reset. After a delay specified by inactive-delay, the GPIO
+is driven active again.  After a delay specified by wait-delay, the
+restart handler completes allowing other restart handlers to be attempted.
+Required properties:
+- compatible : should be "gpio-restart".
+- gpios : The GPIO to set high/low, see "gpios property" in
+  Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
+  low to reset the board set it to "Active Low", otherwise set
+  gpio to "Active High".
+Optional properties:
+- open-source : Treat the GPIO as being open source and defer driving
+  it to when the restart is initiated.  If this optional property is not
+  specified, the GPIO is initialized as an output in its inactive state.
+- priority : A priority ranging from 0 to 255 (default 128) according to
+  the following guidelines:
+        0:      Restart handler of last resort, with limited restart
+                capabilities
+        128:    Default restart handler; use if no other restart handler is
+                expected to be available, and/or if restart functionality is
+                sufficient to restart the entire system
+        255:    Highest priority restart handler, will preempt all other
+                restart handlers
+- active-delay: Delay (default 100) to wait after driving gpio active [ms]
+- inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms]
+- wait-delay: Delay (default 3000) to wait after completing restart
+  sequence [ms]
+Examples:
+gpio-restart {
+        compatible = "gpio-restart";
+        gpios = <&gpio 4 0>;
+        priority = <128>;
+        active-delay = <100>;
+        inactive-delay = <100>;
+        wait-delay = <3000>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt
new file mode 100644
index 000000000000..86dbb05e7758
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt
@@ -0,0 +1,22 @@
+APM X-Gene SoC GPIO controller bindings
+This is a gpio controller that is part of the flash controller.
+This gpio controller controls a total of 48 gpios.
+Required properties:
+- compatible: "apm,xgene-gpio" for X-Gene GPIO controller
+- reg: Physical base address and size of the controller's registers
+- #gpio-cells: Should be two.
+        - first cell is the pin number
+        - second cell is used to specify the gpio polarity:
+                0 = active high
+                1 = active low
+- gpio-controller: Marks the device node as a GPIO controller.
+Example:
+        gpio0: gpio0@1701c000 {
+                compatible = "apm,xgene-gpio";
+                reg = <0x0 0x1701c000 0x0 0x40>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 66416261e14d..b2afdb27adeb 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -19,7 +19,7 @@ Required properties:
 - gpio-controller : Marks the device node as a gpio controller.
 - #gpio-cells : Should be one.  It is the pin number.
-Example:
+Example for a MMP platform:
        gpio: gpio@d4019000 {
                compatible = "marvell,mmp-gpio";
@@ -32,6 +32,19 @@ Example:
                #interrupt-cells = <1>;
      };
+Example for a PXA3xx platform:
+        gpio: gpio@40e00000 {
+                compatible = "intel,pxa3xx-gpio";
+                reg = <0x40e00000 0x10000>;
+                interrupt-names = "gpio0", "gpio1", "gpio_mux";
+                interrupts = <8 9 10>;
+                gpio-controller;
+                #gpio-cells = <0x2>;
+                interrupt-controller;
+                #interrupt-cells = <0x2>;
+        };
 * Marvell Orion GPIO Controller
 Required properties:
diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
index 2391e5c41999..fcca8e744f41 100644
--- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
+++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
@@ -25,6 +25,9 @@ Requires node properties:
 - "io-channels" Channel node of ADC to be used for
                conversion.
+Optional node properties:
+- "#thermal-sensor-cells" Used to expose itself to thermal fw.
 Read more about iio bindings at
        Documentation/devicetree/bindings/iio/iio-bindings.txt
diff --git a/Documentation/devicetree/bindings/i2c/ti,bq32k.txt b/Documentation/devicetree/bindings/i2c/ti,bq32k.txt
new file mode 100644
index 000000000000..e204906b9ad3
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/ti,bq32k.txt
@@ -0,0 +1,18 @@
+* TI BQ32000                I2C Serial Real-Time Clock
+Required properties:
+- compatible: Should contain "ti,bq32000".
+- reg: I2C address for chip
+Optional properties:
+- trickle-resistor-ohms : Selected resistor for trickle charger
+       Values usable are 1120 and 20180
+       Should be given if trickle charger should be enabled
+- trickle-diode-disable : Do not use internal trickle charger diode
+       Should be given if internal trickle charger diode should be disabled
+Example:
+       bq32000: rtc@68 {
+               compatible = "ti,bq32000";
+               trickle-resistor-ohms = <1120>;
+               reg = <0x68>;
+       };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 6af570ec53b4..fbde415078e6 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -35,7 +35,6 @@ catalyst,24c32		i2c serial eeprom
 cirrus,cs42l51          Cirrus Logic CS42L51 audio codec
 dallas,ds1307           64 x 8, Serial, I2C Real-Time Clock
 dallas,ds1338           I2C RTC with 56-Byte NV RAM
-dallas,ds1339           I2C Serial Real-Time Clock
 dallas,ds1340           I2C RTC with Trickle Charger
 dallas,ds1374           I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
 dallas,ds1631           High-Precision Digital Thermometer
@@ -44,7 +43,7 @@ dallas,ds1775		Tiny Digital Thermometer and Thermostat
 dallas,ds3232           Extremely Accurate I²C RTC with Integrated Crystal and SRAM
 dallas,ds4510           CPU Supervisor with Nonvolatile Memory and Programmable I/O
 dallas,ds75             Digital Thermometer and Thermostat
-dialog,da9053           DA9053: flexible system level PMIC with multicore support
+dlg,da9053              DA9053: flexible system level PMIC with multicore support
 epson,rx8025            High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
 epson,rx8581            I2C-BUS INTERFACE REAL TIME CLOCK MODULE
 fsl,mag3110             MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
new file mode 100644
index 000000000000..5d3ec1df226d
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -0,0 +1,24 @@
+Rockchip Successive Approximation Register (SAR) A/D Converter bindings
+Required properties:
+- compatible: Should be "rockchip,saradc"
+- reg: physical base address of the controller and length of memory mapped
+       region.
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+              depends on the interrupt controller.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "saradc" for the converter-clock, and "apb_pclk" for
+               the peripheral clock.
+- vref-supply: The regulator supply ADC reference voltage.
+- #io-channel-cells: Should be 1, see ../iio-bindings.txt
+Example:
+        saradc: saradc@2006c000 {
+                compatible = "rockchip,saradc";
+                reg = <0x2006c000 0x100>;
+                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+                clock-names = "saradc", "apb_pclk";
+                #io-channel-cells = <1>;
+                vref-supply = <&vcc18>;
+        };
diff --git a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt
index dcebff1928e1..1a4a43d5c9ea 100644
--- a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt
@@ -9,7 +9,7 @@ Required properties:
 - interrupts: Should contain the interrupt for the device
 - clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
 - clock-names: Must contain "adc", matching entry in the clocks property.
- vref-supply: The regulator supply ADC refrence voltage.
+- vref-supply: The regulator supply ADC reference voltage.
 Example:
 adc0: adc@4003b000 {
diff --git a/Documentation/devicetree/bindings/iio/dac/max5821.txt b/Documentation/devicetree/bindings/iio/dac/max5821.txt
new file mode 100644
index 000000000000..54276ce8c971
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/dac/max5821.txt
@@ -0,0 +1,14 @@
+Maxim max5821 DAC device driver
+Required properties:
+        - compatible: Must be "maxim,max5821"
+        - reg: Should contain the DAC I2C address
+        - vref-supply: Phandle to the vref power supply
+Example:
+        max5821@38 {
+                compatible = "maxim,max5821";
+                reg = <0x38>;
+                vref-supply = <&reg_max5821>;
+        };
diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
index baef432e8369..1852906517ab 100644
--- a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
+++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
@@ -11,10 +11,17 @@ Required properties:
 Optional properties for main touchpad device:
- linux,gpio-keymap: An array of up to 4 entries indicating the Linux
+- linux,gpio-keymap: When enabled, the SPT_GPIOPWN_T19 object sends messages
-    keycode generated by each GPIO. Linux keycodes are defined in
+    on GPIO bit changes. An array of up to 8 entries can be provided
+    indicating the Linux keycode mapped to each bit of the status byte,
+    starting at the LSB. Linux keycodes are defined in
    <dt-bindings/input/input.h>.
+    Note: the numbering of the GPIOs and the bit they start at varies between
+    maXTouch devices. You must either refer to the documentation, or
+    experiment to determine which bit corresponds to which input. Use
+    KEY_RESERVED for unused padding values.
 Example:
        touch@4b {
diff --git a/Documentation/devicetree/bindings/input/ti,drv260x.txt b/Documentation/devicetree/bindings/input/ti,drv260x.txt
new file mode 100644
index 000000000000..ee09c8f4474a
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/ti,drv260x.txt
@@ -0,0 +1,50 @@
+* Texas Instruments - drv260x Haptics driver family
+Required properties:
+        - compatible - One of:
+                "ti,drv2604" - DRV2604
+                "ti,drv2605" - DRV2605
+                "ti,drv2605l" - DRV2605L
+        - reg -  I2C slave address
+        - vbat-supply - Required supply regulator
+        - mode - Power up mode of the chip (defined in include/dt-bindings/input/ti-drv260x.h)
+                DRV260X_LRA_MODE - Linear Resonance Actuator mode (Piezoelectric)
+                DRV260X_LRA_NO_CAL_MODE - This is a LRA Mode but there is no calibration
+                                sequence during init.  And the device is configured for real
+                                time playback mode (RTP mode).
+                DRV260X_ERM_MODE - Eccentric Rotating Mass mode (Rotary vibrator)
+        - library-sel - These are ROM based waveforms pre-programmed into the IC.
+                                This should be set to set the library to use at power up.
+                                (defined in include/dt-bindings/input/ti-drv260x.h)
+                DRV260X_LIB_EMPTY - Do not use a pre-programmed library
+                DRV260X_ERM_LIB_A - Pre-programmed Library
+                DRV260X_ERM_LIB_B - Pre-programmed Library
+                DRV260X_ERM_LIB_C - Pre-programmed Library
+                DRV260X_ERM_LIB_D - Pre-programmed Library
+                DRV260X_ERM_LIB_E - Pre-programmed Library
+                DRV260X_ERM_LIB_F - Pre-programmed Library
+                DRV260X_LIB_LRA - Pre-programmed LRA Library
+Optional properties:
+        - enable-gpio - gpio pin to enable/disable the device.
+        - vib-rated-mv - The rated voltage of the actuator in millivolts.
+                          If this is not set then the value will be defaulted to
+                          3.2 v.
+        - vib-overdrive-mv - The overdrive voltage of the actuator in millivolts.
+                          If this is not set then the value will be defaulted to
+                          3.2 v.
+Example:
+haptics: haptics@5a {
+        compatible = "ti,drv2605l";
+        reg = <0x5a>;
+        vbat-supply = <&vbat>;
+        enable-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+        mode = <DRV260X_LRA_MODE>;
+        library-sel = <DRV260X_LIB_LRA>;
+        vib-rated-mv = <3200>;
+        vib-overdriver-mv = <3200>;
+}
+For more product information please see the link below:
+http://www.ti.com/product/drv2605
diff --git a/Documentation/devicetree/bindings/input/ti,drv2667.txt b/Documentation/devicetree/bindings/input/ti,drv2667.txt
new file mode 100644
index 000000000000..996382cf994a
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/ti,drv2667.txt
@@ -0,0 +1,17 @@
+* Texas Instruments - drv2667 Haptics driver
+Required properties:
+        - compatible - "ti,drv2667" - DRV2667
+        - reg -  I2C slave address
+        - vbat-supply - Required supply regulator
+Example:
+haptics: haptics@59 {
+        compatible = "ti,drv2667";
+        reg = <0x59>;
+        vbat-supply = <&vbat>;
+};
+For more product information please see the link below:
+http://www.ti.com/product/drv2667
diff --git a/Documentation/devicetree/bindings/input/ti,palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/ti,palmas-pwrbutton.txt
new file mode 100644
index 000000000000..a3dde8c30e67
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/ti,palmas-pwrbutton.txt
@@ -0,0 +1,36 @@
+Texas Instruments Palmas family power button module
+This module is part of the Palmas family of PMICs. For more details
+about the whole chip see:
+Documentation/devicetree/bindings/mfd/palmas.txt.
+This module provides a simple power button event via an Interrupt.
+Required properties:
+- compatible: should be one of the following
+   - "ti,palmas-pwrbutton": For Palmas compatible power on button
+- interrupt-parent: Parent interrupt device, must be handle of palmas node.
+- interrupts: Interrupt number of power button submodule on device.
+Optional Properties:
+- ti,palmas-long-press-seconds: Duration in seconds which the power
+  button should be kept pressed for Palmas to power off automatically.
+  NOTE: This depends on OTP support and POWERHOLD signal configuration
+  on platform. Valid values are 6, 8, 10 and 12.
+- ti,palmas-pwron-debounce-milli-seconds: Duration in milliseconds
+  which the power button should be kept pressed for Palmas to register
+  a press for debouncing purposes. NOTE: This depends on specific
+  Palmas variation capability. Valid values are 15, 100, 500 and 1000.
+Example:
+&palmas {
+        palmas_pwr_button: pwrbutton {
+                compatible = "ti,palmas-pwrbutton";
+                interrupt-parent = <&tps659038>;
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                ti,palmas-long-press-seconds = <12>;
+                ti,palmas-pwron-debounce-milli-seconds = <15>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
index 2742e9cfd6b1..f292917fa00d 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
@@ -2,7 +2,7 @@
 Required properties:
 - compatible: Should be "atmel,<chip>-aic"
-  <chip> can be "at91rm9200" or "sama5d3"
+  <chip> can be "at91rm9200", "sama5d3" or "sama5d4"
 - interrupt-controller: Identifies the node as an interrupt controller.
 - interrupt-parent: For single AIC system, it is an empty property.
 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
new file mode 100644
index 000000000000..ff812a8a82bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
@@ -0,0 +1,86 @@
+Broadcom BCM7120-style Level 2 interrupt controller
+This interrupt controller hardware is a second level interrupt controller that
+is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+platforms. It can be found on BCM7xxx products starting with BCM7120.
+Such an interrupt controller has the following hardware design:
+- outputs multiple interrupts signals towards its interrupt controller parent
+- controls how some of the interrupts will be flowing, whether they will
+  directly output an interrupt signal towards the interrupt controller parent,
+  or if they will output an interrupt signal at this 2nd level interrupt
+  controller, in particular for UARTs
+- not all 32-bits within the interrupt controller actually map to an interrupt
+The typical hardware layout for this controller is represented below:
+2nd level interrupt line                Outputs for the parent controller (e.g: ARM GIC)
+0 -----[ MUX ] ------------|==========> GIC interrupt 75
+          \-----------\
+                       |
+1 -----[ MUX ] --------)---|==========> GIC interrupt 76
+          \------------|
+                       |
+2 -----[ MUX ] --------)---|==========> GIC interrupt 77
+          \------------|
+                       |
+3 ---------------------|
+4 ---------------------|
+5 ---------------------|
+7 ---------------------|---|===========> GIC interrupt 66
+9 ---------------------|
+10 --------------------|
+11 --------------------/
+6 ------------------------\
+                           |===========> GIC interrupt 64
+8 ------------------------/
+12 ........................ X
+13 ........................ X           (not connected)
+..
+31 ........................ X
+Required properties:
+- compatible: should be "brcm,bcm7120-l2-intc"
+- reg: specifies the base physical address and size of the registers
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+  source, should be 1.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+  this one is cascaded from
+- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
+  node, valid values depend on the type of parent interrupt controller
+- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
+  are wired to this 2nd level interrupt controller, and how they match their
+  respective interrupt parents. Should match exactly the number of interrupts
+  specified in the 'interrupts' property.
+Optional properties:
+- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
+  wakeup source for system suspend/resume.
+- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the
+  interrupts which have a mux gate, typically UARTs. Setting these bits will
+  make their respective interrupts outputs bypass this 2nd level interrupt
+  controller completely, it completely transparent for the interrupt controller
+  parent
+Example:
+irq0_intc: interrupt-controller@f0406800 {
+        compatible = "brcm,bcm7120-l2-intc";
+        interrupt-parent = <&intc>;
+        #interrupt-cells = <1>;
+        reg = <0xf0406800 0x8>;
+        interrupt-controller;
+        interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+        brcm,int-map-mask = <0xeb8>, <0x140>;
+        brcm,int-fwd-mask = <0x7>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
index 1486497a24c1..ce6a1a072028 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
@@ -4,11 +4,13 @@ Specifying interrupt information for devices
 1) Interrupt client nodes
 -------------------------
-Nodes that describe devices which generate interrupts must contain an either an
+Nodes that describe devices which generate interrupts must contain an
-"interrupts" property or an "interrupts-extended" property. These properties
+"interrupts" property, an "interrupts-extended" property, or both. If both are
-contain a list of interrupt specifiers, one per output interrupt. The format of
+present, the latter should take precedence; the former may be provided simply
-the interrupt specifier is determined by the interrupt controller to which the
+for compatibility with software that does not recognize the latter. These
-interrupts are routed; see section 2 below for details.
+properties contain a list of interrupt specifiers, one per output interrupt. The
+format of the interrupt specifier is determined by the interrupt controller to
+which the interrupts are routed; see section 2 below for details.
  Example:
        interrupt-parent = <&intc1>;
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
index 1f8b0c507c26..c73acd060093 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -2,7 +2,13 @@ DT bindings for the R-/SH-Mobile irqpin controller
 Required properties:
- compatible: has to be "renesas,intc-irqpin"
+- compatible: has to be "renesas,intc-irqpin-<soctype>", "renesas,intc-irqpin"
+  as fallback.
+  Examples with soctypes are:
+    - "renesas,intc-irqpin-r8a7740" (R-Mobile A1)
+    - "renesas,intc-irqpin-r8a7778" (R-Car M1A)
+    - "renesas,intc-irqpin-r8a7779" (R-Car H1)
+    - "renesas,intc-irqpin-sh73a0" (SH-Mobile AG5)
 - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
  interrupts.txt in this directory
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
new file mode 100644
index 000000000000..1a88e62228e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
@@ -0,0 +1,32 @@
+DT bindings for the R-Mobile/R-Car interrupt controller
+Required properties:
+- compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
+  Examples with soctypes are:
+    - "renesas,irqc-r8a73a4" (R-Mobile AP6)
+    - "renesas,irqc-r8a7790" (R-Car H2)
+    - "renesas,irqc-r8a7791" (R-Car M2-W)
+    - "renesas,irqc-r8a7792" (R-Car V2H)
+    - "renesas,irqc-r8a7793" (R-Car M2-N)
+    - "renesas,irqc-r8a7794" (R-Car E2)
+- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
+  interrupts.txt in this directory
+Optional properties:
+- any properties, listed in interrupts.txt, and any standard resource allocation
+  properties
+Example:
+        irqc0: interrupt-controller@e61c0000 {
+                compatible = "renesas,irqc-r8a7790", "renesas,irqc";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0 0xe61c0000 0 0x200>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 3 IRQ_TYPE_LEVEL_HIGH>;
+        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
new file mode 100644
index 000000000000..d9bb106bdd16
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,keystone-irq.txt
@@ -0,0 +1,36 @@
+Keystone 2 IRQ controller IP
+On Keystone SOCs, DSP cores can send interrupts to ARM
+host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
+The IRQ handler running on HOST OS can identify DSP signal source by
+analyzing SRCCx bits in IPCARx registers. This is one of the component
+used by the IPC mechanism used on Keystone SOCs.
+Required Properties:
+- compatible: should be "ti,keystone-irq"
+- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
+                        access device control registers and the offset inside
+                        device control registers range.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode interrupt
+                                         source should be 1.
+- interrupts: interrupt reference to primary interrupt controller
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+Example:
+        kirq0: keystone_irq0@026202a0 {
+                compatible = "ti,keystone-irq";
+                ti,syscon-dev = <&devctrl 0x2a0>;
+                interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+        dsp0: dsp0 {
+                compatible = "linux,rproc-user";
+                ...
+                interrupt-parent = <&kirq0>;
+                interrupts = <10 2>;
+        };
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 2d0f7cd867ea..06760503a819 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -14,6 +14,7 @@ conditions.
                        "arm,smmu-v1"
                        "arm,smmu-v2"
                        "arm,mmu-400"
+                        "arm,mmu-401"
                        "arm,mmu-500"
                  depending on the particular implementation and/or the
diff --git a/Documentation/devicetree/bindings/leds/register-bit-led.txt b/Documentation/devicetree/bindings/leds/register-bit-led.txt
new file mode 100644
index 000000000000..379cefdc0bda
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/register-bit-led.txt
@@ -0,0 +1,99 @@
+Device Tree Bindings for Register Bit LEDs
+Register bit leds are used with syscon multifunctional devices
+where single bits in a certain register can turn on/off a
+single LED. The register bit LEDs appear as children to the
+syscon device, with the proper compatible string. For the
+syscon bindings see:
+Documentation/devicetree/bindings/mfd/syscon.txt
+Each LED is represented as a sub-node of the syscon device. Each
+node's name represents the name of the corresponding LED.
+LED sub-node properties:
+Required properties:
+- compatible : must be "register-bit-led"
+- offset : register offset to the register controlling this LED
+- mask : bit mask for the bit controlling this LED in the register
+  typically 0x01, 0x02, 0x04 ...
+Optional properties:
+- label : (optional)
+  see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+  see Documentation/devicetree/bindings/leds/common.txt
+- default-state: (optional) The initial state of the LED. Valid
+  values are "on", "off", and "keep". If the LED is already on or off
+  and the default-state property is set the to same value, then no
+  glitch should be produced where the LED momentarily turns off (or
+  on). The "keep" setting will keep the LED at whatever its current
+  state is, without producing a glitch.  The default is off if this
+  property is not present.
+Example:
+syscon: syscon@10000000 {
+        compatible = "arm,realview-pb1176-syscon", "syscon";
+        reg = <0x10000000 0x1000>;
+        led@08.0 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x01>;
+                label = "versatile:0";
+                linux,default-trigger = "heartbeat";
+                default-state = "on";
+        };
+        led@08.1 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x02>;
+                label = "versatile:1";
+                linux,default-trigger = "mmc0";
+                default-state = "off";
+        };
+        led@08.2 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x04>;
+                label = "versatile:2";
+                linux,default-trigger = "cpu0";
+                default-state = "off";
+        };
+        led@08.3 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x08>;
+                label = "versatile:3";
+                default-state = "off";
+        };
+        led@08.4 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x10>;
+                label = "versatile:4";
+                default-state = "off";
+        };
+        led@08.5 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x20>;
+                label = "versatile:5";
+                default-state = "off";
+        };
+        led@08.6 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x40>;
+                label = "versatile:6";
+                default-state = "off";
+        };
+        led@08.7 {
+                compatible = "register-bit-led";
+                offset = <0x08>;
+                mask = <0x80>;
+                label = "versatile:7";
+                default-state = "off";
+        };
+};
diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
new file mode 100644
index 000000000000..48edc4b92afb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
@@ -0,0 +1,108 @@
+OMAP2+ Mailbox Driver
+=====================
+The OMAP mailbox hardware facilitates communication between different processors
+using a queued mailbox interrupt mechanism. The IP block is external to the
+various processor subsystems and is connected on an interconnect bus. The
+communication is achieved through a set of registers for message storage and
+interrupt configuration registers.
+Each mailbox IP block has a certain number of h/w fifo queues and output
+interrupt lines. An output interrupt line is routed to an interrupt controller
+within a processor subsystem, and there can be more than one line going to a
+specific processor's interrupt controller. The interrupt line connections are
+fixed for an instance and are dictated by the IP integration into the SoC
+(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
+programmable through a set of interrupt configuration registers, and have a rx
+and tx interrupt source per h/w fifo. Communication between different processors
+is achieved through the appropriate programming of the rx and tx interrupt
+sources on the appropriate interrupt lines.
+The number of h/w fifo queues and interrupt lines dictate the usable registers.
+All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
+instance. DRA7xx has multiple instances with different number of h/w fifo queues
+and interrupt lines between different instances. The interrupt lines can also be
+routed to different processor sub-systems on DRA7xx as they are routed through
+the Crossbar, a kind of interrupt router/multiplexer.
+Mailbox Device Node:
+====================
+A Mailbox device node is used to represent a Mailbox IP instance within a SoC.
+The sub-mailboxes are represented as child nodes of this parent node.
+Required properties:
+--------------------
+- compatible:           Should be one of the following,
+                            "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
+                            "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
+                            "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
+                                                   AM43xx and DRA7xx SoCs
+- reg:                  Contains the mailbox register address range (base
+                        address and length)
+- interrupts:           Contains the interrupt information for the mailbox
+                        device. The format is dependent on which interrupt
+                        controller the OMAP device uses
+- ti,hwmods:            Name of the hwmod associated with the mailbox
+- ti,mbox-num-users:    Number of targets (processor devices) that the mailbox
+                        device can interrupt
+- ti,mbox-num-fifos:    Number of h/w fifo queues within the mailbox IP block
+Child Nodes:
+============
+A child node is used for representing the actual sub-mailbox device that is
+used for the communication between the host processor and a remote processor.
+Each child node should have a unique node name across all the different
+mailbox device nodes.
+Required properties:
+--------------------
+- ti,mbox-tx:           sub-mailbox descriptor property defining a Tx fifo
+- ti,mbox-rx:           sub-mailbox descriptor property defining a Rx fifo
+Sub-mailbox Descriptor Data
+---------------------------
+Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
+data that represent the following:
+    Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
+                        (ti,mbox-tx) or for receiving (ti,mbox-rx)
+    Cell #2 (irq_id)  - irq identifier index number to use from the parent's
+                        interrupts data. Should be 0 for most of the cases, a
+                        positive index value is seen only on mailboxes that have
+                        multiple interrupt lines connected to the MPU processor.
+    Cell #3 (usr_id)  - mailbox user id for identifying the interrupt line
+                        associated with generating a tx/rx fifo interrupt.
+Example:
+--------
+/* OMAP4 */
+mailbox: mailbox@4a0f4000 {
+        compatible = "ti,omap4-mailbox";
+        reg = <0x4a0f4000 0x200>;
+        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+        ti,hwmods = "mailbox";
+        ti,mbox-num-users = <3>;
+        ti,mbox-num-fifos = <8>;
+        mbox_ipu: mbox_ipu {
+                ti,mbox-tx = <0 0 0>;
+                ti,mbox-rx = <1 0 0>;
+        };
+        mbox_dsp: mbox_dsp {
+                ti,mbox-tx = <3 0 0>;
+                ti,mbox-rx = <2 0 0>;
+        };
+};
+/* AM33xx */
+mailbox: mailbox@480C8000 {
+        compatible = "ti,omap4-mailbox";
+        reg = <0x480C8000 0x200>;
+        interrupts = <77>;
+        ti,hwmods = "mailbox";
+        ti,mbox-num-users = <4>;
+        ti,mbox-num-fifos = <8>;
+        mbox_wkupm3: wkup_m3 {
+                ti,mbox-tx = <0 0 0>;
+                ti,mbox-rx = <0 0 3>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
new file mode 100644
index 000000000000..fb5e7606643a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
@@ -0,0 +1,25 @@
+Device-Tree bindings for hix5hd2 ir IP
+Required properties:
+        - compatible: Should contain "hisilicon,hix5hd2-ir".
+        - reg: Base physical address of the controller and length of memory
+          mapped region.
+        - interrupts: interrupt-specifier for the sole interrupt generated by
+          the device. The interrupt specifier format depends on the interrupt
+          controller parent.
+        - clocks: clock phandle and specifier pair.
+        - hisilicon,power-syscon: phandle of syscon used to control power.
+Optional properties:
+        - linux,rc-map-name : Remote control map name.
+Example node:
+        ir: ir@f8001000 {
+                compatible = "hisilicon,hix5hd2-ir";
+                reg = <0xf8001000 0x1000>;
+                interrupts = <0 47 4>;
+                clocks = <&clock HIX5HD2_FIXED_24M>;
+                hisilicon,power-syscon = <&sysctrl>;
+                linux,rc-map-name = "rc-tivo";
+        };
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
new file mode 100644
index 000000000000..f9c6454146b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
@@ -0,0 +1,11 @@
+Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
+Required properties:
+ - compatible: Should be 'xlnx,zynq-ddrc-a05'
+ - reg: Base address and size of the controllers memory area
+Example:
+        memory-controller@f8006000 {
+                compatible = "xlnx,zynq-ddrc-a05";
+                reg = <0xf8006000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt
index 5c7e7230984a..7bd1273f571a 100644
--- a/Documentation/devicetree/bindings/mfd/arizona.txt
+++ b/Documentation/devicetree/bindings/mfd/arizona.txt
@@ -42,6 +42,13 @@ Optional properties:
    the chip default will be used.  If present exactly five values must
    be specified.
+  - wlf,inmode : A list of INn_MODE register values, where n is the number
+    of input signals. Valid values are 0 (Differential), 1 (Single-ended) and
+    2 (Digital Microphone). If absent, INn_MODE registers set to 0 by default.
+    If present, values must be specified less than or equal to the number of
+    input singals. If values less than the number of input signals, elements
+    that has not been specifed are set to 0 by default.
  - DCVDD-supply, MICVDD-supply : Power supplies, only need to be specified if
    they are being externally supplied. As covered in
    Documentation/devicetree/bindings/regulator/regulator.txt
diff --git a/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
new file mode 100644
index 000000000000..a28569540683
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/atmel-gpbr.txt
@@ -0,0 +1,15 @@
+* Device tree bindings for Atmel GPBR (General Purpose Backup Registers)
+The GPBR are a set of battery-backed registers.
+Required properties:
+- compatible:           "atmel,at91sam9260-gpbr", "syscon"
+- reg:                  contains offset/length value of the GPBR memory
+                        region.
+Example:
+gpbr: gpbr@fffffd50 {
+        compatible = "atmel,at91sam9260-gpbr", "syscon";
+        reg = <0xfffffd50 0x10>;
+};
diff --git a/Documentation/devicetree/bindings/mfd/hi6421.txt b/Documentation/devicetree/bindings/mfd/hi6421.txt
new file mode 100644
index 000000000000..0d5a4466a494
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/hi6421.txt
@@ -0,0 +1,38 @@
+* HI6421 Multi-Functional Device (MFD), by HiSilicon Ltd.
+Required parent device properties:
+- compatible    : contains "hisilicon,hi6421-pmic";
+- reg           : register range space of hi6421;
+Supported Hi6421 sub-devices include:
+Device                     IRQ Names              Supply Names   Description
+------                     ---------              ------------   -----------
+regulators               :  None                 : None         : Regulators
+Required child device properties:
+None.
+Example:
+        hi6421 {
+                compatible = "hisilicon,hi6421-pmic";
+                reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */
+                regulators {
+                        // supply for MLC NAND/ eMMC
+                        hi6421_vout0_reg: hi6421_vout0 {
+                                regulator-name = "VOUT0";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                        };
+                        // supply for 26M Oscillator
+                        hi6421_vout1_reg: hi6421_vout1 {
+                                regulator-name = "VOUT1";
+                                regulator-min-microvolt = <1700000>;
+                                regulator-max-microvolt = <2000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/max14577.txt b/Documentation/devicetree/bindings/mfd/max14577.txt
new file mode 100644
index 000000000000..236264c10b92
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max14577.txt
@@ -0,0 +1,146 @@
+Maxim MAX14577/77836 Multi-Function Device
+MAX14577 is a Multi-Function Device with Micro-USB Interface Circuit, Li+
+Battery Charger and SFOUT LDO output for powering USB devices. It is
+interfaced to host controller using I2C.
+MAX77836 additionally contains PMIC (with two LDO regulators) and Fuel Gauge.
+Required properties:
+- compatible : Must be "maxim,max14577" or "maxim,max77836".
+- reg : I2C slave address for the max14577 chip (0x25 for max14577/max77836)
+- interrupts : IRQ line for the chip.
+- interrupt-parent :  The parent interrupt controller.
+Required nodes:
+ - charger :
+        Node for configuring the charger driver.
+        Required properties:
+                - compatible : "maxim,max14577-charger"
+                        or "maxim,max77836-charger"
+                - maxim,fast-charge-uamp : Current in uA for Fast Charge;
+                        Valid values:
+                        - for max14577: 90000 - 950000;
+                        - for max77836: 45000 - 475000;
+                - maxim,eoc-uamp : Current in uA for End-Of-Charge mode;
+                        Valid values:
+                        - for max14577: 50000 - 200000;
+                        - for max77836: 5000 - 100000;
+                - maxim,ovp-uvolt : OverVoltage Protection Threshold in uV;
+                        In an overvoltage condition, INT asserts and charging
+                        stops. Valid values:
+                        - 6000000, 6500000, 7000000, 7500000;
+                - maxim,constant-uvolt : Battery Constant Voltage in uV;
+                        Valid values:
+                        - 4000000 - 4280000 (step by 20000);
+                        - 4350000;
+Optional nodes:
+- max14577-muic/max77836-muic :
+        Node used only by extcon consumers.
+        Required properties:
+                - compatible : "maxim,max14577-muic" or "maxim,max77836-muic"
+- regulators :
+        Required properties:
+                - compatible : "maxim,max14577-regulator"
+                        or "maxim,max77836-regulator"
+        May contain a sub-node per regulator from the list below. Each
+        sub-node should contain the constraints and initialization information
+        for that regulator. See regulator.txt for a description of standard
+        properties for these sub-nodes.
+        List of valid regulator names:
+        - for max14577: CHARGER, SAFEOUT.
+        - for max77836: CHARGER, SAFEOUT, LDO1, LDO2.
+        The SAFEOUT is a fixed voltage regulator so there is no need to specify
+        voltages for it.
+Example:
+#include <dt-bindings/interrupt-controller/irq.h>
+max14577@25 {
+        compatible = "maxim,max14577";
+        reg = <0x25>;
+        interrupt-parent = <&gpx1>;
+        interrupts = <5 IRQ_TYPE_NONE>;
+        muic: max14577-muic {
+                compatible = "maxim,max14577-muic";
+        };
+        regulators {
+                compatible = "maxim,max14577-regulator";
+                SAFEOUT {
+                        regulator-name = "SAFEOUT";
+                };
+                CHARGER {
+                        regulator-name = "CHARGER";
+                        regulator-min-microamp = <90000>;
+                        regulator-max-microamp = <950000>;
+                        regulator-boot-on;
+                };
+        };
+        charger {
+                compatible = "maxim,max14577-charger";
+                maxim,constant-uvolt = <4350000>;
+                maxim,fast-charge-uamp = <450000>;
+                maxim,eoc-uamp = <50000>;
+                maxim,ovp-uvolt = <6500000>;
+        };
+};
+max77836@25 {
+        compatible = "maxim,max77836";
+        reg = <0x25>;
+        interrupt-parent = <&gpx1>;
+        interrupts = <5 IRQ_TYPE_NONE>;
+        muic: max77836-muic {
+                compatible = "maxim,max77836-muic";
+        };
+        regulators {
+                compatible = "maxim,max77836-regulator";
+                SAFEOUT {
+                        regulator-name = "SAFEOUT";
+                };
+                CHARGER {
+                        regulator-name = "CHARGER";
+                        regulator-min-microamp = <90000>;
+                        regulator-max-microamp = <950000>;
+                        regulator-boot-on;
+                };
+                LDO1 {
+                        regulator-name = "LDO1";
+                        regulator-min-microvolt = <2700000>;
+                        regulator-max-microvolt = <2700000>;
+                };
+                LDO2 {
+                        regulator-name = "LDO2";
+                        regulator-min-microvolt = <800000>;
+                        regulator-max-microvolt = <3950000>;
+                };
+        };
+        charger {
+                compatible = "maxim,max77836-charger";
+                maxim,constant-uvolt = <4350000>;
+                maxim,fast-charge-uamp = <225000>;
+                maxim,eoc-uamp = <7500>;
+                maxim,ovp-uvolt = <6500000>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
new file mode 100644
index 000000000000..7182b8857f57
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
@@ -0,0 +1,64 @@
+          Qualcomm SPMI PMICs multi-function device bindings
+The Qualcomm SPMI series presently includes PM8941, PM8841 and PMA8084
+PMICs.  These PMICs use a QPNP scheme through SPMI interface.
+QPNP is effectively a partitioning scheme for dividing the SPMI extended
+register space up into logical pieces, and set of fixed register
+locations/definitions within these regions, with some of these regions
+specifically used for interrupt handling.
+The QPNP PMICs are used with the Qualcomm Snapdragon series SoCs, and are
+interfaced to the chip via the SPMI (System Power Management Interface) bus.
+Support for multiple independent functions are implemented by splitting the
+16-bit SPMI slave address space into 256 smaller fixed-size regions, 256 bytes
+each. A function can consume one or more of these fixed-size register regions.
+Required properties:
+- compatible:      Should contain one of:
+                     "qcom,pm8941"
+                     "qcom,pm8841"
+                     "qcom,pma8084"
+                     or generalized "qcom,spmi-pmic".
+- reg:             Specifies the SPMI USID slave address for this device.
+                   For more information see:
+                   Documentation/devicetree/bindings/spmi/spmi.txt
+Required properties for peripheral child nodes:
+- compatible:      Should contain "qcom,xxx", where "xxx" is a peripheral name.
+Optional properties for peripheral child nodes:
+- interrupts:      Interrupts are specified as a 4-tuple. For more information
+                   see:
+                   Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
+- interrupt-names: Corresponding interrupt name to the interrupts property
+Each child node of SPMI slave id represents a function of the PMIC. In the
+example below the rtc device node represents a peripheral of pm8941
+SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
+Example:
+        spmi {
+                compatible = "qcom,spmi-pmic-arb";
+                pm8941@0 {
+                        compatible = "qcom,pm8941", "qcom,spmi-pmic";
+                        reg = <0x0 SPMI_USID>;
+                        rtc {
+                                compatible = "qcom,rtc";
+                                interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+                                interrupt-names = "alarm";
+                        };
+                };
+                pm8941@1 {
+                        compatible = "qcom,pm8941", "qcom,spmi-pmic";
+                        reg = <0x1 SPMI_USID>;
+                        regulator {
+                                compatible = "qcom,regulator";
+                                regulator-name = "8941_boost";
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
index 03518dc8b6bd..f24f33409164 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
+++ b/Documentation/devicetree/bindings/mfd/qcom-pm8xxx.txt
@@ -61,6 +61,7 @@ The below bindings specify the set of valid subnodes.
        Definition: must be one of:
                    "qcom,pm8058-rtc"
                    "qcom,pm8921-rtc"
+                    "qcom,pm8941-rtc"
 - reg:
        Usage: required
diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt
new file mode 100644
index 000000000000..9e6e2592e5c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/rk808.txt
@@ -0,0 +1,177 @@
+RK808 Power Management Integrated Circuit
+Required properties:
+- compatible: "rockchip,rk808"
+- reg: I2C slave address
+- interrupt-parent: The parent interrupt controller.
+- interrupts: the interrupt outputs of the controller.
+- #clock-cells: from common clock binding; shall be set to 1 (multiple clock
+  outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
+Optional properties:
+- clock-output-names: From common clock binding to override the
+  default output clock name
+- rockchip,system-power-controller: Telling whether or not this pmic is controlling
+  the system power.
+- vcc1-supply:  The input supply for DCDC_REG1
+- vcc2-supply:  The input supply for DCDC_REG2
+- vcc3-supply:  The input supply for DCDC_REG3
+- vcc4-supply:  The input supply for DCDC_REG4
+- vcc6-supply:  The input supply for LDO_REG1 and LDO_REG2
+- vcc7-supply:  The input supply for LDO_REG3 and LDO_REG7
+- vcc8-supply:  The input supply for SWITCH_REG1
+- vcc9-supply:  The input supply for LDO_REG4 and LDO_REG5
+- vcc10-supply: The input supply for LDO_REG6
+- vcc11-supply: The input supply for LDO_REG8
+- vcc12-supply: The input supply for SWITCH_REG2
+Regulators: All the regulators of RK808 to be instantiated shall be
+listed in a child node named 'regulators'. Each regulator is represented
+by a child node of the 'regulators' node.
+        regulator-name {
+                /* standard regulator bindings here */
+        };
+Following regulators of the RK808 PMIC block are supported. Note that
+the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO
+number as described in RK808 datasheet.
+        - DCDC_REGn
+                - valid values for n are 1 to 4.
+        - LDO_REGn
+                - valid values for n are 1 to 8.
+        - SWITCH_REGn
+                - valid values for n are 1 to 2
+Standard regulator bindings are used inside regulator subnodes. Check
+  Documentation/devicetree/bindings/regulator/regulator.txt
+for more details
+Example:
+        rk808: pmic@1b {
+                compatible = "rockchip,rk808";
+                clock-output-names = "xin32k", "rk808-clkout2";
+                interrupt-parent = <&gpio0>;
+                interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pmic_int>;
+                reg = <0x1b>;
+                rockchip,system-power-controller;
+                wakeup-source;
+                #clock-cells = <1>;
+                vcc8-supply = <&vcc_18>;
+                vcc9-supply = <&vcc_io>;
+                vcc10-supply = <&vcc_io>;
+                vcc12-supply = <&vcc_io>;
+                vddio-supply = <&vccio_pmu>;
+                regulators {
+                        vdd_cpu: DCDC_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <750000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-name = "vdd_arm";
+                        };
+                        vdd_gpu: DCDC_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <850000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-name = "vdd_gpu";
+                        };
+                        vcc_ddr: DCDC_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_ddr";
+                        };
+                        vcc_io: DCDC_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_io";
+                        };
+                        vccio_pmu: LDO_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_pmu";
+                        };
+                        vcc_tp: LDO_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc_tp";
+                        };
+                        vdd_10: LDO_REG3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd_10";
+                        };
+                        vcc18_lcd: LDO_REG4 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc18_lcd";
+                        };
+                        vccio_sd: LDO_REG5 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vccio_sd";
+                        };
+                        vdd10_lcd: LDO_REG6 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-name = "vdd10_lcd";
+                        };
+                        vcc_18: LDO_REG7 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc_18";
+                        };
+                        vcca_codec: LDO_REG8 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcca_codec";
+                        };
+                        vcc_wl: SWITCH_REG1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_wl";
+                        };
+                        vcc_lcd: SWITCH_REG2 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-name = "vcc_lcd";
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/rn5t618.txt b/Documentation/devicetree/bindings/mfd/rn5t618.txt
new file mode 100644
index 000000000000..937785a3eddc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/rn5t618.txt
@@ -0,0 +1,36 @@
+* Ricoh RN5T618 PMIC
+Ricoh RN5T618 is a power management IC which integrates 3 step-down
+DCDC converters, 7 low-dropout regulators, a Li-ion battery charger,
+fuel gauge, ADC, GPIOs and a watchdog timer. It can be controlled
+through a I2C interface.
+Required properties:
+ - compatible: should be "ricoh,rn5t618"
+ - reg: the I2C slave address of the device
+Sub-nodes:
+ - regulators: the node is required if the regulator functionality is
+   needed. The valid regulator names are: DCDC1, DCDC2, DCDC3, LDO1,
+   LDO2, LDO3, LDO4, LDO5, LDORTC1 and LDORTC2.
+   The common bindings for each individual regulator can be found in:
+   Documentation/devicetree/bindings/regulator/regulator.txt
+Example:
+        pmic@32 {
+                compatible = "ricoh,rn5t618";
+                reg = <0x32>;
+                regulators {
+                        DCDC1 {
+                                regulator-min-microvolt = <1050000>;
+                                regulator-max-microvolt = <1050000>;
+                        };
+                        DCDC2 {
+                                regulator-min-microvolt = <1175000>;
+                                regulator-max-microvolt = <1175000>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt
index ba2d7f0f9c5f..0e4026a6cbbf 100644
--- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
+++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
@@ -47,7 +47,7 @@ sub-node should be of the format as listed below.
 regulator-ramp-delay for BUCKs = [6250/12500/25000(default)/50000] uV/us
- BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explictly
+ BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explicitly
 regulator-ramp-delay = <0> can be used for them to disable ramp delay.
 In the absence of the regulator-ramp-delay property, the default ramp
 delay will be used.
diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt
index 56edb5520685..3fb68bfefc8b 100644
--- a/Documentation/devicetree/bindings/mfd/stmpe.txt
+++ b/Documentation/devicetree/bindings/mfd/stmpe.txt
@@ -13,6 +13,7 @@ Optional properties:
 - interrupt-parent             : Specifies which IRQ controller we're connected to
 - wakeup-source                : Marks the input device as wakable
 - st,autosleep-timeout         : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
+ - irq-gpio                     : If present, which GPIO to use for event IRQ
 Example:
diff --git a/Documentation/devicetree/bindings/mfd/tc3589x.txt b/Documentation/devicetree/bindings/mfd/tc3589x.txt
new file mode 100644
index 000000000000..6fcedba46ae9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/tc3589x.txt
@@ -0,0 +1,107 @@
+* Toshiba TC3589x multi-purpose expander
+The Toshiba TC3589x series are I2C-based MFD devices which may expose the
+following built-in devices: gpio, keypad, rotator (vibrator), PWM (for
+e.g. LEDs or vibrators) The included models are:
+- TC35890
+- TC35892
+- TC35893
+- TC35894
+- TC35895
+- TC35896
+Required properties:
+ - compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",
+   "toshiba,tc35894", "toshiba,tc35895" or "toshiba,tc35896"
+ - reg : I2C address of the device
+ - interrupt-parent : specifies which IRQ controller we're connected to
+ - interrupts : the interrupt on the parent the controller is connected to
+ - interrupt-controller : marks the device node as an interrupt controller
+ - #interrupt-cells : should be <1>, the first cell is the IRQ offset on this
+   TC3589x interrupt controller.
+Optional nodes:
+- GPIO
+  This GPIO module inside the TC3589x has 24 (TC35890, TC35892) or 20
+  (other models) GPIO lines.
+ - compatible : must be "toshiba,tc3589x-gpio"
+ - interrupts : interrupt on the parent, which must be the tc3589x MFD device
+ - interrupt-controller : marks the device node as an interrupt controller
+ - #interrupt-cells : should be <2>, the first cell is the IRQ offset on this
+   TC3589x GPIO interrupt controller, the second cell is the interrupt flags
+   in accordance with <dt-bindings/interrupt-controller/irq.h>. The following
+   flags are valid:
+   - IRQ_TYPE_LEVEL_LOW
+   - IRQ_TYPE_LEVEL_HIGH
+   - IRQ_TYPE_EDGE_RISING
+   - IRQ_TYPE_EDGE_FALLING
+   - IRQ_TYPE_EDGE_BOTH
+ - gpio-controller : marks the device node as a GPIO controller
+ - #gpio-cells : should be <2>, the first cell is the GPIO offset on this
+   GPIO controller, the second cell is the flags.
+- Keypad
+  This keypad is the same on all variants, supporting up to 96 different
+  keys. The linux-specific properties are modeled on those already existing
+  in other input drivers.
+ - compatible : must be "toshiba,tc3589x-keypad"
+ - debounce-delay-ms : debounce interval in milliseconds
+ - keypad,num-rows : number of rows in the matrix, see
+   bindings/input/matrix-keymap.txt
+ - keypad,num-columns : number of columns in the matrix, see
+   bindings/input/matrix-keymap.txt
+ - linux,keymap: the definition can be found in
+   bindings/input/matrix-keymap.txt
+ - linux,no-autorepeat: do no enable autorepeat feature.
+ - linux,wakeup: use any event on keypad as wakeup event.
+Example:
+tc35893@44 {
+        compatible = "toshiba,tc35893";
+        reg = <0x44>;
+        interrupt-parent = <&gpio6>;
+        interrupts = <26 IRQ_TYPE_EDGE_RISING>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        tc3589x_gpio {
+                compatible = "toshiba,tc3589x-gpio";
+                interrupts = <0>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        tc3589x_keypad {
+                compatible = "toshiba,tc3589x-keypad";
+                interrupts = <6>;
+                debounce-delay-ms = <4>;
+                keypad,num-columns = <8>;
+                keypad,num-rows = <8>;
+                linux,no-autorepeat;
+                linux,wakeup;
+                linux,keymap = <0x0301006b
+                                0x04010066
+                                0x06040072
+                                0x040200d7
+                                0x0303006a
+                                0x0205000e
+                                0x0607008b
+                                0x0500001c
+                                0x0403000b
+                                0x03040034
+                                0x05020067
+                                0x0305006c
+                                0x040500e7
+                                0x0005009e
+                                0x06020073
+                                0x01030039
+                                0x07060069
+                                0x050500d9>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/mfd/twl4030-power.txt b/Documentation/devicetree/bindings/mfd/twl4030-power.txt
index b9ee7b98d3e2..3d19963312ce 100644
--- a/Documentation/devicetree/bindings/mfd/twl4030-power.txt
+++ b/Documentation/devicetree/bindings/mfd/twl4030-power.txt
@@ -23,8 +23,13 @@ down during off-idle. Note that this does not work on all boards
 depending on how the external oscillator is wired.
 Optional properties:
- ti,use_poweroff: With this flag, the chip will initiates an ACTIVE-to-OFF or
-                   SLEEP-to-OFF transition when the system poweroffs.
+- ti,system-power-controller: This indicates that TWL4030 is the
+  power supply master of the system. With this flag, the chip will
+  initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the
+  system poweroffs.
+- ti,use_poweroff: Deprecated name for ti,system-power-controller
 Example:
 &i2c1 {
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index 431716e37a39..b52628b18a53 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -40,6 +40,8 @@ Optional properties:
 - mmc-hs200-1_2v: eMMC HS200 mode(1.2V I/O) is supported
 - mmc-hs400-1_8v: eMMC HS400 mode(1.8V I/O) is supported
 - mmc-hs400-1_2v: eMMC HS400 mode(1.2V I/O) is supported
+- dsr: Value the card's (optional) Driver Stage Register (DSR) should be
+  programmed with. Valid range: [0 .. 0xffff].
 *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
 polarity properties, we have to fix the meaning of the "normal" and "inverted"
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index c559f3f36309..c327c2d6f23d 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -10,12 +10,14 @@ extensions to the Synopsys Designware Mobile Storage Host Controller.
 Required Properties:
 * compatible: should be
-        - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following
+        - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
+                                                        before RK3288
+        - "rockchip,rk3288-dw-mshc": for Rockchip RK3288
 Example:
        rkdwmmc0@12200000 {
-                compatible = "rockchip,rk2928-dw-mshc";
+                compatible = "rockchip,rk3288-dw-mshc";
                reg = <0x12200000 0x1000>;
                interrupts = <0 75 0>;
                #address-cells = <1>;
diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index fa0f327cde01..400b640fabc7 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -19,6 +19,9 @@ Required properties:
                "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
                "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
                "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
+                "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
+                "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
+                "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
 Optional properties:
 - toshiba,mmc-wrprotect-disable: write-protect detection is unavailable
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index 65f4f7c43136..fb733c4e1c11 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -22,7 +22,7 @@ Optional properties:
                                width of 8 is assumed.
 - ti,nand-ecc-opt:             A string setting the ECC layout to use. One of:
-                "sw"            <deprecated> use "ham1" instead
+                "sw"            1-bit Hamming ecc code via software
                "hw"            <deprecated> use "ham1" instead
                "hw-romcode"    <deprecated> use "ham1" instead
                "ham1"          1-bit Hamming ecc code
@@ -110,8 +110,8 @@ on various other factors also like;
        Other factor which governs the selection of ecc-scheme is oob-size.
        Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
        so the device should have enough free bytes available its OOB/Spare
-        area to accomodate ECC for entire page. In general following expression
+        area to accommodate ECC for entire page. In general following expression
-        helps in determining if given device can accomodate ECC syndrome:
+        helps in determining if given device can accommodate ECC syndrome:
        "2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE"
        where
                OOBSIZE         number of bytes in OOB/spare area
@@ -133,5 +133,5 @@ on various other factors also like;
        Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
                trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
                Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
-                which can be accomodate in the OOB/Spare area of this device
+                which can be accommodated in the OOB/Spare area of this device
                (OOBSIZE=128). So this device can use BCH16 ecc-scheme.
diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
index ebcad25efd0a..cfcc52705ed8 100644
--- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
+++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
@@ -3,7 +3,7 @@ APM X-Gene SoC Ethernet nodes
 Ethernet nodes are defined to describe on-chip ethernet interfaces in
 APM X-Gene SoC.
-Required properties:
+Required properties for all the ethernet interfaces:
 - compatible: Should be "apm,xgene-enet"
 - reg: Address and length of the register set for the device. It contains the
  information of registers in the same order as described by reg-names
@@ -15,6 +15,8 @@ Required properties:
 - clocks: Reference to the clock entry.
 - local-mac-address: MAC address assigned to this device
 - phy-connection-type: Interface type between ethernet device and PHY device
+Required properties for ethernet interfaces that have external PHY:
 - phy-handle: Reference to a PHY node connected to this device
 - mdio: Device tree subnode with the following required properties:
diff --git a/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt b/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt
new file mode 100644
index 000000000000..ab0bb4247d14
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/broadcom-mdio-unimac.txt
@@ -0,0 +1,39 @@
+* Broadcom UniMAC MDIO bus controller
+Required properties:
+- compatible: should one from "brcm,genet-mdio-v1", "brcm,genet-mdio-v2",
+  "brcm,genet-mdio-v3", "brcm,genet-mdio-v4" or "brcm,unimac-mdio"
+- reg: address and length of the regsiter set for the device, first one is the
+  base register, and the second one is optional and for indirect accesses to
+  larger than 16-bits MDIO transactions
+- reg-names: name(s) of the register must be "mdio" and optional "mdio_indir_rw"
+- #size-cells: must be 1
+- #address-cells: must be 0
+Optional properties:
+- interrupts: must be one if the interrupt is shared with the Ethernet MAC or
+  Ethernet switch this MDIO block is integrated from, or must be two, if there
+  are two separate interrupts, first one must be "mdio done" and second must be
+  for "mdio error"
+- interrupt-names: must be "mdio_done_error" when there is a share interrupt fed
+  to this hardware block, or must be "mdio_done" for the first interrupt and
+  "mdio_error" for the second when there are separate interrupts
+Child nodes of this MDIO bus controller node are standard Ethernet PHY device
+nodes as described in Documentation/devicetree/bindings/net/phy.txt
+Example:
+mdio@403c0 {
+        compatible = "brcm,unimac-mdio";
+        reg = <0x403c0 0x8 0x40300 0x18>;
+        reg-names = "mdio", "mdio_indir_rw";
+        #size-cells = <1>;
+        #address-cells = <0>;
+        ...
+        phy@0 {
+                compatible = "ethernet-phy-ieee802.3-c22";
+                reg = <0>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/broadcom-sf2.txt b/Documentation/devicetree/bindings/net/broadcom-sf2.txt
new file mode 100644
index 000000000000..30d487597ecb
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/broadcom-sf2.txt
@@ -0,0 +1,78 @@
+* Broadcom Starfighter 2 integrated swich
+Required properties:
+- compatible: should be "brcm,bcm7445-switch-v4.0"
+- reg: addresses and length of the register sets for the device, must be 6
+  pairs of register addresses and lengths
+- interrupts: interrupts for the devices, must be two interrupts
+- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
+- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt
+- #size-cells: must be 0
+- #address-cells: must be 2, see dsa/dsa.txt
+Subnodes:
+The integrated switch subnode should be specified according to the binding
+described in dsa/dsa.txt.
+Optional properties:
+- reg-names: litteral names for the device base register addresses, when present
+  must be: "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb"
+- interrupt-names: litternal names for the device interrupt lines, when present
+  must be: "switch_0" and "switch_1"
+- brcm,num-gphy: specify the maximum number of integrated gigabit PHYs in the
+  switch
+- brcm,num-rgmii-ports: specify the maximum number of RGMII interfaces supported
+  by the switch
+- brcm,fcb-pause-override: boolean property, if present indicates that the switch
+  supports Failover Control Block pause override capability
+- brcm,acb-packets-inflight: boolean property, if present indicates that the switch
+  Admission Control Block supports reporting the number of packets in-flight in a
+  switch queue
+Example:
+switch_top@f0b00000 {
+        compatible = "simple-bus";
+        #size-cells = <1>;
+        #address-cells = <1>;
+        ranges = <0 0xf0b00000 0x40804>;
+        ethernet_switch@0 {
+                compatible = "brcm,bcm7445-switch-v4.0";
+                #size-cells = <0>;
+                #address-cells = <2>;
+                reg = <0x0 0x40000
+                        0x40000 0x110
+                        0x40340 0x30
+                        0x40380 0x30
+                        0x40400 0x34
+                        0x40600 0x208>;
+                interrupts = <0 0x18 0
+                                0 0x19 0>;
+                brcm,num-gphy = <1>;
+                brcm,num-rgmii-ports = <2>;
+                brcm,fcb-pause-override;
+                brcm,acb-packets-inflight;
+                ...
+                switch@0 {
+                        reg = <0 0>;
+                        #size-cells = <0>;
+                        #address-cells <1>;
+                        port@0 {
+                                label = "gphy";
+                                reg = <0>;
+                        };
+                        ...
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt
new file mode 100644
index 000000000000..9e331777c203
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/m_can.txt
@@ -0,0 +1,67 @@
+Bosch MCAN controller Device Tree Bindings
+-------------------------------------------------
+Required properties:
+- compatible            : Should be "bosch,m_can" for M_CAN controllers
+- reg                   : physical base address and size of the M_CAN
+                          registers map and Message RAM
+- reg-names             : Should be "m_can" and "message_ram"
+- interrupts            : Should be the interrupt number of M_CAN interrupt
+                          line 0 and line 1, could be same if sharing
+                          the same interrupt.
+- interrupt-names       : Should contain "int0" and "int1"
+- clocks                : Clocks used by controller, should be host clock
+                          and CAN clock.
+- clock-names           : Should contain "hclk" and "cclk"
+- pinctrl-<n>           : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
+- pinctrl-names         : Names corresponding to the numbered pinctrl states
+- bosch,mram-cfg        : Message RAM configuration data.
+                          Multiple M_CAN instances can share the same Message
+                          RAM and each element(e.g Rx FIFO or Tx Buffer and etc)
+                          number in Message RAM is also configurable,
+                          so this property is telling driver how the shared or
+                          private Message RAM are used by this M_CAN controller.
+                          The format should be as follows:
+                          <offset sidf_elems xidf_elems rxf0_elems rxf1_elems
+                           rxb_elems txe_elems txb_elems>
+                          The 'offset' is an address offset of the Message RAM
+                          where the following elements start from. This is
+                          usually set to 0x0 if you're using a private Message
+                          RAM. The remain cells are used to specify how many
+                          elements are used for each FIFO/Buffer.
+                          M_CAN includes the following elements according to user manual:
+                          11-bit Filter 0-128 elements / 0-128 words
+                          29-bit Filter 0-64 elements / 0-128 words
+                          Rx FIFO 0     0-64 elements / 0-1152 words
+                          Rx FIFO 1     0-64 elements / 0-1152 words
+                          Rx Buffers    0-64 elements / 0-1152 words
+                          Tx Event FIFO 0-32 elements / 0-64 words
+                          Tx Buffers    0-32 elements / 0-576 words
+                          Please refer to 2.4.1 Message RAM Configuration in
+                          Bosch M_CAN user manual for details.
+Example:
+SoC dtsi:
+m_can1: can@020e8000 {
+        compatible = "bosch,m_can";
+        reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
+        reg-names = "m_can", "message_ram";
+        interrupts = <0 114 0x04>,
+                     <0 114 0x04>;
+        interrupt-names = "int0", "int1";
+        clocks = <&clks IMX6SX_CLK_CANFD>,
+                 <&clks IMX6SX_CLK_CANFD>;
+        clock-names = "hclk", "cclk";
+        bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
+        status = "disabled";
+};
+Board dts:
+&m_can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_m_can1>;
+        status = "enabled";
+};
diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt
new file mode 100644
index 000000000000..002d8440bf66
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/rcar_can.txt
@@ -0,0 +1,43 @@
+Renesas R-Car CAN controller Device Tree Bindings
+-------------------------------------------------
+Required properties:
+- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
+              "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
+              "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
+              "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
+- reg: physical base address and size of the R-Car CAN register map.
+- interrupts: interrupt specifier for the sole interrupt.
+- clocks: phandles and clock specifiers for 3 CAN clock inputs.
+- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must be "default".
+Optional properties:
+- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
+                            <0x0> (default) : Peripheral clock (clkp1)
+                            <0x1> : Peripheral clock (clkp2)
+                            <0x3> : Externally input clock
+Example
+-------
+SoC common .dtsi file:
+        can0: can@e6e80000 {
+                compatible = "renesas,can-r8a7791";
+                reg = <0 0xe6e80000 0 0x1000>;
+                interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
+                         <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
+                clock-names = "clkp1", "clkp2", "can_clk";
+                status = "disabled";
+        };
+Board specific .dts file:
+&can0 {
+        pinctrl-0 = <&can0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index ae2b8b7f9c38..33fe8462edf4 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -24,15 +24,17 @@ Optional properties:
 - ti,hwmods             : Must be "cpgmac0"
 - no_bd_ram             : Must be 0 or 1
 - dual_emac             : Specifies Switch to act as Dual EMAC
+- syscon                : Phandle to the system control device node, which is
+                          the control module device of the am33x
 Slave Properties:
 Required properties:
 - phy_id                : Specifies slave phy id
 - phy-mode              : See ethernet.txt file in the same directory
- mac-address           : See ethernet.txt file in the same directory
 Optional properties:
 - dual_emac_res_vlan    : Specifies VID to be used to segregate the ports
+- mac-address           : See ethernet.txt file in the same directory
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
@@ -57,6 +59,7 @@ Examples:
                active_slave = <0>;
                cpts_clock_mult = <0x80000000>;
                cpts_clock_shift = <29>;
+                syscon = <&cm>;
                cpsw_emac0: slave@0 {
                        phy_id = <&davinci_mdio>, <0>;
                        phy-mode = "rgmii-txid";
@@ -85,6 +88,7 @@ Examples:
                active_slave = <0>;
                cpts_clock_mult = <0x80000000>;
                cpts_clock_shift = <29>;
+                syscon = <&cm>;
                cpsw_emac0: slave@0 {
                        phy_id = <&davinci_mdio>, <0>;
                        phy-mode = "rgmii-txid";
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt
index 49f4f7ae3f51..a62c889aafca 100644
--- a/Documentation/devicetree/bindings/net/dsa/dsa.txt
+++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt
@@ -39,6 +39,22 @@ Optionnal property:
                          This property is only used when switches are being
                          chained/cascaded together.
+- phy-handle            : Phandle to a PHY on an external MDIO bus, not the
+                          switch internal one. See
+                          Documentation/devicetree/bindings/net/ethernet.txt
+                          for details.
+- phy-mode              : String representing the connection to the designated
+                          PHY node specified by the 'phy-handle' property. See
+                          Documentation/devicetree/bindings/net/ethernet.txt
+                          for details.
+Optional subnodes:
+- fixed-link            : Fixed-link subnode describing a link to a non-MDIO
+                          managed entity. See
+                          Documentation/devicetree/bindings/net/fixed-link.txt
+                          for details.
 Example:
        dsa@0 {
@@ -58,6 +74,7 @@ Example:
                        port@0 {
                                reg = <0>;
                                label = "lan1";
+                                phy-handle = <&phy0>;
                        };
                        port@1 {
diff --git a/Documentation/devicetree/bindings/net/emac_rockchip.txt b/Documentation/devicetree/bindings/net/emac_rockchip.txt
new file mode 100644
index 000000000000..8dc1c79fef7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/emac_rockchip.txt
@@ -0,0 +1,50 @@
+* ARC EMAC 10/100 Ethernet platform driver for Rockchip Rk3066/RK3188 SoCs
+Required properties:
+- compatible: Should be "rockchip,rk3066-emac" or "rockchip,rk3188-emac"
+  according to the target SoC.
+- reg: Address and length of the register set for the device
+- interrupts: Should contain the EMAC interrupts
+- rockchip,grf: phandle to the syscon grf used to control speed and mode
+  for emac.
+- phy: see ethernet.txt file in the same directory.
+- phy-mode: see ethernet.txt file in the same directory.
+Optional properties:
+- phy-supply: phandle to a regulator if the PHY needs one
+Clock handling:
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "hclk" for the host clock needed to calculate and set
+  polling period of EMAC and "macref" for the reference clock needed to transfer
+  data to and from the phy.
+Child nodes of the driver are the individual PHY devices connected to the
+MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
+Examples:
+ethernet@10204000 {
+        compatible = "rockchip,rk3188-emac";
+        reg = <0xc0fc2000 0x3c>;
+        interrupts = <6>;
+        mac-address = [ 00 11 22 33 44 55 ];
+        clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
+        clock-names = "hclk", "macref";
+        pinctrl-names = "default";
+        pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>;
+        rockchip,grf = <&grf>;
+        phy = <&phy0>;
+        phy-mode = "rmii";
+        phy-supply = <&vcc_rmii>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        phy0: ethernet-phy@0 {
+              reg = <1>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 8a2c7b55ec16..0c8775c45798 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -16,6 +16,12 @@ Optional properties:
 - phy-handle : phandle to the PHY device connected to this device.
 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
  Use instead of phy-handle.
+- fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
+  hw multi queues. Should specify the tx queue number, otherwise set tx queue
+  number to 1.
+- fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
+  hw multi queues. Should specify the rx queue number, otherwise set rx queue
+  number to 1.
 Optional subnodes:
 - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
diff --git a/Documentation/devicetree/bindings/net/marvell-pxa168.txt b/Documentation/devicetree/bindings/net/marvell-pxa168.txt
new file mode 100644
index 000000000000..845a148a346e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/marvell-pxa168.txt
@@ -0,0 +1,36 @@
+* Marvell PXA168 Ethernet Controller
+Required properties:
+- compatible: should be "marvell,pxa168-eth".
+- reg: address and length of the register set for the device.
+- interrupts: interrupt for the device.
+- clocks: pointer to the clock for the device.
+Optional properties:
+- port-id: Ethernet port number. Should be '0','1' or '2'.
+- #address-cells: must be 1 when using sub-nodes.
+- #size-cells: must be 0 when using sub-nodes.
+- phy-handle: see ethernet.txt file in the same directory.
+- local-mac-address: see ethernet.txt file in the same directory.
+Sub-nodes:
+Each PHY can be represented as a sub-node. This is not mandatory.
+Sub-nodes required properties:
+- reg: the MDIO address of the PHY.
+Example:
+        eth0: ethernet@f7b90000 {
+                compatible = "marvell,pxa168-eth";
+                reg = <0xf7b90000 0x10000>;
+                clocks = <&chip CLKID_GETH0>;
+                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                phy-handle = <&ethphy0>;
+                ethphy0: ethernet-phy@0 {
+                        reg = <0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/net/meson-dwmac.txt b/Documentation/devicetree/bindings/net/meson-dwmac.txt
new file mode 100644
index 000000000000..ec633d74a8a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/meson-dwmac.txt
@@ -0,0 +1,25 @@
+* Amlogic Meson DWMAC Ethernet controller
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file net/stmmac.txt with the following changes.
+Required properties:
+- compatible: should be "amlogic,meson6-dwmac" along with "snps,dwmac"
+              and any applicable more detailed version number
+              described in net/stmmac.txt
+- reg: should contain a register range for the dwmac controller and
+       another one for the Amlogic specific configuration
+Example:
+        ethmac: ethernet@c9410000 {
+                compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+                reg = <0xc9410000 0x10000
+                       0xc1108108 0x4>;
+                interrupts = <0 8 1>;
+                interrupt-names = "macirq";
+                clocks = <&clk81>;
+                clock-names = "stmmaceth";
+        }
diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt
index 98a3e61f9ee8..e1d99b95c4ec 100644
--- a/Documentation/devicetree/bindings/net/micrel.txt
+++ b/Documentation/devicetree/bindings/net/micrel.txt
@@ -16,3 +16,9 @@ Optional properties:
              KSZ8051: register 0x1f, bits 5..4
              See the respective PHY datasheet for the mode values.
+ - clocks, clock-names: contains clocks according to the common clock bindings.
+              supported clocks:
+              - KSZ8021, KSZ8031: "rmii-ref": The RMII refence input clock. Used
+                to determine the XI input clock.
diff --git a/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt b/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt
index 3b58ae480344..9005608cbbd1 100644
--- a/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt
+++ b/Documentation/devicetree/bindings/net/nfc/st21nfcb.txt
@@ -26,7 +26,7 @@ Example (for ARM-based BeagleBoard xM with ST21NFCB on I2C2):
                clock-frequency = <400000>;
                interrupt-parent = <&gpio5>;
-                interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
                reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
        };
diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
index 1e436133685f..7c89ca290ced 100644
--- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
+++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
@@ -13,6 +13,11 @@ Optional SoC Specific Properties:
 - pinctrl-names: Contains only one value - "default".
 - pintctrl-0: Specifies the pin control groups used for this controller.
 - autosuspend-delay: Specify autosuspend delay in milliseconds.
+- vin-voltage-override: Specify voltage of VIN pin in microvolts.
+- irq-status-read-quirk: Specify that the trf7970a being used has the
+  "IRQ Status Read" erratum.
+- en2-rf-quirk: Specify that the trf7970a being used has the "EN2 RF"
+  erratum.
 Example (for ARM-based BeagleBone with TRF7970A on SPI1):
@@ -30,7 +35,10 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
                ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>,
                                  <&gpio2 5 GPIO_ACTIVE_LOW>;
                vin-supply = <&ldo3_reg>;
+                vin-voltage-override = <5000000>;
                autosuspend-delay = <30000>;
+                irq-status-read-quirk;
+                en2-rf-quirk;
                status = "okay";
        };
 };
diff --git a/Documentation/devicetree/bindings/net/qca-qca7000-spi.txt b/Documentation/devicetree/bindings/net/qca-qca7000-spi.txt
new file mode 100644
index 000000000000..c74989c0d8ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/qca-qca7000-spi.txt
@@ -0,0 +1,47 @@
+* Qualcomm QCA7000 (Ethernet over SPI protocol)
+Note: The QCA7000 is useable as a SPI device. In this case it must be defined
+as a child of a SPI master in the device tree.
+Required properties:
+- compatible : Should be "qca,qca7000"
+- reg : Should specify the SPI chip select
+- interrupts : The first cell should specify the index of the source interrupt
+  and the second cell should specify the trigger type as rising edge
+- spi-cpha : Must be set
+- spi-cpol: Must be set
+Optional properties:
+- interrupt-parent : Specify the pHandle of the source interrupt
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
+  Numbers smaller than 1000000 or greater than 16000000 are invalid. Missing
+  the property will set the SPI frequency to 8000000 Hertz.
+- local-mac-address: 6 bytes, MAC address
+- qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
+  In this mode the SPI master must toggle the chip select between each data
+  word. In burst mode these gaps aren't necessary, which is faster.
+  This setting depends on how the QCA7000 is setup via GPIO pin strapping.
+  If the property is missing the driver defaults to burst mode.
+Example:
+/* Freescale i.MX28 SPI master*/
+ssp2: spi@80014000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx28-spi";
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi2_pins_a>;
+        status = "okay";
+        qca7000: ethernet@0 {
+                compatible = "qca,qca7000";
+                reg = <0x0>;
+                interrupt-parent = <&gpio3>;      /* GPIO Bank 3 */
+                interrupts = <25 0x1>;            /* Index: 25, rising edge */
+                spi-cpha;                         /* SPI mode: CPHA=1 */
+                spi-cpol;                         /* SPI mode: CPOL=1 */
+                spi-max-frequency = <8000000>;    /* freq: 8 MHz */
+                local-mac-address = [ A0 B0 C0 D0 E0 F0 ];
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
index 989f6c95cfd5..888c250197fe 100644
--- a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
+++ b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
@@ -17,7 +17,7 @@ Required properties:
 - samsung,pbl: Integer, Programmable Burst Length.
  Supported values are 1, 2, 4, 8, 16, or 32.
 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
-  This is an interger and represents allowable DMA bursts when fixed burst.
+  This is an integer and represents allowable DMA bursts when fixed burst.
  Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
  When fixed length is needed for burst mode, it can be set within allowable
  range.
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
index 2a60cd3e8d5d..3a9d67951606 100644
--- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
@@ -12,6 +12,10 @@ Required properties:
 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
   encompasses the glue register, the register offset, and the register shift.
+Optional properties:
+altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
+                DWMAC controller is connected emac splitter.
 Example:
 gmac0: ethernet@ff700000 {
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
index 9b03c57563a4..c41afd963edf 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -39,6 +39,10 @@ Optional properties:
  further clocks may be specified in derived bindings.
 - clock-names: One name for each entry in the clocks property, the
  first one should be "stmmaceth".
+- clk_ptp_ref: this is the PTP reference clock; in case of the PTP is
+  available this clock is used for programming the Timestamp Addend Register.
+  If not passed then the system clock will be used and this is fine on some
+  platforms.
 Examples:
@@ -54,5 +58,5 @@ Examples:
                snps,multicast-filter-bins = <256>;
                snps,perfect-filter-entries = <128>;
                clocks = <&clock>;
-                clock-names = "stmmaceth">;
+                clock-names = "stmmaceth";
        };
diff --git a/Documentation/devicetree/bindings/panel/auo,b101xtn01.txt b/Documentation/devicetree/bindings/panel/auo,b101xtn01.txt
new file mode 100644
index 000000000000..889d511d66c9
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/auo,b101xtn01.txt
@@ -0,0 +1,7 @@
+AU Optronics Corporation 10.1" WXGA TFT LCD panel
+Required properties:
+- compatible: should be "auo,b101xtn01"
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index d0d15ee42834..9f4faa8e8d00 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -2,6 +2,10 @@
 Required properties:
 - compatible: should contain "snps,dw-pcie" to identify the core.
+- reg: Should contain the configuration address space.
+- reg-names: Must be "config" for the PCIe configuration space.
+    (The old way of getting the configuration address space from "ranges"
+    is deprecated and should be avoided.)
 - #address-cells: set to <3>
 - #size-cells: set to <2>
 - device_type: set to "pci"
@@ -19,3 +23,6 @@ Required properties:
 Optional properties:
 - reset-gpio: gpio pin number of power good signal
+- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
+  specify this property, to keep backwards compatibility a range of 0x00-0xff
+  is assumed if not present)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index 9455fd0ec830..6fbba53a309b 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -17,7 +17,9 @@ Example:
        pcie@0x01000000 {
                compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
-                reg = <0x01ffc000 0x4000>;
+                reg = <0x01ffc000 0x04000>,
+                      <0x01f00000 0x80000>;
+                reg-names = "dbi", "config";
                #address-cells = <3>;
                #size-cells = <2>;
                device_type = "pci";
diff --git a/Documentation/devicetree/bindings/pci/fsl,pci.txt b/Documentation/devicetree/bindings/pci/fsl,pci.txt
new file mode 100644
index 000000000000..d8ac4a768e7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/fsl,pci.txt
@@ -0,0 +1,27 @@
+* Bus Enumeration by Freescale PCI-X Agent
+Typically any Freescale PCI-X bridge hardware strapped into Agent mode
+is prevented from enumerating the bus. The PrPMC form-factor requires
+all mezzanines to be PCI-X Agents, but one per system may still
+enumerate the bus.
+The property defined below will allow a PCI-X bridge to be used for bus
+enumeration despite being strapped into Agent mode.
+Required properties:
+- fsl,pci-agent-force-enum : There is no value associated with this
+  property. The property itself is treated as a boolean.
+Example:
+        /* PCI-X bridge known to be PrPMC Monarch */
+        pci0: pci@ef008000 {
+                fsl,pci-agent-force-enum;
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
+                device_type = "pci";
+                ...
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.txt b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
index f0b0436807b4..cf3e205e0b7e 100644
--- a/Documentation/devicetree/bindings/pci/host-generic-pci.txt
+++ b/Documentation/devicetree/bindings/pci/host-generic-pci.txt
@@ -55,7 +55,7 @@ For CAM, this 24-bit offset is:
        cfg_offset(bus, device, function, register) =
                   bus << 16 | device << 11 | function << 8 | register
-Whilst ECAM extends this by 4 bits to accomodate 4k of function space:
+Whilst ECAM extends this by 4 bits to accommodate 4k of function space:
        cfg_offset(bus, device, function, register) =
                   bus << 20 | device << 15 | function << 12 | register
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 0823362548dc..d763e047c6ae 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -1,7 +1,10 @@
 NVIDIA Tegra PCIe controller
 Required properties:
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
+- compatible: Must be one of:
+  - "nvidia,tegra20-pcie"
+  - "nvidia,tegra30-pcie"
+  - "nvidia,tegra124-pcie"
 - device_type: Must be "pci"
 - reg: A list of physical base address and length for each set of controller
  registers. Must contain an entry for each entry in the reg-names property.
@@ -57,6 +60,11 @@ Required properties:
  - afi
  - pcie_x
+Required properties on Tegra124 and later:
+- phys: Must contain an entry for each entry in phy-names.
+- phy-names: Must include the following entries:
+  - pcie
 Power supplies for Tegra20:
 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
@@ -84,6 +92,21 @@ Power supplies for Tegra30:
    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
+Power supplies for Tegra124:
+- Required:
+  - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
+  - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
+  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
+    supply 1.05 V.
+  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
+    Must supply 3.3 V.
+  - hvdd-pex-pll-e-supply: High-voltage supply for PLLE (shared with USB3).
+    Must supply 3.3 V.
+  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
+    supply 2.8-3.3 V.
+  - avdd-pll-erefe-supply: Power supply for PLLE (shared with USB3). Must
+    supply 1.05 V.
 Root ports are defined as subnodes of the PCIe controller node.
 Required properties:
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
new file mode 100644
index 000000000000..54eae2938174
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -0,0 +1,63 @@
+TI Keystone PCIe interface
+Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
+It shares common functions with PCIe Designware core driver and inherit
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt
+Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
+for the details of Designware DT bindings.  Additional properties are
+described here as well as properties that are not applicable.
+Required Properties:-
+compatibility: "ti,keystone-pcie"
+reg:    index 1 is the base address and length of DW application registers.
+        index 2 is the base address and length of PCI device ID register.
+pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
+        interrupt-cells: should be set to 1
+        interrupt-parent: Parent interrupt controller phandle
+        interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
+ Example:
+        pcie_msi_intc: msi-interrupt-controller {
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        interrupt-parent = <&gic>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                                        <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
+        };
+pcie_intc: Interrupt controller device node for Legacy IRQ chip
+        interrupt-cells: should be set to 1
+        interrupt-parent: Parent interrupt controller phandle
+        interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
+ Example:
+        pcie_intc: legacy-interrupt-controller {
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                interrupt-parent = <&gic>;
+                interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
+                        <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
+                        <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
+                        <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
+        };
+Optional properties:-
+        phys: phandle to Generic Keystone SerDes phy for PCI
+        phy-names: name of the Generic Keystine SerDes phy for PCI
+          - If boot loader already does PCI link establishment, then phys and
+            phy-names shouldn't be present.
+Designware DT Properties not applicable for Keystone PCI
+1. pcie_bus clock-names not used.  Instead, a phandle to phys is used.
diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
new file mode 100644
index 000000000000..3d217911b313
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -0,0 +1,59 @@
+TI PCI Controllers
+PCIe Designware Controller
+ - compatible: Should be "ti,dra7-pcie""
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+               The second entry must be "rc-dbics" for the designware pcie
+               registers
+               The third entry must be "config" for the PCIe configuration space
+ - phys : list of PHY specifiers (used by generic PHY framework)
+ - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+               number of PHYs as specified in *phys* property.
+ - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
+               where <X> is the instance number of the pcie from the HW spec.
+ - interrupts : Two interrupt entries must be specified. The first one is for
+                main interrupt line and the second for MSI interrupt line.
+ - #address-cells,
+   #size-cells,
+   #interrupt-cells,
+   device_type,
+   ranges,
+   num-lanes,
+   interrupt-map-mask,
+   interrupt-map : as specified in ../designware-pcie.txt
+Example:
+axi {
+        compatible = "simple-bus";
+        #size-cells = <1>;
+        #address-cells = <1>;
+        ranges = <0x51000000 0x51000000 0x3000
+                  0x0        0x20000000 0x10000000>;
+        pcie@51000000 {
+                compatible = "ti,dra7-pcie";
+                reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
+                reg-names = "rc_dbics", "ti_conf", "config";
+                interrupts = <0 232 0x4>, <0 233 0x4>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x03000 0 0x00010000
+                          0x82000000 0 0x20013000 0x13000 0 0xffed000>;
+                #interrupt-cells = <1>;
+                num-lanes = <1>;
+                ti,hwmods = "pcie1";
+                phys = <&pcie1_phy>;
+                phy-names = "pcie-phy0";
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pcie_intc 1>,
+                                <0 0 0 2 &pcie_intc 2>,
+                                <0 0 0 3 &pcie_intc 3>,
+                                <0 0 0 4 &pcie_intc 4>;
+                pcie_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/pci/xgene-pci.txt b/Documentation/devicetree/bindings/pci/xgene-pci.txt
new file mode 100644
index 000000000000..1070b068c7c6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xgene-pci.txt
@@ -0,0 +1,57 @@
+* AppliedMicro X-Gene PCIe interface
+Required properties:
+- device_type: set to "pci"
+- compatible: should contain "apm,xgene-pcie" to identify the core.
+- reg: A list of physical base address and length for each set of controller
+       registers. Must contain an entry for each entry in the reg-names
+       property.
+- reg-names: Must include the following entries:
+  "csr": controller configuration registers.
+  "cfg": pcie configuration space registers.
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- ranges: ranges for the outbound memory, I/O regions.
+- dma-ranges: ranges for the inbound memory regions.
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+        to define the mapping of the PCIe interface to interrupt
+        numbers.
+- clocks: from common clock binding: handle to pci clock.
+Optional properties:
+- status: Either "ok" or "disabled".
+- dma-coherent: Present if dma operations are coherent
+Example:
+SoC specific DT Entry:
+        pcie0: pcie@1f2b0000 {
+                status = "disabled";
+                device_type = "pci";
+                compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                        0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
+                reg-names = "csr", "cfg";
+                ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
+                          0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
+                dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+                              0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
+                interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+                                 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+                                 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
+                                 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
+                dma-coherent;
+                clocks = <&pcie0clk 0>;
+        };
+Board specific DT Entry:
+        &pcie0 {
+                status = "ok";
+        };
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
new file mode 100644
index 000000000000..3e2c88d97ad4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -0,0 +1,62 @@
+* Xilinx AXI PCIe Root Port Bridge DT description
+Required properties:
+- #address-cells: Address representation for root ports, set to <3>
+- #size-cells: Size representation for root ports, set to <2>
+- #interrupt-cells: specifies the number of cells needed to encode an
+        interrupt source. The value must be 1.
+- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
+- reg: Should contain AXI PCIe registers location and length
+- device_type: must be "pci"
+- interrupts: Should contain AXI PCIe interrupt
+- interrupt-map-mask,
+  interrupt-map: standard PCI properties to define the mapping of the
+        PCI interface to interrupt numbers.
+- ranges: ranges for the PCI memory regions (I/O space region is not
+        supported by hardware)
+        Please refer to the standard PCI bus binding document for a more
+        detailed explanation
+Optional properties:
+- bus-range: PCI bus numbers covered
+Interrupt controller child node
+++++++++++++++++++++++++++++++
+Required properties:
+- interrupt-controller: identifies the node as an interrupt controller
+- #address-cells: specifies the number of cells needed to encode an
+        address. The value must be 0.
+- #interrupt-cells: specifies the number of cells needed to encode an
+        interrupt source. The value must be 1.
+NOTE:
+The core provides a single interrupt for both INTx/MSI messages. So,
+created a interrupt controller node to support 'interrupt-map' DT
+functionality.  The driver will create an IRQ domain for this map, decode
+the four INTx interrupts in ISR and route them to this domain.
+Example:
++++++++
+        pci_express: axi-pcie@50000000 {
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                compatible = "xlnx,axi-pcie-host-1.00.a";
+                reg = < 0x50000000 0x10000000 >;
+                device_type = "pci";
+                interrupts = < 0 52 4 >;
+                interrupt-map-mask = <0 0 0 7>;
+                interrupt-map = <0 0 0 1 &pcie_intc 1>,
+                                <0 0 0 2 &pcie_intc 2>,
+                                <0 0 0 3 &pcie_intc 3>,
+                                <0 0 0 4 &pcie_intc 4>;
+                ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
+                pcie_intc: interrupt-controller {
+                        interrupt-controller;
+                        #address-cells = <0>;
+                        #interrupt-cells = <1>;
+                }
+        };
diff --git a/Documentation/devicetree/bindings/phy/phy-bindings.txt b/Documentation/devicetree/bindings/phy/phy-bindings.txt
index 2aa1840200ed..1293c321754c 100644
--- a/Documentation/devicetree/bindings/phy/phy-bindings.txt
+++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt
@@ -27,7 +27,7 @@ phys: phy {
 };
 That node describes an IP block (PHY provider) that implements 2 different PHYs.
-In order to differentiate between these 2 PHYs, an additonal specifier should be
+In order to differentiate between these 2 PHYs, an additional specifier should be
 given while trying to get a reference to it.
 PHY user node
diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
new file mode 100644
index 000000000000..1ef8228db73b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
@@ -0,0 +1,30 @@
+ST STiH407 USB PHY controller
+This file documents the dt bindings for the usb picoPHY driver which is the PHY for both USB2 and USB3
+host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC family from STMicroelectronics.
+Required properties:
+- compatible            : should be "st,stih407-usb2-phy"
+- reg                   : contain the offset and length of the system configuration registers
+                          used as glue logic to control & parameter phy
+- reg-names             : the names of the system configuration registers in "reg", should be "param" and "reg"
+- st,syscfg             : sysconfig register to manage phy parameter at driver level
+- resets                : list of phandle and reset specifier pairs. There should be two entries, one
+                          for the whole phy and one for the port
+- reset-names           : list of reset signal names. Should be "global" and "port"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+Example:
+usb2_picophy0: usbpicophy@f8 {
+        compatible      = "st,stih407-usb2-phy";
+        reg             = <0xf8 0x04>,  /* syscfg 5062 */
+                          <0xf4 0x04>;  /* syscfg 5061 */
+        reg-names       = "param", "ctrl";
+        #phy-cells      = <0>;
+        st,syscfg       = <&syscfg_core>;
+        resets          = <&softreset STIH407_PICOPHY_SOFTRESET>,
+                          <&picophyreset STIH407_PICOPHY0_RESET>;
+        reset-names     = "global", "port";
+};
diff --git a/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt
new file mode 100644
index 000000000000..00944a05ee6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-stih41x-usb.txt
@@ -0,0 +1,24 @@
+STMicroelectronics STiH41x USB PHY binding
+------------------------------------------
+This file contains documentation for the usb phy found in STiH415/6 SoCs from
+STMicroelectronics.
+Required properties:
+- compatible    : should be "st,stih416-usb-phy" or "st,stih415-usb-phy"
+- st,syscfg     : should be a phandle of the syscfg node
+- clock-names   : must contain "osc_phy"
+- clocks        : must contain an entry for each name in clock-names.
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- #phy-cells    : must be 0 for this phy
+See: Documentation/devicetree/bindings/phy/phy-bindings.txt
+Example:
+usb2_phy: usb2phy@0 {
+        compatible      = "st,stih416-usb-phy";
+        #phy-cell       = <0>;
+        st,syscfg       = <&syscfg_rear>;
+        clocks          = <&clk_sysin>;
+        clock-names     = "osc_phy";
+};
diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
new file mode 100644
index 000000000000..86f2dbe07ed4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
@@ -0,0 +1,39 @@
+Qualcomm DWC3 HS AND SS PHY CONTROLLER
+--------------------------------------
+DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
+controllers.  Each DWC3 PHY controller should have its own node.
+Required properties:
+- compatible: should contain one of the following:
+        - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
+        - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
+- reg: offset and length of the DWC3 PHY controller register set
+- #phy-cells: must be zero
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+- clock-names: Should contain "ref" for the PHY reference clock
+Optional clocks:
+  "xo"          External reference clock
+Example:
+                phy@100f8800 {
+                        compatible = "qcom,dwc3-hs-usb-phy";
+                        reg = <0x100f8800 0x30>;
+                        clocks = <&gcc USB30_0_UTMI_CLK>;
+                        clock-names = "ref";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
+                phy@100f8830 {
+                        compatible = "qcom,dwc3-ss-usb-phy";
+                        reg = <0x100f8830 0x30>;
+                        clocks = <&gcc USB30_0_MASTER_CLK>;
+                        clock-names = "ref";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
new file mode 100644
index 000000000000..00fc52a034b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
@@ -0,0 +1,51 @@
+* Renesas R-Car generation 2 USB PHY
+This file provides information on what the device node for the R-Car generation
+2 USB PHY contains.
+Required properties:
+- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
+              "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
+- reg: offset and length of the register block.
+- #address-cells: number of address cells for the USB channel subnodes, must
+                  be <1>.
+- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
+- clocks: clock phandle and specifier pair.
+- clock-names: string, clock input name, must be "usbhs".
+The USB PHY device tree node should have the subnodes corresponding to the USB
+channels. These subnodes must contain the following properties:
+- reg: the USB controller selector; see the table below for the values.
+- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
+The phandle's argument in the PHY specifier is the USB controller selector for
+the USB channel; see the selector meanings below:
+-----------+---------------+---------------+
+|\ Selector |               |               |
+ --------- +       0       |       1       |
+| Channel  \|               |               |
+-----------+---------------+---------------+
+| 0         | PCI EHCI/OHCI | HS-USB        |
+| 2         | PCI EHCI/OHCI | xHCI          |
+-----------+---------------+---------------+
+Example (Lager board):
+        usb-phy@e6590100 {
+                compatible = "renesas,usb-phy-r8a7790";
+                reg = <0 0xe6590100 0 0x100>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+                clock-names = "usbhs";
+                usb-channel@0 {
+                        reg = <0>;
+                        #phy-cells = <1>;
+                };
+                usb-channel@2 {
+                        reg = <2>;
+                        #phy-cells = <1>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 7a6feea2a48b..15e0f2c7130f 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -17,8 +17,11 @@ Samsung EXYNOS SoC series Display Port PHY
 -------------------------------------------------
 Required properties:
- compatible : should be "samsung,exynos5250-dp-video-phy";
+- compatible : should be one of the following supported values:
- reg : offset and length of the Display Port PHY register set;
+         - "samsung,exynos5250-dp-video-phy"
+         - "samsung,exynos5420-dp-video-phy"
+- samsung,pmu-syscon: phandle for PMU system controller interface, used to
+                      control pmu registers for power isolation.
 - #phy-cells : from the generic PHY bindings, must be 0;
 Samsung S5P/EXYNOS SoC series USB PHY
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 02ab5ab198a4..b7a93e80a302 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -19,6 +19,7 @@ such as pull-up, multi drive, etc.
 Required properties for iomux controller:
 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
+                or "atmel,sama5d3-pinctrl"
 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
  configured in this periph mode. All the periph and bank need to be describe.
@@ -85,13 +86,20 @@ Required properties for pin configuration node:
  PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
 Bits used for CONFIG:
-PULL_UP         (1 << 0): indicate this pin need a pull up.
+PULL_UP         (1 << 0): indicate this pin needs a pull up.
-MULTIDRIVE      (1 << 1): indicate this pin need to be configured as multidrive.
+MULTIDRIVE      (1 << 1): indicate this pin needs to be configured as multi-drive.
-DEGLITCH        (1 << 2): indicate this pin need deglitch.
+                        Multi-drive is equivalent to open-drain type output.
-PULL_DOWN       (1 << 3): indicate this pin need a pull down.
+DEGLITCH        (1 << 2): indicate this pin needs deglitch.
-DIS_SCHMIT      (1 << 4): indicate this pin need to disable schmit trigger.
+PULL_DOWN       (1 << 3): indicate this pin needs a pull down.
-DEBOUNCE        (1 << 16): indicate this pin need debounce.
+DIS_SCHMIT      (1 << 4): indicate this pin needs to the disable schmitt trigger.
-DEBOUNCE_VAL    (0x3fff << 17): debounce val.
+DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
+                        following values:
+                                00 - No change (reset state value kept)
+                                01 - Low
+                                10 - Medium
+                                11 - High
+DEBOUNCE        (1 << 16): indicate this pin needs debounce.
+DEBOUNCE_VAL    (0x3fff << 17): debounce value.
 NOTE:
 Some requirements for using atmel,at91rm9200-pinctrl binding:
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
index 6464bf769460..189814e7cdc7 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
@@ -10,6 +10,7 @@ Required properties:
 - reg: Should contain a list of base address and size pairs for:
    -- first entry - the drive strength and pad control registers.
    -- second entry - the pinmux registers
+    -- third entry - the MIPI_PAD_CTRL register
 Tegra124 adds the following optional properties for pin configuration subnodes.
 The macros for options are defined in the
@@ -91,6 +92,12 @@ Valid values for pin and group names are:
    dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
    gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
+  MIPI pad control groups:
+    These support only the nvidia,function property.
+    dsi_b
 Valid values for nvidia,functions are:
  blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
@@ -101,14 +108,15 @@ Valid values for nvidia,functions are:
  sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
  uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
  vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
-  dp, rtck, sys, clk tmds.
+  dp, rtck, sys, clk tmds, csi, dsi_b
 Example:
        pinmux: pinmux {
                compatible = "nvidia,tegra124-pinmux";
-                reg = <0x70000868 0x164         /* Pad control registers */
+                reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
-                       0x70003000 0x434>;       /* PinMux registers */
+                      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
+                      <0x0 0x70000820 0x0 0x8>;   /* MIPI pad control */
        };
 Example pinmux entries:
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index fa40a177164c..98eb94d91a1c 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -127,6 +127,24 @@ whether there is any interaction between the child and intermediate parent
 nodes, is again defined entirely by the binding for the individual pin
 controller device.
+== Generic pin multiplexing node content ==
+pin multiplexing nodes:
+function                - the mux function to select
+groups                  - the list of groups to select with this function
+Example:
+state_0_node_a {
+        function = "uart0";
+        groups = "u0rxtx", "u0rtscts";
+};
+state_1_node_a {
+        function = "spi0";
+        groups = "spi0pins";
+};
 == Generic pin configuration node content ==
 Many data items that are represented in a pin configuration node are common
@@ -139,8 +157,12 @@ structure of the DT nodes that contain these properties.
 Supported generic properties are:
 pins                    - the list of pins that properties in the node
-                          apply to
+                          apply to (either this or "group" has to be
-function                - the mux function to select
+                          specified)
+group                   - the group to apply the properties to, if the driver
+                          supports configuration of whole groups rather than
+                          individual pins (either this or "pins" has to be
+                          specified)
 bias-disable            - disable any pin bias
 bias-high-impedance     - high impedance mode ("third-state", "floating")
 bias-bus-hold           - latch weakly
@@ -163,6 +185,21 @@ output-low		- set the pin to output mode with low level
 output-high             - set the pin to output mode with high level
 slew-rate               - set the slew rate
+For example:
+state_0_node_a {
+        pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
+        bias-pull-up;
+};
+state_1_node_a {
+        pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
+        output-high;
+};
+state_2_node_a {
+        group = "foo-group";
+        bias-pull-up;
+};
 Some of the generic properties take arguments. For those that do, the
 arguments are described below.
@@ -170,15 +207,6 @@ arguments are described below.
  binding for the hardware defines:
  - Whether the entries are integers or strings, and their meaning.
- function takes a list of function names/IDs as a required argument. The
-  specific binding for the hardware defines:
-  - Whether the entries are integers or strings, and their meaning.
-  - Whether only a single entry is allowed (which is applied to all entries
-    in the pins property), or whether there may alternatively be one entry per
-    entry in the pins property, in which case the list lengths must match, and
-    for each list index i, the function at list index i is applied to the pin
-    at list index i.
 - bias-pull-up, -down and -pin-default take as optional argument on hardware
  supporting it the pull strength in Ohm. bias-disable will disable the pull.
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
index 0211c6d8a522..2fb90b37aa09 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
@@ -50,7 +50,7 @@ Valid values for function are:
  gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
  gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
  gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
-  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
+  riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
 Example:
@@ -62,7 +62,7 @@ Example:
                #gpio-cells = <2>;
                interrupt-controller;
                #interrupt-cells = <2>;
-                interrupts = <0 32 0x4>;
+                interrupts = <0 16 0x4>;
                pinctrl-names = "default";
                pinctrl-0 = <&gsbi5_uart_default>;
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
new file mode 100644
index 000000000000..ffafa1990a30
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt
@@ -0,0 +1,179 @@
+Qualcomm APQ8084 TLMM block
+This binding describes the Top Level Mode Multiplexer block found in the
+MSM8960 platform.
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be "qcom,apq8084-pinctrl"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the base address and size of the TLMM register space.
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: should specify the TLMM summary IRQ.
+- interrupt-controller:
+        Usage: required
+        Value type: <none>
+        Definition: identifies this node as an interrupt controller
+- #interrupt-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: must be 2. Specifying the pin number and flags, as defined
+                    in <dt-bindings/interrupt-controller/irq.h>
+- gpio-controller:
+        Usage: required
+        Value type: <none>
+        Definition: identifies this node as a gpio controller
+- #gpio-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: must be 2. Specifying the pin number and flags, as defined
+                    in <dt-bindings/gpio/gpio.h>
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+The pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+PIN CONFIGURATION NODES:
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+- pins:
+        Usage: required
+        Value type: <string-array>
+        Definition: List of gpio pins affected by the properties specified in
+                    this subnode.  Valid pins are:
+                    gpio0-gpio146,
+                    sdc1_clk,
+                    sdc1_cmd,
+                    sdc1_data
+                    sdc2_clk,
+                    sdc2_cmd,
+                    sdc2_data
+- function:
+        Usage: required
+        Value type: <string>
+        Definition: Specify the alternative function to be configured for the
+                    specified pins. Functions are only valid for gpio pins.
+                    Valid values are:
+                    adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
+                    blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
+                    blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
+                    blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
+                    blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
+                    blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
+                    blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
+                    blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
+                    blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
+                    blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
+                    blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
+                    cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
+                    cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+                    edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
+                    gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
+                    hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
+                    ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
+                    pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
+                    qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
+                    sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
+                    spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
+                    tsif2, uim, uim_batt_alarm
+- bias-disable:
+        Usage: optional
+        Value type: <none>
+        Definition: The specified pins should be configued as no pull.
+- bias-pull-down:
+        Usage: optional
+        Value type: <none>
+        Definition: The specified pins should be configued as pull down.
+- bias-pull-up:
+        Usage: optional
+        Value type: <none>
+        Definition: The specified pins should be configued as pull up.
+- output-high:
+        Usage: optional
+        Value type: <none>
+        Definition: The specified pins are configured in output mode, driven
+                    high.
+                    Not valid for sdc pins.
+- output-low:
+        Usage: optional
+        Value type: <none>
+        Definition: The specified pins are configured in output mode, driven
+                    low.
+                    Not valid for sdc pins.
+- drive-strength:
+        Usage: optional
+        Value type: <u32>
+        Definition: Selects the drive strength for the specified pins, in mA.
+                    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+Example:
+        tlmm: pinctrl@fd510000 {
+                compatible = "qcom,apq8084-pinctrl";
+                reg = <0xfd510000 0x4000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                interrupts = <0 208 0>;
+                uart2: uart2-default {
+                        mux {
+                                pins = "gpio4", "gpio5";
+                                function = "blsp_uart2";
+                        };
+                        tx {
+                                pins = "gpio4";
+                                drive-strength = <4>;
+                                bias-disable;
+                        };
+                        rx {
+                                pins = "gpio5";
+                                drive-strength = <2>;
+                                bias-pull-up;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 4658b69d4f4d..388b213249fd 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -2,8 +2,8 @@
 The Rockchip Pinmux Controller, enables the IC
 to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
+multiplexing the PAD input/output signals. For each PAD there are several
-4 muxing options with option 0 being the use as a GPIO.
+muxing options with option 0 being the use as a GPIO.
 Please refer to pinctrl-bindings.txt in this directory for details of the
 common pinctrl bindings used by client devices, including the meaning of the
@@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
 Required properties for pin configuration node:
  - rockchip,pins: 3 integers array, represents a group of pins mux and config
    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
-    The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
+    The MUX 0 means gpio and MUX 1 to N mean the specific device function.
    The phandle of a node containing the generic pinconfig options
    to use, as described in pinctrl-bindings.txt in this directory.
diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
new file mode 100644
index 000000000000..88c80273da91
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
@@ -0,0 +1,13 @@
+OMAP Pinctrl definitions
+Required properties:
+- compatible : Should be one of:
+  "ti,omap2420-padconf" - OMAP2420 compatible pinctrl
+  "ti,omap2430-padconf" - OMAP2430 compatible pinctrl
+  "ti,omap3-padconf" - OMAP3 compatible pinctrl
+  "ti,omap4-padconf" - OMAP4 compatible pinctrl
+  "ti,omap5-padconf" - OMAP5 compatible pinctrl
+  "ti,dra7-padconf" - DRA7 compatible pinctrl
+  "ti,am437-padconf" - AM437x compatible pinctrl
+See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.
diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt
new file mode 100644
index 000000000000..98c16672ab5f
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/power_domain.txt
@@ -0,0 +1,49 @@
+* Generic PM domains
+System on chip designs are often divided into multiple PM domains that can be
+used for power gating of selected IP blocks for power saving by reduced leakage
+current.
+This device tree binding can be used to bind PM domain consumer devices with
+their PM domains provided by PM domain providers. A PM domain provider can be
+represented by any node in the device tree and can provide one or more PM
+domains. A consumer node can refer to the provider by a phandle and a set of
+phandle arguments (so called PM domain specifiers) of length specified by the
+#power-domain-cells property in the PM domain provider node.
+==PM domain providers==
+Required properties:
+ - #power-domain-cells : Number of cells in a PM domain specifier;
+   Typically 0 for nodes representing a single PM domain and 1 for nodes
+   providing multiple PM domains (e.g. power controllers), but can be any value
+   as specified by device tree binding documentation of particular provider.
+Example:
+        power: power-controller@12340000 {
+                compatible = "foo,power-controller";
+                reg = <0x12340000 0x1000>;
+                #power-domain-cells = <1>;
+        };
+The node above defines a power controller that is a PM domain provider and
+expects one cell as its phandle argument.
+==PM domain consumers==
+Required properties:
+ - power-domains : A phandle and PM domain specifier as defined by bindings of
+                   the power controller specified by phandle.
+Example:
+        leaky-device@12350000 {
+                compatible = "foo,i-leak-current";
+                reg = <0x12350000 0x1000>;
+                power-domains = <&power 0>;
+        };
+The node above defines a typical PM domain consumer device, which is located
+inside a PM domain with index 0 of a power controller represented by a node
+with the label "power".
diff --git a/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt
new file mode 100644
index 000000000000..0c94c637f63b
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ltc2952-poweroff.txt
@@ -0,0 +1,26 @@
+Binding for the LTC2952 PowerPath controller
+This chip is used to externally trigger a system shut down. Once the trigger has
+been sent, the chips' watchdog has to be reset to gracefully shut down.
+If the Linux systems decides to shut down it powers off the platform via the
+kill signal.
+Required properties:
+- compatible:           Must contain: "lltc,ltc2952"
+- trigger-gpios:        phandle + gpio-specifier for the GPIO connected to the
+                        chip's trigger line
+- watchdog-gpios:       phandle + gpio-specifier for the GPIO connected to the
+                        chip's watchdog line
+- kill-gpios:           phandle + gpio-specifier for the GPIO connected to the
+                        chip's kill line
+Example:
+ltc2952 {
+        compatible = "lltc,ltc2952";
+        trigger-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+        watchdog-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+        kill-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+};
diff --git a/Documentation/devicetree/bindings/power/reset/st-reset.txt b/Documentation/devicetree/bindings/power/reset/st-reset.txt
new file mode 100644
index 000000000000..809af54f02f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/st-reset.txt
@@ -0,0 +1,11 @@
+*Device-Tree bindings for ST SW reset functionality
+Required properties:
+- compatible: should be "st,<chip>-restart".
+- st,syscfg: should be a phandle of the syscfg node.
+Example node:
+        restart {
+                compatible = "st,stih416-restart";
+                st,syscfg = <&syscfg_sbc>;
+        };
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
new file mode 100644
index 000000000000..11906316b43d
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
@@ -0,0 +1,23 @@
+Generic SYSCON mapped register reset driver
+This is a generic reset driver using syscon to map the reset register.
+The reset is generally performed with a write to the reset register
+defined by the register map pointed by syscon reference plus the offset
+with the mask defined in the reboot node.
+Required properties:
+- compatible: should contain "syscon-reboot"
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the reboot register (in bytes)
+- mask: the reset value written to the reboot register (32 bit access)
+Default will be little endian mode, 32 bit access only.
+Examples:
+        reboot {
+           compatible = "syscon-reboot";
+           regmap = <&regmapnode>;
+           offset = <0x0>;
+           mask = <0x1>;
+        };
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.txt b/Documentation/devicetree/bindings/power/rockchip-io-domain.txt
new file mode 100644
index 000000000000..6fbf6e7ecde6
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/rockchip-io-domain.txt
@@ -0,0 +1,83 @@
+Rockchip SRAM for IO Voltage Domains:
+-------------------------------------
+IO domain voltages on some Rockchip SoCs are variable but need to be
+kept in sync between the regulators and the SoC using a special
+register.
+A specific example using rk3288:
+- If the regulator hooked up to a pin like SDMMC0_VDD is 3.3V then
+  bit 7 of GRF_IO_VSEL needs to be 0.  If the regulator hooked up to
+  that same pin is 1.8V then bit 7 of GRF_IO_VSEL needs to be 1.
+Said another way, this driver simply handles keeping bits in the SoC's
+general register file (GRF) in sync with the actual value of a voltage
+hooked up to the pins.
+Note that this driver specifically doesn't include:
+- any logic for deciding what voltage we should set regulators to
+- any logic for deciding whether regulators (or internal SoC blocks)
+  should have power or not have power
+If there were some other software that had the smarts of making
+decisions about regulators, it would work in conjunction with this
+driver.  When that other software adjusted a regulator's voltage then
+this driver would handle telling the SoC about it.  A good example is
+vqmmc for SD.  In that case the dw_mmc driver simply is told about a
+regulator.  It changes the regulator between 3.3V and 1.8V at the
+right time.  This driver notices the change and makes sure that the
+SoC is on the same page.
+Required properties:
+- compatible: should be one of:
+  - "rockchip,rk3188-io-voltage-domain" for rk3188
+  - "rockchip,rk3288-io-voltage-domain" for rk3288
+- rockchip,grf: phandle to the syscon managing the "general register files"
+You specify supplies using the standard regulator bindings by including
+a phandle the the relevant regulator.  All specified supplies must be able
+to report their voltage.  The IO Voltage Domain for any non-specified
+supplies will be not be touched.
+Possible supplies for rk3188:
+- ap0-supply:    The supply connected to AP0_VCC.
+- ap1-supply:    The supply connected to AP1_VCC.
+- cif-supply:    The supply connected to CIF_VCC.
+- flash-supply:  The supply connected to FLASH_VCC.
+- lcdc0-supply:  The supply connected to LCD0_VCC.
+- lcdc1-supply:  The supply connected to LCD1_VCC.
+- vccio0-supply: The supply connected to VCCIO0.
+- vccio1-supply: The supply connected to VCCIO1.
+                 Sometimes also labeled VCCIO1 and VCCIO2.
+Possible supplies for rk3288:
+- audio-supply:  The supply connected to APIO4_VDD.
+- bb-supply:     The supply connected to APIO5_VDD.
+- dvp-supply:    The supply connected to DVPIO_VDD.
+- flash0-supply: The supply connected to FLASH0_VDD.  Typically for eMMC
+- flash1-supply: The supply connected to FLASH1_VDD.  Also known as SDIO1.
+- gpio30-supply: The supply connected to APIO1_VDD.
+- gpio1830       The supply connected to APIO2_VDD.
+- lcdc-supply:   The supply connected to LCDC_VDD.
+- sdcard-supply: The supply connected to SDMMC0_VDD.
+- wifi-supply:   The supply connected to APIO3_VDD.  Also known as SDIO0.
+Example:
+        io-domains {
+                compatible = "rockchip,rk3288-io-voltage-domain";
+                rockchip,grf = <&grf>;
+                audio-supply = <&vcc18_codec>;
+                bb-supply = <&vcc33_io>;
+                dvp-supply = <&vcc_18>;
+                flash0-supply = <&vcc18_flashio>;
+                gpio1830-supply = <&vcc33_io>;
+                gpio30-supply = <&vcc33_pmuio>;
+                lcdc-supply = <&vcc33_lcd>;
+                sdcard-supply = <&vccio_sd>;
+                wifi-supply = <&vcc18_wl>;
+        };
diff --git a/Documentation/devicetree/bindings/power_supply/charger-manager.txt b/Documentation/devicetree/bindings/power_supply/charger-manager.txt
index 2b33750e3db2..ec4fe9de3137 100644
--- a/Documentation/devicetree/bindings/power_supply/charger-manager.txt
+++ b/Documentation/devicetree/bindings/power_supply/charger-manager.txt
@@ -24,7 +24,7 @@ Optional properties :
 - cm-thermal-zone : name of external thermometer's thermal zone
 - cm-battery-* : threshold battery temperature for charging
        -cold : critical cold temperature of battery for charging
-        -cold-in-minus : flag that cold temerature is in minus degree
+        -cold-in-minus : flag that cold temperature is in minus degrees
        -hot : critical hot temperature of battery for charging
        -temp-diff : temperature difference to allow recharging
 - cm-dis/charging-max = limits of charging duration
diff --git a/Documentation/devicetree/bindings/regmap/regmap.txt b/Documentation/devicetree/bindings/regmap/regmap.txt
new file mode 100644
index 000000000000..b494f8b8ef72
--- /dev/null
+++ b/Documentation/devicetree/bindings/regmap/regmap.txt
@@ -0,0 +1,47 @@
+Device-Tree binding for regmap
+The endianness mode of CPU & Device scenarios:
+Index     Device     Endianness properties
+---------------------------------------------------
+1         BE         'big-endian'
+2         LE         'little-endian'
+For one device driver, which will run in different scenarios above
+on different SoCs using the devicetree, we need one way to simplify
+this.
+Required properties:
+- {big,little}-endian: these are boolean properties, if absent
+  meaning that the CPU and the Device are in the same endianness mode,
+  these properties are for register values and all the buffers only.
+Examples:
+Scenario 1 : CPU in LE mode & device in LE mode.
+dev: dev@40031000 {
+              compatible = "name";
+              reg = <0x40031000 0x1000>;
+              ...
+};
+Scenario 2 : CPU in LE mode & device in BE mode.
+dev: dev@40031000 {
+              compatible = "name";
+              reg = <0x40031000 0x1000>;
+              ...
+              big-endian;
+};
+Scenario 3 : CPU in BE mode & device in BE mode.
+dev: dev@40031000 {
+              compatible = "name";
+              reg = <0x40031000 0x1000>;
+              ...
+};
+Scenario 4 : CPU in BE mode & device in LE mode.
+dev: dev@40031000 {
+              compatible = "name";
+              reg = <0x40031000 0x1000>;
+              ...
+              little-endian;
+};
diff --git a/Documentation/devicetree/bindings/regulator/da9210.txt b/Documentation/devicetree/bindings/regulator/da9210.txt
index f120f229d67d..3297c53cb915 100644
--- a/Documentation/devicetree/bindings/regulator/da9210.txt
+++ b/Documentation/devicetree/bindings/regulator/da9210.txt
@@ -2,7 +2,7 @@
 Required properties:
- compatible:   must be "diasemi,da9210"
+- compatible:   must be "dlg,da9210"
 - reg:          the i2c slave address of the regulator. It should be 0x68.
 Any standard regulator properties can be used to configure the single da9210
@@ -11,7 +11,7 @@ DCDC.
 Example:
        da9210@68 {
-                compatible = "diasemi,da9210";
+                compatible = "dlg,da9210";
                reg = <0x68>;
                regulator-min-microvolt = <900000>;
diff --git a/Documentation/devicetree/bindings/regulator/da9211.txt b/Documentation/devicetree/bindings/regulator/da9211.txt
new file mode 100644
index 000000000000..240019a82f9a
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/da9211.txt
@@ -0,0 +1,63 @@
+* Dialog Semiconductor DA9211/DA9213 Voltage Regulator
+Required properties:
+- compatible: "dlg,da9211" or "dlg,da9213".
+- reg: I2C slave address, usually 0x68.
+- interrupts: the interrupt outputs of the controller
+- regulators: A node that houses a sub-node for each regulator within the
+  device. Each sub-node is identified using the node's name, with valid
+  values listed below. The content of each sub-node is defined by the
+  standard binding for regulators; see regulator.txt.
+  BUCKA and BUCKB.
+Optional properties:
+- Any optional property defined in regulator.txt
+Example 1) DA9211
+        pmic: da9211@68 {
+                compatible = "dlg,da9211";
+                reg = <0x68>;
+                interrupts = <3 27>;
+                regulators {
+                        BUCKA {
+                                regulator-name = "VBUCKA";
+                                regulator-min-microvolt = < 300000>;
+                                regulator-max-microvolt = <1570000>;
+                                regulator-min-microamp  = <2000000>;
+                                regulator-max-microamp  = <5000000>;
+                        };
+                        BUCKB {
+                                regulator-name = "VBUCKB";
+                                regulator-min-microvolt = < 300000>;
+                                regulator-max-microvolt = <1570000>;
+                                regulator-min-microamp  = <2000000>;
+                                regulator-max-microamp  = <5000000>;
+                        };
+                };
+        };
+Example 2) DA92113
+        pmic: da9213@68 {
+                compatible = "dlg,da9213";
+                reg = <0x68>;
+                interrupts = <3 27>;
+                regulators {
+                        BUCKA {
+                                regulator-name = "VBUCKA";
+                                regulator-min-microvolt = < 300000>;
+                                regulator-max-microvolt = <1570000>;
+                                regulator-min-microamp  = <3000000>;
+                                regulator-max-microamp  = <6000000>;
+                        };
+                        BUCKB {
+                                regulator-name = "VBUCKB";
+                                regulator-min-microvolt = < 300000>;
+                                regulator-max-microvolt = <1570000>;
+                                regulator-min-microamp  = <3000000>;
+                                regulator-max-microamp  = <6000000>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/fan53555.txt b/Documentation/devicetree/bindings/regulator/fan53555.txt
new file mode 100644
index 000000000000..54a3f2c80e3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/fan53555.txt
@@ -0,0 +1,23 @@
+Binding for Fairchild FAN53555 regulators
+Required properties:
+  - compatible: one of "fcs,fan53555", "silergy,syr827", "silergy,syr828"
+  - reg: I2C address
+Optional properties:
+  - fcs,suspend-voltage-selector: declare which of the two available
+                voltage selector registers should be used for the suspend
+                voltage. The other one is used for the runtime voltage setting
+                Possible values are either <0> or <1>
+  - vin-supply: regulator supplying the vin pin
+Example:
+        regulator@40 {
+                compatible = "fcs,fan53555";
+                regulator-name = "fan53555";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1800000>;
+                vin-supply = <&parent_reg>;
+                fcs,suspend-voltage-selector = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/isl9305.txt b/Documentation/devicetree/bindings/regulator/isl9305.txt
new file mode 100644
index 000000000000..a626fc1bbf0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/isl9305.txt
@@ -0,0 +1,36 @@
+Intersil ISL9305/ISL9305H voltage regulator
+Required properties:
+- compatible: "isl,isl9305" or "isl,isl9305h"
+- reg: I2C slave address, usually 0x68.
+- regulators: A node that houses a sub-node for each regulator within the
+  device. Each sub-node is identified using the node's name, with valid
+  values being "dcd1", "dcd2", "ldo1" and "ldo2". The content of each sub-node
+  is defined by the standard binding for regulators; see regulator.txt.
+- VINDCD1-supply: A phandle to a regulator node supplying VINDCD1.
+  VINDCD2-supply: A phandle to a regulator node supplying VINDCD2.
+  VINLDO1-supply: A phandle to a regulator node supplying VINLDO1.
+  VINLDO2-supply: A phandle to a regulator node supplying VINLDO2.
+Optional properties:
+- Per-regulator optional properties are defined in regulator.txt
+Example
+        pmic: isl9305@68 {
+                compatible = "isl,isl9305";
+                reg = <0x68>;
+                VINDCD1-supply = <&system_power>;
+                VINDCD2-supply = <&system_power>;
+                VINLDO1-supply = <&system_power>;
+                VINLDO2-supply = <&system_power>;
+                regulators {
+                        dcd1 {
+                                regulator-name = "VDD_DSP";
+                                regulator-always-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/max1586-regulator.txt b/Documentation/devicetree/bindings/regulator/max1586-regulator.txt
new file mode 100644
index 000000000000..c050c1744cb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max1586-regulator.txt
@@ -0,0 +1,28 @@
+Maxim MAX1586 voltage regulator
+Required properties:
+- compatible: must be "maxim,max1586"
+- reg: I2C slave address, usually 0x14
+- v3-gain: integer specifying the V3 gain as per datasheet
+           (1 + R24/R25 + R24/185.5kOhm)
+- any required generic properties defined in regulator.txt
+Example:
+        i2c_master {
+                max1586@14 {
+                        compatible = "maxim,max1586";
+                        reg = <0x14>;
+                        v3-gain = <1000000>;
+                        regulators {
+                                vcc_core: v3 {
+                                        regulator-name = "vcc_core";
+                                        regulator-compatible = "Output_V3";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1705000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/max77802.txt b/Documentation/devicetree/bindings/regulator/max77802.txt
new file mode 100644
index 000000000000..5aeaffc0f1f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max77802.txt
@@ -0,0 +1,53 @@
+Binding for Maxim MAX77802 regulators
+This is a part of device tree bindings of MAX77802 multi-function device.
+More information can be found in bindings/mfd/max77802.txt file.
+The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout (LDO)
+regulators that can be controlled over I2C.
+Following properties should be present in main device node of the MFD chip.
+Optional node:
+- regulators : The regulators of max77802 have to be instantiated
+  under subnode named "regulators" using the following format.
+        regulator-name {
+                standard regulator constraints....
+        };
+        refer Documentation/devicetree/bindings/regulator/regulator.txt
+The regulator node name should be initialized with a string to get matched
+with their hardware counterparts as follow. The valid names are:
+        -LDOn   :       for LDOs, where n can lie in ranges 1-15, 17-21, 23-30
+                        and 32-35.
+                        example: LDO1, LDO2, LDO35.
+        -BUCKn  :       for BUCKs, where n can lie in range 1 to 10.
+                        example: BUCK1, BUCK5, BUCK10.
+Example:
+        max77802@09 {
+                compatible = "maxim,max77802";
+                interrupt-parent = <&wakeup_eint>;
+                interrupts = <26 0>;
+                reg = <0x09>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                regulators {
+                        ldo11_reg: LDO11 {
+                                regulator-name = "vdd_ldo11";
+                                regulator-min-microvolt = <1900000>;
+                                regulator-max-microvolt = <1900000>;
+                                regulator-always-on;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
new file mode 100644
index 000000000000..ce91f61feb12
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
@@ -0,0 +1,27 @@
+pwm regulator bindings
+Required properties:
+- compatible: Should be "pwm-regulator"
+- pwms: OF device-tree PWM specification (see PWM binding pwm.txt)
+- voltage-table: voltage and duty table, include 2 members in each set of
+  brackets, first one is voltage(unit: uv), the next is duty(unit: percent)
+Any property defined as part of the core regulator binding defined in
+regulator.txt can also be used.
+Example:
+        pwm_regulator {
+                compatible = "pwm-regulator;
+                pwms = <&pwm1 0 8448 0>;
+                voltage-table = <1114000 0>,
+                                <1095000 10>,
+                                <1076000 20>,
+                                <1056000 30>,
+                                <1036000 40>,
+                                <1016000 50>;
+                regulator-min-microvolt = <1016000>;
+                regulator-max-microvolt = <1114000>;
+                regulator-name = "vdd_logic";
+        };
diff --git a/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt b/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt
new file mode 100644
index 000000000000..882455e9b36d
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/sky81452-regulator.txt
@@ -0,0 +1,16 @@
+SKY81452 voltage regulator
+Required properties:
+- any required generic properties defined in regulator.txt
+Optional properties:
+- any available generic properties defined in regulator.txt
+Example:
+        regulator {
+                /* generic regulator properties */
+                regulator-name = "touch_en";
+                regulator-min-microvolt = <4500000>;
+                regulator-max-microvolt = <8000000>;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/tps65090.txt b/Documentation/devicetree/bindings/regulator/tps65090.txt
index 340980239ea9..ca69f5e3040c 100644
--- a/Documentation/devicetree/bindings/regulator/tps65090.txt
+++ b/Documentation/devicetree/bindings/regulator/tps65090.txt
@@ -45,8 +45,8 @@ Example:
                infet5-supply = <&some_reg>;
                infet6-supply = <&some_reg>;
                infet7-supply = <&some_reg>;
-                vsys_l1-supply = <&some_reg>;
+                vsys-l1-supply = <&some_reg>;
-                vsys_l2-supply = <&some_reg>;
+                vsys-l2-supply = <&some_reg>;
                regulators {
                        dcdc1 {
diff --git a/Documentation/devicetree/bindings/rng/apm,rng.txt b/Documentation/devicetree/bindings/rng/apm,rng.txt
new file mode 100644
index 000000000000..4dde4b06cdd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/apm,rng.txt
@@ -0,0 +1,17 @@
+APM X-Gene SoC random number generator.
+Required properties:
+- compatible  : should be "apm,xgene-rng"
+- reg         : specifies base physical address and size of the registers map
+- clocks      : phandle to clock-controller plus clock-specifier pair
+- interrupts  : specify the fault interrupt for the RNG device
+Example:
+        rng: rng@10520000 {
+                compatible = "apm,xgene-rng";
+                reg = <0x0 0x10520000 0x0 0x100>;
+                interrupts =   <0x0 0x41 0x4>;
+                clocks = <&rngpkaclk 0>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt b/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt
new file mode 100644
index 000000000000..916f57601a8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/dallas,ds1339.txt
@@ -0,0 +1,18 @@
+* Dallas DS1339         I2C Serial Real-Time Clock
+Required properties:
+- compatible: Should contain "dallas,ds1339".
+- reg: I2C address for chip
+Optional properties:
+- trickle-resistor-ohms : Selected resistor for trickle charger
+        Values usable for ds1339 are 250, 2000, 4000
+        Should be given if trickle charger should be enabled
+- trickle-diode-disable : Do not use internal trickle charger diode
+        Should be given if internal trickle charger diode should be disabled
+Example:
+        ds1339: rtc@68 {
+                compatible = "dallas,ds1339";
+                trickle-resistor-ohms = <250>;
+                reg = <0x68>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
index 7ac7259fe9ea..ab757b84daa7 100644
--- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
@@ -3,7 +3,10 @@
 Required properties:
 - compatible: should be one of the following.
    * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
+    * "samsung,s3c2416-rtc" - for controllers compatible with s3c2416 rtc.
+    * "samsung,s3c2443-rtc" - for controllers compatible with s3c2443 rtc.
    * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
+    * "samsung,exynos3250-rtc" - for controllers compatible with exynos3250 rtc.
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: Two interrupt numbers to the cpu should be specified. First
diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
new file mode 100644
index 000000000000..f007e428a1ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
@@ -0,0 +1,17 @@
+* sun6i Real Time Clock
+RTC controller for the Allwinner A31
+Required properties:
+- compatible    : Should be "allwinner,sun6i-a31-rtc"
+- reg           : physical base address of the controller and length of
+                  memory mapped region.
+- interrupts    : IRQ lines for the RTC alarm 0 and alarm 1, in that order.
+Example:
+rtc: rtc@01f00000 {
+        compatible = "allwinner,sun6i-a31-rtc";
+        reg = <0x01f00000 0x54>;
+        interrupts = <0 40 4>, <0 41 4>;
+};
diff --git a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt
index 12f3cf834deb..caaeb2583579 100644
--- a/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt
+++ b/Documentation/devicetree/bindings/serial/cirrus,clps711x-uart.txt
@@ -8,7 +8,8 @@ Required properties:
 - syscon: Phandle to SYSCON node, which contain UART control bits.
 Optional properties:
- uart-use-ms: Indicate the UART has modem signal (DCD, DSR, CTS).
+- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
+  line respectively.
 Note: Each UART port should have an alias correctly numbered
 in "aliases" node.
@@ -24,5 +25,7 @@ Example:
                interrupts = <12 13>;
                clocks = <&clks 11>;
                syscon = <&syscon1>;
-                uart-use-ms;
+                cts-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
+                dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
+                dcd-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
        };
diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt
new file mode 100644
index 000000000000..48358a33ea7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt
@@ -0,0 +1,22 @@
+* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
+Required properties:
+- compatible should contain:
+  * "mediatek,mt6589-uart" for MT6589 compatible UARTS
+  * "mediatek,mt6582-uart" for MT6582 compatible UARTS
+  * "mediatek,mt6577-uart" for all compatible UARTS (MT6589, MT6582, MT6577)
+- reg: The base address of the UART register bank.
+- interrupts: A single interrupt specifier.
+- clocks: Clock driving the hardware.
+Example:
+        uart0: serial@11006000 {
+                compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart";
+                reg = <0x11006000 0x400>;
+                interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
+                clocks = <&uart_clk>;
+        };
diff --git a/Documentation/devicetree/bindings/serial/of-serial.txt b/Documentation/devicetree/bindings/serial/of-serial.txt
index 77054772a8f4..8c4fd0332028 100644
--- a/Documentation/devicetree/bindings/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/serial/of-serial.txt
@@ -14,6 +14,7 @@ Required properties:
        - "altr,16550-FIFO32"
        - "altr,16550-FIFO64"
        - "altr,16550-FIFO128"
+        - "fsl,16550-FIFO64"
        - "serial" if the port type is unknown.
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
@@ -37,7 +38,6 @@ Optional properties:
 - auto-flow-control: one way to enable automatic flow control support. The
  driver is allowed to detect support for the capability even without this
  property.
- has-hw-flow-control: the hardware has flow control capability.
 Example:
diff --git a/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt
deleted file mode 100644
index 5feef1ef167d..000000000000
--- a/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-VIA/Wondermedia VT8500 UART Controller
-----------------------------------------------------
-Required properties:
- compatible : "via,vt8500-uart"
- reg : Should contain 1 register ranges(address and length)
- interrupts : UART interrupt
- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
-Example:
-        uart@d8210000 {
-                compatible = "via,vt8500-uart";
-                reg = <0xd8210000 0x1040>;
-                interrupts = <47>;
-                clocks = <&ref24>;
-        };
diff --git a/Documentation/devicetree/bindings/serial/vt8500-uart.txt b/Documentation/devicetree/bindings/serial/vt8500-uart.txt
index 795c393d09c4..2b64e6107fb3 100644
--- a/Documentation/devicetree/bindings/serial/vt8500-uart.txt
+++ b/Documentation/devicetree/bindings/serial/vt8500-uart.txt
@@ -1,7 +1,8 @@
 * VIA VT8500 and WonderMedia WM8xxx UART Controller
 Required properties:
- compatible: should be "via,vt8500-uart"
+- compatible: should be "via,vt8500-uart" (for VIA/WonderMedia chips up to and
+        including WM8850/WM8950), or "wm,wm8880-uart" (for WM8880 and later)
 - reg: base physical address of the controller and length of memory mapped
        region.
diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt
new file mode 100644
index 000000000000..337c4ea5c57b
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-dma.txt
@@ -0,0 +1,111 @@
+Keystone Navigator DMA Controller
+This document explains the device tree bindings for the packet dma
+on keystone devices. The Keystone Navigator DMA driver sets up the dma
+channels and flows for the QMSS(Queue Manager SubSystem) who triggers
+the actual data movements across clients using destination queues. Every
+client modules like  NETCP(Network Coprocessor), SRIO(Serial Rapid IO),
+CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
+an internal packet DMA module which is used as an infrastructure DMA
+with zero copy.
+Navigator DMA cloud layout:
+        ------------------
+        | Navigator DMAs |
+        ------------------
+                |
+                |-> DMA instance #0
+                |
+                |-> DMA instance #1
+                        .
+                        .
+                |
+                |-> DMA instance #n
+Navigator DMA properties:
+Required properties:
+ - compatible: Should be "ti,keystone-navigator-dma"
+ - clocks: phandle to dma instances clocks. The clock handles can be as
+        many as the dma instances. The order should be maintained as per
+        the dma instances.
+ - ti,navigator-cloud-address: Should contain base address for the multi-core
+        navigator cloud and number of addresses depends on SOC integration
+        configuration.. Navigator cloud global address needs to be programmed
+        into DMA and the DMA uses it as the physical addresses to reach queue
+        managers. Note that these addresses though points to queue managers,
+        they are relevant only from DMA perspective. The QMSS may not choose to
+        use them since it has a different address space view to reach all
+        its components.
+DMA instance properties:
+Required properties:
+ - reg: Should contain register location and length of the following dma
+        register regions. Register regions should be specified in the following
+        order.
+        - Global control register region (global).
+        - Tx DMA channel configuration register region (txchan).
+        - Rx DMA channel configuration register region (rxchan).
+        - Tx DMA channel Scheduler configuration register region (txsched).
+        - Rx DMA flow configuration register region (rxflow).
+Optional properties:
+ - reg-names: Names for the register regions.
+ - ti,enable-all: Enable all DMA channels vs clients opening specific channels
+        what they need. This property is useful for the userspace fast path
+        case where the linux drivers enables the channels used by userland
+        stack.
+ - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for
+              infrastructure transfers.
+ - ti,rx-retry-timeout: Number of dma cycles to wait before retry on buffer
+                     starvation.
+Example:
+        knav_dmas: knav_dmas@0 {
+                compatible = "ti,keystone-navigator-dma";
+                clocks = <&papllclk>, <&clkxge>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,navigator-cloud-address = <0x23a80000 0x23a90000
+                                           0x23aa0000 0x23ab0000>;
+                dma_gbe: dma_gbe@0 {
+                        reg = <0x2004000 0x100>,
+                                  <0x2004400 0x120>,
+                                  <0x2004800 0x300>,
+                                  <0x2004c00 0x120>,
+                                  <0x2005000 0x400>;
+                        reg-names = "global", "txchan", "rxchan",
+                                        "txsched", "rxflow";
+                };
+                dma_xgbe: dma_xgbe@0 {
+                        reg = <0x2fa1000 0x100>,
+                                <0x2fa1400 0x200>,
+                                <0x2fa1800 0x200>,
+                                <0x2fa1c00 0x200>,
+                                <0x2fa2000 0x400>;
+                        reg-names = "global", "txchan", "rxchan",
+                                        "txsched", "rxflow";
+                };
+        };
+Navigator DMA client:
+Required properties:
+ - ti,navigator-dmas: List of one or more DMA specifiers, each consisting of
+                        - A phandle pointing to DMA instance node
+                        - A DMA channel number as a phandle arg.
+ - ti,navigator-dma-names: Contains dma channel name for each DMA specifier in
+                        the 'ti,navigator-dmas' property.
+Example:
+        netcp: netcp@2090000 {
+                ..
+                ti,navigator-dmas = <&dma_gbe 22>,
+                                <&dma_gbe 23>,
+                                <&dma_gbe 8>;
+                ti,navigator-dma-names = "netrx0", "netrx1", "nettx";
+                ..
+        };
diff --git a/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
new file mode 100644
index 000000000000..d8e8cdb733f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt
@@ -0,0 +1,232 @@
+* Texas Instruments Keystone Navigator Queue Management SubSystem driver
+The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of
+the main hardware sub system which forms the backbone of the Keystone
+multi-core Navigator. QMSS consist of queue managers, packed-data structure
+processors(PDSP), linking RAM, descriptor pools and infrastructure
+Packet DMA.
+The Queue Manager is a hardware module that is responsible for accelerating
+management of the packet queues. Packets are queued/de-queued by writing or
+reading descriptor address to a particular memory mapped location. The PDSPs
+perform QMSS related functions like accumulation, QoS, or event management.
+Linking RAM registers are used to link the descriptors which are stored in
+descriptor RAM. Descriptor RAM is configurable as internal or external memory.
+The QMSS driver manages the PDSP setups, linking RAM regions,
+queue pool management (allocation, push, pop and notify) and descriptor
+pool management.
+Required properties:
+- compatible    : Must be "ti,keystone-navigator-qmss";
+- clocks        : phandle to the reference clock for this device.
+- queue-range   : <start number> total range of queue numbers for the device.
+- linkram0      : <address size> for internal link ram, where size is the total
+                  link ram entries.
+- linkram1      : <address size> for external link ram, where size is the total
+                  external link ram entries. If the address is specified as "0"
+                  driver will allocate memory.
+- qmgrs         : child node describing the individual queue managers on the
+                  SoC. On keystone 1 devices there should be only one node.
+                  On keystone 2 devices there can be more than 1 node.
+  -- managed-queues     : the actual queues managed by each queue manager
+                          instance, specified as <"base queue #" "# of queues">.
+  -- reg                : Address and size of the register set for the device.
+                          Register regions should be specified in the following
+                          order
+                          - Queue Peek region.
+                          - Queue status RAM.
+                          - Queue configuration region.
+                          - Descriptor memory setup region.
+                          - Queue Management/Queue Proxy region for queue Push.
+                          - Queue Management/Queue Proxy region for queue Pop.
+- queue-pools   : child node classifying the queue ranges into pools.
+                  Queue ranges are grouped into 3 type of pools:
+                  - qpend           : pool of qpend(interruptible) queues
+                  - general-purpose : pool of general queues, primarly used
+                                      as free descriptor queues or the
+                                      transmit DMA queues.
+                  - accumulator     : pool of queues on PDSP accumulator channel
+                  Each range can have the following properties:
+  -- qrange             : number of queues to use per queue range, specified as
+                          <"base queue #" "# of queues">.
+  -- interrupts         : Optional property to specify the interrupt mapping
+                          for interruptible queues. The driver additionaly sets
+                          the interrupt affinity hint based on the cpu mask.
+  -- qalloc-by-id       : Optional property to specify that the queues in this
+                          range can only be allocated by queue id.
+  -- accumulator        : Accumulator channel specification. Any of the PDSPs in
+                          QMSS can be loaded with the accumulator firmware. The
+                          accumulator firmware’s job is to poll a select number of
+                          queues looking for descriptors that have been pushed
+                          into them. Descriptors are popped from the queue and
+                          placed in a buffer provided by the host. When the list
+                          becomes full or a programmed time period expires, the
+                          accumulator triggers an interrupt to the host to read
+                          the buffer for descriptor information. This firmware
+                          comes in 16, 32, and 48 channel builds. Each of these
+                          channels can be configured to monitor 32 contiguous
+                          queues.  Accumulator channel property is specified as:
+                          <pdsp-id, channel, entries, pacing mode, latency>
+                          pdsp-id     : QMSS PDSP running accumulator firmware
+                                        on which the channel has to be
+                                        configured
+                          channel     : Accumulator channel number
+                          entries     : Size of the accumulator descriptor list
+                          pacing mode : Interrupt pacing mode
+                                        0 : None, i.e interrupt on list full only
+                                        1 : Time delay since last interrupt
+                                        2 : Time delay since first new packet
+                                        3 : Time delay since last new packet
+                          latency     : time to delay the interrupt, specified
+                                        in microseconds.
+  -- multi-queue        : Optional property to specify that the channel has to
+                          monitor upto 32 queues starting at the base queue #.
+- descriptor-regions    : child node describing the memory regions for keystone
+                          navigator packet DMA descriptors. The memory for
+                          descriptors will be allocated by the driver.
+  -- id                         : region number in QMSS.
+  -- region-spec                : specifies the number of descriptors in the
+                                  region, specified as
+                                  <"# of descriptors" "descriptor size">.
+  -- link-index                 : start index, i.e. index of the first
+                                  descriptor in the region.
+Optional properties:
+- dma-coherent  : Present if DMA operations are coherent.
+- pdsps         : child node describing the PDSP configuration.
+  -- firmware           : firmware to be loaded on the PDSP.
+  -- id                 : the qmss pdsp that will run the firmware.
+  -- reg                : Address and size of the register set for the PDSP.
+                          Register regions should be specified in the following
+                          order
+                          - PDSP internal RAM region.
+                          - PDSP control/status region registers.
+                          - QMSS interrupt distributor registers.
+                          - PDSP command interface region.
+Example:
+qmss: qmss@2a40000 {
+        compatible = "ti,keystone-qmss";
+        dma-coherent;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        clocks = <&chipclk13>;
+        ranges;
+        queue-range     = <0 0x4000>;
+        linkram0        = <0x100000 0x8000>;
+        linkram1        = <0x0 0x10000>;
+        qmgrs {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                qmgr0 {
+                        managed-queues = <0 0x2000>;
+                        reg = <0x2a40000 0x20000>,
+                              <0x2a06000 0x400>,
+                              <0x2a02000 0x1000>,
+                              <0x2a03000 0x1000>,
+                              <0x23a80000 0x20000>,
+                              <0x2a80000 0x20000>;
+                };
+                qmgr1 {
+                        managed-queues = <0x2000 0x2000>;
+                        reg = <0x2a60000 0x20000>,
+                              <0x2a06400 0x400>,
+                              <0x2a04000 0x1000>,
+                              <0x2a05000 0x1000>,
+                              <0x23aa0000 0x20000>,
+                              <0x2aa0000 0x20000>;
+                };
+        };
+        queue-pools {
+                qpend {
+                        qpend-0 {
+                                qrange = <658 8>;
+                                interrupts =<0 40 0xf04 0 41 0xf04 0 42 0xf04
+                                             0 43 0xf04 0 44 0xf04 0 45 0xf04
+                                             0 46 0xf04 0 47 0xf04>;
+                        };
+                        qpend-1 {
+                                qrange = <8704 16>;
+                                interrupts = <0 48 0xf04 0 49 0xf04 0 50 0xf04
+                                              0 51 0xf04 0 52 0xf04 0 53 0xf04
+                                              0 54 0xf04 0 55 0xf04 0 56 0xf04
+                                              0 57 0xf04 0 58 0xf04 0 59 0xf04
+                                              0 60 0xf04 0 61 0xf04 0 62 0xf04
+                                              0 63 0xf04>;
+                                qalloc-by-id;
+                        };
+                        qpend-2 {
+                                qrange = <8720 16>;
+                                interrupts = <0 64 0xf04 0 65 0xf04 0 66 0xf04
+                                              0 59 0xf04 0 68 0xf04 0 69 0xf04
+                                              0 70 0xf04 0 71 0xf04 0 72 0xf04
+                                              0 73 0xf04 0 74 0xf04 0 75 0xf04
+                                              0 76 0xf04 0 77 0xf04 0 78 0xf04
+                                              0 79 0xf04>;
+                        };
+                };
+                general-purpose {
+                        gp-0 {
+                                qrange = <4000 64>;
+                        };
+                        netcp-tx {
+                                qrange = <640 9>;
+                                qalloc-by-id;
+                        };
+                };
+                accumulator {
+                        acc-0 {
+                                qrange = <128 32>;
+                                accumulator = <0 36 16 2 50>;
+                                interrupts = <0 215 0xf01>;
+                                multi-queue;
+                                qalloc-by-id;
+                        };
+                        acc-1 {
+                                qrange = <160 32>;
+                                accumulator = <0 37 16 2 50>;
+                                interrupts = <0 216 0xf01>;
+                                multi-queue;
+                        };
+                        acc-2 {
+                                qrange = <192 32>;
+                                accumulator = <0 38 16 2 50>;
+                                interrupts = <0 217 0xf01>;
+                                multi-queue;
+                        };
+                        acc-3 {
+                                qrange = <224 32>;
+                                accumulator = <0 39 16 2 50>;
+                                interrupts = <0 218 0xf01>;
+                                multi-queue;
+                        };
+                };
+        };
+        descriptor-regions {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                region-12 {
+                        id = <12>;
+                        region-spec = <8192 128>; /* num_desc desc_size */
+                        link-index = <0x4000>;
+                };
+        };
+        pdsps {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                pdsp0@0x2a10000 {
+                        firmware = "keystone/qmss_pdsp_acc48_k2_le_1_0_0_8.fw";
+                        reg = <0x2a10000 0x1000>,
+                              <0x2a0f000 0x100>,
+                              <0x2a0c000 0x3c8>,
+                              <0x2a20000 0x4000>;
+                        id = <0>;
+                };
+        };
+}; /* qmss */
diff --git a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
index 46f344965313..4eb7997674a0 100644
--- a/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
+++ b/Documentation/devicetree/bindings/sound/adi,axi-spdif-tx.txt
@@ -1,7 +1,7 @@
 ADI AXI-SPDIF controller
 Required properties:
- - compatible : Must be "adi,axi-spdif-1.00.a"
+ - compatible : Must be "adi,axi-spdif-tx-1.00.a"
 - reg : Must contain SPDIF core's registers location and length
 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
   The controller expects two clocks, the clock used for the AXI interface and
diff --git a/Documentation/devicetree/bindings/sound/adi,ssm2602.txt b/Documentation/devicetree/bindings/sound/adi,ssm2602.txt
new file mode 100644
index 000000000000..3b3302fe399b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/adi,ssm2602.txt
@@ -0,0 +1,19 @@
+Analog Devices SSM2602, SSM2603 and SSM2604 I2S audio CODEC devices
+SSM2602 support both I2C and SPI as the configuration interface,
+the selection is made by the MODE strap-in pin.
+SSM2603 and SSM2604 only support I2C as the configuration interface.
+Required properties:
+  - compatible : One of "adi,ssm2602", "adi,ssm2603" or "adi,ssm2604"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+ Example:
+        ssm2602: ssm2602@1a {
+                compatible = "adi,ssm2602";
+                reg = <0x1a>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/cs35l32.txt b/Documentation/devicetree/bindings/sound/cs35l32.txt
new file mode 100644
index 000000000000..1417d3f5cc22
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs35l32.txt
@@ -0,0 +1,62 @@
+CS35L32 audio CODEC
+Required properties:
+  - compatible : "cirrus,cs35l32"
+  - reg : the I2C address of the device for I2C. Address is determined by the level
+  of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
+  - VA-supply, VP-supply : power supplies for the device,
+  as covered in Documentation/devicetree/bindings/regulator/regulator.txt.
+Optional properties:
+  - reset-gpios : a GPIO spec for the reset pin. If specified, it will be
+  deasserted before communication to the codec starts.
+  - cirrus,boost-manager : Boost voltage control.
+  0 = Automatically managed.  Boost-converter output voltage is the higher
+  of the two: Class G or adaptive LED voltage.
+  1 = Automatically managed irrespective of audio, adapting for low-power
+  dissipation when LEDs are ON, and operating in Fixed-Boost Bypass Mode
+  if LEDs are OFF (VBST = VP).
+  2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP).
+  3 = Boost voltage fixed at 5 V.
+  - cirrus,sdout-datacfg : Data configuration for dual CS35L32 applications only.
+  Determines the data packed in a two-CS35L32 configuration.
+  0 = Left/right channels VMON[11:0], IMON[11:0], VPMON[7:0].
+  1 = Left/right channels VMON[11:0], IMON[11:0], STATUS.
+  2 = (Default) left/right channels VMON[15:0], IMON [15:0].
+  3 = Left/right channels VPMON[7:0], STATUS.
+  - cirrus,sdout-share : SDOUT sharing. Determines whether one or two CS35L32
+  devices are on board sharing SDOUT.
+  0 = (Default) One IC.
+  1 = Two IC's.
+  - cirrus,battery-recovery : Low battery nominal recovery threshold, rising VP.
+  0 = 3.1V
+  1 = 3.2V
+  2 = 3.3V (Default)
+  3 = 3.4V
+  - cirrus,battery-threshold : Low battery nominal threshold, falling VP.
+  0 = 3.1V
+  1 = 3.2V
+  2 = 3.3V
+  3 = 3.4V (Default)
+  4 = 3.5V
+  5 = 3.6V
+Example:
+codec: codec@40 {
+        compatible = "cirrus,cs35l32";
+        reg = <0x40>;
+        reset-gpios = <&gpio 10 0>;
+        cirrus,boost-manager = <0x03>;
+        cirrus,sdout-datacfg = <0x02>;
+        VA-supply = <&reg_audio>;
+};
diff --git a/Documentation/devicetree/bindings/sound/es8328.txt b/Documentation/devicetree/bindings/sound/es8328.txt
new file mode 100644
index 000000000000..30ea8a318ae9
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/es8328.txt
@@ -0,0 +1,38 @@
+Everest ES8328 audio CODEC
+This device supports both I2C and SPI.
+Required properties:
+  - compatible : "everest,es8328"
+  - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
+  - AVDD-supply : Regulator providing analog supply voltage 3.3V
+  - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
+  - IPVDD-supply : Regulator providing analog output voltage 3.3V
+  - clocks : A 22.5792 or 11.2896 MHz clock
+  - reg : the I2C address of the device for I2C, the chip select number for SPI
+Pins on the device (for linking into audio routes):
+  * LOUT1
+  * LOUT2
+  * ROUT1
+  * ROUT2
+  * LINPUT1
+  * RINPUT1
+  * LINPUT2
+  * RINPUT2
+  * Mic Bias
+Example:
+codec: es8328@11 {
+        compatible = "everest,es8328";
+        DVDD-supply = <&reg_3p3v>;
+        AVDD-supply = <&reg_3p3v>;
+        PVDD-supply = <&reg_3p3v>;
+        HPVDD-supply = <&reg_3p3v>;
+        clocks = <&clks 169>;
+        reg = <0x11>;
+};
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt
index aeb8c4a0b88d..52f5b6bf3e8e 100644
--- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
@@ -7,7 +7,8 @@ other DSPs. It has up to six transmitters and four receivers.
 Required properties:
-  - compatible : Compatible list, must contain "fsl,imx35-esai".
+  - compatible : Compatible list, must contain "fsl,imx35-esai" or
+                 "fsl,vf610-esai"
  - reg : Offset and length of the register set for the device.
diff --git a/Documentation/devicetree/bindings/sound/fsl,ssi.txt b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
index 3aa4a8f528f4..5b76be45d18b 100644
--- a/Documentation/devicetree/bindings/sound/fsl,ssi.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,ssi.txt
@@ -58,13 +58,7 @@ Optional properties:
                    Documentation/devicetree/bindings/dma/dma.txt.
 - dma-names:        Two dmas have to be defined, "tx" and "rx", if fsl,imx-fiq
                    is not defined.
- fsl,mode:         The operating mode for the SSI interface.
+- fsl,mode:         The operating mode for the AC97 interface only.
-                    "i2s-slave" - I2S mode, SSI is clock slave
-                    "i2s-master" - I2S mode, SSI is clock master
-                    "lj-slave" - left-justified mode, SSI is clock slave
-                    "lj-master" - l.j. mode, SSI is clock master
-                    "rj-slave" - right-justified mode, SSI is clock slave
-                    "rj-master" - r.j., SSI is clock master
                    "ac97-slave" - AC97 mode, SSI is clock slave
                    "ac97-master" - AC97 mode, SSI is clock master
diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
new file mode 100644
index 000000000000..a96774c194c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt
@@ -0,0 +1,82 @@
+Freescale Generic ASoC Sound Card with ASRC support
+The Freescale Generic ASoC Sound Card can be used, ideally, for all Freescale
+SoCs connecting with external CODECs.
+The idea of this generic sound card is a bit like ASoC Simple Card. However,
+for Freescale SoCs (especially those released in recent years), most of them
+have ASRC (Documentation/devicetree/bindings/sound/fsl,asrc.txt) inside. And
+this is a specific feature that might be painstakingly controlled and merged
+into the Simple Card.
+So having this generic sound card allows all Freescale SoC users to benefit
+from the simplification of a new card support and the capability of the wide
+sample rates support through ASRC.
+Note: The card is initially designed for those sound cards who use I2S and
+      PCM DAI formats. However, it'll be also possible to support those non
+      I2S/PCM type sound cards, such as S/PDIF audio and HDMI audio, as long
+      as the driver has been properly upgraded.
+The compatible list for this generic sound card currently:
+ "fsl,imx-audio-cs42888"
+ "fsl,imx-audio-wm8962"
+ (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt)
+ "fsl,imx-audio-sgtl5000"
+ (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
+Required properties:
+  - compatible          : Contains one of entries in the compatible list.
+  - model               : The user-visible name of this sound complex
+  - audio-cpu           : The phandle of an CPU DAI controller
+  - audio-codec         : The phandle of an audio codec
+  - audio-routing       : A list of the connections between audio components.
+                          Each entry is a pair of strings, the first being the
+                          connection's sink, the second being the connection's
+                          source. There're a few pre-designed board connectors:
+                           * Line Out Jack
+                           * Line In Jack
+                           * Headphone Jack
+                           * Mic Jack
+                           * Ext Spk
+                           * AMIC (stands for Analog Microphone Jack)
+                           * DMIC (stands for Digital Microphone Jack)
+                          Note: The "Mic Jack" and "AMIC" are redundant while
+                                coexsiting in order to support the old bindings
+                                of wm8962 and sgtl5000.
+Optional properties:
+  - audio-asrc          : The phandle of ASRC. It can be absent if there's no
+                          need to add ASRC support via DPCM.
+Example:
+sound-cs42888 {
+        compatible = "fsl,imx-audio-cs42888";
+        model = "cs42888-audio";
+        audio-cpu = <&esai>;
+        audio-asrc = <&asrc>;
+        audio-codec = <&cs42888>;
+        audio-routing =
+                "Line Out Jack", "AOUT1L",
+                "Line Out Jack", "AOUT1R",
+                "Line Out Jack", "AOUT2L",
+                "Line Out Jack", "AOUT2R",
+                "Line Out Jack", "AOUT3L",
+                "Line Out Jack", "AOUT3R",
+                "Line Out Jack", "AOUT4L",
+                "Line Out Jack", "AOUT4R",
+                "AIN1L", "Line In Jack",
+                "AIN1R", "Line In Jack",
+                "AIN2L", "Line In Jack",
+                "AIN2R", "Line In Jack";
+};
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 0f4e23828190..4956b14d4b06 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -18,12 +18,26 @@ Required properties:
 - pinctrl-names: Must contain a "default" entry.
 - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
  See ../pinctrl/pinctrl-bindings.txt for details of the property values.
- big-endian-regs: If this property is absent, the little endian mode will
+- big-endian: Boolean property, required if all the FTM_PWM registers
-  be in use as default, or the big endian mode will be in use for all the
+  are big-endian rather than little-endian.
-  device registers.
+- lsb-first: Configures whether the LSB or the MSB is transmitted first for
- big-endian-data: If this property is absent, the little endian mode will
+  the fifo data. If this property is absent, the MSB is transmitted first as
-  be in use as default, or the big endian mode will be in use for all the
+  default, or the LSB is transmitted first.
-  fifo data.
+- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
+  that SAI will work in the synchronous mode (sync Tx with Rx) which means
+  both the transimitter and receiver will send and receive data by following
+  receiver's bit clocks and frame sync clocks.
+- fsl,sai-asynchronous: This is a boolean property. If present, indicating
+  that SAI will work in the asynchronous mode, which means both transimitter
+  and receiver will send and receive data by following their own bit clocks
+  and frame sync clocks separately.
+Note:
+- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
+  default synchronous mode (sync Rx with Tx) will be used, which means both
+  transimitter and receiver will send and receive data by following clocks
+  of transimitter.
+- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
 Example:
 sai2: sai@40031000 {
@@ -38,6 +52,6 @@ sai2: sai@40031000 {
              dma-names = "tx", "rx";
              dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
                   <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
-              big-endian-regs;
+              big-endian;
-              big-endian-data;
+              lsb-first;
 };
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt b/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt
new file mode 100644
index 000000000000..07b68ab206fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-es8328.txt
@@ -0,0 +1,60 @@
+Freescale i.MX audio complex with ES8328 codec
+Required properties:
+- compatible       : "fsl,imx-audio-es8328"
+- model            : The user-visible name of this sound complex
+- ssi-controller   : The phandle of the i.MX SSI controller
+- jack-gpio        : Optional GPIO for headphone jack
+- audio-amp-supply : Power regulator for speaker amps
+- audio-codec      : The phandle of the ES8328 audio codec
+- audio-routing    : A list of the connections between audio components.
+                     Each entry is a pair of strings, the first being the
+                     connection's sink, the second being the connection's
+                     source. Valid names could be power supplies, ES8328
+                     pins, and the jacks on the board:
+                        Power supplies:
+                           * audio-amp
+                        ES8328 pins:
+                           * LOUT1
+                           * LOUT2
+                           * ROUT1
+                           * ROUT2
+                           * LINPUT1
+                           * LINPUT2
+                           * RINPUT1
+                           * RINPUT2
+                           * Mic PGA
+                        Board connectors:
+                           * Headphone
+                           * Speaker
+                           * Mic Jack
+- mux-int-port     : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port     : The external port of the i.MX audio muxer (AUDMIX)
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+Example:
+sound {
+        compatible = "fsl,imx-audio-es8328";
+        model = "imx-audio-es8328";
+        ssi-controller = <&ssi1>;
+        audio-codec = <&codec>;
+        jack-gpio = <&gpio5 15 0>;
+        audio-amp-supply = <&reg_audio_amp>;
+        audio-routing =
+                "Speaker", "LOUT2",
+                "Speaker", "ROUT2",
+                "Speaker", "audio-amp",
+                "Headphone", "ROUT1",
+                "Headphone", "LOUT1",
+                "LINPUT1", "Mic Jack",
+                "RINPUT1", "Mic Jack",
+                "Mic Jack", "Mic Bias";
+        mux-int-port = <1>;
+        mux-ext-port = <3>;
+};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt
index 9c7c55c71370..c949abc2992f 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-max98090.txt
@@ -25,6 +25,7 @@ Required properties:
 Optional properties:
 - nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,mic-det-gpios : The GPIO that detect microphones are plugged in
 Example:
diff --git a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
index 6c55fcfe5e1d..9b82c20b306b 100644
--- a/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip-i2s.txt
@@ -31,7 +31,7 @@ i2s@ff890000 {
        #address-cells = <1>;
        #size-cells = <0>;
        dmas = <&pdma1 0>, <&pdma1 1>;
-        dma-names = "rx", "tx";
+        dma-names = "tx", "rx";
        clock-names = "i2s_hclk", "i2s_clk";
        clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 };
diff --git a/Documentation/devicetree/bindings/sound/rt5677.txt b/Documentation/devicetree/bindings/sound/rt5677.txt
new file mode 100644
index 000000000000..0701b834fc73
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5677.txt
@@ -0,0 +1,59 @@
+RT5677 audio CODEC
+This device supports I2C only.
+Required properties:
+- compatible : "realtek,rt5677".
+- reg : The I2C address of the device.
+- interrupts : The CODEC's interrupt output.
+- gpio-controller : Indicates this device is a GPIO controller.
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters (currently unused).
+Optional properties:
+- realtek,pow-ldo2-gpio : The GPIO that controls the CODEC's POW_LDO2 pin.
+- realtek,in1-differential
+- realtek,in2-differential
+- realtek,lout1-differential
+- realtek,lout2-differential
+- realtek,lout3-differential
+  Boolean. Indicate MIC1/2 input and LOUT1/2/3 outputs are differential,
+  rather than single-ended.
+Pins on the device (for linking into audio routes):
+  * IN1P
+  * IN1N
+  * IN2P
+  * IN2N
+  * MICBIAS1
+  * DMIC1
+  * DMIC2
+  * DMIC3
+  * DMIC4
+  * LOUT1
+  * LOUT2
+  * LOUT3
+Example:
+rt5677 {
+        compatible = "realtek,rt5677";
+        reg = <0x2c>;
+        interrupt-parent = <&gpio>;
+        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        realtek,pow-ldo2-gpio =
+                <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+        realtek,in1-differential = "true";
+};
diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt
index c2e9841dfce4..c3cba600bf11 100644
--- a/Documentation/devicetree/bindings/sound/simple-card.txt
+++ b/Documentation/devicetree/bindings/sound/simple-card.txt
@@ -17,6 +17,10 @@ Optional properties:
                                          source.
 - simple-audio-card,mclk-fs             : Multiplication factor between stream rate and codec
                                          mclk.
+- simple-audio-card,hp-det-gpio         : Reference to GPIO that signals when
+                                          headphones are attached.
+- simple-audio-card,mic-det-gpio        : Reference to GPIO that signals when
+                                          a microphone is attached.
 Optional subnodes:
diff --git a/Documentation/devicetree/bindings/sound/ssm4567.txt b/Documentation/devicetree/bindings/sound/ssm4567.txt
new file mode 100644
index 000000000000..ec3d9e7004b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ssm4567.txt
@@ -0,0 +1,15 @@
+Analog Devices SSM4567 audio amplifier
+This device supports I2C only.
+Required properties:
+  - compatible : Must be "adi,ssm4567"
+  - reg : the I2C address of the device. This will either be 0x34 (LR_SEL/ADDR connected to AGND),
+        0x35 (LR_SEL/ADDR connected to IOVDD) or 0x36 (LR_SEL/ADDR open).
+Example:
+        ssm4567: ssm4567@34 {
+                compatible = "adi,ssm4567";
+                reg = <0x34>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/st,sta350.txt b/Documentation/devicetree/bindings/sound/st,sta350.txt
index b7e71bf5caf4..307398ef2317 100644
--- a/Documentation/devicetree/bindings/sound/st,sta350.txt
+++ b/Documentation/devicetree/bindings/sound/st,sta350.txt
@@ -33,7 +33,7 @@ Optional properties:
        0: Channel 1
        1: Channel 2
        2: Channel 3
-        If parameter is missing, channel 1 is choosen.
+        If parameter is missing, channel 1 is chosen.
        This properties have to be specified as '/bits/ 8' values.
  -  st,thermal-warning-recover:
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
index 4256a6df9b79..aad527b357a0 100644
--- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
@@ -7,6 +7,9 @@ Required properties:
 - interrupts : Should contain CSPI/eCSPI interrupt
 - fsl,spi-num-chipselects : Contains the number of the chipselect
 - cs-gpios : Specifies the gpio pins to be used for chipselects.
+- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
+                Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request names should include "tx" and "rx" if present.
 Example:
@@ -19,4 +22,6 @@ ecspi@70010000 {
        fsl,spi-num-chipselects = <2>;
        cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
                   <&gpio3 25 0>; /* GPIO3_25 */
+        dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
+        dma-names = "rx", "tx";
 };
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index f24baf3b6cc1..d11c3721e7cd 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -6,8 +6,17 @@ Required properties:
                         "renesas,sh-mobile-msiof" for SH Mobile series.
                         Examples with soctypes are:
                         "renesas,msiof-r8a7790" (R-Car H2)
-                         "renesas,msiof-r8a7791" (R-Car M2)
+                         "renesas,msiof-r8a7791" (R-Car M2-W)
- reg                  : Offset and length of the register set for the device
+                         "renesas,msiof-r8a7792" (R-Car V2H)
+                         "renesas,msiof-r8a7793" (R-Car M2-N)
+                         "renesas,msiof-r8a7794" (R-Car E2)
+- reg                  : A list of offsets and lengths of the register sets for
+                         the device.
+                         If only one register set is present, it is to be used
+                         by both the CPU and the DMA engine.
+                         If two register sets are present, the first is to be
+                         used by the CPU, and the second is to be used by the
+                         DMA engine.
 - interrupt-parent     : The phandle for the interrupt controller that
                         services interrupts for this device
 - interrupts           : Interrupt specifier
@@ -17,12 +26,16 @@ Required properties:
 Optional properties:
 - clocks               : Must contain a reference to the functional clock.
 - num-cs               : Total number of chip-selects (default is 1)
+- dmas                 : Must contain a list of two references to DMA
+                         specifiers, one for transmission, and one for
+                         reception.
+- dma-names            : Must contain a list of two DMA names, "tx" and "rx".
 Optional properties, deprecated for soctype-specific bindings:
 - renesas,tx-fifo-size : Overrides the default tx fifo size given in words
                         (default is 64)
 - renesas,rx-fifo-size : Overrides the default rx fifo size given in words
-                         (default is 64, or 256 on R-Car H2 and M2)
+                         (default is 64, or 256 on R-Car Gen2)
 Pinctrl properties might be needed, too.  See
 Documentation/devicetree/bindings/pinctrl/renesas,*.
@@ -31,9 +44,11 @@ Example:
        msiof0: spi@e6e20000 {
                compatible = "renesas,msiof-r8a7791";
-                reg = <0 0xe6e20000 0 0x0064>;
+                reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
                interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+                dmas = <&dmac0 0x51>, <&dmac0 0x52>;
+                dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt
index f80887bca0d6..12ecfe9e3599 100644
--- a/Documentation/devicetree/bindings/spi/spi-davinci.txt
+++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -1,5 +1,10 @@
 Davinci SPI controller device bindings
+Links on DM:
+Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
+dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
+OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
 Required properties:
 - #address-cells: number of cells required to define a chip select
        address on the SPI bus. Should be set to 1.
@@ -24,6 +29,30 @@ Optional:
        cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
        where first three are internal CS and last two are GPIO CS.
+Optional properties for slave devices:
+SPI slave nodes can contain the following properties.
+Not all SPI Peripherals from Texas Instruments support this.
+Please check SPI peripheral documentation for a device before using these.
+- ti,spi-wdelay : delay between transmission of words
+        (SPIFMTn.WDELAY, SPIDAT1.WDEL) must be specified in number of SPI module
+        clock periods.
+        delay = WDELAY * SPI_module_clock_period + 2 * SPI_module_clock_period
+Below is timing diagram which shows functional meaning of
+"ti,spi-wdelay" parameter.
+             +-+ +-+ +-+ +-+ +-+                           +-+ +-+ +-+
+SPI_CLK      | | | | | | | | | |                           | | | | | |
+  +----------+ +-+ +-+ +-+ +-+ +---------------------------+ +-+ +-+ +-
+SPI_SOMI/SIMO+-----------------+                           +-----------
+  +----------+ word1           +---------------------------+word2
+             +-----------------+                           +-----------
+                                          WDELAY
+                                <-------------------------->
 Example of a NOR flash slave device (n25q032) connected to DaVinci
 SPI controller device over the SPI bus.
@@ -43,6 +72,7 @@ spi0:spi@20BF0000 {
                compatible = "st,m25p32";
                spi-max-frequency = <25000000>;
                reg = <0>;
+                ti,spi-wdelay = <8>;
                partition@0 {
                        label = "u-boot-spl";
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index 5376de40f10b..cbbe16ed3874 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -10,7 +10,12 @@ Required properties:
 - pinctrl-names: must contain a "default" entry.
 - spi-num-chipselects : the number of the chipselect signals.
 - bus-num : the slave chip chipselect signal number.
- big-endian : if DSPI modudle is big endian, the bool will be set in node.
+Optional property:
+- big-endian: If present the dspi device's registers are implemented
+  in big endian mode, otherwise in native mode(same with CPU), for more
+  detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
 Example:
 dspi0@4002c000 {
diff --git a/Documentation/devicetree/bindings/spi/spi-orion.txt b/Documentation/devicetree/bindings/spi/spi-orion.txt
index a3ff50fc76fb..50c3a3de61c1 100644
--- a/Documentation/devicetree/bindings/spi/spi-orion.txt
+++ b/Documentation/devicetree/bindings/spi/spi-orion.txt
@@ -1,7 +1,7 @@
 Marvell Orion SPI device
 Required properties:
- compatible : should be "marvell,orion-spi".
+- compatible : should be "marvell,orion-spi" or "marvell,armada-370-spi".
 - reg : offset and length of the register set for the device
 - cell-index : Which of multiple SPI controllers is this.
 Optional properties:
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 7bab35575817..467dec441c62 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -16,11 +16,15 @@ Required Properties:
 - clocks: Must contain an entry for each entry in clock-names.
 - clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
                           the peripheral clock.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+Optional Properties:
 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
                Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: DMA request names should include "tx" and "rx" if present.
- #address-cells: should be 1.
- #size-cells: should be 0.
 Example:
diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt
index d57d82a74054..8f4169f63936 100644
--- a/Documentation/devicetree/bindings/spi/spi-rspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt
@@ -11,7 +11,10 @@ Required properties:
                        - "renesas,rspi-sh7757" (SH)
                        - "renesas,rspi-r7s72100" (RZ/A1H)
                        - "renesas,qspi-r8a7790" (R-Car H2)
-                        - "renesas,qspi-r8a7791" (R-Car M2)
+                        - "renesas,qspi-r8a7791" (R-Car M2-W)
+                        - "renesas,qspi-r8a7792" (R-Car V2H)
+                        - "renesas,qspi-r8a7793" (R-Car M2-N)
+                        - "renesas,qspi-r8a7794" (R-Car E2)
 - reg              : Address start and address range size of the device
 - interrupts       : A list of interrupt-specifiers, one for each entry in
                     interrupt-names.
@@ -30,6 +33,9 @@ Required properties:
 Optional properties:
 - clocks           : Must contain a reference to the functional clock.
+- dmas             : Must contain a list of two references to DMA specifiers,
+                     one for transmission, and one for reception.
+- dma-names        : Must contain a list of two DMA names, "tx" and "rx".
 Pinctrl properties might be needed, too.  See
 Documentation/devicetree/bindings/pinctrl/renesas,*.
@@ -58,4 +64,6 @@ Examples:
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
+                dma-names = "tx", "rx";
        };
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
index 578a1fca366e..443bcb6134d5 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
@@ -56,6 +56,9 @@ Required properties:
 - fsl,data-width : should be <18> or <24>
 - port: A port node with endpoint definitions as defined in
   Documentation/devicetree/bindings/media/video-interfaces.txt.
+   On i.MX5, the internal two-input-multiplexer is used.
+   Due to hardware limitations, only one port (port@[0,1])
+   can be used for each channel (lvds-channel@[0,1], respectively)
   On i.MX6, there should be four ports (port@[0-3]) that correspond
   to the four LVDS multiplexer inputs.
@@ -78,6 +81,8 @@ ldb: ldb@53fa8008 {
                      "di0", "di1";
        lvds-channel@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
                reg = <0>;
                fsl,data-mapping = "spwg";
                fsl,data-width = <24>;
@@ -86,7 +91,9 @@ ldb: ldb@53fa8008 {
                        /* ... */
                };
-                port {
+                port@0 {
+                        reg = <0>;
                        lvds0_in: endpoint {
                                remote-endpoint = <&ipu_di0_lvds0>;
                        };
@@ -94,6 +101,8 @@ ldb: ldb@53fa8008 {
        };
        lvds-channel@1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
                reg = <1>;
                fsl,data-mapping = "spwg";
                fsl,data-width = <24>;
@@ -102,7 +111,9 @@ ldb: ldb@53fa8008 {
                        /* ... */
                };
-                port {
+                port@1 {
+                        reg = <1>;
                        lvds1_in: endpoint {
                                remote-endpoint = <&ipu_di1_lvds1>;
                        };
diff --git a/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
new file mode 100644
index 000000000000..a092053f7902
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/amlogic,meson6-timer.txt
@@ -0,0 +1,15 @@
+Amlogic Meson6 SoCs Timer Controller
+Required properties:
+- compatible : should be "amlogic,meson6-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+Example:
+timer@c1109940 {
+        compatible = "amlogic,meson6-timer";
+        reg = <0xc1109940 0x14>;
+        interrupts = <0 10 1>;
+};
diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
index a17418b0ece3..1a05c1b243c1 100644
--- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt
@@ -11,15 +11,47 @@ datasheets.
 Required Properties:
-  - compatible: must contain one of the following.
+  - compatible: must contain one or more of the following:
-    - "renesas,cmt-32" for the 32-bit CMT
+    - "renesas,cmt-32-r8a7740" for the r8a7740 32-bit CMT
+                (CMT0)
+    - "renesas,cmt-32-sh7372" for the sh7372 32-bit CMT
+                (CMT0)
+    - "renesas,cmt-32-sh73a0" for the sh73a0 32-bit CMT
+                (CMT0)
+    - "renesas,cmt-32" for all 32-bit CMT without fast clock support
                (CMT0 on sh7372, sh73a0 and r8a7740)
-    - "renesas,cmt-32-fast" for the 32-bit CMT with fast clock support
+                This is a fallback for the above renesas,cmt-32-* entries.
+    - "renesas,cmt-32-fast-r8a7740" for the r8a7740 32-bit CMT with fast
+                clock support (CMT[234])
+    - "renesas,cmt-32-fast-sh7372" for the sh7372 32-bit CMT with fast
+                clock support (CMT[234])
+    - "renesas,cmt-32-fast-sh73a0" for the sh73A0 32-bit CMT with fast
+                clock support (CMT[234])
+    - "renesas,cmt-32-fast" for all 32-bit CMT with fast clock support
                (CMT[234] on sh7372, sh73a0 and r8a7740)
-    - "renesas,cmt-48" for the 48-bit CMT
+                This is a fallback for the above renesas,cmt-32-fast-* entries.
+    - "renesas,cmt-48-sh7372" for the sh7372 48-bit CMT
+                (CMT1)
+    - "renesas,cmt-48-sh73a0" for the sh73A0 48-bit CMT
+                (CMT1)
+    - "renesas,cmt-48-r8a7740" for the r8a7740 48-bit CMT
+                (CMT1)
+    - "renesas,cmt-48" for all non-second generation 48-bit CMT
                (CMT1 on sh7372, sh73a0 and r8a7740)
-    - "renesas,cmt-48-gen2" for the second generation 48-bit CMT
+                This is a fallback for the above renesas,cmt-48-* entries.
+    - "renesas,cmt-48-r8a73a4" for the r8a73a4 48-bit CMT
+                (CMT[01])
+    - "renesas,cmt-48-r8a7790" for the r8a7790 48-bit CMT
+                (CMT[01])
+    - "renesas,cmt-48-r8a7791" for the r8a7791 48-bit CMT
+                (CMT[01])
+    - "renesas,cmt-48-gen2" for all second generation 48-bit CMT
                (CMT[01] on r8a73a4, r8a7790 and r8a7791)
+                This is a fallback for the renesas,cmt-48-r8a73a4,
+                renesas,cmt-48-r8a7790 and renesas,cmt-48-r8a7791 entries.
  - reg: base address and length of the registers block for the timer module.
  - interrupts: interrupt-specifier for the timer, one per channel.
@@ -36,7 +68,7 @@ Example: R8A7790 (R-Car H2) CMT0 node
        them channels 0 and 1 in the documentation.
        cmt0: timer@ffca0000 {
-                compatible = "renesas,cmt-48-gen2";
+                compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
                reg = <0 0xffca0000 0 0x1004>;
                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
                             <0 142 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt
index 917453f826bc..d9a8d5af1a21 100644
--- a/Documentation/devicetree/bindings/timer/renesas,mtu2.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,mtu2.txt
@@ -8,7 +8,10 @@ are independent. The MTU2 hardware supports five channels indexed from 0 to 4.
 Required Properties:
-  - compatible: must contain "renesas,mtu2"
+  - compatible: must be one or more of the following:
+    - "renesas,mtu2-r7s72100" for the r7s72100 MTU2
+    - "renesas,mtu2" for any MTU2
+      This is a fallback for the above renesas,mtu2-* entries
  - reg: base address and length of the registers block for the timer module.
@@ -26,7 +29,7 @@ Required Properties:
 Example: R7S72100 (RZ/A1H) MTU2 node
        mtu2: timer@fcff0000 {
-                compatible = "renesas,mtu2";
+                compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
                reg = <0xfcff0000 0x400>;
                interrupts = <0 139 IRQ_TYPE_LEVEL_HIGH>,
                             <0 146 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
index 425d0c5f4aee..7db89fb25444 100644
--- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt
+++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt
@@ -8,7 +8,10 @@ are independent. The TMU hardware supports up to three channels.
 Required Properties:
-  - compatible: must contain "renesas,tmu"
+  - compatible: must contain one or more of the following:
+    - "renesas,tmu-r8a7779" for the r8a7779 TMU
+    - "renesas,tmu" for any TMU.
+      This is a fallback for the above renesas,tmu-* entries
  - reg: base address and length of the registers block for the timer module.
@@ -27,7 +30,7 @@ Optional Properties:
 Example: R8A7779 (R-Car H1) TMU0 node
        tmu0: timer@ffd80000 {
-                compatible = "renesas,tmu";
+                compatible = "renesas,tmu-r8a7779", "renesas,tmu";
                reg = <0xffd80000 0x30>;
                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
index 20468b2a7516..53579197eca2 100644
--- a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
+++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
@@ -8,9 +8,50 @@ Required properties:
 - interrupts        : <interrupt mapping for UFS host controller IRQ>
 - reg               : <registers mapping>
+Optional properties:
+- vdd-hba-supply        : phandle to UFS host controller supply regulator node
+- vcc-supply            : phandle to VCC supply regulator node
+- vccq-supply           : phandle to VCCQ supply regulator node
+- vccq2-supply          : phandle to VCCQ2 supply regulator node
+- vcc-supply-1p8        : For embedded UFS devices, valid VCC range is 1.7-1.95V
+                          or 2.7-3.6V. This boolean property when set, specifies
+                          to use low voltage range of 1.7-1.95V. Note for external
+                          UFS cards this property is invalid and valid VCC range is
+                          always 2.7-3.6V.
+- vcc-max-microamp      : specifies max. load that can be drawn from vcc supply
+- vccq-max-microamp     : specifies max. load that can be drawn from vccq supply
+- vccq2-max-microamp    : specifies max. load that can be drawn from vccq2 supply
+- <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
+- clocks                : List of phandle and clock specifier pairs
+- clock-names           : List of clock input name strings sorted in the same
+                          order as the clocks property.
+- freq-table-hz         : Array of <min max> operating frequencies stored in the same
+                          order as the clocks property. If this property is not
+                          defined or a value in the array is "0" then it is assumed
+                          that the frequency is set by the parent clock or a
+                          fixed rate clock source.
+Note: If above properties are not defined it can be assumed that the supply
+regulators or clocks are always on.
 Example:
        ufshc@0xfc598000 {
                compatible = "jedec,ufs-1.1";
                reg = <0xfc598000 0x800>;
                interrupts = <0 28 0>;
+                vdd-hba-supply = <&xxx_reg0>;
+                vdd-hba-fixed-regulator;
+                vcc-supply = <&xxx_reg1>;
+                vcc-supply-1p8;
+                vccq-supply = <&xxx_reg2>;
+                vccq2-supply = <&xxx_reg3>;
+                vcc-max-microamp = 500000;
+                vccq-max-microamp = 200000;
+                vccq2-max-microamp = 200000;
+                clocks = <&core 0>, <&ref 0>, <&iface 0>;
+                clock-names = "core_clk", "ref_clk", "iface_clk";
+                freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;
        };
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
index 1bae71e9ad47..38a548001e3a 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
@@ -19,6 +19,7 @@ Optional properties:
 - disable-over-current: disable over current detect
 - external-vbus-divider: enables off-chip resistor divider for Vbus
 - maximum-speed: limit the maximum connection speed to "full-speed".
+- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
 Examples:
 usb@02184000 { /* USB OTG */
@@ -30,4 +31,5 @@ usb@02184000 { /* USB OTG */
        disable-over-current;
        external-vbus-divider;
        maximum-speed = "full-speed";
+        tpl-support;
 };
diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 467ddd15d40c..482f815363ef 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -4,6 +4,9 @@ Platform DesignWare HS OTG USB 2.0 controller
 Required properties:
 - compatible : One of:
  - brcm,bcm2835-usb: The DWC2 USB controller instance in the BCM2835 SoC.
+  - rockchip,rk3066-usb: The DWC2 USB controller instance in the rk3066 Soc;
+  - "rockchip,rk3188-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3188 Soc;
+  - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
  - snps,dwc2: A generic DWC2 USB controller with default parameters.
 - reg : Should contain 1 register range (address and length)
 - interrupts : Should contain 1 interrupt
@@ -15,6 +18,8 @@ Optional properties:
 - phys: phy provider specifier
 - phy-names: shall be "usb2-phy"
 Refer to phy/phy-bindings.txt for generic phy consumer properties
+- dr_mode: shall be one of "host", "peripheral" and "otg"
+  Refer to usb/generic.txt
 Example:
diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt
new file mode 100644
index 000000000000..f9d70252bbb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/dwc3-st.txt
@@ -0,0 +1,68 @@
+ST DWC3 glue logic
+This file documents the parameters for the dwc3-st driver.
+This driver controls the glue logic used to configure the dwc3 core on
+STiH407 based platforms.
+Required properties:
+ - compatible   : must be "st,stih407-dwc3"
+ - reg          : glue logic base address and USB syscfg ctrl register offset
+ - reg-names    : should be "reg-glue" and "syscfg-reg"
+ - st,syscon    : should be phandle to system configuration node which
+                  encompasses the glue registers
+ - resets       : list of phandle and reset specifier pairs. There should be two entries, one
+                  for the powerdown and softreset lines of the usb3 IP
+ - reset-names  : list of reset signal names. Names should be "powerdown" and "softreset"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+   with 'reg' property
+ - pinctl-names : A pinctrl state named "default" must be defined
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ - pinctrl-0    : Pin control group
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ - ranges       : allows valid 1:1 translation between child's address space and
+                  parent's address space
+Sub-nodes:
+The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
+example below. The DT binding details of dwc3 can be found in:
+Documentation/devicetree/bindings/usb/dwc3.txt
+NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
+is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
+or "device".
+[1] Documentation/devicetree/bindings/usb/generic.txt
+Example:
+st_dwc3: dwc3@8f94000 {
+        status          = "disabled";
+        compatible      = "st,stih407-dwc3";
+        reg             = <0x08f94000 0x1000>, <0x110 0x4>;
+        reg-names       = "reg-glue", "syscfg-reg";
+        st,syscfg       = <&syscfg_core>;
+        resets          = <&powerdown STIH407_USB3_POWERDOWN>,
+                          <&softreset STIH407_MIPHY2_SOFTRESET>;
+        reset-names     = "powerdown",
+                          "softreset";
+        #address-cells  = <1>;
+        #size-cells     = <1>;
+        pinctrl-names   = "default";
+        pinctrl-0       = <&pinctrl_usb3>;
+        ranges;
+        dwc3: dwc3@9900000 {
+                compatible      = "snps,dwc3";
+                reg             = <0x09900000 0x100000>;
+                interrupts      = <GIC_SPI 155 IRQ_TYPE_NONE>;
+                dr_mode         = "host";
+                phys-names      = "usb2-phy", "usb3-phy";
+                phys            = <&usb2_picophy2>, <&phy_port2 MIPHY_TYPE_USB>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/usb/ehci-st.txt b/Documentation/devicetree/bindings/usb/ehci-st.txt
new file mode 100644
index 000000000000..fb45fa5770bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ehci-st.txt
@@ -0,0 +1,39 @@
+ST USB EHCI controller
+Required properties:
+ - compatible           : must be "st,st-ehci-300x"
+ - reg                  : physical base addresses of the controller and length of memory mapped
+                          region
+ - interrupts           : one EHCI interrupt should be described here
+ - pinctrl-names        : a pinctrl state named "default" must be defined
+ - pinctrl-0            : phandle referencing pin configuration of the USB controller
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+ - clocks               : phandle list of usb clocks
+ - clock-names          : should be "ic" for interconnect clock and "clk48"
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - phys                 : phandle for the PHY device
+ - phy-names            : should be "usb"
+ - resets               : phandle + reset specifier pairs to the powerdown and softreset lines
+                          of the USB IP
+ - reset-names          : should be "power" and "softreset"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+Example:
+        ehci1: usb@0xfe203e00 {
+                compatible = "st,st-ehci-300x";
+                reg = <0xfe203e00 0x100>;
+                interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usb1>;
+                clocks = <&clk_s_a1_ls 0>;
+                phys = <&usb2_phy>;
+                phy-names = "usb";
+                status = "okay";
+                resets = <&powerdown STIH416_USB1_POWERDOWN>,
+                         <&softreset STIH416_USB1_SOFTRESET>;
+                reset-names = "power", "softreset";
+        };
diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt
index cef181a9d8bd..379b84a567cc 100644
--- a/Documentation/devicetree/bindings/usb/mxs-phy.txt
+++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt
@@ -5,6 +5,8 @@ Required properties:
        * "fsl,imx23-usbphy" for imx23 and imx28
        * "fsl,imx6q-usbphy" for imx6dq and imx6dl
        * "fsl,imx6sl-usbphy" for imx6sl
+        * "fsl,vf610-usbphy" for Vybrid vf610
+        * "fsl,imx6sx-usbphy" for imx6sx
  "fsl,imx23-usbphy" is still a fallback for other strings
 - reg: Should contain registers location and length
 - interrupts: Should contain phy interrupt
diff --git a/Documentation/devicetree/bindings/usb/ohci-st.txt b/Documentation/devicetree/bindings/usb/ohci-st.txt
new file mode 100644
index 000000000000..6d8393748da2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ohci-st.txt
@@ -0,0 +1,37 @@
+ST USB OHCI controller
+Required properties:
+ - compatible           : must be "st,st-ohci-300x"
+ - reg                  : physical base addresses of the controller and length of memory mapped
+                          region
+ - interrupts           : one OHCI controller interrupt should be described here
+ - clocks               : phandle list of usb clocks
+ - clock-names          : should be "ic" for interconnect clock and "clk48"
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - phys                 : phandle for the PHY device
+ - phy-names            : should be "usb"
+ - resets               : phandle to the powerdown and reset controller for the USB IP
+ - reset-names          : should be "power" and "softreset".
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+Example:
+        ohci0: usb@0xfe1ffc00 {
+                compatible = "st,st-ohci-300x";
+                reg = <0xfe1ffc00 0x100>;
+                interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+                clocks = <&clk_s_a1_ls 0>,
+                         <&clockgen_b0 0>;
+                clock-names = "ic", "clk48";
+                phys = <&usb2_phy>;
+                phy-names = "usb";
+                status = "okay";
+                resets = <&powerdown STIH416_USB0_POWERDOWN>,
+                         <&softreset STIH416_USB0_SOFTRESET>;
+                reset-names = "power", "softreset";
+        };
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
new file mode 100644
index 000000000000..ca164e71dd50
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -0,0 +1,66 @@
+Qualcomm SuperSpeed DWC3 USB SoC controller
+Required properties:
+- compatible:   should contain "qcom,dwc3"
+- clocks:               A list of phandle + clock-specifier pairs for the
+                                clocks listed in clock-names
+- clock-names:  Should contain the following:
+  "core"                Master/Core clock, have to be >= 125 MHz for SS
+                                operation and >= 60MHz for HS operation
+Optional clocks:
+  "iface"               System bus AXI clock.  Not present on all platforms
+  "sleep"               Sleep clock, used when USB3 core goes into low
+                                power mode (U3).
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
+Example device nodes:
+                hs_phy: phy@100f8800 {
+                        compatible = "qcom,dwc3-hs-usb-phy";
+                        reg = <0x100f8800 0x30>;
+                        clocks = <&gcc USB30_0_UTMI_CLK>;
+                        clock-names = "ref";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
+                ss_phy: phy@100f8830 {
+                        compatible = "qcom,dwc3-ss-usb-phy";
+                        reg = <0x100f8830 0x30>;
+                        clocks = <&gcc USB30_0_MASTER_CLK>;
+                        clock-names = "ref";
+                        #phy-cells = <0>;
+                        status = "ok";
+                };
+                usb3_0: usb30@0 {
+                        compatible = "qcom,dwc3";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clocks = <&gcc USB30_0_MASTER_CLK>;
+                        clock-names = "core";
+                        ranges;
+                        status = "ok";
+                        dwc3@10000000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x10000000 0xcd00>;
+                                interrupts = <0 205 0x4>;
+                                phys = <&hs_phy>, <&ss_phy>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                                tx-fifo-resize;
+                                dr_mode = "host";
+                        };
+                };
diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
new file mode 100644
index 000000000000..b08c903f8668
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -0,0 +1,24 @@
+Renesas Electronics USBHS driver
+Required properties:
+  - compatible: Must contain one of the following:
+        - "renesas,usbhs-r8a7790"
+        - "renesas,usbhs-r8a7791"
+  - reg: Base address and length of the register for the USBHS
+  - interrupts: Interrupt specifier for the USBHS
+  - clocks: A list of phandle + clock specifier pairs
+Optional properties:
+  - renesas,buswait: Integer to use BUSWAIT register
+  - renesas,enable-gpio: A gpio specifier to check GPIO determining if USB
+                         function should be enabled
+  - phys: phandle + phy specifier pair
+  - phy-names: must be "usb"
+Example:
+        usbhs: usb@e6590000 {
+                compatible = "renesas,usbhs-r8a7790";
+                reg = <0 0xe6590000 0 0x100>;
+                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/udc-xilinx.txt b/Documentation/devicetree/bindings/usb/udc-xilinx.txt
new file mode 100644
index 000000000000..47b4e397a08d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/udc-xilinx.txt
@@ -0,0 +1,18 @@
+Xilinx USB2 device controller
+Required properties:
+- compatible            : Should be "xlnx,usb2-device-4.00.a"
+- reg                   : Physical base address and size of the USB2
+                          device registers map.
+- interrupts            : Should contain single irq line of USB2 device
+                          controller
+- xlnx,has-builtin-dma  : if DMA is included
+Example:
+                axi-usb2-device@42e00000 {
+                        compatible = "xlnx,usb2-device-4.00.a";
+                        interrupts = <0x0 0x39 0x1>;
+                        reg = <0x42e00000 0x10000>;
+                        xlnx,has-builtin-dma;
+                };
diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt
index 221ac0dbc678..52493b1480e2 100644
--- a/Documentation/devicetree/bindings/usb/usb3503.txt
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -8,8 +8,8 @@ Optional properties:
       if I2C is used.
 - connect-gpios: Should specify GPIO for connect.
 - disabled-ports: Should specify the ports unused.
-        '1' or '2' or '3' are availe for this property to describe the port
+        '1' or '2' or '3' are available for this property to describe the port
-        number. 1~3 property values are possible to be desribed.
+        number. 1~3 property values are possible to be described.
        Do not describe this property if all ports have to be enabled.
 - intn-gpios: Should specify GPIO for interrupt.
 - reset-gpios: Should specify GPIO for reset.
diff --git a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
index 97ce94e1a6cc..c101a4b17131 100644
--- a/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
@@ -4,6 +4,7 @@ Required properties:
 - #index-cells: Cells used to descibe usb controller index. Should be <1>
 - compatible: Should be one of below:
        "fsl,imx6q-usbmisc" for imx6q
+        "fsl,vf610-usbmisc" for Vybrid vf610
 - reg: Should contain registers location and length
 Examples:
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index d3a45796d249..723999d73744 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -14,6 +14,7 @@ allwinner	Allwinner Technology Co., Ltd.
 altr    Altera Corp.
 amcc    Applied Micro Circuits Corporation (APM, formally AMCC)
 amd     Advanced Micro Devices (AMD), Inc.
+amlogic Amlogic, Inc.
 ams     AMS AG
 amstaos AMS-Taos Inc.
 apm     Applied Micro Circuits Corporation (APM)
@@ -29,6 +30,7 @@ calxeda	Calxeda
 capella Capella Microsystems, Inc
 cavium  Cavium, Inc.
 cdns    Cadence Design Systems Inc.
+chipidea        Chipidea, Inc
 chrp    Common Hardware Reference Platform
 chunghwa        Chunghwa Picture Tubes Ltd.
 cirrus  Cirrus Logic, Inc.
@@ -38,24 +40,30 @@ dallas	Maxim Integrated Products (formerly Dallas Semiconductor)
 davicom DAVICOM Semiconductor, Inc.
 denx    Denx Software Engineering
 digi    Digi International Inc.
+dlg     Dialog Semiconductor
 dlink   D-Link Corporation
 dmo     Data Modul AG
 ebv     EBV Elektronik
 edt     Emerging Display Technologies
 emmicro EM Microelectronic
+energymicro     Silicon Laboratories (formerly Energy Micro AS)
 epcos   EPCOS AG
 epfl    Ecole Polytechnique Fédérale de Lausanne
 epson   Seiko Epson Corp.
 est     ESTeem Wireless Modems
 eukrea  Eukréa Electromatique
+everest Everest Semiconductor Co. Ltd.
 excito  Excito
+fcs     Fairchild Semiconductor
 fsl     Freescale Semiconductor
 GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
 gef     GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+geniatech       Geniatech, Inc.
 globalscale     Globalscale Technologies, Inc.
 gmt     Global Mixed-mode Technology, Inc.
 google  Google, Inc.
 gumstix Gumstix, Inc.
+gw      Gateworks Corporation
 haoyu   Haoyu Microelectronic Co. Ltd.
 hisilicon       Hisilicon Limited.
 honeywell       Honeywell
@@ -65,6 +73,7 @@ ibm	International Business Machines (IBM)
 idt     Integrated Device Technologies, Inc.
 iom     Iomega Corporation
 img     Imagination Technologies Ltd.
+innolux Innolux Corporation
 intel   Intel Corporation
 intercontrol    Inter Control Group
 isee    ISEE 2007 S.L.
@@ -83,6 +92,7 @@ maxim	Maxim Integrated Products
 mediatek        MediaTek Inc.
 micrel  Micrel Inc.
 microchip       Microchip Technology Inc.
+mitsubishi      Mitsubishi Electric Corporation
 mosaixtech      Mosaix Technologies, Inc.
 moxa    Moxa
 mpl     MPL AG
@@ -124,7 +134,9 @@ sil	Silicon Image
 silabs  Silicon Laboratories
 simtek
 sii     Seiko Instruments, Inc.
+silergy Silergy Corp.
 sirf    SiRF Technology, Inc.
+sitronix        Sitronix Technology Corporation
 smsc    Standard Microsystems Corporation
 snps    Synopsys, Inc.
 solidrun        SolidRun
@@ -134,12 +146,13 @@ st	STMicroelectronics
 ste     ST-Ericsson
 stericsson      ST-Ericsson
 synology        Synology, Inc.
+thine   THine Electronics, Inc.
 ti      Texas Instruments
 tlm     Trusted Logic Mobility
 toradex Toradex AG
 toshiba Toshiba Corporation
 toumaz  Toumaz
-usi     Universal Scientifc Industrial Co., Ltd.
+usi     Universal Scientific Industrial Co., Ltd.
 v3      V3 Semiconductor
 variscite       Variscite Ltd.
 via     VIA Technologies, Inc.
@@ -148,6 +161,7 @@ winbond Winbond Electronics corp.
 wlf     Wolfson Microelectronics
 wm      Wondermedia Technologies, Inc.
 xes     Extreme Engineering Solutions (X-ES)
+xillybus        Xillybus Ltd.
 xlnx    Xilinx
 zyxel   ZyXEL Communications Corp.
 zarlink Zarlink Semiconductor
diff --git a/Documentation/devicetree/bindings/video/adi,adv7123.txt b/Documentation/devicetree/bindings/video/adi,adv7123.txt
new file mode 100644
index 000000000000..a6b2b2b8f3d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/adi,adv7123.txt
@@ -0,0 +1,50 @@
+Analog Device ADV7123 Video DAC
+-------------------------------
+The ADV7123 is a digital-to-analog converter that outputs VGA signals from a
+parallel video input.
+Required properties:
+- compatible: Should be "adi,adv7123"
+Optional properties:
+- psave-gpios: Power save control GPIO
+Required nodes:
+The ADV7123 has two video ports. Their connections are modeled using the OF
+graph bindings specified in Documentation/devicetree/bindings/graph.txt.
+- Video port 0 for DPI input
+- Video port 1 for VGA output
+Example
+-------
+        adv7123: encoder@0 {
+                compatible = "adi,adv7123";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                adv7123_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                adv7123_out: endpoint@0 {
+                                        remote-endpoint = <&vga_connector_in>;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/video/analog-tv-connector.txt b/Documentation/devicetree/bindings/video/analog-tv-connector.txt
index 0218fcdc1299..0c0970c210ab 100644
--- a/Documentation/devicetree/bindings/video/analog-tv-connector.txt
+++ b/Documentation/devicetree/bindings/video/analog-tv-connector.txt
@@ -2,7 +2,7 @@ Analog TV Connector
 ===================
 Required properties:
- compatible: "composite-connector" or "svideo-connector"
+- compatible: "composite-video-connector" or "svideo-connector"
 Optional properties:
 - label: a symbolic name for the connector
@@ -14,7 +14,7 @@ Example
 -------
 tv: connector {
-        compatible = "composite-connector";
+        compatible = "composite-video-connector";
        label = "tv";
        port {
diff --git a/Documentation/devicetree/bindings/video/atmel,lcdc.txt b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
index b75af94a5e52..7d0c4a1ab811 100644
--- a/Documentation/devicetree/bindings/video/atmel,lcdc.txt
+++ b/Documentation/devicetree/bindings/video/atmel,lcdc.txt
@@ -39,8 +39,8 @@ Atmel LCDC Display
 -----------------------------------------------------
 Required properties (as per of_videomode_helper):
- - atmel,dmacon: dma controler configuration
+ - atmel,dmacon: dma controller configuration
- - atmel,lcdcon2: lcd controler configuration
+ - atmel,lcdcon2: lcd controller configuration
 - atmel,guard-time: lcd guard time (Delay in frame periods)
 - bits-per-pixel: lcd panel bit-depth.
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
index 31036c667d54..e74243b4b317 100644
--- a/Documentation/devicetree/bindings/video/exynos_dsim.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -2,6 +2,7 @@ Exynos MIPI DSI Master
 Required properties:
  - compatible: value should be one of the following
+                "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
                "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
                "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
  - reg: physical base address and length of the registers set for the device
diff --git a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
index 0329f60d431e..8c8c2f4e4c3f 100644
--- a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
+++ b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
@@ -20,7 +20,7 @@ Optional properties:
        register is not modified as recommended by the datasheet.
 - fsl,lpccr: Contrast Control Register value. This property provides the
        default value for the contrast control register.
-        If that property is ommited, the register is zeroed.
+        If that property is omitted, the register is zeroed.
 - fsl,lscr1: LCDC Sharp Configuration Register value.
 Example:
diff --git a/Documentation/devicetree/bindings/video/renesas,du.txt b/Documentation/devicetree/bindings/video/renesas,du.txt
new file mode 100644
index 000000000000..5102830f2760
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/renesas,du.txt
@@ -0,0 +1,84 @@
+* Renesas R-Car Display Unit (DU)
+Required Properties:
+  - compatible: must be one of the following.
+    - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
+    - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
+    - "renesas,du-r8a7791" for R8A7791 (R-Car M2) compatible DU
+  - reg: A list of base address and length of each memory resource, one for
+    each entry in the reg-names property.
+  - reg-names: Name of the memory resources. The DU requires one memory
+    resource for the DU core (named "du") and one memory resource for each
+    LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
+    index).
+  - interrupt-parent: phandle of the parent interrupt controller.
+  - interrupts: Interrupt specifiers for the DU interrupts.
+  - clocks: A list of phandles + clock-specifier pairs, one for each entry in
+    the clock-names property.
+  - clock-names: Name of the clocks. This property is model-dependent.
+    - R8A7779 uses a single functional clock. The clock doesn't need to be
+      named.
+    - R8A7790 and R8A7791 use one functional clock per channel and one clock
+      per LVDS encoder. The functional clocks must be named "du.x" with "x"
+      being the channel numerical index. The LVDS clocks must be named
+      "lvds.x" with "x" being the LVDS encoder numerical index.
+Required nodes:
+The connections to the DU output video ports are modeled using the OF graph
+bindings specified in Documentation/devicetree/bindings/graph.txt.
+The following table lists for each supported model the port number
+corresponding to each DU output.
+                Port 0          Port1           Port2
+-----------------------------------------------------------------------------
+ R8A7779 (H1)   DPAD 0          DPAD 1          -
+ R8A7790 (H2)   DPAD            LVDS 0          LVDS 1
+ R8A7791 (M2)   DPAD            LVDS 0          -
+Example: R8A7790 (R-Car H2) DU
+        du: du@feb00000 {
+                compatible = "renesas,du-r8a7790";
+                reg = <0 0xfeb00000 0 0x70000>,
+                      <0 0xfeb90000 0 0x1c>,
+                      <0 0xfeb94000 0 0x1c>;
+                reg-names = "du", "lvds.0", "lvds.1";
+                interrupt-parent = <&gic>;
+                interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 268 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 269 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp7_clks R8A7790_CLK_DU0>,
+                         <&mstp7_clks R8A7790_CLK_DU1>,
+                         <&mstp7_clks R8A7790_CLK_DU2>,
+                         <&mstp7_clks R8A7790_CLK_LVDS0>,
+                         <&mstp7_clks R8A7790_CLK_LVDS1>;
+                clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                du_out_rgb: endpoint {
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                du_out_lvds0: endpoint {
+                                };
+                        };
+                        port@2 {
+                                reg = <2>;
+                                du_out_lvds1: endpoint {
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index ecc899b9817b..4e6c77c85546 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -9,6 +9,7 @@ Required properties:
                "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
                "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
                "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
+                "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
                "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
                "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
diff --git a/Documentation/devicetree/bindings/video/thine,thc63lvdm83d b/Documentation/devicetree/bindings/video/thine,thc63lvdm83d
new file mode 100644
index 000000000000..527e236e9a2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/thine,thc63lvdm83d
@@ -0,0 +1,50 @@
+THine Electronics THC63LVDM83D LVDS serializer
+----------------------------------------------
+The THC63LVDM83D is an LVDS serializer designed to support pixel data
+transmission between a host and a flat panel.
+Required properties:
+- compatible: Should be "thine,thc63lvdm83d"
+Optional properties:
+- pwdn-gpios: Power down control GPIO
+Required nodes:
+The THC63LVDM83D has two video ports. Their connections are modeled using the
+OFgraph bindings specified in Documentation/devicetree/bindings/graph.txt.
+- Video port 0 for CMOS/TTL input
+- Video port 1 for LVDS output
+Example
+-------
+        lvds_enc: encoder@0 {
+                compatible = "thine,thc63lvdm83d";
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                lvds_enc_in: endpoint@0 {
+                                        remote-endpoint = <&rgb_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                lvds_enc_out: endpoint@0 {
+                                        remote-endpoint = <&panel_in>;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/video/vga-connector.txt b/Documentation/devicetree/bindings/video/vga-connector.txt
new file mode 100644
index 000000000000..c727f298e7ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/vga-connector.txt
@@ -0,0 +1,36 @@
+VGA Connector
+=============
+Required properties:
+- compatible: "vga-connector"
+Optional properties:
+- label: a symbolic name for the connector corresponding to a hardware label
+- ddc-i2c-bus: phandle to the I2C bus that is connected to VGA DDC
+Required nodes:
+The VGA connector internal connections are modeled using the OF graph bindings
+specified in Documentation/devicetree/bindings/graph.txt.
+The VGA connector has a single port that must be connected to a video source
+port.
+Example
+-------
+vga0: connector@0 {
+        compatible = "vga-connector";
+        label = "vga";
+        ddc-i2c-bus = <&i2c3>;
+        port {
+                vga_connector_in: endpoint {
+                        remote-endpoint = <&adv7123_out>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/staging/xillybus.txt b/Documentation/devicetree/bindings/xillybus/xillybus.txt
index 9e316dc2e40f..9e316dc2e40f 100644
--- a/Documentation/devicetree/bindings/staging/xillybus.txt
+++ b/Documentation/devicetree/bindings/xillybus/xillybus.txt
diff --git a/Documentation/devicetree/booting-without-of.txt b/Documentation/devicetree/booting-without-of.txt
index 1f013bd0d320..77685185cf3b 100644
--- a/Documentation/devicetree/booting-without-of.txt
+++ b/Documentation/devicetree/booting-without-of.txt
@@ -51,6 +51,8 @@ Table of Contents
  VIII - Specifying device power management information (sleep property)
+  IX - Specifying dma bus information
  Appendix A - Sample SOC node for MPC8540
@@ -1332,6 +1334,57 @@ reasonably grouped in this manner, then create a virtual sleep controller
 (similar to an interrupt nexus, except that defining a standardized
 sleep-map should wait until its necessity is demonstrated).
+IX - Specifying dma bus information
+Some devices may have DMA memory range shifted relatively to the beginning of
+RAM, or even placed outside of kernel RAM. For example, the Keystone 2 SoC
+worked in LPAE mode with 4G memory has:
+- RAM range: [0x8 0000 0000, 0x8 FFFF FFFF]
+- DMA range: [  0x8000 0000,   0xFFFF FFFF]
+and DMA range is aliased into first 2G of RAM in HW.
+In such cases, DMA addresses translation should be performed between CPU phys
+and DMA addresses. The "dma-ranges" property is intended to be used
+for describing the configuration of such system in DT.
+In addition, each DMA master device on the DMA bus may or may not support
+coherent DMA operations. The "dma-coherent" property is intended to be used
+for identifying devices supported coherent DMA operations in DT.
+* DMA Bus master
+Optional property:
+- dma-ranges: <prop-encoded-array> encoded as arbitrary number of triplets of
+        (child-bus-address, parent-bus-address, length). Each triplet specified
+        describes a contiguous DMA address range.
+        The dma-ranges property is used to describe the direct memory access (DMA)
+        structure of a memory-mapped bus whose device tree parent can be accessed
+        from DMA operations originating from the bus. It provides a means of
+        defining a mapping or translation between the physical address space of
+        the bus and the physical address space of the parent of the bus.
+        (for more information see ePAPR specification)
+* DMA Bus child
+Optional property:
+- dma-ranges: <empty> value. if present - It means that DMA addresses
+        translation has to be enabled for this device.
+- dma-coherent: Present if dma operations are coherent
+Example:
+soc {
+                compatible = "ti,keystone","simple-bus";
+                ranges = <0x0 0x0 0x0 0xc0000000>;
+                dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
+                [...]
+                usb: usb@2680000 {
+                        compatible = "ti,keystone-dwc3";
+                        [...]
+                        dma-coherent;
+                };
+};
 Appendix A - Sample SOC node for MPC8540
 ========================================
diff --git a/Documentation/devicetree/dynamic-resolution-notes.txt b/Documentation/devicetree/dynamic-resolution-notes.txt
new file mode 100644
index 000000000000..083d23262abe
--- /dev/null
+++ b/Documentation/devicetree/dynamic-resolution-notes.txt
@@ -0,0 +1,25 @@
+Device Tree Dynamic Resolver Notes
+----------------------------------
+This document describes the implementation of the in-kernel
+Device Tree resolver, residing in drivers/of/resolver.c and is a
+companion document to Documentation/devicetree/dt-object-internal.txt[1]
+How the resolver works
+----------------------
+The resolver is given as an input an arbitrary tree compiled with the
+proper dtc option and having a /plugin/ tag. This generates the
+appropriate __fixups__ & __local_fixups__ nodes as described in [1].
+In sequence the resolver works by the following steps:
+1. Get the maximum device tree phandle value from the live tree + 1.
+2. Adjust all the local phandles of the tree to resolve by that amount.
+3. Using the __local__fixups__ node information adjust all local references
+   by the same amount.
+4. For each property in the __fixups__ node locate the node it references
+   in the live tree. This is the label used to tag the node.
+5. Retrieve the phandle of the target of the fixup.
+6. For each fixup in the property locate the node:property:offset location
+   and replace it with the phandle value.
diff --git a/Documentation/devicetree/of_selftest.txt b/Documentation/devicetree/of_selftest.txt
new file mode 100644
index 000000000000..1e3d5c92b5e3
--- /dev/null
+++ b/Documentation/devicetree/of_selftest.txt
@@ -0,0 +1,211 @@
+Open Firmware Device Tree Selftest
+----------------------------------
+Author: Gaurav Minocha <gaurav.minocha.os@gmail.com>
+1. Introduction
+This document explains how the test data required for executing OF selftest
+is attached to the live tree dynamically, independent of the machine's
+architecture.
+It is recommended to read the following documents before moving ahead.
+[1] Documentation/devicetree/usage-model.txt
+[2] http://www.devicetree.org/Device_Tree_Usage
+OF Selftest has been designed to test the interface (include/linux/of.h)
+provided to device driver developers to fetch the device information..etc.
+from the unflattened device tree data structure. This interface is used by
+most of the device drivers in various use cases.
+2. Test-data
+The Device Tree Source file (drivers/of/testcase-data/testcases.dts) contains
+the test data required for executing the unit tests automated in
+drivers/of/selftests.c. Currently, following Device Tree Source Include files
+(.dtsi) are included in testcase.dts:
+drivers/of/testcase-data/tests-interrupts.dtsi
+drivers/of/testcase-data/tests-platform.dtsi
+drivers/of/testcase-data/tests-phandle.dtsi
+drivers/of/testcase-data/tests-match.dtsi
+When the kernel is build with OF_SELFTEST enabled, then the following make rule
+$(obj)/%.dtb: $(src)/%.dts FORCE
+        $(call if_changed_dep, dtc)
+is used to compile the DT source file (testcase.dts) into a binary blob
+(testcase.dtb), also referred as flattened DT.
+After that, using the following rule the binary blob above is wrapped as an
+assembly file (testcase.dtb.S).
+$(obj)/%.dtb.S: $(obj)/%.dtb
+        $(call cmd, dt_S_dtb)
+The assembly file is compiled into an object file (testcase.dtb.o), and is
+linked into the kernel image.
+2.1. Adding the test data
+Un-flattened device tree structure:
+Un-flattened device tree consists of connected device_node(s) in form of a tree
+structure described below.
+// following struct members are used to construct the tree
+struct device_node {
+    ...
+    struct  device_node *parent;
+    struct  device_node *child;
+    struct  device_node *sibling;
+    struct  device_node *allnext;   /* next in list of all nodes */
+    ...
+ };
+Figure 1, describes a generic structure of machine's un-flattened device tree
+considering only child and sibling pointers. There exists another pointer,
+*parent, that is used to traverse the tree in the reverse direction. So, at
+a particular level the child node and all the sibling nodes will have a parent
+pointer pointing to a common node (e.g. child1, sibling2, sibling3, sibling4's
+parent points to root node)
+root ('/')
+   |
+child1 -> sibling2 -> sibling3 -> sibling4 -> null
+   |         |           |           |
+   |         |           |          null
+   |         |           |
+   |         |        child31 -> sibling32 -> null
+   |         |           |          |
+   |         |          null       null
+   |         |
+   |      child21 -> sibling22 -> sibling23 -> null
+   |         |          |            |
+   |        null       null         null
+   |
+child11 -> sibling12 -> sibling13 -> sibling14 -> null
+   |           |           |            |
+   |           |           |           null
+   |           |           |
+  null        null       child131 -> null
+                           |
+                          null
+Figure 1: Generic structure of un-flattened device tree
+*allnext: it is used to link all the nodes of DT into a list. So, for the
+ above tree the list would be as follows:
+root->child1->child11->sibling12->sibling13->child131->sibling14->sibling2->
+child21->sibling22->sibling23->sibling3->child31->sibling32->sibling4->null
+Before executing OF selftest, it is required to attach the test data to
+machine's device tree (if present). So, when selftest_data_add() is called,
+at first it reads the flattened device tree data linked into the kernel image
+via the following kernel symbols:
+__dtb_testcases_begin - address marking the start of test data blob
+__dtb_testcases_end   - address marking the end of test data blob
+Secondly, it calls of_fdt_unflatten_tree() to unflatten the flattened
+blob. And finally, if the machine's device tree (i.e live tree) is present,
+then it attaches the unflattened test data tree to the live tree, else it
+attaches itself as a live device tree.
+attach_node_and_children() uses of_attach_node() to attach the nodes into the
+live tree as explained below. To explain the same, the test data tree described
+ in Figure 2 is attached to the live tree described in Figure 1.
+root ('/')
+    |
+ testcase-data
+    |
+ test-child0 -> test-sibling1 -> test-sibling2 -> test-sibling3 -> null
+    |               |                |                |
+ test-child01      null             null             null
+allnext list:
+root->testcase-data->test-child0->test-child01->test-sibling1->test-sibling2
+->test-sibling3->null
+Figure 2: Example test data tree to be attached to live tree.
+According to the scenario above, the live tree is already present so it isn't
+required to attach the root('/') node. All other nodes are attached by calling
+of_attach_node() on each node.
+In the function of_attach_node(), the new node is attached as the child of the
+given parent in live tree. But, if parent already has a child then the new node
+replaces the current child and turns it into its sibling. So, when the testcase
+data node is attached to the live tree above (Figure 1), the final structure is
+ as shown in Figure 3.
+root ('/')
+   |
+testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null
+   |               |          |           |           |
+ (...)             |          |           |          null
+                   |          |         child31 -> sibling32 -> null
+                   |          |           |           |
+                   |          |          null        null
+                   |          |
+                   |        child21 -> sibling22 -> sibling23 -> null
+                   |          |           |            |
+                   |         null        null         null
+                   |
+                child11 -> sibling12 -> sibling13 -> sibling14 -> null
+                   |          |            |            |
+                  null       null          |           null
+                                           |
+                                        child131 -> null
+                                           |
+                                          null
+-----------------------------------------------------------------------
+root ('/')
+   |
+testcase-data -> child1 -> sibling2 -> sibling3 -> sibling4 -> null
+   |               |          |           |           |
+   |             (...)      (...)       (...)        null
+   |
+test-sibling3 -> test-sibling2 -> test-sibling1 -> test-child0 -> null
+   |                |                   |                |
+  null             null                null         test-child01
+Figure 3: Live device tree structure after attaching the testcase-data.
+Astute readers would have noticed that test-child0 node becomes the last
+sibling compared to the earlier structure (Figure 2). After attaching first
+test-child0 the test-sibling1 is attached that pushes the child node
+(i.e. test-child0) to become a sibling and makes itself a child node,
+ as mentioned above.
+If a duplicate node is found (i.e. if a node with same full_name property is
+already present in the live tree), then the node isn't attached rather its
+properties are updated to the live tree's node by calling the function
+update_node_properties().
+2.2. Removing the test data
+Once the test case execution is complete, selftest_data_remove is called in
+order to remove the device nodes attached initially (first the leaf nodes are
+detached and then moving up the parent nodes are removed, and eventually the
+whole tree). selftest_data_remove() calls detach_node_and_children() that uses
+of_detach_node() to detach the nodes from the live device tree.
+To detach a node, of_detach_node() first updates all_next linked list, by
+attaching the previous node's allnext to current node's allnext pointer. And
+then, it either updates the child pointer of given node's parent to its
+sibling or attaches the previous sibling to the given node's sibling, as
+appropriate. That is it :)