149 files changed, 3680 insertions, 376 deletions

diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index 20746e5abe6f..06fc7602593a 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -1,10 +1,14 @@
 * ARM architected timer
 
-ARM cores may have a per-core architected timer, which provides per-cpu timers.
+ARM cores may have a per-core architected timer, which provides per-cpu timers,
+or a memory mapped architected timer, which provides up to 8 frames with a
+physical and optional virtual timer per frame.
 
-The timer is attached to a GIC to deliver its per-processor interrupts.
+The per-core architected timer is attached to a GIC to deliver its
+per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
+to deliver its interrupts via SPIs.
 
-** Timer node properties:
+** CP15 Timer node properties:
 
 - compatible : Should at least contain one of
         "arm,armv7-timer"
@@ -26,3 +30,52 @@ Example:
                              <1 10 0xf08>;
                 clock-frequency = <100000000>;
         };
+
+** Memory mapped timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer-mem".
+
+- clock-frequency : The frequency of the main counter, in Hz. Optional.
+
+- reg : The control frame base address.
+
+Note that #address-cells, #size-cells, and ranges shall be present to ensure
+the CPU can address a frame's registers.
+
+A timer node has up to 8 frame sub-nodes, each with the following properties:
+
+- frame-number: 0 to 7.
+
+- interrupts : Interrupt list for physical and virtual timers in that order.
+  The virtual timer interrupt is optional.
+
+- reg : The first and second view base addresses in that order. The second view
+  base address is optional.
+
+- status : "disabled" indicates the frame is not available for use. Optional.
+
+Example:
+
+        timer@f0000000 {
+                compatible = "arm,armv7-timer-mem";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                reg = <0xf0000000 0x1000>;
+                clock-frequency = <50000000>;
+
+                frame@f0001000 {
+                        frame-number = <0>
+                        interrupts = <0 13 0x8>,
+                                     <0 14 0x8>;
+                        reg = <0xf0001000 0x1000>,
+                              <0xf0002000 0x1000>;
+                };
+
+                frame@f0003000 {
+                        frame-number = <1>
+                        interrupts = <0 15 0x8>;
+                        reg = <0xf0003000 0x1000>;
+                        status = "disabled";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/atmel-adc.txt b/Documentation/devicetree/bindings/arm/atmel-adc.txt
index 16769d9cedd6..723c205cb10d 100644
--- a/Documentation/devicetree/bindings/arm/atmel-adc.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-adc.txt
@@ -1,18 +1,15 @@
 * AT91's Analog to Digital Converter (ADC)
 
 Required properties:
-  - compatible: Should be "atmel,at91sam9260-adc"
+  - compatible: Should be "atmel,<chip>-adc"
+    <chip> can be "at91sam9260", "at91sam9g45" or "at91sam9x5"
   - reg: Should contain ADC registers location and length
   - interrupts: Should contain the IRQ line for the ADC
-  - atmel,adc-channel-base: Offset of the first channel data register
   - atmel,adc-channels-used: Bitmask of the channels muxed and enable for this
     device
-  - atmel,adc-drdy-mask: Mask of the DRDY interruption in the ADC
   - atmel,adc-num-channels: Number of channels available in the ADC
   - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
     defined in the datasheet
-  - atmel,adc-status-register: Offset of the Interrupt Status Register
-  - atmel,adc-trigger-register: Offset of the Trigger Register
   - atmel,adc-vref: Reference voltage in millivolts for the conversions
   - atmel,adc-res: List of resolution in bits supported by the ADC. List size
                    must be two at least.
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
index fb7b5cd2652f..0ff6560e6094 100644
--- a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
@@ -6,4 +6,5 @@ bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
 
 Required root node property:
 
-compatible = "bcm,bcm11351";
+compatible = "brcm,bcm11351";
+DEPRECATED: compatible = "bcm,bcm11351";
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt b/Documentation/devicetree/bindings/arm/bcm/kona-timer.txt
index 59fa6e68d4f6..17d88b233d1b 100644
--- a/Documentation/devicetree/bindings/arm/bcm/bcm,kona-timer.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/kona-timer.txt
@@ -4,14 +4,15 @@ This timer is used in the following Broadcom SoCs:
  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
 
 Required properties:
-- compatible : "bcm,kona-timer"
+- compatible : "brcm,kona-timer"
+- DEPRECATED: compatible : "bcm,kona-timer"
 - reg : Register range for the timer
 - interrupts : interrupt for the timer
 - clock-frequency: frequency that the clock operates
 
 Example:
         timer@35006000 {
-                compatible = "bcm,kona-timer";
+                compatible = "brcm,kona-timer";
                 reg = <0x35006000 0x1000>;
                 interrupts = <0x0 7 0x4>;
                 clock-frequency = <32768>;
diff --git a/Documentation/devicetree/bindings/arm/bcm/kona-wdt.txt b/Documentation/devicetree/bindings/arm/bcm/kona-wdt.txt
new file mode 100644
index 000000000000..2b86a00e351d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/kona-wdt.txt
@@ -0,0 +1,15 @@
+Broadcom Kona Family Watchdog Timer
+-----------------------------------
+
+This watchdog timer is used in the following Broadcom SoCs:
+  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155
+
+Required properties:
+  - compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
+  - reg: memory address & range
+
+Example:
+        watchdog@35002f40 {
+                compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
+                reg = <0x35002f40 0x6c>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 69ddf9fad2dc..c0c7626fd0ff 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -16,9 +16,11 @@ Required properties:
      performs the same operation).
         "marvell,"aurora-outer-cache: Marvell Controller designed to be
          compatible with the ARM one with outer cache mode.
-        "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+        "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
         offset needs to be added to the address before passing down to the L2
         cache controller
+        "bcm,bcm11351-a2-pl310-cache": DEPRECATED by
+                                       "brcm,bcm11351-a2-pl310-cache"
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 6d498c758b45..91b7049affa1 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -59,3 +59,6 @@ Boards:
 
 - AM43x EPOS EVM
   compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
+
+- DRA7 EVM:  Software Developement Board for DRA7XX
+  compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
index 69b5ab0b5f4b..d11d80006a19 100644
--- a/Documentation/devicetree/bindings/arm/ste-u300.txt
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -22,7 +22,7 @@ This contains the board-specific information.
 - compatible: must be "stericsson,s365".
 - vana15-supply: the regulator supplying the 1.5V to drive the
   board.
-- syscon: a pointer to the syscon node so we can acccess the
+- syscon: a pointer to the syscon node so we can access the
   syscon registers to set the board as self-powered.
 
 Example:
diff --git a/Documentation/devicetree/bindings/arm/vexpress-scc.txt b/Documentation/devicetree/bindings/arm/vexpress-scc.txt
new file mode 100644
index 000000000000..ae5043e42e5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress-scc.txt
@@ -0,0 +1,33 @@
+ARM Versatile Express Serial Configuration Controller
+-----------------------------------------------------
+
+Test chips for ARM Versatile Express platform implement SCC (Serial
+Configuration Controller) interface, used to set initial conditions
+for the test chip.
+
+In some cases its registers are also mapped in normal address space
+and can be used to obtain runtime information about the chip internals
+(like silicon temperature sensors) and as interface to other subsystems
+like platform configuration control and power management.
+
+Required properties:
+
+- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
+                    where <model> is the full tile model name (as used
+                    in the tile's Technical Reference Manual),
+                    eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
+        compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
+
+Optional properties:
+
+- reg: when the SCC is memory mapped, physical address and size of the
+       registers window
+- interrupts: when the SCC can generate a system-level interrupt
+
+Example:
+
+        scc@7fff0000 {
+                compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
+                reg = <0 0x7fff0000 0 0x1000>;
+                interrupts = <0 95 4>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
index 9cf3f25544c7..5580e9c4bd85 100644
--- a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
+++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
@@ -32,8 +32,8 @@ numbers - see motherboard's TRM for more details.
 The node describing a config device must refer to the sysreg node via
 "arm,vexpress,config-bridge" phandle (can be also defined in the node's
 parent) and relies on the board topology properties - see main vexpress
-node documentation for more details. It must must also define the
-following property:
+node documentation for more details. It must also define the following
+property:
 - arm,vexpress-sysreg,func : must contain two cells:
   - first cell defines function number (eg. 1 for clock generator,
     2 for voltage regulators etc.)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 3ec0c5c4f0e9..89de1564950c 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -4,27 +4,17 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
 Required properties:
-- compatible        : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
+- compatible        : compatible list, contains "snps,spear-ahci"
 - interrupts        : <interrupt mapping for SATA IRQ>
 - reg               : <registers mapping>
 
 Optional properties:
-- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
-                        SATA port to a combophy and a lane within that
-                        combophy
-- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
-                        which indicates that the driver supports SGPIO
-                        indicator lights using the indicated GPIOs
-- calxeda,led-order : a u32 array that map port numbers to offsets within the
-                        SGPIO bitstream.
 - dma-coherent      : Present if dma operations are coherent
 
 Example:
         sata@ffe08000 {
-                compatible = "calxeda,hb-ahci";
-                reg = <0xffe08000 0x1000>;
-                interrupts = <115>;
-                calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
-                                        &combophy0 2 &combophy0 3>;
+                compatible = "snps,spear-ahci";
+                reg = <0xffe08000 0x1000>;
+                interrupts = <115>;
 
         };
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
new file mode 100644
index 000000000000..aa83407cb7a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -0,0 +1,44 @@
+* Calxeda AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+The Calxeda SATA controller mostly conforms to the AHCI interface
+with some special extensions to add functionality.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible        : compatible list, contains "calxeda,hb-ahci"
+- interrupts        : <interrupt mapping for SATA IRQ>
+- reg               : <registers mapping>
+
+Optional properties:
+- dma-coherent      : Present if dma operations are coherent
+- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
+                        SATA port to a combophy and a lane within that
+                        combophy
+- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
+                        which indicates that the driver supports SGPIO
+                        indicator lights using the indicated GPIOs
+- calxeda,led-order : a u32 array that map port numbers to offsets within the
+                        SGPIO bitstream.
+- calxeda,tx-atten  : a u32 array that contains TX attenuation override
+                        codes, one per port. The upper 3 bytes are always
+                        0 and thus ignored.
+- calxeda,pre-clocks : a u32 that indicates the number of additional clock
+                        cycles to transmit before sending an SGPIO pattern
+- calxeda,post-clocks: a u32 that indicates the number of additional clock
+                        cycles to transmit after sending an SGPIO pattern
+
+Example:
+        sata@ffe08000 {
+                compatible = "calxeda,hb-ahci";
+                reg = <0xffe08000 0x1000>;
+                interrupts = <115>;
+                dma-coherent;
+                calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
+                                        &combophy0 2 &combophy0 3>;
+                calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+                calxeda,led-order = <4 0 1 2 3>;
+                calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
+                calxeda,pre-clocks = <10>;
+                calxeda,post-clocks = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
index cedc2a9c4785..0fd76c405208 100644
--- a/Documentation/devicetree/bindings/bus/imx-weim.txt
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -8,7 +8,7 @@ The actual devices are instantiated from the child nodes of a WEIM node.
 
 Required properties:
 
- - compatible:          Should be set to "fsl,imx6q-weim"
+ - compatible:          Should be set to "fsl,<soc>-weim"
  - reg:                 A resource specifier for the register space
                         (see the example below)
  - clocks:              the clock, see the example below.
@@ -21,11 +21,18 @@ Required properties:
 
 Timing property for child nodes. It is mandatory, not optional.
 
- - fsl,weim-cs-timing:  The timing array, contains 6 timing values for the
+ - fsl,weim-cs-timing:  The timing array, contains timing values for the
                         child node. We can get the CS index from the child
-                        node's "reg" property. This property contains the values
-                        for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
-                        EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+                        node's "reg" property. The number of registers depends
+                        on the selected chip.
+                        For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
+                        registers: CSxU, CSxL.
+                        For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
+                        there are three registers: CSCRxU, CSCRxL, CSCRxA.
+                        For i.MX50, i.MX53 ("fsl,imx50-weim"),
+                        i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
+                        there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
+                        CSxRCR2, CSxWCR1, CSxWCR2.
 
 Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
 
diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
new file mode 100644
index 000000000000..7586fb68c072
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
@@ -0,0 +1,276 @@
+
+* Marvell MBus
+
+Required properties:
+
+- compatible:    Should be set to one of the following:
+                 marvell,armada370-mbus
+                 marvell,armadaxp-mbus
+                 marvell,armada370-mbus
+                 marvell,armadaxp-mbus
+                 marvell,kirkwood-mbus
+                 marvell,dove-mbus
+                 marvell,orion5x-88f5281-mbus
+                 marvell,orion5x-88f5182-mbus
+                 marvell,orion5x-88f5181-mbus
+                 marvell,orion5x-88f6183-mbus
+                 marvell,mv78xx0-mbus
+
+- address-cells: Must be '2'. The first cell for the MBus ID encoding,
+                 the second cell for the address offset within the window.
+
+- size-cells:    Must be '1'.
+
+- ranges:        Must be set up to provide a proper translation for each child.
+                 See the examples below.
+
+- controller:    Contains a single phandle referring to the MBus controller
+                 node. This allows to specify the node that contains the
+                 registers that control the MBus, which is typically contained
+                 within the internal register window (see below).
+
+Optional properties:
+
+- pcie-mem-aperture:    This optional property contains the aperture for
+                        the memory region of the PCIe driver.
+                        If it's defined, it must encode the base address and
+                        size for the address decoding windows allocated for
+                        the PCIe memory region.
+
+- pcie-io-aperture:     Just as explained for the above property, this
+                        optional property contains the aperture for the
+                        I/O region of the PCIe driver.
+
+* Marvell MBus controller
+
+Required properties:
+
+- compatible:   Should be set to "marvell,mbus-controller".
+
+- reg:          Device's register space.
+                Two entries are expected (see the examples below):
+                the first one controls the devices decoding window and
+                the second one controls the SDRAM decoding window.
+
+Example:
+
+        soc {
+                compatible = "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+                pcie-mem-aperture = <0xe0000000 0x8000000>;
+                pcie-io-aperture  = <0xe8000000 0x100000>;
+
+                internal-regs {
+                        compatible = "simple-bus";
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        /* more children ...*/
+                };
+        };
+
+** MBus address decoding window specification
+
+The MBus children address space is comprised of two cells: the first one for
+the window ID and the second one for the offset within the window.
+In order to allow to describe valid and non-valid window entries, the
+following encoding is used:
+
+  0xSIAA0000 0x00oooooo
+
+Where:
+
+  S = 0x0 for a MBus valid window
+  S = 0xf for a non-valid window (see below)
+
+If S = 0x0, then:
+
+   I = 4-bit window target ID
+  AA = windpw attribute
+
+If S = 0xf, then:
+
+   I = don't care
+   AA = 1 for internal register
+
+Following the above encoding, for each ranges entry for a MBus valid window
+(S = 0x0), an address decoding window is allocated. On the other side,
+entries for translation that do not correspond to valid windows (S = 0xf)
+are skipped.
+
+        soc {
+                compatible = "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+
+                ranges = <0xf0010000 0 0 0xd0000000 0x100000
+                          0x01e00000 0 0 0xfff00000 0x100000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <0x01e00000 0 0x100000>;
+                };
+
+                /* other children */
+                ...
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        ranges = <0 0xf0010000 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        /* more children ...*/
+                };
+        };
+
+In the shown example, the translation entry in the 'ranges' property is what
+makes the MBus driver create a static decoding window for the corresponding
+given child device. Note that the binding does not require child nodes to be
+present. Of course, child nodes are needed to probe the devices.
+
+Since each window is identified by its target ID and attribute ID there's
+a special macro that can be use to simplify the translation entries:
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+Using this macro, the above example would be:
+
+        soc {
+                compatible = "marvell,armada370-mbus", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                controller = <&mbusc>;
+
+                ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
+                           MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
+                };
+
+                /* other children */
+                ...
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        /* other children */
+                        ...
+                };
+        };
+
+
+** About the window base address
+
+Remember the MBus controller allows a great deal of flexibility for choosing
+the decoding window base address. When planning the device tree layout it's
+possible to choose any address as the base address, provided of course there's
+a region large enough available, and with the required alignment.
+
+Yet in other words: there's nothing preventing us from setting a base address
+of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
+unused.
+
+** Window allocation policy
+
+The mbus-node ranges property defines a set of mbus windows that are expected
+to be set by the operating system and that are guaranteed to be free of overlaps
+with one another or with the system memory ranges.
+
+Each entry in the property refers to exactly one window. If the operating system
+choses to use a different set of mbus windows, it must ensure that any address
+translations performed from downstream devices are adapted accordingly.
+
+The operating system may insert additional mbus windows that do not conflict
+with the ones listed in the ranges, e.g. for mapping PCIe devices.
+As a special case, the internal register window must be set up by the boot
+loader at the address listed in the ranges property, since access to that region
+is needed to set up the other windows.
+
+** Example
+
+See the example below, where a more complete device tree is shown:
+
+        soc {
+                compatible = "marvell,armadaxp-mbus", "simple-bus";
+                controller = <&mbusc>;
+
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000   /* internal-regs */
+                          MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+                          MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
+
+                bootrom {
+                        compatible = "marvell,bootrom";
+                        reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
+                };
+
+                devbus-bootcs {
+                        status = "okay";
+                        ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
+
+                        /* NOR */
+                        nor {
+                                compatible = "cfi-flash";
+                                reg = <0 0x8000000>;
+                                bank-width = <2>;
+                        };
+                };
+
+                pcie-controller {
+                        compatible = "marvell,armada-xp-pcie";
+                        status = "okay";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                                0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
+                                0x81000800 0 0          MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
+
+
+                        pcie@1,0 {
+                                /* Port 0, Lane 0 */
+                                status = "okay";
+                        };
+                };
+
+                internal-regs {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+                        mbusc: mbus-controller@20000 {
+                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                        };
+
+                        interrupt-controller@20000 {
+                              reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt
index d847758f2b20..b0e97144cfb1 100644
--- a/Documentation/devicetree/bindings/c6x/dscr.txt
+++ b/Documentation/devicetree/bindings/c6x/dscr.txt
@@ -5,7 +5,7 @@ TI C6X SoCs contain a region of miscellaneous registers which provide various
 function for SoC control or status. Details vary considerably among from SoC
 to SoC with no two being alike.
 
-In general, the Device State Configuraion Registers (DSCR) will provide one or
+In general, the Device State Configuration Registers (DSCR) will provide one or
 more configuration registers often protected by a lock register where one or
 more key values must be written to a lock register in order to unlock the
 configuration register for writes. These configuration register may be used to
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index a1201802f90d..75e2e1999f87 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -2,7 +2,7 @@
 
 The Samsung Audio Subsystem clock controller generates and supplies clocks
 to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
-binding described here is applicable to all SoC's in Exynos family.
+binding described here is applicable to all SoCs in Exynos family.
 
 Required Properties:
 
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 14d5c2af26f4..c6bf8a6c8f52 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable.
   spi0_isp_sclk       380     Exynos4x12
   spi1_isp_sclk       381     Exynos4x12
   uart_isp_sclk       382     Exynos4x12
+  tmu_apbif           383
 
                 [Mux Clocks]
 
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a6276adf7..24765c146e31 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -59,6 +59,9 @@ clock which they consume.
   sclk_spi0             154
   sclk_spi1             155
   sclk_spi2             156
+  div_i2s1              157
+  div_i2s2              158
+  sclk_hdmiphy          159
 
 
    [Peripheral Clock Gates]
@@ -154,7 +157,16 @@ clock which they consume.
   dsim0                 341
   dp                    342
   mixer                 343
-  hdmi                  345
+  hdmi                  344
+  g2d                   345
+
+
+   [Clock Muxes]
+
+  Clock                 ID
+  ----------------------------
+  mout_hdmi             1024
+
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 9bcc4b1bff51..32aa34ecad36 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -59,6 +59,7 @@ clock which they consume.
   sclk_pwm              155
   sclk_gscl_wa          156
   sclk_gscl_wb          157
+  sclk_hdmiphy          158
 
    [Peripheral Clock Gates]
 
@@ -179,6 +180,17 @@ clock which they consume.
   fimc_lite3            495
   aclk_g3d              500
   g3d                   501
+  smmu_mixer            502
+
+  Mux                   ID
+  ----------------------------
+
+  mout_hdmi             640
+
+  Divider               ID
+  ----------------------------
+
+  dout_pixel            768
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index f46f5625d8ad..4c029a8739d3 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -197,6 +197,7 @@ clocks and IDs.
         spdif0_gate             183
         spdif1_gate             184
         spdif_ipg_gate          185
+        ocram                   186
 
 Examples (for mx53):
 
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index a0e104f0527e..5a90a724b520 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -209,6 +209,12 @@ clocks and IDs.
         pll5_post_div           194
         pll5_video_div          195
         eim_slow                196
+        spdif                   197
+        cko2_sel                198
+        cko2_podf               199
+        cko2                    200
+        cko                     201
+        vdoa                    202
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
new file mode 100644
index 000000000000..fa171dc4bd3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
@@ -0,0 +1,77 @@
+* Samsung S3C64xx Clock Controller
+
+The S3C64xx clock controller generates and supplies clock to various controllers
+within the SoC. The clock binding described here is applicable to all SoCs in
+the S3C64xx family.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
+  - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. Some of the clocks are available only
+on a particular S3C64xx SoC and this is specified where applicable.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
+tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "fin_pll" - PLL input clock (xtal/extclk) - required,
+ - "xusbxti" - USB xtal - required,
+ - "iiscdclk0" - I2S0 codec clock - optional,
+ - "iiscdclk1" - I2S1 codec clock - optional,
+ - "iiscdclk2" - I2S2 codec clock - optional,
+ - "pcmcdclk0" - PCM0 codec clock - optional,
+ - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
+
+Example: Clock controller node:
+
+        clock: clock-controller@7e00f000 {
+                compatible = "samsung,s3c6410-clock";
+                reg = <0x7e00f000 0x1000>;
+                #clock-cells = <1>;
+        };
+
+Example: Required external clocks:
+
+        fin_pll: clock-fin-pll {
+                compatible = "fixed-clock";
+                clock-output-names = "fin_pll";
+                clock-frequency = <12000000>;
+                #clock-cells = <0>;
+        };
+
+        xusbxti: clock-xusbxti {
+                compatible = "fixed-clock";
+                clock-output-names = "xusbxti";
+                clock-frequency = <48000000>;
+                #clock-cells = <0>;
+        };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller (refer to the standard clock bindings for information about
+  "clocks" and "clock-names" properties):
+
+                uart0: serial@7f005000 {
+                        compatible = "samsung,s3c6400-uart";
+                        reg = <0x7f005000 0x100>;
+                        interrupt-parent = <&vic1>;
+                        interrupts = <5>;
+                        clock-names = "uart", "clk_uart_baud2",
+                                        "clk_uart_baud3";
+                        clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
+                                        <&clock SCLK_UART>;
+                        status = "disabled";
+                };
diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt
index 7fc09773de46..40e0cf1f7b99 100644
--- a/Documentation/devicetree/bindings/clock/st,nomadik.txt
+++ b/Documentation/devicetree/bindings/clock/st,nomadik.txt
@@ -17,7 +17,7 @@ Optional properties for the SRC node:
 - disable-mxtal: if present this will disable the MXTALO,
   i.e. the driver output for the main (~19.2 MHz) chrystal,
   if the board has its own circuitry for providing this
-  osciallator
+  oscillator
 
 
 PLL nodes: these nodes represent the two PLLs on the system,
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d495521a79d2..00a5c26454eb 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -8,19 +8,31 @@ Required properties:
 - compatible : shall be one of the following:
         "allwinner,sun4i-osc-clk" - for a gatable oscillator
         "allwinner,sun4i-pll1-clk" - for the main PLL clock
+        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
         "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
         "allwinner,sun4i-axi-clk" - for the AXI clock
         "allwinner,sun4i-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-ahb-clk" - for the AHB clock
         "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
+        "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
+        "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
+        "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
+        "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
         "allwinner,sun4i-apb0-clk" - for the APB0 clock
         "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
+        "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
+        "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
         "allwinner,sun4i-apb1-clk" - for the APB1 clock
         "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
         "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
+        "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
+        "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
+        "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
+        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
+        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
new file mode 100644
index 000000000000..d24279fe1429
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
@@ -0,0 +1,75 @@
+Gate clock outputs
+------------------
+
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+    DRAM                                        0
+
+  * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
+
+    USB0                                        0
+    EHCI0                                       1
+    OHCI0                                       2
+
+    SS                                          5
+    DMA                                         6
+    BIST                                        7
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+
+    NAND                                        13
+    SDRAM                                       14
+
+    EMAC                                        17
+    TS                                          18
+
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+
+    GPS                                         26
+
+    HSTIMER                                     28
+
+    VE                                          32
+
+    TVE                                         34
+
+    LCD                                         36
+
+    CSI                                         40
+
+    HDMI                                        43
+    DE_BE                                       44
+
+    DE_FE                                       46
+
+    IEP                                         51
+    MALI400                                     52
+
+  * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
+
+    CODEC                                       0
+
+    IIS                                         3
+
+    PIO                                         5
+    IR                                          6
+
+    KEYPAD                                      10
+
+  * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
+
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
new file mode 100644
index 000000000000..fe44932b5c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
@@ -0,0 +1,83 @@
+Gate clock outputs
+------------------
+
+  * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk")
+
+    MIPI DSI                                    1
+
+    SS                                          5
+    DMA                                         6
+
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+    MMC3                                        11
+
+    NAND1                                       12
+    NAND0                                       13
+    SDRAM                                       14
+
+    GMAC                                        17
+    TS                                          18
+    HSTIMER                                     19
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+    SPI3                                        23
+    USB_OTG                                     24
+
+    EHCI0                                       26
+    EHCI1                                       27
+
+    OHCI0                                       29
+    OHCI1                                       30
+    OHCI2                                       31
+    VE                                          32
+
+    LCD0                                        36
+    LCD1                                        37
+
+    CSI                                         40
+
+    HDMI                                        43
+    DE_BE0                                      44
+    DE_BE1                                      45
+    DE_FE1                                      46
+    DE_FE1                                      47
+
+    MP                                          50
+
+    GPU                                         52
+
+    DEU0                                        55
+    DEU1                                        56
+    DRC0                                        57
+    DRC1                                        58
+
+  * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk")
+
+    CODEC                                       0
+
+    DIGITAL MIC                                 4
+    PIO                                         5
+
+    DAUDIO0                                     12
+    DAUDIO1                                     13
+
+  * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk")
+
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+    I2C3                                        3
+
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+    UART4                                       20
+    UART5                                       21
+
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
new file mode 100644
index 000000000000..357f4fdc02ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
@@ -0,0 +1,98 @@
+Gate clock outputs
+------------------
+
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+
+    DRAM                                        0
+
+  * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk")
+
+    USB0                                        0
+    EHCI0                                       1
+    OHCI0                                       2
+    EHCI1                                       3
+    OHCI1                                       4
+    SS                                          5
+    DMA                                         6
+    BIST                                        7
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+    MMC3                                        11
+    MS                                          12
+    NAND                                        13
+    SDRAM                                       14
+
+    ACE                                         16
+    EMAC                                        17
+    TS                                          18
+
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+    SPI3                                        23
+
+    SATA                                        25
+
+    HSTIMER                                     28
+
+    VE                                          32
+    TVD                                         33
+    TVE0                                        34
+    TVE1                                        35
+    LCD0                                        36
+    LCD1                                        37
+
+    CSI0                                        40
+    CSI1                                        41
+
+    HDMI1                                       42
+    HDMI0                                       43
+    DE_BE0                                      44
+    DE_BE1                                      45
+    DE_FE1                                      46
+    DE_FE1                                      47
+
+    GMAC                                        49
+    MP                                          50
+
+    MALI400                                     52
+
+  * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk")
+
+    CODEC                                       0
+    SPDIF                                       1
+    AC97                                        2
+    IIS0                                        3
+    IIS1                                        4
+    PIO                                         5
+    IR0                                         6
+    IR1                                         7
+    IIS2                                        8
+
+    KEYPAD                                      10
+
+  * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk")
+
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+    I2C3                                        3
+    CAN                                         4
+    SCR                                         5
+    PS20                                        6
+    PS21                                        7
+
+    I2C4                                        15
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+    UART4                                       20
+    UART5                                       21
+    UART6                                       22
+    UART7                                       23
+
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec6.txt b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
new file mode 100644
index 000000000000..c0a20cd972e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-sec6.txt
@@ -0,0 +1,157 @@
+SEC 6 is as Freescale's Cryptographic Accelerator and Assurance Module (CAAM).
+Currently Freescale powerpc chip C29X is embeded with SEC 6.
+SEC 6 device tree binding include:
+   -SEC 6 Node
+   -Job Ring Node
+   -Full Example
+
+=====================================================================
+SEC 6 Node
+
+Description
+
+    Node defines the base address of the SEC 6 block.
+    This block specifies the address range of all global
+    configuration registers for the SEC 6 block.
+    For example, In C293, we could see three SEC 6 node.
+
+PROPERTIES
+
+   - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0".
+
+   - fsl,sec-era
+      Usage: optional
+      Value type: <u32>
+      Definition: A standard property. Define the 'ERA' of the SEC
+          device.
+
+   - #address-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing physical addresses in child nodes.
+
+   - #size-cells
+       Usage: required
+       Value type: <u32>
+       Definition: A standard property.  Defines the number of cells
+           for representing the size of physical addresses in
+           child nodes.
+
+   - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: A standard property.  Specifies the physical
+          address and length of the SEC 6 configuration registers.
+
+   - ranges
+       Usage: required
+       Value type: <prop-encoded-array>
+       Definition: A standard property.  Specifies the physical address
+           range of the SEC 6.0 register space (-SNVS not included).  A
+           triplet that includes the child address, parent address, &
+           length.
+
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+
+EXAMPLE
+        crypto@a0000 {
+                compatible = "fsl,sec-v6.0";
+                fsl,sec-era = <6>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0xa0000 0x20000>;
+                ranges = <0 0xa0000 0x20000>;
+        };
+
+=====================================================================
+Job Ring (JR) Node
+
+    Child of the crypto node defines data processing interface to SEC 6
+    across the peripheral bus for purposes of processing
+    cryptographic descriptors. The specified address
+    range can be made visible to one (or more) cores.
+    The interrupt defined for this node is controlled within
+    the address range of this node.
+
+  - compatible
+      Usage: required
+      Value type: <string>
+      Definition: Must include "fsl,sec-v6.0-job-ring".
+
+  - reg
+      Usage: required
+      Value type: <prop-encoded-array>
+      Definition: Specifies a two JR parameters:  an offset from
+           the parent physical address and the length the JR registers.
+
+   - interrupts
+      Usage: required
+      Value type: <prop_encoded-array>
+      Definition:  Specifies the interrupts generated by this
+           device.  The value of the interrupts property
+           consists of one interrupt specifier. The format
+           of the specifier is defined by the binding document
+           describing the node's interrupt parent.
+
+EXAMPLE
+        jr@1000 {
+                compatible = "fsl,sec-v6.0-job-ring";
+                reg = <0x1000 0x1000>;
+                interrupts = <49 2 0 0>;
+        };
+
+===================================================================
+Full Example
+
+Since some chips may contain more than one SEC, the dtsi contains
+only the node contents, not the node itself.  A chip using the SEC
+should include the dtsi inside each SEC node.  Example:
+
+In qoriq-sec6.0.dtsi:
+
+        compatible = "fsl,sec-v6.0";
+        fsl,sec-era = <6>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        jr@1000 {
+                compatible = "fsl,sec-v6.0-job-ring",
+                             "fsl,sec-v5.2-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.4-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg        = <0x1000 0x1000>;
+        };
+
+        jr@2000 {
+                compatible = "fsl,sec-v6.0-job-ring",
+                             "fsl,sec-v5.2-job-ring",
+                             "fsl,sec-v5.0-job-ring",
+                             "fsl,sec-v4.4-job-ring",
+                             "fsl,sec-v4.0-job-ring";
+                reg        = <0x2000 0x1000>;
+        };
+
+In the C293 device tree, we add the include of public property:
+
+        crypto@a0000 {
+                /include/ "qoriq-sec6.0.dtsi"
+        }
+
+        crypto@a0000 {
+                reg = <0xa0000 0x20000>;
+                ranges = <0 0xa0000 0x20000>;
+
+                jr@1000 {
+                        interrupts = <49 2 0 0>;
+                };
+
+                jr@2000 {
+                        interrupts = <50 2 0 0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
index c280a0e6f42d..e1f343c7a34b 100644
--- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
@@ -18,14 +18,14 @@ dma0: dma@ffffec00 {
 
 DMA clients connected to the Atmel DMA controller must use the format
 described in the dma.txt file, using a three-cell specifier for each channel:
-a phandle plus two interger cells.
+a phandle plus two integer cells.
 The three cells in order are:
 
 1. A phandle pointing to the DMA controller.
 2. The memory interface (16 most significant bits), the peripheral interface
 (16 less significant bits).
 3. Parameters for the at91 DMA configuration register which are device
-dependant:
+dependent:
   - bit 7-0: peripheral identifier for the hardware handshaking interface. The
   identifier can be different for tx and rx.
   - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
index 2717ecb47db9..7bd8847d6394 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
@@ -34,7 +34,7 @@ Clients have to specify the DMA requests with phandles in a list.
 Required properties:
 - dmas: List of one or more DMA request specifiers. One DMA request specifier
     consists of a phandle to the DMA controller followed by the integer
-    specifiying the request line.
+    specifying the request line.
 - dma-names: List of string identifiers for the DMA requests. For the correct
     names, have a look at the specific client driver.
 
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index 68cee4f5539f..4fa814d38321 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -1,7 +1,12 @@
 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
 
 Required properties:
-- compatible : Should be "fsl,<chip>-sdma"
+- compatible : Should be "fsl,imx31-sdma", "fsl,imx31-to1-sdma",
+  "fsl,imx31-to2-sdma", "fsl,imx35-sdma", "fsl,imx35-to1-sdma",
+  "fsl,imx35-to2-sdma", "fsl,imx51-sdma", "fsl,imx53-sdma" or
+  "fsl,imx6q-sdma". The -to variants should be preferred since they
+  allow to determnine the correct ROM script addresses needed for
+  the driver to work without additional firmware.
 - reg : Should contain SDMA registers location and length
 - interrupts : Should contain SDMA interrupt
 - #dma-cells : Must be <3>.
diff --git a/Documentation/devicetree/bindings/dma/k3dma.txt b/Documentation/devicetree/bindings/dma/k3dma.txt
new file mode 100644
index 000000000000..23f8d712c3ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/k3dma.txt
@@ -0,0 +1,46 @@
+* Hisilicon K3 DMA controller
+
+See dma.txt first
+
+Required properties:
+- compatible: Should be "hisilicon,k3-dma-1.0"
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain one interrupt shared by all channel
+- #dma-cells: see dma.txt, should be 1, para number
+- dma-channels: physical channels supported
+- dma-requests: virtual channels supported, each virtual channel
+                have specific request line
+- clocks: clock required
+
+Example:
+
+Controller:
+                dma0: dma@fcd02000 {
+                        compatible = "hisilicon,k3-dma-1.0";
+                        reg = <0xfcd02000 0x1000>;
+                        #dma-cells = <1>;
+                        dma-channels = <16>;
+                        dma-requests = <27>;
+                        interrupts = <0 12 4>;
+                        clocks = <&pclk>;
+                        status = "disable";
+                };
+
+Client:
+Use specific request line passing from dmax
+For example, i2c0 read channel request line is 18, while write channel use 19
+
+                i2c0: i2c@fcb08000 {
+                        compatible = "snps,designware-i2c";
+                        dmas =  <&dma0 18          /* read channel */
+                                 &dma0 19>;        /* write channel */
+                        dma-names = "rx", "tx";
+                };
+
+                i2c1: i2c@fcb09000 {
+                        compatible = "snps,designware-i2c";
+                        dmas =  <&dma0 20          /* read channel */
+                                 &dma0 21>;        /* write channel */
+                        dma-names = "rx", "tx";
+                };
+
diff --git a/Documentation/devicetree/bindings/dma/shdma.txt b/Documentation/devicetree/bindings/dma/shdma.txt
index c15994aa1939..2a3f3b8946b9 100644
--- a/Documentation/devicetree/bindings/dma/shdma.txt
+++ b/Documentation/devicetree/bindings/dma/shdma.txt
@@ -22,42 +22,51 @@ Optional properties (currently unused):
 * DMA controller
 
 Required properties:
-- compatible:   should be "renesas,shdma"
+- compatible:   should be of the form "renesas,shdma-<soc>", where <soc> should
+                be replaced with the desired SoC model, e.g.
+                "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
 
 Example:
-        dmac: dma-mux0 {
+        dmac: dma-multiplexer@0 {
                 compatible = "renesas,shdma-mux";
                 #dma-cells = <1>;
-                dma-channels = <6>;
+                dma-channels = <20>;
                 dma-requests = <256>;
-                reg = <0 0>;    /* Needed for AUXDATA */
-                #address-cells = <1>;
-                #size-cells = <1>;
+                #address-cells = <2>;
+                #size-cells = <2>;
                 ranges;
 
-                dma0: shdma@fe008020 {
-                        compatible = "renesas,shdma";
-                        reg = <0xfe008020 0x270>,
-                                <0xfe009000 0xc>;
+                dma0: dma-controller@e6700020 {
+                        compatible = "renesas,shdma-r8a73a4";
+                        reg = <0 0xe6700020 0 0x89e0>;
                         interrupt-parent = <&gic>;
-                        interrupts = <0 34 4
-                                        0 28 4
-                                        0 29 4
-                                        0 30 4
-                                        0 31 4
-                                        0 32 4
-                                        0 33 4>;
+                        interrupts = <0 220 4
+                                        0 200 4
+                                        0 201 4
+                                        0 202 4
+                                        0 203 4
+                                        0 204 4
+                                        0 205 4
+                                        0 206 4
+                                        0 207 4
+                                        0 208 4
+                                        0 209 4
+                                        0 210 4
+                                        0 211 4
+                                        0 212 4
+                                        0 213 4
+                                        0 214 4
+                                        0 215 4
+                                        0 216 4
+                                        0 217 4
+                                        0 218 4
+                                        0 219 4>;
                         interrupt-names = "error",
                                         "ch0", "ch1", "ch2", "ch3",
-                                        "ch4", "ch5";
-                };
-
-                dma1: shdma@fe018020 {
-                        ...
-                };
-
-                dma2: shdma@fe028020 {
-                        ...
+                                        "ch4", "ch5", "ch6", "ch7",
+                                        "ch8", "ch9", "ch10", "ch11",
+                                        "ch12", "ch13", "ch14", "ch15",
+                                        "ch16", "ch17", "ch18", "ch19";
                 };
         };
 
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
index bea5b73a7390..a8c21c256baa 100644
--- a/Documentation/devicetree/bindings/dma/ste-dma40.txt
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -37,14 +37,14 @@ Each dmas request consists of 4 cells:
   1. A phandle pointing to the DMA controller
   2. Device Type
   3. The DMA request line number (only when 'use fixed channel' is set)
-  4. A 32bit mask specifying; mode, direction and endianess [NB: This list will grow]
+  4. A 32bit mask specifying; mode, direction and endianness [NB: This list will grow]
         0x00000001: Mode:
                 Logical channel when unset
                 Physical channel when set
         0x00000002: Direction:
                 Memory to Device when unset
                 Device to Memory when set
-        0x00000004: Endianess:
+        0x00000004: Endianness:
                 Little endian when unset
                 Big endian when set
         0x00000008: Use fixed channel:
diff --git a/Documentation/devicetree/bindings/extcon/extcon-twl.txt b/Documentation/devicetree/bindings/extcon/extcon-palmas.txt
index 58f531ab4df3..7dab6a8f4a0e 100644
--- a/Documentation/devicetree/bindings/extcon/extcon-twl.txt
+++ b/Documentation/devicetree/bindings/extcon/extcon-palmas.txt
@@ -1,15 +1,15 @@
-EXTCON FOR TWL CHIPS
+EXTCON FOR PALMAS/TWL CHIPS
 
 PALMAS USB COMPARATOR
 Required Properties:
  - compatible : Should be "ti,palmas-usb" or "ti,twl6035-usb"
- - vbus-supply : phandle to the regulator device tree node.
 
 Optional Properties:
  - ti,wakeup : To enable the wakeup comparator in probe
+ - ti,enable-id-detection: Perform ID detection.
+ - ti,enable-vbus-detection: Perform VBUS detection.
 
 palmas-usb {
        compatible = "ti,twl6035-usb", "ti,palmas-usb";
-       vbus-supply = <&smps10_reg>;
        ti,wakeup;
 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
index 629d0ef17308..daa30174bcc1 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
@@ -3,10 +3,17 @@ Microchip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
 
 Required properties:
 - compatible : Should be
-    - "mcp,mcp23s08" for  8 GPIO SPI version
-    - "mcp,mcp23s17" for 16 GPIO SPI version
-    - "mcp,mcp23008" for  8 GPIO I2C version or
-    - "mcp,mcp23017" for 16 GPIO I2C version of the chip
+    - "mcp,mcp23s08" (DEPRECATED) for  8 GPIO SPI version
+    - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
+    - "mcp,mcp23008" (DEPRECATED) for  8 GPIO I2C version or
+    - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
+
+    - "microchip,mcp23s08" for  8 GPIO SPI version
+    - "microchip,mcp23s17" for 16 GPIO SPI version
+    - "microchip,mcp23008" for  8 GPIO I2C version or
+    - "microchip,mcp23017" for 16 GPIO I2C version of the chip
+    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
+    removed.
 - #gpio-cells : Should be two.
   - first cell is the pin number
   - second cell is used to specify flags. Flags are currently unused.
@@ -15,10 +22,11 @@ Required properties:
         SPI uses this to specify the chipselect line which the chip is
         connected to. The driver and the SPI variant of the chip support
         multiple chips on the same chipselect. Have a look at
-        mcp,spi-present-mask below.
+        microchip,spi-present-mask below.
 
 Required device specific properties (only for SPI chips):
-- mcp,spi-present-mask : This is a present flag, that makes only sense for SPI
+- mcp,spi-present-mask (DEPRECATED)
+- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI
         chips - as the name suggests. Multiple SPI chips can share the same
         SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a
         chip connected with the corresponding spi address set. For example if
@@ -26,11 +34,13 @@ Required device specific properties (only for SPI chips):
         which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not
         possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at
         least one bit to 1 for SPI chips.
+    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
+    removed.
 - spi-max-frequency = The maximum frequency this chip is able to handle
 
 Example I2C:
 gpiom1: gpio@20 {
-        compatible = "mcp,mcp23017";
+        compatible = "microchip,mcp23017";
         gpio-controller;
         #gpio-cells = <2>;
         reg = <0x20>;
@@ -38,7 +48,7 @@ gpiom1: gpio@20 {
 
 Example SPI:
 gpiom1: gpio@0 {
-        compatible = "mcp,mcp23s17";
+        compatible = "microchip,mcp23s17";
         gpio-controller;
         #gpio-cells = <2>;
         spi-present-mask = <0x01>;
diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
new file mode 100644
index 000000000000..08b5b52a3ae0
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
@@ -0,0 +1,27 @@
+Palmas GPIO controller bindings
+
+Required properties:
+- compatible:
+  - "ti,palams-gpio" for palma series of the GPIO controller
+  - "ti,tps80036-gpio" for Palma series device TPS80036.
+  - "ti,tps65913-gpio" for palma series device TPS65913.
+  - "ti,tps65914-gpio" for palma series device TPS65914.
+- #gpio-cells : Should be two.
+  - first cell is the gpio pin number
+  - second cell is used to specify the gpio polarity:
+      0 = active high
+      1 = active low
+- gpio-controller : Marks the device node as a GPIO controller.
+
+Note: This gpio node will be sub node of palmas node.
+
+Example:
+        palmas: tps65913@58 {
+                :::::::::::
+                palmas_gpio: palmas_gpio {
+                        compatible = "ti,palmas-gpio";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                :::::::::::
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt
new file mode 100644
index 000000000000..1fd98ffa8cb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-tz1090-pdc.txt
@@ -0,0 +1,45 @@
+ImgTec TZ1090 PDC GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "img,tz1090-pdc-gpio".
+
+- reg: Physical base address of the controller and length of memory mapped
+  region. This starts at and cover the SOC_GPIO_CONTROL registers.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+
+- #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
+  nodes should have the following values.
+     <[phandle of the gpio controller node]
+      [PDC gpio number]
+      [gpio flags]>
+
+  Values for gpio specifier:
+  - GPIO number: a value in the range 0 to 6.
+  - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
+    Only the following flags are supported:
+      GPIO_ACTIVE_HIGH
+      GPIO_ACTIVE_LOW
+
+Optional properties:
+- gpio-ranges: Mapping to pin controller pins (as described in
+  Documentation/devicetree/bindings/gpio/gpio.txt)
+
+- interrupts: Individual syswake interrupts (other GPIOs cannot interrupt)
+
+
+Example:
+
+        pdc_gpios: gpio-controller@02006500 {
+                gpio-controller;
+                #gpio-cells = <2>;
+
+                compatible = "img,tz1090-pdc-gpio";
+                reg = <0x02006500 0x100>;
+
+                interrupt-parent = <&pdc>;
+                interrupts =    <8  IRQ_TYPE_NONE>,     /* Syswake 0 */
+                                <9  IRQ_TYPE_NONE>,     /* Syswake 1 */
+                                <10 IRQ_TYPE_NONE>;     /* Syswake 2 */
+                gpio-ranges = <&pdc_pinctrl 0 0 7>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt b/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt
new file mode 100644
index 000000000000..174cdf309170
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-tz1090.txt
@@ -0,0 +1,88 @@
+ImgTec TZ1090 GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "img,tz1090-gpio".
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- #address-cells: Should be 1 (for bank subnodes)
+
+- #size-cells: Should be 0 (for bank subnodes)
+
+- Each bank of GPIOs should have a subnode to represent it.
+
+  Bank subnode required properties:
+  - reg: Index of bank in the range 0 to 2.
+
+  - gpio-controller: Specifies that the node is a gpio controller.
+
+  - #gpio-cells: Should be 2. The syntax of the gpio specifier used by client
+    nodes should have the following values.
+       <[phandle of the gpio controller node]
+        [gpio number within the gpio bank]
+        [gpio flags]>
+
+    Values for gpio specifier:
+    - GPIO number: a value in the range 0 to 29.
+    - GPIO flags: bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
+      Only the following flags are supported:
+        GPIO_ACTIVE_HIGH
+        GPIO_ACTIVE_LOW
+
+  Bank subnode optional properties:
+  - gpio-ranges: Mapping to pin controller pins (as described in
+    Documentation/devicetree/bindings/gpio/gpio.txt)
+
+  - interrupts: Interrupt for the entire bank
+
+  - interrupt-controller: Specifies that the node is an interrupt controller
+
+  - #interrupt-cells: Should be 2. The syntax of the interrupt specifier used by
+    client nodes should have the following values.
+       <[phandle of the interurupt controller]
+        [gpio number within the gpio bank]
+        [irq flags]>
+
+    Values for irq specifier:
+    - GPIO number: a value in the range 0 to 29
+    - IRQ flags: value to describe edge and level triggering, as defined in
+      <dt-bindings/interrupt-controller/irq.h>. Only the following flags are
+      supported:
+        IRQ_TYPE_EDGE_RISING
+        IRQ_TYPE_EDGE_FALLING
+        IRQ_TYPE_EDGE_BOTH
+        IRQ_TYPE_LEVEL_HIGH
+        IRQ_TYPE_LEVEL_LOW
+
+
+
+Example:
+
+        gpios: gpio-controller@02005800 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "img,tz1090-gpio";
+                reg = <0x02005800 0x90>;
+
+                /* bank 0 with an interrupt */
+                gpios0: bank@0 {
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        reg = <0>;
+                        interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 0 30>;
+                        interrupt-controller;
+                };
+
+                /* bank 2 without interrupt */
+                gpios2: bank@2 {
+                        #gpio-cells = <2>;
+                        reg = <2>;
+                        gpio-controller;
+                        gpio-ranges = <&pinctrl 0 60 30>;
+                };
+        };
+
+
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index d933af370697..6cec6ff20d2e 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -75,23 +75,36 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
                 gpio-controller;
         };
 
-2.1) gpio-controller and pinctrl subsystem
-------------------------------------------
+2.1) gpio- and pin-controller interaction
+-----------------------------------------
 
-gpio-controller on a SOC might be tightly coupled with the pinctrl
-subsystem, in the sense that the pins can be used by other functions
-together with optional gpio feature.
+Some or all of the GPIOs provided by a GPIO controller may be routed to pins
+on the package via a pin controller. This allows muxing those pins between
+GPIO and other functions.
 
-While the pin allocation is totally managed by the pin ctrl subsystem,
-gpio (under gpiolib) is still maintained by gpio drivers. It may happen
-that different pin ranges in a SoC is managed by different gpio drivers.
+It is useful to represent which GPIOs correspond to which pins on which pin
+controllers. The gpio-ranges property described below represents this, and
+contains information structures as follows:
 
-This makes it logical to let gpio drivers announce their pin ranges to
-the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
-request the corresponding pin before any gpio usage.
+        gpio-range-list ::= <single-gpio-range> [gpio-range-list]
+        single-gpio-range ::=
+                        <pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
+        gpio-phandle : phandle to pin controller node.
+        gpio-base : Base GPIO ID in the GPIO controller
+        pinctrl-base : Base pinctrl pin ID in the pin controller
+        count : The number of GPIOs/pins in this range
 
-For this, the gpio controller can use a pinctrl phandle and pins to
-announce the pinrange to the pin ctrl subsystem. For example,
+The "pin controller node" mentioned above must conform to the bindings
+described in ../pinctrl/pinctrl-bindings.txt.
+
+Previous versions of this binding required all pin controller nodes that
+were referenced by any gpio-ranges property to contain a property named
+#gpio-range-cells with value <3>. This requirement is now deprecated.
+However, that property may still exist in older device trees for
+compatibility reasons, and would still be required even in new device
+trees that need to be compatible with older software.
+
+Example:
 
         qe_pio_e: gpio-controller@1460 {
                 #gpio-cells = <2>;
@@ -99,16 +112,8 @@ announce the pinrange to the pin ctrl subsystem. For example,
                 reg = <0x1460 0x18>;
                 gpio-controller;
                 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
+        };
 
-    }
-
-where,
-   &pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
-
-   Next values specify the base pin and number of pins for the range
-   handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
-   pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
-   pinctrl2 with gpio offset 10 is handled by this gpio controller.
-
-The pinctrl node must have "#gpio-range-cells" property to show number of
-arguments to pass with phandle from gpio controllers node.
+Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
+pinctrl1's pins 20..29, and GPIOs 10..19 routed to pin controller pinctrl2's
+pins 50..59.
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 9b3f1d4a88d6..66416261e14d 100644
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -10,8 +10,9 @@ Required properties:
   There're three gpio interrupts in arch-pxa, and they're gpio0,
   gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
   gpio_mux.
-- interrupt-name : Should be the name of irq resource. Each interrupt
-  binds its interrupt-name.
+- interrupt-names : Should be the names of irq resources. Each interrupt
+  uses its own interrupt name, so there should be as many interrupt names
+  as referenced interrups.
 - interrupt-controller : Identifies the node as an interrupt controller.
 - #interrupt-cells: Specifies the number of cells needed to encode an
   interrupt source.
@@ -24,7 +25,7 @@ Example:
                 compatible = "marvell,mmp-gpio";
                 reg = <0xd4019000 0x1000>;
                 interrupts = <49>;
-                interrupt-name = "gpio_mux";
+                interrupt-names = "gpio_mux";
                 gpio-controller;
                 #gpio-cells = <1>;
                 interrupt-controller;
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
index cb3dc7bcd8e6..8655df9440d5 100644
--- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -23,6 +23,10 @@ Required Properties:
 Please refer to gpio.txt in this directory for details of gpio-ranges property
 and the common GPIO bindings used by client devices.
 
+The GPIO controller also acts as an interrupt controller. It uses the default
+two cells specifier as described in Documentation/devicetree/bindings/
+interrupt-controller/interrupts.txt.
+
 Example: R8A7779 (R-Car H1) GPIO controller nodes
 
         gpio0: gpio@ffc40000 {
@@ -33,6 +37,8 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 0 32>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
         };
         ...
         gpio6: gpio@ffc46000 {
@@ -43,4 +49,6 @@ Example: R8A7779 (R-Car H1) GPIO controller nodes
                 #gpio-cells = <2>;
                 gpio-controller;
                 gpio-ranges = <&pfc 0 192 9>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
         };
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 3f454ffc654a..c4f358dafdaa 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -11,8 +11,11 @@ Required properties:
 
   - interrupts : G2D interrupt number to the CPU.
   - clocks : from common clock binding: handle to G2D clocks.
-  - clock-names : from common clock binding: must contain "sclk_fimg2d" and
-                  "fimg2d", corresponding to entries in the clocks property.
+  - clock-names : names of clocks listed in clocks property, in the same
+                  order, depending on SoC type:
+                  - for S5PV210 and Exynos4 based SoCs: "fimg2d" and
+                    "sclk_fimg2d"
+                  - for Exynos5250 SoC: "fimg2d".
 
 Example:
         g2d@12800000 {
diff --git a/Documentation/devicetree/bindings/gpu/samsung-rotator.txt b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt
new file mode 100644
index 000000000000..82cd1ed0be93
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/samsung-rotator.txt
@@ -0,0 +1,27 @@
+* Samsung Image Rotator
+
+Required properties:
+  - compatible : value should be one of the following:
+        (a) "samsung,exynos4210-rotator" for Rotator IP in Exynos4210
+        (b) "samsung,exynos4212-rotator" for Rotator IP in Exynos4212/4412
+        (c) "samsung,exynos5250-rotator" for Rotator IP in Exynos5250
+
+  - reg : Physical base address of the IP registers and length of memory
+          mapped region.
+
+  - interrupts : Interrupt specifier for rotator interrupt, according to format
+                 specific to interrupt parent.
+
+  - clocks : Clock specifier for rotator clock, according to generic clock
+             bindings. (See Documentation/devicetree/bindings/clock/exynos*.txt)
+
+  - clock-names : Names of clocks. For exynos rotator, it should be "rotator".
+
+Example:
+        rotator@12810000 {
+                compatible = "samsung,exynos4210-rotator";
+                reg = <0x12810000 0x1000>;
+                interrupts = <0 83 0>;
+                clocks = <&clock 278>;
+                clock-names = "rotator";
+        };
diff --git a/Documentation/devicetree/bindings/hid/hid-over-i2c.txt b/Documentation/devicetree/bindings/hid/hid-over-i2c.txt
new file mode 100644
index 000000000000..488edcb264c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/hid/hid-over-i2c.txt
@@ -0,0 +1,28 @@
+* HID over I2C Device-Tree bindings
+
+HID over I2C provides support for various Human Interface Devices over the
+I2C bus. These devices can be for example touchpads, keyboards, touch screens
+or sensors.
+
+The specification has been written by Microsoft and is currently available here:
+http://msdn.microsoft.com/en-us/library/windows/hardware/hh852380.aspx
+
+If this binding is used, the kernel module i2c-hid will handle the communication
+with the device and the generic hid core layer will handle the protocol.
+
+Required properties:
+- compatible: must be "hid-over-i2c"
+- reg: i2c slave address
+- hid-descr-addr: HID descriptor address
+- interrupt-parent: the phandle for the interrupt controller
+- interrupts: interrupt line
+
+Example:
+
+        i2c-hid-dev@2c {
+                compatible = "hid-over-i2c";
+                reg = <0x2c>;
+                hid-descr-addr = <0x0020>;
+                interrupt-parent = <&gpx3>;
+                interrupts = <3 2>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
index 3614242e7732..4a8513e44740 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
@@ -1,7 +1,10 @@
 * Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
 
 Required properties:
-- compatible : Should be "fsl,<chip>-i2c"
+- compatible :
+  - "fsl,imx1-i2c" for I2C compatible with the one integrated on i.MX1 SoC
+  - "fsl,imx21-i2c" for I2C compatible with the one integrated on i.MX21 SoC
+  - "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC
 - reg : Should contain I2C/HS-I2C registers location and length
 - interrupts : Should contain I2C/HS-I2C interrupt
 
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
index 6113f9275f42..82e8f6f17179 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
@@ -5,6 +5,7 @@ Required properties :
 
  - reg             : Offset and length of the register set for the device
  - compatible      : Should be "marvell,mv64xxx-i2c" or "allwinner,sun4i-i2c"
+                     or "marvell,mv78230-i2c"
  - interrupts      : The interrupt number
 
 Optional properties :
@@ -20,3 +21,12 @@ Examples:
                 interrupts = <29>;
                 clock-frequency = <100000>;
         };
+
+For the Armada XP:
+
+        i2c@11000 {
+                compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
+                reg = <0x11000 0x100>;
+                interrupts = <29>;
+                clock-frequency = <100000>;
+        };
diff --git a/Documentation/devicetree/bindings/iio/accel/bma180.txt b/Documentation/devicetree/bindings/iio/accel/bma180.txt
new file mode 100644
index 000000000000..c5933573e0f6
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/accel/bma180.txt
@@ -0,0 +1,24 @@
+* Bosch BMA180 triaxial acceleration sensor
+
+http://omapworld.com/BMA180_111_1002839.pdf
+
+Required properties:
+
+  - compatible : should be "bosch,bma180"
+  - reg : the I2C address of the sensor
+
+Optional properties:
+
+  - interrupt-parent : should be the phandle for the interrupt controller
+
+  - interrupts : interrupt mapping for GPIO IRQ, it should by configured with
+                flags IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING
+
+Example:
+
+bma180@40 {
+        compatible = "bosch,bma180";
+        reg = <0x40>;
+        interrupt-parent = <&gpio6>;
+        interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>;
+};
diff --git a/Documentation/devicetree/bindings/iio/adc/nuvoton-nau7802.txt b/Documentation/devicetree/bindings/iio/adc/nuvoton-nau7802.txt
new file mode 100644
index 000000000000..e9582e6fe350
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/nuvoton-nau7802.txt
@@ -0,0 +1,18 @@
+* Nuvoton NAU7802 Analog to Digital Converter (ADC)
+
+Required properties:
+  - compatible: Should be "nuvoton,nau7802"
+  - reg: Should contain the ADC I2C address
+
+Optional properties:
+  - nuvoton,vldo: Internal reference voltage in millivolts to be
+    configured valid values are between 2400 mV and 4500 mV.
+  - interrupts: IRQ line for the ADC. If not used the driver will use
+    polling.
+
+Example:
+adc2: nau7802@2a {
+        compatible = "nuvoton,nau7802";
+        reg = <0x2a>;
+        nuvoton,vldo = <3000>;
+};
diff --git a/Documentation/devicetree/bindings/iio/light/apds9300.txt b/Documentation/devicetree/bindings/iio/light/apds9300.txt
new file mode 100644
index 000000000000..d6f66c73ddbf
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/light/apds9300.txt
@@ -0,0 +1,22 @@
+* Avago APDS9300 ambient light sensor
+
+http://www.avagotech.com/docs/AV02-1077EN
+
+Required properties:
+
+  - compatible : should be "avago,apds9300"
+  - reg : the I2C address of the sensor
+
+Optional properties:
+
+  - interrupt-parent : should be the phandle for the interrupt controller
+  - interrupts : interrupt mapping for GPIO IRQ
+
+Example:
+
+apds9300@39 {
+        compatible = "avago,apds9300";
+        reg = <0x39>;
+        interrupt-parent = <&gpio2>;
+        interrupts = <29 8>;
+};
diff --git a/Documentation/devicetree/bindings/input/input-reset.txt b/Documentation/devicetree/bindings/input/input-reset.txt
new file mode 100644
index 000000000000..2bb2626fdb78
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/input-reset.txt
@@ -0,0 +1,33 @@
+Input: sysrq reset sequence
+
+A simple binding to represent a set of keys as described in
+include/uapi/linux/input.h. This is to communicate a sequence of keys to the
+sysrq driver. Upon holding the keys for a specified amount of time (if
+specified) the system is sync'ed and reset.
+
+Key sequences are global to the system but all the keys in a set must be coming
+from the same input device.
+
+The /chosen node should contain a 'linux,sysrq-reset-seq' child node to define
+a set of keys.
+
+Required property:
+sysrq-reset-seq: array of Linux keycodes, one keycode per cell.
+
+Optional property:
+timeout-ms: duration keys must be pressed together in milliseconds before
+generating a sysrq. If omitted the system is rebooted immediately when a valid
+sequence has been recognized.
+
+Example:
+
+ chosen {
+                linux,sysrq-reset-seq {
+                        keyset = <0x03
+                                  0x04
+                                  0x0a>;
+                        timeout-ms = <3000>;
+                };
+         };
+
+Would represent KEY_2, KEY_3 and KEY_9.
diff --git a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
index df70318a617f..49fa14ed155c 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/egalax-ts.txt
@@ -6,7 +6,7 @@ Required properties:
 - interrupt-parent: the phandle for the interrupt controller
 - interrupts: touch controller interrupt
 - wakeup-gpios: the gpio pin to be used for waking up the controller
-  as well as uased as irq pin
+  and also used as irq pin
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/media/i2c/adv7343.txt b/Documentation/devicetree/bindings/media/i2c/adv7343.txt
new file mode 100644
index 000000000000..5653bc2428b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/adv7343.txt
@@ -0,0 +1,48 @@
+* Analog Devices adv7343 video encoder
+
+The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
+package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
+(CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
+definition (SD), enhanced definition (ED), or high definition (HD) video
+formats.
+
+Required Properties :
+- compatible: Must be "adi,adv7343"
+
+Optional Properties :
+- adi,power-mode-sleep-mode: on enable the current consumption is reduced to
+                              micro ampere level. All DACs and the internal PLL
+                              circuit are disabled.
+- adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
+                           internal PLL 1 circuit to be powered down and the
+                           oversampling to be switched off.
+- ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
+                              0 = OFF and 1 = ON, Default value when this
+                              property is not specified is <0 0 0 0 0 0>.
+- ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
+                                 and 1 = ON, Default value when this property is
+                                 not specified is <0 0>.
+
+Example:
+
+i2c0@1c22000 {
+        ...
+        ...
+
+        adv7343@2a {
+                compatible = "adi,adv7343";
+                reg = <0x2a>;
+
+                port {
+                        adv7343_1: endpoint {
+                                        adi,power-mode-sleep-mode;
+                                        adi,power-mode-pll-ctrl;
+                                        /* Use DAC1..3, DAC6 */
+                                        adi,dac-enable = <1 1 1 0 0 1>;
+                                        /* Use SD DAC output 1 */
+                                        adi,sd-dac-enable = <1 0>;
+                        };
+                };
+        };
+        ...
+};
diff --git a/Documentation/devicetree/bindings/media/i2c/ths8200.txt b/Documentation/devicetree/bindings/media/i2c/ths8200.txt
new file mode 100644
index 000000000000..285f6ae7dfa9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ths8200.txt
@@ -0,0 +1,19 @@
+* Texas Instruments THS8200 video encoder
+
+The ths8200 device is a digital to analog converter used in DVD players, video
+recorders, set-top boxes.
+
+Required Properties :
+- compatible : value must be "ti,ths8200"
+
+Example:
+
+        i2c0@1c22000 {
+                ...
+                ...
+                ths8200@5c {
+                        compatible = "ti,ths8200";
+                        reg = <0x5c>;
+                };
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/media/i2c/tvp7002.txt b/Documentation/devicetree/bindings/media/i2c/tvp7002.txt
new file mode 100644
index 000000000000..5f28b5d9abcc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/tvp7002.txt
@@ -0,0 +1,53 @@
+* Texas Instruments TV7002 video decoder
+
+The TVP7002 device supports digitizing of video and graphics signal in RGB and
+YPbPr color space.
+
+Required Properties :
+- compatible : Must be "ti,tvp7002"
+
+Optional Properties:
+- hsync-active: HSYNC Polarity configuration for the bus. Default value when
+  this property is not specified is <0>.
+
+- vsync-active: VSYNC Polarity configuration for the bus. Default value when
+  this property is not specified is <0>.
+
+- pclk-sample: Clock polarity of the bus. Default value when this property is
+  not specified is <0>.
+
+- sync-on-green-active: Active state of Sync-on-green signal property of the
+  endpoint.
+  0 = Normal Operation (Active Low, Default)
+  1 = Inverted operation
+
+- field-even-active: Active-high Field ID output polarity control of the bus.
+  Under normal operation, the field ID output is set to logic 1 for an odd field
+  (field 1) and set to logic 0 for an even field (field 0).
+  0 = Normal Operation (Active Low, Default)
+  1 = FID output polarity inverted
+
+For further reading of port node refer Documentation/devicetree/bindings/media/
+video-interfaces.txt.
+
+Example:
+
+        i2c0@1c22000 {
+                ...
+                ...
+                tvp7002@5c {
+                        compatible = "ti,tvp7002";
+                        reg = <0x5c>;
+
+                        port {
+                                tvp7002_1: endpoint {
+                                        hsync-active = <1>;
+                                        vsync-active = <1>;
+                                        pclk-sample = <0>;
+                                        sync-on-green-active = <1>;
+                                        field-even-active = <0>;
+                                };
+                        };
+                };
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index df37b0230c75..f4181680831b 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -10,14 +10,15 @@ Required properties:
   - compatible : value should be either one among the following
         (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
         (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+        (b) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC
 
   - reg : Physical base address of the IP registers and length of memory
           mapped region.
 
   - interrupts : MFC interrupt number to the CPU.
-  - clocks : from common clock binding: handle to mfc clocks.
-  - clock-names : from common clock binding: must contain "sclk_mfc" and "mfc",
-                  corresponding to entries in the clocks property.
+  - clocks : from common clock binding: handle to mfc clock.
+  - clock-names : from common clock binding: must contain "mfc",
+                  corresponding to entry in the clocks property.
 
   - samsung,mfc-r : Base address of the first memory bank used by MFC
                     for DMA contiguous memory allocation and its size.
@@ -37,8 +38,8 @@ mfc: codec@13400000 {
         reg = <0x13400000 0x10000>;
         interrupts = <0 94 0>;
         samsung,power-domain = <&pd_mfc>;
-        clocks = <&clock 170>, <&clock 273>;
-        clock-names = "sclk_mfc", "mfc";
+        clocks = <&clock 273>;
+        clock-names = "mfc";
 };
 
 Board specific DT entry:
diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt
index e022d2dc4962..ce719f89dd1c 100644
--- a/Documentation/devicetree/bindings/media/video-interfaces.txt
+++ b/Documentation/devicetree/bindings/media/video-interfaces.txt
@@ -88,6 +88,8 @@ Optional endpoint properties
 - field-even-active: field signal level during the even field data transmission.
 - pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
   signal.
+- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for
+  LOW/HIGH respectively.
 - data-lanes: an array of physical data lane indexes. Position of an entry
   determines the logical lane number, while the value of an entry indicates
   physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
diff --git a/Documentation/devicetree/bindings/memory.txt b/Documentation/devicetree/bindings/memory.txt
new file mode 100644
index 000000000000..eb2469365593
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory.txt
@@ -0,0 +1,168 @@
+*** Memory binding ***
+
+The /memory node provides basic information about the address and size
+of the physical memory. This node is usually filled or updated by the
+bootloader, depending on the actual memory configuration of the given
+hardware.
+
+The memory layout is described by the following node:
+
+/ {
+        #address-cells = <(n)>;
+        #size-cells = <(m)>;
+        memory {
+                device_type = "memory";
+                reg =  <(baseaddr1) (size1)
+                        (baseaddr2) (size2)
+                        ...
+                        (baseaddrN) (sizeN)>;
+        };
+        ...
+};
+
+A memory node follows the typical device tree rules for "reg" property:
+n:              number of cells used to store base address value
+m:              number of cells used to store size value
+baseaddrX:      defines a base address of the defined memory bank
+sizeX:          the size of the defined memory bank
+
+
+More than one memory bank can be defined.
+
+
+*** Reserved memory regions ***
+
+In /memory/reserved-memory node one can create child nodes describing
+particular reserved (excluded from normal use) memory regions. Such
+memory regions are usually designed for the special usage by various
+device drivers. A good example are contiguous memory allocations or
+memory sharing with other operating system on the same hardware board.
+Those special memory regions might depend on the board configuration and
+devices used on the target system.
+
+Parameters for each memory region can be encoded into the device tree
+with the following convention:
+
+[(label):] (name) {
+        compatible = "linux,contiguous-memory-region", "reserved-memory-region";
+        reg = <(address) (size)>;
+        (linux,default-contiguous-region);
+};
+
+compatible:     one or more of:
+        - "linux,contiguous-memory-region" - enables binding of this
+          region to Contiguous Memory Allocator (special region for
+          contiguous memory allocations, shared with movable system
+          memory, Linux kernel-specific).
+        - "reserved-memory-region" - compatibility is defined, given
+          region is assigned for exclusive usage for by the respective
+          devices.
+
+reg:    standard property defining the base address and size of
+        the memory region
+
+linux,default-contiguous-region: property indicating that the region
+        is the default region for all contiguous memory
+        allocations, Linux specific (optional)
+
+It is optional to specify the base address, so if one wants to use
+autoconfiguration of the base address, '0' can be specified as a base
+address in the 'reg' property.
+
+The /memory/reserved-memory node must contain the same #address-cells
+and #size-cells value as the root node.
+
+
+*** Device node's properties ***
+
+Once regions in the /memory/reserved-memory node have been defined, they
+may be referenced by other device nodes. Bindings that wish to reference
+memory regions should explicitly document their use of the following
+property:
+
+memory-region = <&phandle_to_defined_region>;
+
+This property indicates that the device driver should use the memory
+region pointed by the given phandle.
+
+
+*** Example ***
+
+This example defines a memory consisting of 4 memory banks. 3 contiguous
+regions are defined for Linux kernel, one default of all device drivers
+(named contig_mem, placed at 0x72000000, 64MiB), one dedicated to the
+framebuffer device (labelled display_mem, placed at 0x78000000, 8MiB)
+and one for multimedia processing (labelled multimedia_mem, placed at
+0x77000000, 64MiB). 'display_mem' region is then assigned to fb@12300000
+device for DMA memory allocations (Linux kernel drivers will use CMA is
+available or dma-exclusive usage otherwise). 'multimedia_mem' is
+assigned to scaler@12500000 and codec@12600000 devices for contiguous
+memory allocations when CMA driver is enabled.
+
+The reason for creating a separate region for framebuffer device is to
+match the framebuffer base address to the one configured by bootloader,
+so once Linux kernel drivers starts no glitches on the displayed boot
+logo appears. Scaller and codec drivers should share the memory
+allocations.
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        /* ... */
+
+        memory {
+                reg =  <0x40000000 0x10000000
+                        0x50000000 0x10000000
+                        0x60000000 0x10000000
+                        0x70000000 0x10000000>;
+
+                reserved-memory {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        /*
+                         * global autoconfigured region for contiguous allocations
+                         * (used only with Contiguous Memory Allocator)
+                         */
+                        contig_region@0 {
+                                compatible = "linux,contiguous-memory-region";
+                                reg = <0x0 0x4000000>;
+                                linux,default-contiguous-region;
+                        };
+
+                        /*
+                         * special region for framebuffer
+                         */
+                        display_region: region@78000000 {
+                                compatible = "linux,contiguous-memory-region", "reserved-memory-region";
+                                reg = <0x78000000 0x800000>;
+                        };
+
+                        /*
+                         * special region for multimedia processing devices
+                         */
+                        multimedia_region: region@77000000 {
+                                compatible = "linux,contiguous-memory-region";
+                                reg = <0x77000000 0x4000000>;
+                        };
+                };
+        };
+
+        /* ... */
+
+        fb0: fb@12300000 {
+                status = "okay";
+                memory-region = <&display_region>;
+        };
+
+        scaler: scaler@12500000 {
+                status = "okay";
+                memory-region = <&multimedia_region>;
+        };
+
+        codec: codec@12600000 {
+                status = "okay";
+                memory-region = <&multimedia_region>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/metag/pdc-intc.txt b/Documentation/devicetree/bindings/metag/pdc-intc.txt
new file mode 100644
index 000000000000..a69118550344
--- /dev/null
+++ b/Documentation/devicetree/bindings/metag/pdc-intc.txt
@@ -0,0 +1,105 @@
+* ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
+
+This binding specifies what properties must be available in the device tree
+representation of a PDC IRQ controller. This has a number of input interrupt
+lines which can wake the system, and are passed on through output interrupt
+lines.
+
+Required properties:
+
+    - compatible: Specifies the compatibility list for the interrupt controller.
+      The type shall be <string> and the value shall include "img,pdc-intc".
+
+    - reg: Specifies the base PDC physical address(s) and size(s) of the
+      addressable register space. The type shall be <prop-encoded-array>.
+
+    - interrupt-controller: The presence of this property identifies the node
+      as an interrupt controller. No property value shall be defined.
+
+    - #interrupt-cells: Specifies the number of cells needed to encode an
+      interrupt source. The type shall be a <u32> and the value shall be 2.
+
+    - num-perips: Number of waking peripherals.
+
+    - num-syswakes: Number of SysWake inputs.
+
+    - interrupts: List of interrupt specifiers. The first specifier shall be the
+      shared SysWake interrupt, and remaining specifies shall be PDC peripheral
+      interrupts in order.
+
+* Interrupt Specifier Definition
+
+  Interrupt specifiers consists of 2 cells encoded as follows:
+
+    - <1st-cell>: The interrupt-number that identifies the interrupt source.
+                    0-7:  Peripheral interrupts
+                    8-15: SysWake interrupts
+
+    - <2nd-cell>: The level-sense information, encoded using the Linux interrupt
+                  flags as follows (only 4 valid for peripheral interrupts):
+                    0 = none (decided by software)
+                    1 = low-to-high edge triggered
+                    2 = high-to-low edge triggered
+                    3 = both edge triggered
+                    4 = active-high level-sensitive (required for perip irqs)
+                    8 = active-low level-sensitive
+
+* Examples
+
+Example 1:
+
+        /*
+         * TZ1090 PDC block
+         */
+        pdc: pdc@0x02006000 {
+                // This is an interrupt controller node.
+                interrupt-controller;
+
+                // Three cells to encode interrupt sources.
+                #interrupt-cells = <2>;
+
+                // Offset address of 0x02006000 and size of 0x1000.
+                reg = <0x02006000 0x1000>;
+
+                // Compatible with Meta hardware trigger block.
+                compatible = "img,pdc-intc";
+
+                // Three peripherals are connected.
+                num-perips = <3>;
+
+                // Four SysWakes are connected.
+                num-syswakes = <4>;
+
+                interrupts = <18 4 /* level */>, /* Syswakes */
+                             <30 4 /* level */>, /* Peripheral 0 (RTC) */
+                             <29 4 /* level */>, /* Peripheral 1 (IR) */
+                             <31 4 /* level */>; /* Peripheral 2 (WDT) */
+        };
+
+Example 2:
+
+        /*
+         * An SoC peripheral that is wired through the PDC.
+         */
+        rtc0 {
+                // The interrupt controller that this device is wired to.
+                interrupt-parent = <&pdc>;
+
+                // Interrupt source Peripheral 0
+                interrupts = <0   /* Peripheral 0 (RTC) */
+                              4>  /* IRQ_TYPE_LEVEL_HIGH */
+        };
+
+Example 3:
+
+        /*
+         * An interrupt generating device that is wired to a SysWake pin.
+         */
+        touchscreen0 {
+                // The interrupt controller that this device is wired to.
+                interrupt-parent = <&pdc>;
+
+                // Interrupt source SysWake 0 that is active-low level-sensitive
+                interrupts = <8 /* SysWake0 */
+                              8 /* IRQ_TYPE_LEVEL_LOW */>;
+        };
diff --git a/Documentation/devicetree/bindings/mfd/cros-ec.txt b/Documentation/devicetree/bindings/mfd/cros-ec.txt
index e0e59c58a1f9..5f229c5f6da9 100644
--- a/Documentation/devicetree/bindings/mfd/cros-ec.txt
+++ b/Documentation/devicetree/bindings/mfd/cros-ec.txt
@@ -4,7 +4,7 @@ Google's ChromeOS EC is a Cortex-M device which talks to the AP and
 implements various function such as keyboard and battery charging.
 
 The EC can be connect through various means (I2C, SPI, LPC) and the
-compatible string used depends on the inteface. Each connection method has
+compatible string used depends on the interface. Each connection method has
 its own driver which connects to the top level interface-agnostic EC driver.
 Other Linux driver (such as cros-ec-keyb for the matrix keyboard) connect to
 the top-level driver.
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
index 892537d1a48f..e5f0f8303461 100644
--- a/Documentation/devicetree/bindings/mfd/palmas.txt
+++ b/Documentation/devicetree/bindings/mfd/palmas.txt
@@ -5,6 +5,7 @@ twl6035 (palmas)
 twl6037 (palmas)
 tps65913 (palmas)
 tps65914 (palmas)
+tps659038
 
 Required properties:
 - compatible : Should be from the list
@@ -14,6 +15,7 @@ Required properties:
   ti,tps65913
   ti,tps65914
   ti,tps80036
+  ti,tps659038
 and also the generic series names
   ti,palmas
 - interrupt-controller : palmas has its own internal IRQs
diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt
new file mode 100644
index 000000000000..c9332c626021
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
@@ -0,0 +1,109 @@
+
+* Samsung S2MPS11 Voltage and Current Regulator
+
+The Samsung S2MP211 is a multi-function device which includes voltage and
+current regulators, RTC, charger controller and other sub-blocks. It is
+interfaced to the host controller using a I2C interface. Each sub-block is
+addressed by the host system using different I2C slave address.
+
+Required properties:
+- compatible: Should be "samsung,s2mps11-pmic".
+- reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
+
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from s2mps11 are delivered to.
+- interrupts: Interrupt specifiers for interrupt sources.
+
+Optional nodes:
+- clocks: s2mps11 provides three(AP/CP/BT) buffered 32.768 KHz outputs, so to
+  register these as clocks with common clock framework instantiate a sub-node
+  named "clocks". It uses the common clock binding documented in :
+  [Documentation/devicetree/bindings/clock/clock-bindings.txt]
+  - #clock-cells: should be 1.
+
+  - The following is the list of clocks generated by the controller. Each clock
+    is assigned an identifier and client nodes use this identifier to specify
+    the clock which they consume.
+    Clock               ID
+    ----------------------
+    32KhzAP             0
+    32KhzCP             1
+    32KhzBT             2
+
+- regulators: The regulators of s2mps11 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+
+        regulator_name {
+                [standard regulator constraints....];
+        };
+
+ regulator-ramp-delay for BUCKs = [6250/12500/25000(default)/50000] uV/us
+
+ BUCK[2/3/4/6] supports disabling ramp delay on hardware, so explictly
+ regulator-ramp-delay = <0> can be used for them to disable ramp delay.
+ In absence of regulator-ramp-delay property, default ramp delay will be used.
+
+NOTE: Some BUCKs share the ramp rate setting i.e. same ramp value will be set
+for a particular group of BUCKs. So provide same regulator-ramp-delay<value>.
+Grouping of BUCKs sharing ramp rate setting is as follow : BUCK[1, 6],
+BUCK[3, 4], and BUCK[7, 8, 10]
+
+The regulator constraints inside the regulator nodes use the standard regulator
+bindings which are documented elsewhere.
+
+The following are the names of the regulators that the s2mps11 pmic block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of s2mps11.
+
+        - LDOn
+                  - valid values for n are 1 to 28
+                  - Example: LDO0, LD01, LDO28
+        - BUCKn
+                  - valid values for n are 1 to 9.
+                  - Example: BUCK1, BUCK2, BUCK9
+
+Example:
+
+        s2mps11_pmic@66 {
+                compatible = "samsung,s2mps11-pmic";
+                reg = <0x66>;
+
+                s2m_osc: clocks{
+                        #clock-cells = 1;
+                        clock-output-names = "xx", "yy", "zz";
+                };
+
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VDD_ABB_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VDD_ALIVE_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
+
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <50000>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/misc/smc.txt b/Documentation/devicetree/bindings/misc/smc.txt
index 02b428136177..6c9f176f3571 100644
--- a/Documentation/devicetree/bindings/misc/smc.txt
+++ b/Documentation/devicetree/bindings/misc/smc.txt
@@ -4,11 +4,12 @@ This binding defines the location of the bounce buffer
 used for non-secure to secure communications.
 
 Required properties:
-- compatible : "bcm,kona-smc"
+- compatible : "brcm,kona-smc"
+- DEPRECATED: compatible : "bcm,kona-smc"
 - reg : Location and size of bounce buffer
 
 Example:
         smc@0x3404c000 {
-                compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
+                compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
                 reg = <0x3404c000 0x400>; //1 KiB in SRAM
         };
diff --git a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
index bd9be0b5bc20..b7943f3f9995 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt
@@ -19,6 +19,9 @@ Optional properties:
     "bus-width = <1>" property.
   - sdhci,auto-cmd12: specifies that a controller can only handle auto
     CMD12.
+  - voltage-ranges : two cells are required, first cell specifies minimum
+    slot voltage (mV), second cell specifies maximum slot voltage (mV).
+    Several ranges could be specified.
 
 Example:
 
@@ -29,4 +32,5 @@ sdhci@2e000 {
         interrupt-parent = <&ipic>;
         /* Filled in by U-Boot */
         clock-frequency = <0>;
+        voltage-ranges = <3300 3300>;
 };
diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/kona-sdhci.txt
index 094ae010f2fb..789fb07a426d 100644
--- a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/kona-sdhci.txt
@@ -4,12 +4,13 @@ This file documents differences between the core properties in mmc.txt
 and the properties present in the bcm281xx SDHCI
 
 Required properties:
-- compatible : Should be "bcm,kona-sdhci"
+- compatible : Should be "brcm,kona-sdhci"
+- DEPRECATED: compatible : Should be "bcm,kona-sdhci"
 
 Example:
 
 sdio2: sdio@0x3f1a0000 {
-        compatible = "bcm,kona-sdhci";
+        compatible = "brcm,kona-sdhci";
         reg = <0x3f1a0000 0x10000>;
         interrupts = <0x0 74 0x4>;
 };
diff --git a/Documentation/devicetree/bindings/mtd/atmel-nand.txt b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
index d555421ea49f..c4728839d0c1 100644
--- a/Documentation/devicetree/bindings/mtd/atmel-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/atmel-nand.txt
@@ -15,6 +15,7 @@ Required properties:
   optional gpio and may be set to 0 if not present.
 
 Optional properties:
+- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
 - nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
   Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
   "soft_bch".
@@ -29,6 +30,14 @@ Optional properties:
   sector size 1024.
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- Nand Flash Controller(NFC) is a slave driver under Atmel nand flash
+  - Required properties:
+    - compatible : "atmel,sama5d3-nfc".
+    - reg : should specify the address and size used for NFC command registers,
+            NFC registers and NFC Sram. NFC Sram address and size can be absent
+            if don't want to use it.
+  - Optional properties:
+    - atmel,write-by-sram: boolean to enable NFC write by sram.
 
 Examples:
 nand0: nand@40000000,0 {
@@ -77,3 +86,22 @@ nand0: nand@40000000 {
                 ...
         };
 };
+
+/* for NFC supported chips */
+nand0: nand@40000000 {
+        compatible = "atmel,at91rm9200-nand";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        ...
+        nfc@70000000 {
+                compatible = "atmel,sama5d3-nfc";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <
+                        0x70000000 0x10000000   /* NFC Command Registers */
+                        0xffffc000 0x00000070   /* NFC HSMC regs */
+                        0x00200000 0x00100000   /* NFC SRAM banks */
+                >;
+        };
+};
diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
index 2240ac09f6ba..ec42935f3908 100644
--- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt
@@ -1,4 +1,5 @@
-* FSMC NAND
+ST Microelectronics Flexible Static Memory Controller (FSMC)
+NAND Interface
 
 Required properties:
 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
@@ -9,6 +10,26 @@ Optional properties:
 - bank-width : Width (in bytes) of the device.  If not present, the width
   defaults to 1 byte
 - nand-skip-bbtscan: Indicates the the BBT scanning should be skipped
+- timings: array of 6 bytes for NAND timings. The meanings of these bytes
+  are:
+  byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
+                 are valid. Zero means one clockcycle, 15 means 16 clock
+                 cycles.
+  byte 1 TAR   : ALE to RE delay, 4 bits are valid. Same format as TCLR.
+  byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
+                 kept in Hi-Z (tristate) after the start of a write access.
+                 Only valid for write transactions. Zero means zero cycles,
+                 255 means 255 cycles.
+  byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
+                 when writing) after the command deassertation. Zero means
+                 one cycle, 255 means 256 cycles.
+  byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
+                 NAND flash in response to SMWAITn. Zero means 1 cycle,
+                 255 means 256 cycles.
+  byte 5 TSET  : number of HCLK clock cycles to assert the address before the
+                 command is asserted. Zero means one cycle, 255 means 256
+                 cycles.
+- bank: default NAND bank to use (0-3 are valid, 0 is the default).
 
 Example:
 
@@ -24,6 +45,8 @@ Example:
 
                 bank-width = <1>;
                 nand-skip-bbtscan;
+                timings = /bits/ 8 <0 0 0 2 3 0>;
+                bank = <1>;
 
                 partition@0 {
                         ...
diff --git a/Documentation/devicetree/bindings/mtd/partition.txt b/Documentation/devicetree/bindings/mtd/partition.txt
index 9315ac96b49b..8e5557da1955 100644
--- a/Documentation/devicetree/bindings/mtd/partition.txt
+++ b/Documentation/devicetree/bindings/mtd/partition.txt
@@ -4,6 +4,7 @@ Partitions can be represented by sub-nodes of an mtd device. This can be used
 on platforms which have strong conventions about which portions of a flash are
 used for what purposes, but which don't use an on-flash partition table such
 as RedBoot.
+NOTE: if the sub-node has a compatible string, then it is not a partition.
 
 #address-cells & #size-cells must both be present in the mtd device. There are
 two valid values for both:
diff --git a/Documentation/devicetree/bindings/net/can/atmel-can.txt b/Documentation/devicetree/bindings/net/can/atmel-can.txt
index 72cf0c5daff4..14e52a0d86ec 100644
--- a/Documentation/devicetree/bindings/net/can/atmel-can.txt
+++ b/Documentation/devicetree/bindings/net/can/atmel-can.txt
@@ -8,7 +8,7 @@ Required properties:
 Example:
 
         can0: can@f000c000 {
-                compatbile = "atmel,at91sam9x5-can";
+                compatible = "atmel,at91sam9x5-can";
                 reg = <0xf000c000 0x300>;
                 interrupts = <40 4 5>
         };
diff --git a/Documentation/devicetree/bindings/net/can/sja1000.txt b/Documentation/devicetree/bindings/net/can/sja1000.txt
index c2dbcec0ee31..f2105a47ec87 100644
--- a/Documentation/devicetree/bindings/net/can/sja1000.txt
+++ b/Documentation/devicetree/bindings/net/can/sja1000.txt
@@ -37,7 +37,7 @@ Optional properties:
         If not specified or if the specified value is 0, the CLKOUT pin
         will be disabled.
 
-- nxp,no-comparator-bypass : Allows to disable the CAN input comperator.
+- nxp,no-comparator-bypass : Allows to disable the CAN input comparator.
 
 For further information, please have a look to the SJA1000 data sheet.
 
diff --git a/Documentation/devicetree/bindings/net/micrel-ksz9021.txt b/Documentation/devicetree/bindings/net/micrel-ksz9021.txt
new file mode 100644
index 000000000000..997a63f1aea1
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/micrel-ksz9021.txt
@@ -0,0 +1,49 @@
+Micrel KSZ9021 Gigabit Ethernet PHY
+
+Some boards require special tuning values, particularly when it comes to
+clock delays.  You can specify clock delay values by adding
+micrel-specific properties to an Ethernet OF device node.
+
+All skew control options are specified in picoseconds.  The minimum
+value is 0, and the maximum value is 3000.
+
+Optional properties:
+ - rxc-skew-ps : Skew control of RXC pad
+ - rxdv-skew-ps : Skew control of RX CTL pad
+ - txc-skew-ps : Skew control of TXC pad
+ - txen-skew-ps : Skew control of TX_CTL pad
+ - rxd0-skew-ps : Skew control of RX data 0 pad
+ - rxd1-skew-ps : Skew control of RX data 1 pad
+ - rxd2-skew-ps : Skew control of RX data 2 pad
+ - rxd3-skew-ps : Skew control of RX data 3 pad
+ - txd0-skew-ps : Skew control of TX data 0 pad
+ - txd1-skew-ps : Skew control of TX data 1 pad
+ - txd2-skew-ps : Skew control of TX data 2 pad
+ - txd3-skew-ps : Skew control of TX data 3 pad
+
+Examples:
+
+        /* Attach to an Ethernet device with autodetected PHY */
+        &enet {
+                rxc-skew-ps = <3000>;
+                rxdv-skew-ps = <0>;
+                txc-skew-ps = <3000>;
+                txen-skew-ps = <0>;
+                status = "okay";
+        };
+
+        /* Attach to an explicitly-specified PHY */
+        mdio {
+                phy0: ethernet-phy@0 {
+                        rxc-skew-ps = <3000>;
+                        rxdv-skew-ps = <0>;
+                        txc-skew-ps = <3000>;
+                        txen-skew-ps = <0>;
+                        reg = <0>;
+                };
+        };
+        ethernet@70000 {
+                status = "okay";
+                phy = <&phy0>;
+                phy-mode = "rgmii-id";
+        };
diff --git a/Documentation/devicetree/bindings/net/moxa,moxart-mac.txt b/Documentation/devicetree/bindings/net/moxa,moxart-mac.txt
new file mode 100644
index 000000000000..583418b2c127
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/moxa,moxart-mac.txt
@@ -0,0 +1,21 @@
+MOXA ART Ethernet Controller
+
+Required properties:
+
+- compatible : Must be "moxa,moxart-mac"
+- reg : Should contain register location and length
+- interrupts : Should contain the mac interrupt number
+
+Example:
+
+        mac0: mac@90900000 {
+                compatible = "moxa,moxart-mac";
+                reg =   <0x90900000 0x100>;
+                interrupts = <25 0>;
+        };
+
+        mac1: mac@92000000 {
+                compatible = "moxa,moxart-mac";
+                reg =   <0x92000000 0x100>;
+                interrupts = <27 0>;
+        };
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
index 261c563b5f06..eba0e5e59ebe 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -22,6 +22,11 @@ Required properties:
 - snps,pbl              Programmable Burst Length
 - snps,fixed-burst      Program the DMA to use the fixed burst mode
 - snps,mixed-burst      Program the DMA to use the mixed burst mode
+- snps,force_thresh_dma_mode    Force DMA to use the threshold mode for
+                                both tx and rx
+- snps,force_sf_dma_mode        Force DMA to use the Store and Forward
+                                mode for both tx and rx. This flag is
+                                ignored if force_thresh_dma_mode is set.
 
 Optional properties:
 - mac-address: 6 bytes, mac address
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index e2371f5cdebe..eabcb4b5db6e 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -18,6 +18,7 @@ Required properties:
 - interrupt-map-mask and interrupt-map: standard PCI properties
         to define the mapping of the PCIe interface to interrupt
         numbers.
+- num-lanes: number of lanes to use
 - reset-gpio: gpio pin number of power good signal
 
 Example:
@@ -41,6 +42,7 @@ SoC specific DT Entry:
                 #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0x0 0 &gic 53>;
+                num-lanes = <4>;
         };
 
         pcie@2a0000 {
@@ -60,6 +62,7 @@ SoC specific DT Entry:
                 #interrupt-cells = <1>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0x0 0 &gic 56>;
+                num-lanes = <4>;
         };
 
 Board specific DT Entry:
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
index f8d405897a94..9556e2fedf6d 100644
--- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -1,6 +1,7 @@
 * Marvell EBU PCIe interfaces
 
 Mandatory properties:
+
 - compatible: one of the following values:
     marvell,armada-370-pcie
     marvell,armada-xp-pcie
@@ -10,11 +11,49 @@ Mandatory properties:
 - #interrupt-cells, set to <1>
 - bus-range: PCI bus numbers covered
 - device_type, set to "pci"
-- ranges: ranges for the PCI memory and I/O regions, as well as the
-  MMIO registers to control the PCIe interfaces.
+- ranges: ranges describing the MMIO registers to control the PCIe
+  interfaces, and ranges describing the MBus windows needed to access
+  the memory and I/O regions of each PCIe interface.
+
+The ranges describing the MMIO registers have the following layout:
+
+    0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
+
+where:
+
+  * r is a 32-bits value that gives the offset of the MMIO
+  registers of this PCIe interface, from the base of the internal
+  registers.
+
+  * s is a 32-bits value that give the size of this MMIO
+  registers area. This range entry translates the '0x82000000 0 r' PCI
+  address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
+  of the internal register window (as identified by MBUS_ID(0xf0,
+  0x01)).
+
+The ranges describing the MBus windows have the following layout:
+
+    0x8t000000 s 0     MBUS_ID(w, a) 0 1 0
+
+where:
+
+   * t is the type of the MBus window (as defined by the standard PCI DT
+   bindings), 1 for I/O and 2 for memory.
 
-In addition, the Device Tree node must have sub-nodes describing each
+   * s is the PCI slot that corresponds to this PCIe interface
+
+   * w is the 'target ID' value for the MBus window
+
+   * a the 'attribute' value for the MBus window.
+
+Since the location and size of the different MBus windows is not fixed in
+hardware, and only determined in runtime, those ranges cover the full first
+4 GB of the physical address space, and do not translate into a valid CPU
+address.
+
+In addition, the device tree node must have sub-nodes describing each
 PCIe interface, having the following mandatory properties:
+
 - reg: used only for interrupt mapping, so only the first four bytes
   are used to refer to the correct bus number and device number.
 - assigned-addresses: reference to the MMIO registers used to control
@@ -26,7 +65,8 @@ PCIe interface, having the following mandatory properties:
 - #address-cells, set to <3>
 - #size-cells, set to <2>
 - #interrupt-cells, set to <1>
-- ranges, empty property.
+- ranges, translating the MBus windows ranges of the parent node into
+  standard PCI addresses.
 - interrupt-map-mask and interrupt-map, standard PCI properties to
   define the mapping of the PCIe interface to interrupt numbers.
 
@@ -47,27 +87,50 @@ pcie-controller {
 
         bus-range = <0x00 0xff>;
 
-        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
-                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
-                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
-                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
-                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
-                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
-                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
-                  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
-                  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
-                  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
-                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
-                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+        ranges =
+               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
+                0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
+                0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
+                0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
+                0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
+                0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
+                0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
+                0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
+                0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
+                0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
+                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
+                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
+                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
+                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
+                0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
+                0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
+                0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
+                0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
+
+                0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
+                0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
+                0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
+                0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
+                0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
+                0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
+                0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
+                0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
+
+                0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
+                0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
+
+                0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
+                0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 
         pcie@1,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
                 reg = <0x0800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 58>;
                 marvell,pcie-port = <0>;
@@ -78,12 +141,13 @@ pcie-controller {
 
         pcie@2,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+                assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
                 reg = <0x1000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+                          0x81000000 0 0 0x81000000 0x2 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 59>;
                 marvell,pcie-port = <0>;
@@ -94,12 +158,13 @@ pcie-controller {
 
         pcie@3,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+                assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
                 reg = <0x1800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+                          0x81000000 0 0 0x81000000 0x3 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 60>;
                 marvell,pcie-port = <0>;
@@ -110,12 +175,13 @@ pcie-controller {
 
         pcie@4,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+                assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
                 reg = <0x2000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+                          0x81000000 0 0 0x81000000 0x4 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 61>;
                 marvell,pcie-port = <0>;
@@ -126,12 +192,13 @@ pcie-controller {
 
         pcie@5,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
                 reg = <0x2800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
+                          0x81000000 0 0 0x81000000 0x5 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 62>;
                 marvell,pcie-port = <1>;
@@ -142,12 +209,13 @@ pcie-controller {
 
         pcie@6,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+                assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
                 reg = <0x3000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
+                          0x81000000 0 0 0x81000000 0x6 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 63>;
                 marvell,pcie-port = <1>;
@@ -158,12 +226,13 @@ pcie-controller {
 
         pcie@7,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+                assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
                 reg = <0x3800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
+                          0x81000000 0 0 0x81000000 0x7 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 64>;
                 marvell,pcie-port = <1>;
@@ -174,12 +243,13 @@ pcie-controller {
 
         pcie@8,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+                assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
                 reg = <0x4000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
+                          0x81000000 0 0 0x81000000 0x8 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 65>;
                 marvell,pcie-port = <1>;
@@ -187,14 +257,16 @@ pcie-controller {
                 clocks = <&gateclk 12>;
                 status = "disabled";
         };
+
         pcie@9,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+                assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
                 reg = <0x4800 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
+                          0x81000000 0 0 0x81000000 0x9 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 99>;
                 marvell,pcie-port = <2>;
@@ -205,12 +277,13 @@ pcie-controller {
 
         pcie@10,0 {
                 device_type = "pci";
-                assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+                assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
                 reg = <0x5000 0 0 0 0>;
                 #address-cells = <3>;
                 #size-cells = <2>;
                 #interrupt-cells = <1>;
-                ranges;
+                ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
+                          0x81000000 0 0 0x81000000 0xa 0 1 0>;
                 interrupt-map-mask = <0 0 0 0>;
                 interrupt-map = <0 0 0 0 &mpic 103>;
                 marvell,pcie-port = <3>;
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
new file mode 100644
index 000000000000..6b7510775c50
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -0,0 +1,163 @@
+NVIDIA Tegra PCIe controller
+
+Required properties:
+- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
+- device_type: Must be "pci"
+- reg: A list of physical base address and length for each set of controller
+  registers. Must contain an entry for each entry in the reg-names property.
+- reg-names: Must include the following entries:
+  "pads": PADS registers
+  "afi": AFI registers
+  "cs": configuration space region
+- interrupts: A list of interrupt outputs of the controller. Must contain an
+  entry for each entry in the interrupt-names property.
+- interrupt-names: Must include the following entries:
+  "intr": The Tegra interrupt that is asserted for controller interrupts
+  "msi": The Tegra interrupt that is asserted when an MSI is received
+- pex-clk-supply: Supply voltage for internal reference clock
+- vdd-supply: Power supply for controller (1.05V)
+- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
+- bus-range: Range of bus numbers associated with this controller
+- #address-cells: Address representation for root ports (must be 3)
+  - cell 0 specifies the bus and device numbers of the root port:
+    [23:16]: bus number
+    [15:11]: device number
+  - cell 1 denotes the upper 32 address bits and should be 0
+  - cell 2 contains the lower 32 address bits and is used to translate to the
+    CPU address space
+- #size-cells: Size representation for root ports (must be 2)
+- ranges: Describes the translation of addresses for root ports and standard
+  PCI regions. The entries must be 6 cells each, where the first three cells
+  correspond to the address as described for the #address-cells property
+  above, the fourth cell is the physical CPU address to translate to and the
+  fifth and six cells are as described for the #size-cells property above.
+  - The first two entries are expected to translate the addresses for the root
+    port registers, which are referenced by the assigned-addresses property of
+    the root port nodes (see below).
+  - The remaining entries setup the mapping for the standard I/O, memory and
+    prefetchable PCI regions. The first cell determines the type of region
+    that is setup:
+    - 0x81000000: I/O memory region
+    - 0x82000000: non-prefetchable memory region
+    - 0xc2000000: prefetchable memory region
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
+- clocks: List of clock inputs of the controller. Must contain an entry for
+  each entry in the clock-names property.
+- clock-names: Must include the following entries:
+  "pex": The Tegra clock of that name
+  "afi": The Tegra clock of that name
+  "pcie_xclk": The Tegra clock of that name
+  "pll_e": The Tegra clock of that name
+  "cml": The Tegra clock of that name (not required for Tegra20)
+
+Root ports are defined as subnodes of the PCIe controller node.
+
+Required properties:
+- device_type: Must be "pci"
+- assigned-addresses: Address and size of the port configuration registers
+- reg: PCI bus address of the root port
+- #address-cells: Must be 3
+- #size-cells: Must be 2
+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
+  property is sufficient.
+- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
+  are:
+  - Root port 0 uses 4 lanes, root port 1 is unused.
+  - Both root ports use 2 lanes.
+
+Example:
+
+SoC DTSI:
+
+        pcie-controller {
+                compatible = "nvidia,tegra20-pcie";
+                device_type = "pci";
+                reg = <0x80003000 0x00000800   /* PADS registers */
+                       0x80003800 0x00000200   /* AFI registers */
+                       0x90000000 0x10000000>; /* configuration space */
+                reg-names = "pads", "afi", "cs";
+                interrupts = <0 98 0x04   /* controller interrupt */
+                              0 99 0x04>; /* MSI interrupt */
+                interrupt-names = "intr", "msi";
+
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+
+                ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
+                          0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
+                          0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0xa0000000 0xa0000000 0 0x10000000   /* non-prefetchable memory */
+                          0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
+
+                clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
+                         <&tegra_car 118>;
+                clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+                status = "disabled";
+
+                pci@1,0 {
+                        device_type = "pci";
+                        assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
+                        reg = <0x000800 0 0 0 0>;
+                        status = "disabled";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges;
+
+                        nvidia,num-lanes = <2>;
+                };
+
+                pci@2,0 {
+                        device_type = "pci";
+                        assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
+                        reg = <0x001000 0 0 0 0>;
+                        status = "disabled";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        ranges;
+
+                        nvidia,num-lanes = <2>;
+                };
+        };
+
+
+Board DTS:
+
+        pcie-controller {
+                status = "okay";
+
+                vdd-supply = <&pci_vdd_reg>;
+                pex-clk-supply = <&pci_clk_reg>;
+
+                /* root port 00:01.0 */
+                pci@1,0 {
+                        status = "okay";
+
+                        /* bridge 01:00.0 (optional) */
+                        pci@0,0 {
+                                reg = <0x010000 0 0 0 0>;
+
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+
+                                device_type = "pci";
+
+                                /* endpoint 02:00.0 */
+                                pci@0,0 {
+                                        reg = <0x020000 0 0 0 0>;
+                                };
+                        };
+                };
+        };
+
+Note that devices on the PCI bus are dynamically discovered using PCI's bus
+enumeration and therefore don't need corresponding device nodes in DT. However
+if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
+device nodes need to be added in order to allow the bus' children to be
+instantiated at the proper location in the operating system's device tree (as
+illustrated by the optional nodes in the example above).
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
index 648d60eb9fd8..7ccae490ff6d 100644
--- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -37,7 +37,7 @@ Bank: 3 (A, B and C)
   0xffffffff 0x7fff3ccf  /* pioB */
   0xffffffff 0x007fffff  /* pioC */
 
-For each peripheral/bank we will descibe in a u32 if a pin can can be
+For each peripheral/bank we will descibe in a u32 if a pin can be
 configured in it by putting 1 to the pin bit (1 << pin)
 
 Let's take the pioA on peripheral B
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
index e204d009f16c..fb70856c5b51 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
@@ -80,6 +80,17 @@ Valid values for pin and group names are:
     dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
     gmh, owr, uda.
 
+Valid values for nvidia,functions are:
+
+  blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
+  displaya_alt, displayb, dtv, emc_dll, extperiph1, extperiph2,
+  extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr,
+  i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, nand, nand_alt, owr, pmi,
+  pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, rsvd2, rsvd3,
+  rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3,
+  spi4, spi5, spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi,
+  usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3
+
 Example:
 
         pinmux: pinmux {
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
index 683fde93c4fb..61e73cde9ae9 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
@@ -103,6 +103,17 @@ Valid values for pin and group names are:
     drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
     drive_uda.
 
+Valid values for nvidia,functions are:
+
+  ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5,
+  displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int,
+  hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
+  osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3,
+  pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck,
+  sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt,
+  spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
+  vi, vi_sensor_clk, xio
+
 Example:
 
         pinctrl@70000000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
index 6f426ed7009e..0e6354c11e6d 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
@@ -91,6 +91,18 @@ Valid values for pin and group names are:
     gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
     uart3, uda, vi1.
 
+Valid values for nvidia,functions are:
+
+  blink, cec, clk_12m_out, clk_32k_in, core_pwr_req, cpu_pwr_req, crt,
+  dap, ddr, dev3, displaya, displayb, dtv, extperiph1, extperiph2,
+  extperiph3, gmi, gmi_alt, hda, hdcp, hdmi, hsi, i2c1, i2c2, i2c3,
+  i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, invalid, kbc, mio, nand,
+  nand_alt, owr, pcie, pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2,
+  rsvd3, rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif, spi1,
+  spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test, trace, uarta,
+  uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
+  vi, vi_alt1, vi_alt2, vi_alt3
+
 Example:
 
         pinctrl@70000000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index aeb3c995cc04..1958ca9f9e5c 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -127,21 +127,20 @@ whether there is any interaction between the child and intermediate parent
 nodes, is again defined entirely by the binding for the individual pin
 controller device.
 
-== Using generic pinconfig options ==
+== Generic pin configuration node content ==
 
-Generic pinconfig parameters can be used by defining a separate node containing
-the applicable parameters (and optional values), like:
+Many data items that are represented in a pin configuration node are common
+and generic. Pin control bindings should use the properties defined below
+where they are applicable; not all of these properties are relevant or useful
+for all hardware or binding structures. Each individual binding document
+should state which of these generic properties, if any, are used, and the
+structure of the DT nodes that contain these properties.
 
-pcfg_pull_up: pcfg_pull_up {
-        bias-pull-up;
-        drive-strength = <20>;
-};
-
-This node should then be referenced in the appropriate pinctrl node as a phandle
-and parsed in the driver using the pinconf_generic_parse_dt_config function.
-
-Supported configuration parameters are:
+Supported generic properties are:
 
+pins                    - the list of pins that properties in the node
+                          apply to
+function                - the mux function to select
 bias-disable            - disable any pin bias
 bias-high-impedance     - high impedance mode ("third-state", "floating")
 bias-bus-hold           - latch weakly
@@ -160,7 +159,21 @@ low-power-disable	- disable low power mode
 output-low              - set the pin to output mode with low level
 output-high             - set the pin to output mode with high level
 
-Arguments for parameters:
+Some of the generic properties take arguments. For those that do, the
+arguments are described below.
+
+- pins takes a list of pin names or IDs as a required argument. The specific
+  binding for the hardware defines:
+  - Whether the entries are integers or strings, and their meaning.
+
+- function takes a list of function names/IDs as a required argument. The
+  specific binding for the hardware defines:
+  - Whether the entries are integers or strings, and their meaning.
+  - Whether only a single entry is allowed (which is applied to all entries
+    in the pins property), or whether there may alternatively be one entry per
+    entry in the pins property, in which case the list lengths must match, and
+    for each list index i, the function at list index i is applied to the pin
+    at list index i.
 
 - bias-pull-up, -down and -pin-default take as optional argument on hardware
   supporting it the pull strength in Ohm. bias-disable will disable the pull.
@@ -170,7 +183,5 @@ Arguments for parameters:
 - input-debounce takes the debounce time in usec as argument
   or 0 to disable debouncing
 
-All parameters not listed here, do not take an argument.
-
 More in-depth documentation on these parameters can be found in
 <include/linux/pinctrl/pinconfig-generic.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt
new file mode 100644
index 000000000000..734d9b04d533
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt
@@ -0,0 +1,96 @@
+Palmas Pincontrol bindings
+
+The pins of Palmas device can be set on different option and provides
+the configuration for Pull UP/DOWN, open drain etc.
+
+Required properties:
+- compatible: It must be one of following:
+  - "ti,palmas-pinctrl" for Palma series of the pincontrol.
+  - "ti,tps65913-pinctrl" for Palma series device TPS65913.
+  - "ti,tps80036-pinctrl" for Palma series device TPS80036.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+Palmas's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+list of pins. This configuration can include the mux function to select on
+those pin(s), and various pin configuration parameters, such as pull-up,
+open drain.
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+Optional properties:
+- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
+        Selection primary or secondary function associated to I2C2_SCL_SCE,
+        I2C2_SDA_SDO pin/pad for DVFS1 interface
+- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode.
+        Selection primary or secondary function associated to GPADC_START
+        and SYSEN2 pin/pad for DVFS2 interface
+
+This binding uses the following generic properties as defined in
+pinctrl-bindings.txt:
+
+Required: pins
+Options: function, bias-disable, bias-pull-up, bias-pull-down,
+         bias-pin-default, drive-open-drain.
+
+Note that many of these properties are only valid for certain specific pins.
+See the Palmas device datasheet for complete details regarding which pins
+support which functionality.
+
+Valid values for pin names are:
+        gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9,
+        gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood,
+        nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2,
+        int.
+
+Valid value of function names are:
+        gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det,
+        vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm,
+        simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start,
+        reset_in, nsleep, enable.
+
+There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these
+functions is selected then directly pins register will be written with 0, 1, 2
+or 3 respectively if it is valid for that pins or list of pins.
+
+Example:
+        palmas: tps65913 {
+                ....
+                pinctrl {
+                        compatible = "ti,tps65913-pinctrl";
+                        ti,palmas-enable-dvfs1;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&palmas_pins_state>;
+
+                        palmas_pins_state: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "id";
+                                        bias-pull-up;
+                                };
+
+                                vac {
+                                        pins = "vac";
+                                        function = "vacok";
+                                        bias-pull-down;
+                                };
+
+                                gpio5 {
+                                        pins = "gpio5";
+                                        function = "opt0";
+                                        drive-open-drain = <1>;
+                                };
+                        };
+                };
+                ....
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 36281e7a2a46..257677de3e6b 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -12,6 +12,7 @@ Required Properties:
   - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
   - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
   - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
+  - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
   - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
   - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
   - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
@@ -128,7 +129,7 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
      - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
        found on Samsung S3C64xx SoCs,
      - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
-       found on Samsung Exynos4210 SoC.
+       found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
    - interrupt-parent: phandle of the interrupt parent to which the external
      wakeup interrupts are forwarded to.
    - interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
index 9a2f3f420526..6b33b9f18e88 100644
--- a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
+++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
@@ -1,8 +1,8 @@
 ST Ericsson Nomadik pinmux controller
 
 Required properties:
-- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
-              "stericsson,nmk-pinctrl-stn8815"
+- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
+              "stericsson,stn8815-pinctrl"
 - reg: Should contain the register physical address and length of the PRCMU.
 
 Please refer to pinctrl-bindings.txt in this directory for details of the
@@ -68,7 +68,7 @@ Optional subnode-properties:
 Example board file extract:
 
         pinctrl@80157000 {
-                compatible = "stericsson,nmk-pinctrl";
+                compatible = "stericsson,db8500-pinctrl";
                 reg = <0x80157000 0x2000>;
 
                 pinctrl-names = "default";
diff --git a/Documentation/devicetree/bindings/power_supply/msm-poweroff.txt b/Documentation/devicetree/bindings/power_supply/msm-poweroff.txt
new file mode 100644
index 000000000000..ce44ad357565
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/msm-poweroff.txt
@@ -0,0 +1,17 @@
+MSM Restart Driver
+
+A power supply hold (ps-hold) bit is set to power the msm chipsets.
+Clearing that bit allows us to restart/poweroff. The difference
+between poweroff and restart is determined by unique power manager IC
+settings.
+
+Required Properties:
+-compatible: "qcom,pshold"
+-reg: Specifies the physical address of the ps-hold register
+
+Example:
+
+        restart@fc4ab000 {
+                compatible = "qcom,pshold";
+                reg = <0xfc4ab000 0x4>;
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5693877ab377..82dd5b65cf48 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -1,21 +1,20 @@
 * Freescale MSI interrupt controller
 
 Required properties:
-- compatible : compatible list, contains 2 entries,
-  first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
-  etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
-  the parent type.
+- compatible : compatible list, may contain one or two entries
+  The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
+  etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
+  "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
+  version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
+  provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
+  should be used. The first entry is optional; the second entry is
+  required.
 
 - reg : It may contain one or two regions. The first region should contain
   the address and the length of the shared message interrupt register set.
-  The second region should contain the address of aliased MSIIR register for
-  platforms that have such an alias.
-
-- msi-available-ranges: use <start count> style section to define which
-  msi interrupt can be used in the 256 msi interrupts. This property is
-  optional, without this, all the 256 MSI interrupts can be used.
-  Each available range must begin and end on a multiple of 32 (i.e.
-  no splitting an individual MSI register or the associated PIC interrupt).
+  The second region should contain the address of aliased MSIIR or MSIIR1
+  register for platforms that have such an alias, if using MSIIR1, the second
+  region must be added because different MSI group has different MSIIR1 offset.
 
 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
   and routed to the host interrupt controller. the interrupts should
@@ -28,6 +27,14 @@ Required properties:
   to MPIC.
 
 Optional properties:
+- msi-available-ranges: use <start count> style section to define which
+  msi interrupt can be used in the 256 msi interrupts. This property is
+  optional, without this, all the MSI interrupts can be used.
+  Each available range must begin and end on a multiple of 32 (i.e.
+  no splitting an individual MSI register or the associated PIC interrupt).
+  MPIC v4.3 does not support this property because the 32 interrupts of an
+  individual register are not continuous when using MSIIR1.
+
 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
   is used for MSI messaging.  The address of MSIIR in PCI address space is
   the MSI message address.
@@ -54,6 +61,28 @@ Example:
                 interrupt-parent = <&mpic>;
         };
 
+        msi@41600 {
+                compatible = "fsl,mpic-msi-v4.3";
+                reg = <0x41600 0x200 0x44148 4>;
+                interrupts = <
+                        0xe0 0 0 0
+                        0xe1 0 0 0
+                        0xe2 0 0 0
+                        0xe3 0 0 0
+                        0xe4 0 0 0
+                        0xe5 0 0 0
+                        0xe6 0 0 0
+                        0xe7 0 0 0
+                        0x100 0 0 0
+                        0x101 0 0 0
+                        0x102 0 0 0
+                        0x103 0 0 0
+                        0x104 0 0 0
+                        0x105 0 0 0
+                        0x106 0 0 0
+                        0x107 0 0 0>;
+        };
+
 The Freescale hypervisor and msi-address-64
 -------------------------------------------
 Normally, PCI devices have access to all of CCSR via an ATMU mapping.  The
diff --git a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
index de0eaed86651..8031148bcf85 100644
--- a/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/atmel-tcb-pwm.txt
@@ -2,11 +2,9 @@ Atmel TCB PWM controller
 
 Required properties:
 - compatible: should be "atmel,tcb-pwm"
-- #pwm-cells: Should be 3.  The first cell specifies the per-chip index
-  of the PWM to use, the second cell is the period in nanoseconds and
-  bit 0 in the third cell is used to encode the polarity of PWM output.
-  Set bit 0 of the third cell in PWM specifier to 1 for inverse polarity &
-  set to 0 for normal polarity.
+- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+  the cells format. The only third cell flag supported by this binding is
+  PWM_POLARITY_INVERTED.
 - tc-block: The Timer Counter block to use as a PWM chip.
 
 Example:
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
index 8522bfbccfd7..b50d7a6d9d7f 100644
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
@@ -3,8 +3,8 @@ Freescale i.MX PWM controller
 Required properties:
 - compatible: should be "fsl,<soc>-pwm"
 - reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+  the cells format.
 - interrupts: The interrupt for the pwm controller
 
 Example:
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
index 9e3f8f1d46a2..96cdde5f6208 100644
--- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt
@@ -3,8 +3,8 @@ Freescale MXS PWM controller
 Required properties:
 - compatible: should be "fsl,imx23-pwm"
 - reg: physical base address and length of the controller's registers
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+  the cells format.
 - fsl,pwm-number: the number of PWM devices
 
 Example:
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
index 01438ecd6628..c3fc57af8772 100644
--- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt
@@ -5,9 +5,8 @@ Required properties:
   - "nvidia,tegra20-pwm"
   - "nvidia,tegra30-pwm"
 - reg: physical base address and length of the controller's registers
-- #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The
-  first cell specifies the per-chip index of the PWM to use and the second
-  cell is the period in nanoseconds.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+  the cells format.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt b/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt
index 1e3dfe7a4894..f84ec9d291ea 100644
--- a/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/nxp,pca9685-pwm.txt
@@ -3,8 +3,8 @@ NXP PCA9685 16-channel 12-bit PWM LED controller
 
 Required properties:
   - compatible: "nxp,pca9685-pwm"
-  - #pwm-cells: should be 2. The first cell specifies the per-chip index
-    of the PWM to use and the second cell is the period in nanoseconds.
+  - #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
+    the cells format.
     The index 16 is the ALLCALL channel, that sets all PWM channels at the same
     time.
 
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
index ac67c687a327..d61fccd40bad 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
@@ -19,13 +19,19 @@ Required properties:
 - reg: base address and size of register area
 - interrupts: list of timer interrupts (one interrupt per timer, starting at
   timer 0)
-- #pwm-cells: number of cells used for PWM specifier - must be 3
-   the specifier format is as follows:
-     - phandle to PWM controller node
-     - index of PWM channel (from 0 to 4)
-     - PWM signal period in nanoseconds
-     - bitmask of optional PWM flags:
-        0x1 - invert PWM signal
+- clock-names: should contain all following required clock names:
+    - "timers" - PWM base clock used to generate PWM signals,
+  and any subset of following optional clock names:
+    - "pwm-tclk0" - first external PWM clock source,
+    - "pwm-tclk1" - second external PWM clock source.
+  Note that not all IP variants allow using all external clock sources.
+  Refer to SoC documentation to learn which clock source configurations
+  are available.
+- clocks: should contain clock specifiers of all clocks, which input names
+  have been specified in clock-names property, in same order.
+- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+  the cells format. The only third cell flag supported by this binding is
+  PWM_POLARITY_INVERTED.
 
 Optional properties:
 - samsung,pwm-outputs: list of PWM channels used as PWM outputs on particular
@@ -38,6 +44,8 @@ Example:
                 reg = <0x7f006000 0x1000>;
                 interrupt-parent = <&vic0>;
                 interrupts = <23>, <24>, <25>, <27>, <28>;
+                clocks = <&clock 67>;
+                clock-names = "timers";
                 samsung,pwm-outputs = <0>, <1>;
                 #pwm-cells = <3>;
         }
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
index 681afad73778..fb81179dce37 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
@@ -4,11 +4,9 @@ Required properties:
 - compatible: Must be "ti,<soc>-ecap".
   for am33xx - compatible = "ti,am33xx-ecap";
   for da850  - compatible = "ti,da850-ecap", "ti,am33xx-ecap";
-- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
-  First cell specifies the per-chip index of the PWM to use, the second
-  cell is the period in nanoseconds and bit 0 in the third cell is used to
-  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
-  to 1 for inverse polarity & set to 0 for normal polarity.
+- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+  the cells format. The PWM channel index ranges from 0 to 4. The only third
+  cell flag supported by this binding is PWM_POLARITY_INVERTED.
 - reg: physical base address and size of the registers map.
 
 Optional properties:
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 337c6fc65d3f..9c100b2c5b23 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -4,11 +4,9 @@ Required properties:
 - compatible: Must be "ti,<soc>-ehrpwm".
   for am33xx - compatible = "ti,am33xx-ehrpwm";
   for da850  - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
-- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
-  First cell specifies the per-chip index of the PWM to use, the second
-  cell is the period in nanoseconds and bit 0 in the third cell is used to
-  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
-  to 1 for inverse polarity & set to 0 for normal polarity.
+- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+  the cells format. The only third cell flag supported by this binding is
+  PWM_POLARITY_INVERTED.
 - reg: physical base address and size of the registers map.
 
 Optional properties:
diff --git a/Documentation/devicetree/bindings/pwm/pwm.txt b/Documentation/devicetree/bindings/pwm/pwm.txt
index 06e67247859a..8556263b8502 100644
--- a/Documentation/devicetree/bindings/pwm/pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm.txt
@@ -43,13 +43,14 @@ because the name "backlight" would be used as fallback anyway.
 pwm-specifier typically encodes the chip-relative PWM number and the PWM
 period in nanoseconds.
 
-Optionally, the pwm-specifier can encode a number of flags in a third cell:
-- bit 0: PWM signal polarity (0: normal polarity, 1: inverse polarity)
+Optionally, the pwm-specifier can encode a number of flags (defined in
+<dt-bindings/pwm/pwm.h>) in a third cell:
+- PWM_POLARITY_INVERTED: invert the PWM signal polarity
 
 Example with optional PWM specifier for inverse polarity
 
         bl: backlight {
-                pwms = <&pwm 0 5000000 1>;
+                pwms = <&pwm 0 5000000 PWM_POLARITY_INVERTED>;
                 pwm-names = "backlight";
         };
 
diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
new file mode 100644
index 000000000000..b067e84a94b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.txt
@@ -0,0 +1,28 @@
+* Renesas R-Car Timer Pulse Unit PWM Controller
+
+Required Properties:
+
+  - compatible: should be one of the following.
+    - "renesas,tpu-r8a73a4": for R8A77A4 (R-Mobile APE6) compatible PWM controller.
+    - "renesas,tpu-r8a7740": for R8A7740 (R-Mobile A1) compatible PWM controller.
+    - "renesas,tpu-r8a7790": for R8A7790 (R-Car H2) compatible PWM controller.
+    - "renesas,tpu-sh7372": for SH7372 (SH-Mobile AP4) compatible PWM controller.
+    - "renesas,tpu": for generic R-Car TPU PWM controller.
+
+  - reg: Base address and length of each memory resource used by the PWM
+    controller hardware module.
+
+  - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+    the cells format. The only third cell flag supported by this binding is
+    PWM_POLARITY_INVERTED.
+
+Please refer to pwm.txt in this directory for details of the common PWM bindings
+used by client devices.
+
+Example: R8A7740 (R-Car A1) TPU controller node
+
+        tpu: pwm@e6600000 {
+                compatible = "renesas,tpu-r8a7740", "renesas,tpu";
+                reg = <0xe6600000 0x100>;
+                #pwm-cells = <3>;
+        };
diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt b/Documentation/devicetree/bindings/pwm/spear-pwm.txt
index 3ac779d83386..b486de2c3fe3 100644
--- a/Documentation/devicetree/bindings/pwm/spear-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/spear-pwm.txt
@@ -5,9 +5,8 @@ Required properties:
   - "st,spear320-pwm"
   - "st,spear1340-pwm"
 - reg: physical base address and length of the controller's registers
-- #pwm-cells: number of cells used to specify PWM which is fixed to 2 on
-  SPEAr. The first cell specifies the per-chip index of the PWM to use and
-  the second cell is the period in nanoseconds.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+  the cells format.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
index 2943ee5fce00..4e32bee11201 100644
--- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt
@@ -6,8 +6,8 @@ On TWL6030 series: PWM0 and PWM1
 
 Required properties:
 - compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm"
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+  the cells format.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
index cb64f3acc10f..9f4b46090782 100644
--- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
+++ b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt
@@ -6,8 +6,8 @@ On TWL6030 series: LED PWM (mainly used as charging indicator LED)
 
 Required properties:
 - compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled"
-- #pwm-cells: should be 2.  The first cell specifies the per-chip index
-  of the PWM to use and the second cell is the period in nanoseconds.
+- #pwm-cells: should be 2. See pwm.txt in this directory for a description of
+  the cells format.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
index d21d82d29855..a76390e6df2e 100644
--- a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
+++ b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt
@@ -3,11 +3,9 @@ VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller
 Required properties:
 - compatible: should be "via,vt8500-pwm"
 - reg: physical base address and length of the controller's registers
-- #pwm-cells: Should be 3. Number of cells being used to specify PWM property.
-  First cell specifies the per-chip index of the PWM to use, the second
-  cell is the period in nanoseconds and bit 0 in the third cell is used to
-  encode the polarity of PWM output. Set bit 0 of the third in PWM specifier
-  to 1 for inverse polarity & set to 0 for normal polarity.
+- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
+  the cells format. The only third cell flag supported by this binding is
+  PWM_POLARITY_INVERTED.
 - clocks: phandle to the PWM source clock
 
 Example:
diff --git a/Documentation/devicetree/bindings/regulator/88pm800.txt b/Documentation/devicetree/bindings/regulator/88pm800.txt
new file mode 100644
index 000000000000..e8a54c2a5821
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/88pm800.txt
@@ -0,0 +1,38 @@
+Marvell 88PM800 regulator
+
+Required properties:
+- compatible: "marvell,88pm800"
+- reg: I2C slave address
+- regulators: A node that houses a sub-node for each regulator within the
+  device. Each sub-node is identified using the node's name (or the deprecated
+  regulator-compatible property if present), with valid values listed below.
+  The content of each sub-node is defined by the standard binding for
+  regulators; see regulator.txt.
+
+The valid names for regulators are:
+
+  buck1, buck2, buck3, buck4, buck5, ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7,
+  ldo8, ldo9, ldo10, ldo11, ldo12, ldo13, ldo14, ldo15, ldo16, ldo17, ldo18, ldo19
+
+Example:
+
+        pmic: 88pm800@31 {
+                compatible = "marvell,88pm800";
+                reg = <0x31>;
+
+                regulators {
+                        buck1 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <3950000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        ldo1 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <15000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+...
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/max8660.txt b/Documentation/devicetree/bindings/regulator/max8660.txt
new file mode 100644
index 000000000000..8ba994d8a142
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8660.txt
@@ -0,0 +1,47 @@
+Maxim MAX8660 voltage regulator
+
+Required properties:
+- compatible: must be one of "maxim,max8660", "maxim,max8661"
+- reg: I2C slave address, usually 0x34
+- any required generic properties defined in regulator.txt
+
+Example:
+
+        i2c_master {
+                max8660@34 {
+                        compatible = "maxim,max8660";
+                        reg = <0x34>;
+
+                        regulators {
+                                regulator@0 {
+                                        regulator-compatible= "V3(DCDC)";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@1 {
+                                        regulator-compatible= "V4(DCDC)";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@2 {
+                                        regulator-compatible= "V5(LDO)";
+                                        regulator-min-microvolt = <1700000>;
+                                        regulator-max-microvolt = <2000000>;
+                                };
+
+                                regulator@3 {
+                                        regulator-compatible= "V6(LDO)";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@4 {
+                                        regulator-compatible= "V7(LDO)";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
index 30b0581bb1ce..875639ae0606 100644
--- a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
+++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
@@ -25,8 +25,8 @@ Optional nodes:
                Additional custom properties  are listed below.
 
                For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
-               smps45, smps457, smps7 depending on variant, smps6, smps[8-10],
-               ldo[1-9], ldoln, ldousb.
+               smps45, smps457, smps7 depending on variant, smps6, smps[8-9],
+               smps10_out2, smps10_out1, do[1-9], ldoln, ldousb.
 
                Optional sub-node properties:
                ti,warm-reset - maintain voltage during warm reset(boolean)
@@ -36,6 +36,9 @@ Optional nodes:
                ti,smps-range - OTP has the wrong range set for the hardware so override
                0 - low range, 1 - high range.
 
+- ti,system-power-controller: Telling whether or not this pmic is controlling
+                              the system power.
+
 Example:
 
 #include <dt-bindings/interrupt-controller/irq.h>
@@ -48,6 +51,8 @@ pmic {
 
         ti,ldo6-vibrator;
 
+        ti,system-power-controller;
+
         regulators {
                 smps12_reg : smps12 {
                         regulator-name = "smps12";
diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt
new file mode 100644
index 000000000000..fc989b2e8057
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt
@@ -0,0 +1,115 @@
+PFUZE100 family of regulators
+
+Required properties:
+- compatible: "fsl,pfuze100"
+- reg: I2C slave address
+
+Required child node:
+- regulators: This is the list of child nodes that specify the regulator
+  initialization data for defined regulators. Please refer to below doc
+  Documentation/devicetree/bindings/regulator/regulator.txt.
+
+  The valid names for regulators are:
+  sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
+
+Each regulator is defined using the standard binding for regulators.
+
+Example:
+
+        pmic: pfuze100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+
+                        sw1c_reg: sw1c {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        sw4_reg: sw4 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt
index 48a3b8e5d6bd..2bd8f0978765 100644
--- a/Documentation/devicetree/bindings/regulator/regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/regulator.txt
@@ -12,6 +12,8 @@ Optional properties:
 - regulator-allow-bypass: allow the regulator to go into bypass mode
 - <name>-supply: phandle to the parent supply/regulator node
 - regulator-ramp-delay: ramp delay for regulator(in uV/uS)
+  For hardwares which support disabling ramp rate, it should be explicitly
+  intialised to zero (regulator-ramp-delay = <0>) for disabling ramp delay.
 
 Deprecated properties:
 - regulator-compatible: If a regulator chip contains multiple
diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
index eb2327b2bdb3..c703d51abb6c 100644
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt
@@ -1,7 +1,10 @@
 * Designware APB timer
 
 Required properties:
-- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc"
+- compatible: One of:
+        "snps,dw-apb-timer"
+        "snps,dw-apb-timer-sp" <DEPRECATED>
+        "snps,dw-apb-timer-osc" <DEPRECATED>
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: IRQ line for the timer.
@@ -20,25 +23,10 @@ systems may use one.
 
 
 Example:
-
-                timer1: timer@ffc09000 {
-                                compatible = "snps,dw-apb-timer-sp";
-                                interrupts = <0 168 4>;
-                                clock-frequency = <200000000>;
-                                reg = <0xffc09000 0x1000>;
-                        };
-
-                timer2: timer@ffd00000 {
-                                compatible = "snps,dw-apb-timer-osc";
-                                interrupts = <0 169 4>;
-                                clock-frequency = <200000000>;
-                                reg = <0xffd00000 0x1000>;
-                        };
-
-                timer3: timer@ffe00000 {
-                                compatible = "snps,dw-apb-timer-osc";
-                                interrupts = <0 170 4>;
-                                reg = <0xffe00000 0x1000>;
-                                clocks = <&timer_clk>, <&timer_pclk>;
-                                clock-names = "timer", "pclk";
-                        };
+        timer@ffe00000 {
+                compatible = "snps,dw-apb-timer";
+                interrupts = <0 170 4>;
+                reg = <0xffe00000 0x1000>;
+                clocks = <&timer_clk>, <&timer_pclk>;
+                clock-names = "timer", "pclk";
+        };
diff --git a/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt b/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt
new file mode 100644
index 000000000000..c9d3ac1477fe
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/moxa,moxart-rtc.txt
@@ -0,0 +1,17 @@
+MOXA ART real-time clock
+
+Required properties:
+
+- compatible : Should be "moxa,moxart-rtc"
+- gpio-rtc-sclk : RTC sclk gpio, with zero flags
+- gpio-rtc-data : RTC data gpio, with zero flags
+- gpio-rtc-reset : RTC reset gpio, with zero flags
+
+Example:
+
+        rtc: rtc {
+                compatible = "moxa,moxart-rtc";
+                gpio-rtc-sclk = <&gpio 5 0>;
+                gpio-rtc-data = <&gpio 6 0>;
+                gpio-rtc-reset = <&gpio 7 0>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
index b47aa415c820..5a0f02d34d95 100644
--- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt
+++ b/Documentation/devicetree/bindings/rtc/rtc-omap.txt
@@ -1,7 +1,11 @@
 TI Real Time Clock
 
 Required properties:
-- compatible: "ti,da830-rtc"
+- compatible:
+        - "ti,da830-rtc"  - for RTC IP used similar to that on DA8xx SoC family.
+        - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
+                            This RTC IP has special WAKE-EN Register to enable
+                            Wakeup generation for event Alarm.
 - reg: Address range of rtc register set
 - interrupts: rtc timer, alarm interrupts in order
 - interrupt-parent: phandle for the interrupt controller
diff --git a/Documentation/devicetree/bindings/rtc/rtc-palmas.txt b/Documentation/devicetree/bindings/rtc/rtc-palmas.txt
new file mode 100644
index 000000000000..adbccc0a51e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-palmas.txt
@@ -0,0 +1,33 @@
+Palmas RTC controller bindings
+
+Required properties:
+- compatible:
+  - "ti,palmas-rtc" for palma series of the RTC controller
+- interrupt-parent: Parent interrupt device, must be handle of palmas node.
+- interrupts: Interrupt number of RTC submodule on device.
+
+Optional properties:
+
+- ti,backup-battery-chargeable: The Palmas series device like TPS65913 or
+        TPS80036 supports the backup battery for powering the RTC when main
+        battery is removed or in very low power state. The backup battery
+        can be chargeable or non-chargeable. This flag will tells whether
+        battery is chargeable or not. If charging battery then driver can
+        enable the charging.
+- ti,backup-battery-charge-high-current: Enable high current charging in
+        backup battery. Device supports the < 100mA and > 100mA charging.
+        The high current will be > 100mA. Absence of this property will
+        charge battery to lower current i.e. < 100mA.
+
+Example:
+        palmas: tps65913@58 {
+                ...
+                palmas_rtc: rtc {
+                        compatible = "ti,palmas-rtc";
+                        interrupt-parent = <&palmas>;
+                        interrupts = <8 0>;
+                        ti,backup-battery-chargeable;
+                        ti,backup-battery-charge-high-current;
+                };
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/serial/altera_jtaguart.txt b/Documentation/devicetree/bindings/serial/altera_jtaguart.txt
index c152f65f9a28..55a901051e8f 100644
--- a/Documentation/devicetree/bindings/serial/altera_jtaguart.txt
+++ b/Documentation/devicetree/bindings/serial/altera_jtaguart.txt
@@ -1,4 +1,5 @@
 Altera JTAG UART
 
 Required properties:
-- compatible : should be "ALTR,juart-1.0"
+- compatible : should be "ALTR,juart-1.0" <DEPRECATED>
+- compatible : should be "altr,juart-1.0"
diff --git a/Documentation/devicetree/bindings/serial/altera_uart.txt b/Documentation/devicetree/bindings/serial/altera_uart.txt
index 71cae3f70100..81bf7ffb1a81 100644
--- a/Documentation/devicetree/bindings/serial/altera_uart.txt
+++ b/Documentation/devicetree/bindings/serial/altera_uart.txt
@@ -1,7 +1,8 @@
 Altera UART
 
 Required properties:
-- compatible : should be "ALTR,uart-1.0"
+- compatible : should be "ALTR,uart-1.0" <DEPRECATED>
+- compatible : should be "altr,uart-1.0"
 
 Optional properties:
 - clock-frequency : frequency of the clock input to the UART
diff --git a/Documentation/devicetree/bindings/tty/serial/arc-uart.txt b/Documentation/devicetree/bindings/serial/arc-uart.txt
index 5cae2eb686f8..5cae2eb686f8 100644
--- a/Documentation/devicetree/bindings/tty/serial/arc-uart.txt
+++ b/Documentation/devicetree/bindings/serial/arc-uart.txt
diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt
index a49d9a1d4ccf..2191dcb9f1da 100644
--- a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
+++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt
@@ -10,13 +10,18 @@ Required properties:
 Optional properties:
 - atmel,use-dma-rx: use of PDC or DMA for receiving data
 - atmel,use-dma-tx: use of PDC or DMA for transmitting data
+- add dma bindings for dma transfer:
+        - dmas: DMA specifier, consisting of a phandle to DMA controller node,
+                memory peripheral interface and USART DMA channel ID, FIFO configuration.
+                Refer to dma.txt and atmel-dma.txt for details.
+        - dma-names: "rx" for RX channel, "tx" for TX channel.
 
 <chip> compatible description:
 - at91rm9200:  legacy USART support
 - at91sam9260: generic USART implementation for SAM9 SoCs
 
 Example:
-
+- use PDC:
         usart0: serial@fff8c000 {
                 compatible = "atmel,at91sam9260-usart";
                 reg = <0xfff8c000 0x4000>;
@@ -25,3 +30,14 @@ Example:
                 atmel,use-dma-tx;
         };
 
+- use DMA:
+        usart0: serial@f001c000 {
+                compatible = "atmel,at91sam9260-usart";
+                reg = <0xf001c000 0x100>;
+                interrupts = <12 4 5>;
+                atmel,use-dma-rx;
+                atmel,use-dma-tx;
+                dmas = <&dma0 2 0x3>,
+                       <&dma0 2 0x204>;
+                dma-names = "tx", "rx";
+        };
diff --git a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt b/Documentation/devicetree/bindings/serial/efm32-uart.txt
index 8e080b893b49..8e080b893b49 100644
--- a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt
+++ b/Documentation/devicetree/bindings/serial/efm32-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
index c58573b5b1a4..35ae1fb3537f 100644
--- a/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-imx-uart.txt
@@ -1,35 +1,29 @@
-* Freescale i.MX UART controller
+* Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
 
 Required properties:
-- compatible : should be "fsl,imx21-uart"
+- compatible : Should be "fsl,<soc>-uart"
 - reg : Address and length of the register set for the device
-- interrupts : Should contain UART interrupt number
+- interrupts : Should contain uart interrupt
 
 Optional properties:
-- fsl,uart-has-rtscts: indicate that RTS/CTS signals are used
+- fsl,uart-has-rtscts : Indicate the uart has rts and cts
+- fsl,irda-mode : Indicate the uart supports irda mode
+- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
+                  is DCE mode by default.
 
 Note: Each uart controller should have an alias correctly numbered
 in "aliases" node.
 
 Example:
 
-- From imx51.dtsi:
 aliases {
         serial0 = &uart1;
-        serial1 = &uart2;
-        serial2 = &uart3;
 };
 
 uart1: serial@73fbc000 {
         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
         reg = <0x73fbc000 0x4000>;
         interrupts = <31>;
-        status = "disabled";
-}
-
-- From imx51-babbage.dts:
-uart1: serial@73fbc000 {
         fsl,uart-has-rtscts;
-        status = "okay";
+        fsl,dte-mode;
 };
-
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
index 6fd1dd1638dd..6fd1dd1638dd 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt
index 2c00ec64628e..59a40f18d551 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt
@@ -10,6 +10,10 @@ Required properties:
   Refer to dma.txt and fsl-mxs-dma.txt for details.
 - dma-names: "rx" for RX channel, "tx" for TX channel.
 
+Optional properties:
+- fsl,uart-has-rtscts : Indicate the UART has RTS and CTS lines,
+        it also means you enable the DMA support for this UART.
+
 Example:
 auart0: serial@8006a000 {
         compatible = "fsl,imx28-auart", "fsl,imx23-auart";
diff --git a/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt b/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt
index 0d439dfc1aa5..0d439dfc1aa5 100644
--- a/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt
+++ b/Documentation/devicetree/bindings/serial/nxp-lpc32xx-hsuart.txt
diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/serial/of-serial.txt
index 1928a3e83cd0..1928a3e83cd0 100644
--- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/serial/of-serial.txt
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt
new file mode 100644
index 000000000000..ce8c90161959
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uart.txt
@@ -0,0 +1,25 @@
+* MSM Serial UART
+
+The MSM serial UART hardware is designed for low-speed use cases where a
+dma-engine isn't needed. From a software perspective it's mostly compatible
+with the MSM serial UARTDM except that it only supports reading and writing one
+character at a time.
+
+Required properties:
+- compatible: Should contain "qcom,msm-uart"
+- reg: Should contain UART register location and length.
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock.
+- clock-names: Should be "core".
+
+Example:
+
+A uart device at 0xa9c00000 with interrupt 11.
+
+serial@a9c00000 {
+        compatible = "qcom,msm-uart";
+        reg = <0xa9c00000 0x1000>;
+        interrupts = <11>;
+        clocks = <&uart_cxc>;
+        clock-names = "core";
+};
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
new file mode 100644
index 000000000000..ffa5b784c66e
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -0,0 +1,53 @@
+* MSM Serial UARTDM
+
+The MSM serial UARTDM hardware is designed for high-speed use cases where the
+transmit and/or receive channels can be offloaded to a dma-engine. From a
+software perspective it's mostly compatible with the MSM serial UART except
+that it supports reading and writing multiple characters at a time.
+
+Required properties:
+- compatible: Should contain at least "qcom,msm-uartdm".
+              A more specific property should be specified as follows depending
+              on the version:
+                "qcom,msm-uartdm-v1.1"
+                "qcom,msm-uartdm-v1.2"
+                "qcom,msm-uartdm-v1.3"
+                "qcom,msm-uartdm-v1.4"
+- reg: Should contain UART register locations and lengths. The first
+       register shall specify the main control registers. An optional second
+       register location shall specify the GSBI control region.
+       "qcom,msm-uartdm-v1.3" is the only compatible value that might
+       need the GSBI control region.
+- interrupts: Should contain UART interrupt.
+- clocks: Should contain the core clock and the AHB clock.
+- clock-names: Should be "core" for the core clock and "iface" for the
+               AHB clock.
+
+Optional properties:
+- dmas: Should contain dma specifiers for transmit and receive channels
+- dma-names: Should contain "tx" for transmit and "rx" for receive channels
+
+Examples:
+
+A uartdm v1.4 device with dma capabilities.
+
+serial@f991e000 {
+        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+        reg = <0xf991e000 0x1000>;
+        interrupts = <0 108 0x0>;
+        clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
+        clock-names = "core", "iface";
+        dmas = <&dma0 0>, <&dma0 1>;
+        dma-names = "tx", "rx";
+};
+
+A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
+
+serial@19c40000 {
+        compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+        reg = <0x19c40000 0x1000>,
+              <0x19c00000 0x1000>;
+        interrupts = <0 195 0x0>;
+        clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
+        clock-names = "core", "iface";
+};
diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt
index 1e753c69fc83..32b1fa1f2a5b 100644
--- a/Documentation/devicetree/bindings/serial/rs485.txt
+++ b/Documentation/devicetree/bindings/serial/rs485.txt
@@ -7,7 +7,7 @@ UART node.
 
 Required properties:
 - rs485-rts-delay: prop-encoded-array <a b> where:
-  * a is the delay beteween rts signal and beginning of data sent in milliseconds.
+  * a is the delay between rts signal and beginning of data sent in milliseconds.
       it corresponds to the delay before sending data.
   * b is the delay between end of data sent and rts signal in milliseconds
       it corresponds to the delay after sending data and actual release of the line.
diff --git a/Documentation/devicetree/bindings/serial/sirf-uart.txt b/Documentation/devicetree/bindings/serial/sirf-uart.txt
new file mode 100644
index 000000000000..a2dfc6522a91
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/sirf-uart.txt
@@ -0,0 +1,33 @@
+* CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
+
+Required properties:
+- compatible : Should be "sirf,prima2-uart" or "sirf, prima2-usp-uart"
+- reg : Offset and length of the register set for the device
+- interrupts : Should contain uart interrupt
+- fifosize : Should define hardware rx/tx fifo size
+- clocks : Should contain uart clock number
+
+Optional properties:
+- sirf,uart-has-rtscts: we have hardware flow controller pins in hardware
+- rts-gpios: RTS pin for USP-based UART if sirf,uart-has-rtscts is true
+- cts-gpios: CTS pin for USP-based UART if sirf,uart-has-rtscts is true
+
+Example:
+
+uart0: uart@b0050000 {
+        cell-index = <0>;
+        compatible = "sirf,prima2-uart";
+        reg = <0xb0050000 0x1000>;
+        interrupts = <17>;
+        fifosize = <128>;
+        clocks = <&clks 13>;
+};
+
+On the board-specific dts, we can put rts-gpios and cts-gpios like
+
+usp@b0090000 {
+        compatible = "sirf,prima2-usp-uart";
+        sirf,uart-has-rtscts;
+        rts-gpios = <&gpio 15 0>;
+        cts-gpios = <&gpio 46 0>;
+};
diff --git a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index f13f1c5be91c..f13f1c5be91c 100644
--- a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
diff --git a/Documentation/devicetree/bindings/serial/st-asc.txt b/Documentation/devicetree/bindings/serial/st-asc.txt
new file mode 100644
index 000000000000..75d877f5968f
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/st-asc.txt
@@ -0,0 +1,18 @@
+*st-asc(Serial Port)
+
+Required properties:
+- compatible : Should be "st,asc".
+- reg, reg-names, interrupts, interrupt-names   : Standard way to define device
+                        resources with names. look in
+                        Documentation/devicetree/bindings/resource-names.txt
+
+Optional properties:
+- st,hw-flow-ctrl       bool flag to enable hardware flow control.
+- st,force-m1           bool flat to force asc to be in Mode-1 recommeded
+                        for high bit rates (above 19.2K)
+Example:
+serial@fe440000{
+    compatible    = "st,asc";
+    reg         = <0xfe440000 0x2c>;
+    interrupts     =  <0 209 0>;
+};
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt
index 5feef1ef167d..5feef1ef167d 100644
--- a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
+++ b/Documentation/devicetree/bindings/serial/via,vt8500-uart.txt
diff --git a/Documentation/devicetree/bindings/serio/altera_ps2.txt b/Documentation/devicetree/bindings/serio/altera_ps2.txt
index 4d9eecc2ef7d..520199e2e347 100644
--- a/Documentation/devicetree/bindings/serio/altera_ps2.txt
+++ b/Documentation/devicetree/bindings/serio/altera_ps2.txt
@@ -1,4 +1,5 @@
 Altera UP PS/2 controller
 
 Required properties:
-- compatible : should be "ALTR,ps2-1.0".
+- compatible : should be "ALTR,ps2-1.0". <DEPRECATED>
+- compatible : should be "altr,ps2-1.0".
diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt
new file mode 100644
index 000000000000..a590ca51be75
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/efm32-spi.txt
@@ -0,0 +1,34 @@
+* Energy Micro EFM32 SPI
+
+Required properties:
+- #address-cells: see spi-bus.txt
+- #size-cells: see spi-bus.txt
+- compatible: should be "efm32,spi"
+- reg: Offset and length of the register set for the controller
+- interrupts: pair specifying rx and tx irq
+- clocks: phandle to the spi clock
+- cs-gpios: see spi-bus.txt
+- location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.
+
+Example:
+
+spi1: spi@0x4000c400 { /* USART1 */
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "efm32,spi";
+        reg = <0x4000c400 0x400>;
+        interrupts = <15 16>;
+        clocks = <&cmu 20>;
+        cs-gpios = <&gpio 51 1>; // D3
+        location = <1>;
+        status = "ok";
+
+        ks8851@0 {
+                compatible = "ks8851";
+                spi-max-frequency = <6000000>;
+                reg = <0>;
+                interrupt-parent = <&boardfpga>;
+                interrupts = <4>;
+                status = "ok";
+        };
+};
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index 296015e3c632..800dafe5b01b 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -55,6 +55,16 @@ contain the following properties.
                 chip select active high
 - spi-3wire       - (optional) Empty property indicating device requires
                     3-wire mode.
+- spi-tx-bus-width - (optional) The bus width(number of data wires) that
+                      used for MOSI. Defaults to 1 if not present.
+- spi-rx-bus-width - (optional) The bus width(number of data wires) that
+                      used for MISO. Defaults to 1 if not present.
+
+Some SPI controllers and devices support Dual and Quad SPI transfer mode.
+It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
+Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
+only 1(SINGLE), 2(DUAL) and 4(QUAD).
+Dual/Quad mode is not allowed when 3-wire mode is used.
 
 If a gpio chipselect is used for the SPI slave the gpio number will be passed
 via the cs_gpio
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
new file mode 100644
index 000000000000..a1fb3035a42b
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -0,0 +1,42 @@
+ARM Freescale DSPI controller
+
+Required properties:
+- compatible : "fsl,vf610-dspi"
+- reg : Offset and length of the register set for the device
+- interrupts : Should contain SPI controller interrupt
+- clocks: from common clock binding: handle to dspi clock.
+- clock-names: from common clock binding: Shall be "dspi".
+- pinctrl-0: pin control group to be used for this controller.
+- pinctrl-names: must contain a "default" entry.
+- spi-num-chipselects : the number of the chipselect signals.
+- bus-num : the slave chip chipselect signal number.
+Example:
+
+dspi0@4002c000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,vf610-dspi";
+        reg = <0x4002c000 0x1000>;
+        interrupts = <0 67 0x04>;
+        clocks = <&clks VF610_CLK_DSPI0>;
+        clock-names = "dspi";
+        spi-num-chipselects = <5>;
+        bus-num = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_dspi0_1>;
+        status = "okay";
+
+        sflash: at26df081a@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "atmel,at26df081a";
+                spi-max-frequency = <16000000>;
+                spi-cpol;
+                spi-cpha;
+                reg = <0>;
+                linux,modalias = "m25p80";
+                modal = "at26df081a";
+        };
+};
+
+
diff --git a/Documentation/devicetree/bindings/spi/spi_altera.txt b/Documentation/devicetree/bindings/spi/spi_altera.txt
index dda375943506..31319dcf30ab 100644
--- a/Documentation/devicetree/bindings/spi/spi_altera.txt
+++ b/Documentation/devicetree/bindings/spi/spi_altera.txt
@@ -1,4 +1,5 @@
 Altera SPI
 
 Required properties:
-- compatible : should be "ALTR,spi-1.0".
+- compatible : should be "ALTR,spi-1.0". <DEPRECATED>
+- compatible : should be "altr,spi-1.0".
diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt
new file mode 100644
index 000000000000..1f9641ade0b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt
@@ -0,0 +1,22 @@
+TI QSPI controller.
+
+Required properties:
+- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
+- reg: Should contain QSPI registers location and length.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+- ti,hwmods: Name of the hwmod associated to the QSPI
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+qspi: qspi@4b300000 {
+        compatible = "ti,dra7xxx-qspi";
+        reg = <0x4b300000 0x100>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        spi-max-frequency = <25000000>;
+        ti,hwmods = "qspi";
+};
diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
new file mode 100644
index 000000000000..284f5300fd8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -0,0 +1,55 @@
+* Exynos Thermal Management Unit (TMU)
+
+** Required properties:
+
+- compatible : One of the following:
+               "samsung,exynos4412-tmu"
+               "samsung,exynos4210-tmu"
+               "samsung,exynos5250-tmu"
+               "samsung,exynos5440-tmu"
+- interrupt-parent : The phandle for the interrupt controller
+- reg : Address range of the thermal registers. For soc's which has multiple
+        instances of TMU and some registers are shared across all TMU's like
+        interrupt related then 2 set of register has to supplied. First set
+        belongs to each instance of TMU and second set belongs to common TMU
+        registers.
+- interrupts : Should contain interrupt for thermal system
+- clocks : The main clock for TMU device
+- clock-names : Thermal system clock name
+- vtmu-supply: This entry is optional and provides the regulator node supplying
+                voltage to TMU. If needed this entry can be placed inside
+                board/platform specific dts file.
+
+Example 1):
+
+        tmu@100C0000 {
+                compatible = "samsung,exynos4412-tmu";
+                interrupt-parent = <&combiner>;
+                reg = <0x100C0000 0x100>;
+                interrupts = <2 4>;
+                clocks = <&clock 383>;
+                clock-names = "tmu_apbif";
+                status = "disabled";
+                vtmu-supply = <&tmu_regulator_node>;
+        };
+
+Example 2):
+
+        tmuctrl_0: tmuctrl@160118 {
+                compatible = "samsung,exynos5440-tmu";
+                reg = <0x160118 0x230>, <0x160368 0x10>;
+                interrupts = <0 58 0>;
+                clocks = <&clock 21>;
+                clock-names = "tmu_apbif";
+        };
+
+Note: For multi-instance tmu each instance should have an alias correctly
+numbered in "aliases" node.
+
+Example:
+
+aliases {
+        tmuctrl0 = &tmuctrl_0;
+        tmuctrl1 = &tmuctrl_1;
+        tmuctrl2 = &tmuctrl_2;
+};
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
new file mode 100644
index 000000000000..541c25e49abf
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -0,0 +1,17 @@
+* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
+
+Required properties:
+- compatible : "fsl,imx6q-thermal"
+- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
+  control registers, e.g. ANATOP on imx6q.
+- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
+  calibration data, e.g. OCOTP on imx6q.  The details about calibration data
+  can be found in SoC Reference Manual.
+
+Example:
+
+tempmon {
+        compatible = "fsl,imx6q-tempmon";
+        fsl,tempmon = <&anatop>;
+        fsl,tempmon-data = <&ocotp>;
+};
diff --git a/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
new file mode 100644
index 000000000000..da2d510cae47
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
@@ -0,0 +1,17 @@
+MOXA ART timer
+
+Required properties:
+
+- compatible : Must be "moxa,moxart-timer"
+- reg : Should contain registers location and length
+- interrupts : Should contain the timer interrupt number
+- clocks : Should contain phandle for the clock that drives the counter
+
+Example:
+
+        timer: timer@98400000 {
+                compatible = "moxa,moxart-timer";
+                reg = <0x98400000 0x42>;
+                interrupts = <19 1>;
+                clocks = <&coreclk>;
+        };
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
deleted file mode 100644
index c662eb36be29..000000000000
--- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
-
-Required properties:
-- compatible : Should be "fsl,<soc>-uart"
-- reg : Address and length of the register set for the device
-- interrupts : Should contain uart interrupt
-
-Optional properties:
-- fsl,uart-has-rtscts : Indicate the uart has rts and cts
-- fsl,irda-mode : Indicate the uart supports irda mode
-- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
-                  is DCE mode by default.
-
-Example:
-
-serial@73fbc000 {
-        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
-        reg = <0x73fbc000 0x4000>;
-        interrupts = <31>;
-        fsl,uart-has-rtscts;
-        fsl,dte-mode;
-};
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
deleted file mode 100644
index aef383eb8876..000000000000
--- a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-* Qualcomm MSM UART
-
-Required properties:
-- compatible :
-        - "qcom,msm-uart", and one of "qcom,msm-hsuart" or
-          "qcom,msm-lsuart".
-- reg : offset and length of the register set for the device
-        for the hsuart operating in compatible mode, there should be a
-        second pair describing the gsbi registers.
-- interrupts : should contain the uart interrupt.
-
-There are two different UART blocks used in MSM devices,
-"qcom,msm-hsuart" and "qcom,msm-lsuart".  The msm-serial driver is
-able to handle both of these, and matches against the "qcom,msm-uart"
-as the compatibility.
-
-The registers for the "qcom,msm-hsuart" device need to specify both
-register blocks, even for the common driver.
-
-Example:
-
-        uart@19c400000 {
-                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
-                reg = <0x19c40000 0x1000>,
-                      <0x19c00000 0x1000>;
-                interrupts = <195>;
-        };
diff --git a/Documentation/devicetree/bindings/tty/serial/qca,ar9330-uart.txt b/Documentation/devicetree/bindings/tty/serial/qca,ar9330-uart.txt
new file mode 100644
index 000000000000..c5e032c85bf9
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/qca,ar9330-uart.txt
@@ -0,0 +1,34 @@
+* Qualcomm Atheros AR9330 High-Speed UART
+
+Required properties:
+
+- compatible: Must be "qca,ar9330-uart"
+
+- reg: Specifies the physical base address of the controller and
+  the length of the memory mapped region.
+
+- interrupt-parent: The phandle for the interrupt controller that
+  services interrupts for this device.
+
+- interrupts: Specifies the interrupt source of the parent interrupt
+  controller. The format of the interrupt specifier depends on the
+  parent interrupt controller.
+
+Additional requirements:
+
+  Each UART port must have an alias correctly numbered in "aliases"
+  node.
+
+Example:
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        uart0: uart@18020000 {
+                compatible = "qca,ar9330-uart";
+                reg = <0x18020000 0x14>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <3>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
index dc9dc8c87f15..20c2ff2ba07e 100644
--- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt
+++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
@@ -1,35 +1,197 @@
-AM33XX MUSB GLUE
- - compatible : Should be "ti,musb-am33xx"
- - reg : offset and length of register sets, first usbss, then for musb instances
- - interrupts : usbss, musb instance interrupts in order
- - ti,hwmods : must be "usb_otg_hs"
- - multipoint : Should be "1" indicating the musb controller supports
-   multipoint. This is a MUSB configuration-specific setting.
- - num-eps : Specifies the number of endpoints. This is also a
-   MUSB configuration-specific setting. Should be set to "16"
- - ram-bits : Specifies the ram address size. Should be set to "12"
- - port0-mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
-   represents PERIPHERAL.
- - port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
-   represents PERIPHERAL.
- - power : Should be "250". This signifies the controller can supply up to
-   500mA when operating in host mode.
+  AM33xx MUSB
+~~~~~~~~~~~~~~~
+- compatible: ti,am33xx-usb
+- reg: offset and length of the usbss register sets
+- ti,hwmods : must be "usb_otg_hs"
+
+The glue layer contains multiple child nodes. It is required the have
+at least a control module node, USB node and a PHY node. The second USB
+node and its PHY node is optional. The DMA node is also optional.
+
+Reset module
+~~~~~~~~~~~~
+- compatible: ti,am335x-usb-ctrl-module
+- reg: offset and length of the "USB control registers" in the "Control
+  Module" block. A second offset and length for the USB wake up control
+  in the same memory block.
+- reg-names: "phy_ctrl" for the "USB control registers" and "wakeup" for
+  the USB wake up control register.
+
+USB PHY
+~~~~~~~
+compatible: ti,am335x-usb-phy
+reg: offset and length of the "USB PHY" register space
+ti,ctrl_mod: reference to the "reset module" node
+reg-names: phy
+The PHY should have a "phy" alias numbered properly in the alias
+node.
+
+USB
+~~~
+- compatible: ti,musb-am33xx
+- reg: offset and length of "USB Controller Registers", and offset and
+  length of "USB Core" register space.
+- reg-names: control for the ""USB Controller Registers" and "mc" for
+  "USB Core" register space
+- interrupts: USB interrupt number
+- interrupt-names: mc
+- dr_mode: Should be one of "host", "peripheral" or "otg".
+- mentor,multipoint: Should be "1" indicating the musb controller supports
+  multipoint. This is a MUSB configuration-specific setting.
+- mentor,num-eps: Specifies the number of endpoints. This is also a
+  MUSB configuration-specific setting. Should be set to "16"
+- mentor,ram-bits: Specifies the ram address size. Should be set to "12"
+- mentor,power: Should be "500". This signifies the controller can supply up to
+  500mA when operating in host mode.
+- phys: reference to the USB phy
+- dmas: specifies the dma channels
+- dma-names: specifies the names of the channels. Use "rxN" for receive
+  and "txN" for transmit endpoints. N specifies the endpoint number.
+
+The controller should have an "usb" alias numbered properly in the alias
+node.
+
+DMA
+~~~
+- compatible: ti,am3359-cppi41
+- reg: offset and length of the following register spaces: USBSS, USB
+  CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
+- reg-names: glue, controller, scheduler, queuemgr
+- #dma-cells: should be set to 2. The first number represents the
+  endpoint number (0 … 14 for endpoints 1 … 15 on instance 0 and 15 … 29
+  for endpoints 1 … 15 on instance 1). The second number is 0 for RX and
+  1 for TX transfers.
+- #dma-channels: should be set to 30 representing the 15 endpoints for
+  each USB instance.
 
 Example:
+~~~~~~~~
+The following example contains all the nodes as used on am335x-evm:
+
+aliases {
+        usb0 = &usb0;
+        usb1 = &usb1;
+        phy0 = &usb0_phy;
+        phy1 = &usb1_phy;
+};
 
-usb@47400000  {
-        compatible = "ti,musb-am33xx";
-        reg = <0x47400000 0x1000        /* usbss */
-               0x47401000 0x800         /* musb instance 0 */
-               0x47401800 0x800>;       /* musb instance 1 */
-        interrupts = <17                /* usbss */
-                      18                /* musb instance 0 */
-                      19>;              /* musb instance 1 */
-        multipoint = <1>;
-        num-eps = <16>;
-        ram-bits = <12>;
-        port0-mode = <3>;
-        port1-mode = <3>;
-        power = <250>;
+usb: usb@47400000 {
+        compatible = "ti,am33xx-usb";
+        reg = <0x47400000 0x1000>;
+        ranges;
+        #address-cells = <1>;
+        #size-cells = <1>;
         ti,hwmods = "usb_otg_hs";
+
+        ctrl_mod: control@44e10000 {
+                compatible = "ti,am335x-usb-ctrl-module";
+                reg = <0x44e10620 0x10
+                        0x44e10648 0x4>;
+                reg-names = "phy_ctrl", "wakeup";
+        };
+
+        usb0_phy: usb-phy@47401300 {
+                compatible = "ti,am335x-usb-phy";
+                reg = <0x47401300 0x100>;
+                reg-names = "phy";
+                ti,ctrl_mod = <&ctrl_mod>;
+        };
+
+        usb0: usb@47401000 {
+                compatible = "ti,musb-am33xx";
+                reg = <0x47401400 0x400
+                        0x47401000 0x200>;
+                reg-names = "mc", "control";
+
+                interrupts = <18>;
+                interrupt-names = "mc";
+                dr_mode = "otg"
+                mentor,multipoint = <1>;
+                mentor,num-eps = <16>;
+                mentor,ram-bits = <12>;
+                mentor,power = <500>;
+                phys = <&usb0_phy>;
+
+                dmas = <&cppi41dma  0 0 &cppi41dma  1 0
+                        &cppi41dma  2 0 &cppi41dma  3 0
+                        &cppi41dma  4 0 &cppi41dma  5 0
+                        &cppi41dma  6 0 &cppi41dma  7 0
+                        &cppi41dma  8 0 &cppi41dma  9 0
+                        &cppi41dma 10 0 &cppi41dma 11 0
+                        &cppi41dma 12 0 &cppi41dma 13 0
+                        &cppi41dma 14 0 &cppi41dma  0 1
+                        &cppi41dma  1 1 &cppi41dma  2 1
+                        &cppi41dma  3 1 &cppi41dma  4 1
+                        &cppi41dma  5 1 &cppi41dma  6 1
+                        &cppi41dma  7 1 &cppi41dma  8 1
+                        &cppi41dma  9 1 &cppi41dma 10 1
+                        &cppi41dma 11 1 &cppi41dma 12 1
+                        &cppi41dma 13 1 &cppi41dma 14 1>;
+                dma-names =
+                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                        "rx14", "rx15",
+                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                        "tx14", "tx15";
+        };
+
+        usb1_phy: usb-phy@47401b00 {
+                compatible = "ti,am335x-usb-phy";
+                reg = <0x47401b00 0x100>;
+                reg-names = "phy";
+                ti,ctrl_mod = <&ctrl_mod>;
+        };
+
+        usb1: usb@47401800 {
+                compatible = "ti,musb-am33xx";
+                reg = <0x47401c00 0x400
+                        0x47401800 0x200>;
+                reg-names = "mc", "control";
+                interrupts = <19>;
+                interrupt-names = "mc";
+                dr_mode = "host"
+                mentor,multipoint = <1>;
+                mentor,num-eps = <16>;
+                mentor,ram-bits = <12>;
+                mentor,power = <500>;
+                phys = <&usb1_phy>;
+
+                dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+                        &cppi41dma 17 0 &cppi41dma 18 0
+                        &cppi41dma 19 0 &cppi41dma 20 0
+                        &cppi41dma 21 0 &cppi41dma 22 0
+                        &cppi41dma 23 0 &cppi41dma 24 0
+                        &cppi41dma 25 0 &cppi41dma 26 0
+                        &cppi41dma 27 0 &cppi41dma 28 0
+                        &cppi41dma 29 0 &cppi41dma 15 1
+                        &cppi41dma 16 1 &cppi41dma 17 1
+                        &cppi41dma 18 1 &cppi41dma 19 1
+                        &cppi41dma 20 1 &cppi41dma 21 1
+                        &cppi41dma 22 1 &cppi41dma 23 1
+                        &cppi41dma 24 1 &cppi41dma 25 1
+                        &cppi41dma 26 1 &cppi41dma 27 1
+                        &cppi41dma 28 1 &cppi41dma 29 1>;
+                dma-names =
+                        "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+                        "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+                        "rx14", "rx15",
+                        "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+                        "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+                        "tx14", "tx15";
+        };
+
+        cppi41dma: dma-controller@07402000 {
+                compatible = "ti,am3359-cppi41";
+                reg =  <0x47400000 0x1000
+                        0x47402000 0x1000
+                        0x47403000 0x1000
+                        0x47404000 0x4000>;
+                reg-names = "glue", "controller", "scheduler", "queuemgr";
+                interrupts = <17>;
+                interrupt-names = "glue";
+                #dma-cells = <2>;
+                #dma-channels = <30>;
+                #dma-requests = <256>;
+        };
 };
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 7a95c651ceb3..e807635f9e1c 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -3,10 +3,12 @@ synopsys DWC3 CORE
 DWC3- USB3 CONTROLLER
 
 Required properties:
- - compatible: must be "synopsys,dwc3"
+ - compatible: must be "snps,dwc3"
  - reg : Address and length of the register set for the device
  - interrupts: Interrupts used by the dwc3 controller.
- - usb-phy : array of phandle for the PHY device
+ - usb-phy : array of phandle for the PHY device.  The first element
+   in the array is expected to be a handle to the USB2/HS PHY and
+   the second element is expected to be a handle to the USB3/SS PHY
 
 Optional properties:
  - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
@@ -14,7 +16,7 @@ Optional properties:
 This is usually a subnode to DWC3 glue to which it is connected.
 
 dwc3@4a030000 {
-        compatible = "synopsys,dwc3";
+        compatible = "snps,dwc3";
         reg = <0x4a030000 0xcfff>;
         interrupts = <0 92 4>
         usb-phy = <&usb2_phy>, <&usb3,phy>;
diff --git a/Documentation/devicetree/bindings/usb/generic.txt b/Documentation/devicetree/bindings/usb/generic.txt
new file mode 100644
index 000000000000..477d5bb5e51c
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/generic.txt
@@ -0,0 +1,24 @@
+Generic USB Properties
+
+Optional properties:
+ - maximum-speed: tells USB controllers we want to work up to a certain
+                        speed. Valid arguments are "super-speed", "high-speed",
+                        "full-speed" and "low-speed". In case this isn't passed
+                        via DT, USB controllers should default to their maximum
+                        HW capability.
+ - dr_mode: tells Dual-Role USB controllers that we want to work on a
+                        particular mode. Valid arguments are "host",
+                        "peripheral" and "otg". In case this attribute isn't
+                        passed via DT, USB DRD controllers should default to
+                        OTG.
+
+This is an attribute to a USB controller such as:
+
+dwc3@4a030000 {
+        compatible = "synopsys,dwc3";
+        reg = <0x4a030000 0xcfff>;
+        interrupts = <0 92 4>
+        usb-phy = <&usb2_phy>, <&usb3,phy>;
+        maximum-speed = "super-speed";
+        dr_mode = "otg";
+};
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
index c4c9e9e664aa..ba797d3e6326 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -3,7 +3,7 @@ Tegra SOC USB PHY
 The device node for Tegra SOC USB PHY:
 
 Required properties :
- - compatible : Should be "nvidia,tegra20-usb-phy".
+ - compatible : Should be "nvidia,tegra<chip>-usb-phy".
  - reg : Defines the following set of registers, in the order listed:
    - The PHY's own register set.
      Always present.
@@ -24,17 +24,26 @@ Required properties :
 Required properties for phy_type == ulpi:
   - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
 
-Required PHY timing params for utmi phy:
+Required PHY timing params for utmi phy, for all chips:
   - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
     start of sync launches RxActive
   - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
   - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
     before declare IDLE.
   - nvidia,term-range-adj : Range adjusment on terminations
-  - nvidia,xcvr-setup : HS driver output control
+  - Either one of the following for HS driver output control:
+    - nvidia,xcvr-setup : integer, uses the provided value.
+    - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
+      from the on-chip fuses
+    If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
   - nvidia,xcvr-lsfslew : LS falling slew rate control.
   - nvidia,xcvr-lsrslew :  LS rising slew rate control.
 
+Required PHY timing params for utmi phy, only on Tegra30 and above:
+  - nvidia,xcvr-hsslew : HS slew rate control.
+  - nvidia,hssquelch-level : HS squelch detector level.
+  - nvidia,hsdiscon-level : HS disconnect detector level.
+
 Optional properties:
   - nvidia,has-legacy-mode : boolean indicates whether this controller can
     operate in legacy mode (as APX 2500 / 2600). In legacy mode some
@@ -48,5 +57,5 @@ Optional properties:
       peripheral means it is device controller
       otg means it can operate as either ("on the go")
 
-Required properties for dr_mode == otg:
+VBUS control (required for dr_mode == otg, optional for dr_mode == host):
   - vbus-supply: regulator for VBUS
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 57e71f6817d0..9088ab09e200 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -53,6 +53,11 @@ OMAP DWC3 GLUE
    It should be set to "1" for HW mode and "2" for SW mode.
  - ranges: the child address space are mapped 1:1 onto the parent address space
 
+Optional Properties:
+ - extcon : phandle for the extcon device omap dwc3 uses to detect
+   connect/disconnect events.
+ - vbus-supply : phandle to the regulator device tree node if needed.
+
 Sub-nodes:
 The dwc3 core should be added as subnode to omap dwc3 glue.
 - dwc3 :
diff --git a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
new file mode 100644
index 000000000000..b83d428a265e
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
@@ -0,0 +1,40 @@
+Samsung High Speed USB OTG controller
+-----------------------------
+
+The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards.
+It gives functionality of OTG-compliant USB 2.0 host and device with
+support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)
+operation.
+
+Currently only device mode is supported.
+
+Binding details
+-----
+
+Required properties:
+- compatible: "samsung,s3c6400-hsotg" should be used for all currently
+    supported SoC,
+- interrupt-parent: phandle for the interrupt controller to which the
+    interrupt signal of the HSOTG block is routed,
+- interrupts: specifier of interrupt signal of interrupt controller,
+    according to bindings of interrupt controller,
+- clocks: contains an array of clock specifiers:
+    - first entry: OTG clock
+- clock-names: contains array of clock names:
+    - first entry: must be "otg"
+- vusb_d-supply: phandle to voltage regulator of digital section,
+- vusb_a-supply: phandle to voltage regulator of analog section.
+
+Example
+-----
+
+        hsotg@12480000 {
+                compatible = "samsung,s3c6400-hsotg";
+                reg = <0x12480000 0x20000>;
+                interrupts = <0 71 0>;
+                clocks = <&clock 305>;
+                clock-names = "otg";
+                vusb_d-supply = <&vusb_reg>;
+                vusb_a-supply = <&vusbdac_reg>;
+        };
+
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
new file mode 100644
index 000000000000..5752df0e17a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -0,0 +1,14 @@
+USB xHCI controllers
+
+Required properties:
+  - compatible: should be "xhci-platform".
+  - reg: should contain address and length of the standard XHCI
+    register set for the device.
+  - interrupts: one XHCI interrupt should be described here.
+
+Example:
+        usb@f0931000 {
+                compatible = "xhci-platform";
+                reg = <0xf0931000 0x8c8>;
+                interrupts = <0x0 0x4e 0x0>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt
index 8c5be48b43c8..a018da4a7ad7 100644
--- a/Documentation/devicetree/bindings/usb/usb3503.txt
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -1,8 +1,11 @@
 SMSC USB3503 High-Speed Hub Controller
 
 Required properties:
-- compatible: Should be "smsc,usb3503".
-- reg: Specifies the i2c slave address, it should be 0x08.
+- compatible: Should be "smsc,usb3503" or "smsc,usb3503a".
+
+Optional properties:
+- reg: Specifies the i2c slave address, it is required and should be 0x08
+       if I2C is used.
 - connect-gpios: Should specify GPIO for connect.
 - disabled-ports: Should specify the ports unused.
         '1' or '2' or '3' are availe for this property to describe the port
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 366ce9b87240..2956800f0240 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -7,10 +7,12 @@ ad	Avionic Design GmbH
 adi     Analog Devices, Inc.
 aeroflexgaisler Aeroflex Gaisler AB
 ak      Asahi Kasei Corp.
+altr    Altera Corp.
 amcc    Applied Micro Circuits Corporation (APM, formally AMCC)
 apm     Applied Micro Circuits Corporation (APM)
 arm     ARM Ltd.
 atmel   Atmel Corporation
+avago   Avago Technologies
 bosch   Bosch Sensortec GmbH
 brcm    Broadcom Corporation
 cavium  Cavium, Inc.
@@ -36,6 +38,7 @@ linux	Linux-specific binding
 lsi     LSI Corp. (LSI Logic)
 marvell Marvell Technology Group Ltd.
 maxim   Maxim Integrated Products
+microchip       Microchip Technology Inc.
 mosaixtech      Mosaix Technologies, Inc.
 national        National Semiconductor
 nintendo        Nintendo
diff --git a/Documentation/devicetree/bindings/video/simple-framebuffer.txt b/Documentation/devicetree/bindings/video/simple-framebuffer.txt
index 3ea460583111..70c26f3a5b9a 100644
--- a/Documentation/devicetree/bindings/video/simple-framebuffer.txt
+++ b/Documentation/devicetree/bindings/video/simple-framebuffer.txt
@@ -12,6 +12,7 @@ Required properties:
 - stride: The number of bytes in each line of the framebuffer.
 - format: The format of the framebuffer surface. Valid values are:
   - r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b).
+  - a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r).
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
index ecd650adff31..e39cb266c8f4 100644
--- a/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -1,8 +1,9 @@
-Allwinner sun4i Watchdog timer
+Allwinner SoCs Watchdog timer
 
 Required properties:
 
-- compatible : should be "allwinner,sun4i-wdt"
+- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
+  SoC families being sun4i and sun6i
 - reg : Specifies base physical address and size of the registers.
 
 Example: