60 files changed, 1723 insertions, 44 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
index 07c65e3cdcbe..f4d04a067282 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
@@ -3,9 +3,11 @@ Altera SOCFPGA System Manager
 Required properties:
 - compatible : "altr,sys-mgr"
 - reg : Should contain 1 register ranges(address and length)
+- cpu1-start-addr : CPU1 start address in hex.
 Example:
         sysmgr@ffd08000 {
                compatible = "altr,sys-mgr";
                reg = <0xffd08000 0x1000>;
+                cpu1-start-addr = <0xffd080c4>;
        };
diff --git a/Documentation/devicetree/bindings/arm/atmel-aic.txt b/Documentation/devicetree/bindings/arm/atmel-aic.txt
index 19078bf5cca8..ad031211b5b8 100644
--- a/Documentation/devicetree/bindings/arm/atmel-aic.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-aic.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible: Should be "atmel,<chip>-aic"
 - interrupt-controller: Identifies the node as an interrupt controller.
 - interrupt-parent: For single AIC system, it is an empty property.
- #interrupt-cells: The number of cells to define the interrupts. It sould be 3.
+- #interrupt-cells: The number of cells to define the interrupts. It should be 3.
  The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet).
  The second cell is used to specify flags:
    bits[3:0] trigger type and level flags:
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 62eb8df1e08d..3dfb0c0384f5 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -42,7 +42,7 @@ Main node required properties:
 Optional
 - interrupts    : Interrupt source of the parent interrupt controller on
-  secondary GICs, or VGIC maintainance interrupt on primary GIC (see
+  secondary GICs, or VGIC maintenance interrupt on primary GIC (see
  below).
 - cpu-offset    : per-cpu offset within the distributor and cpu interface
@@ -74,7 +74,7 @@ Required properties:
  virtual interface control register base and size. The 2nd additional
  region is the GIC virtual cpu interface register base and size.
- interrupts : VGIC maintainance interrupt.
+- interrupts : VGIC maintenance interrupt.
 Example:
diff --git a/Documentation/devicetree/bindings/arm/kirkwood.txt b/Documentation/devicetree/bindings/arm/kirkwood.txt
new file mode 100644
index 000000000000..98cce9a653eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/kirkwood.txt
@@ -0,0 +1,27 @@
+Marvell Kirkwood Platforms Device Tree Bindings
+-----------------------------------------------
+Boards with a SoC of the Marvell Kirkwood
+shall have the following property:
+Required root node property:
+compatible: must contain "marvell,kirkwood";
+In order to support the kirkwood cpufreq driver, there must be a node
+cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave",
+where the "powersave" clock is a gating clock used to switch the CPU
+between the "cpu_clk" and the "ddrclk".
+Example:
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                      device_type = "cpu";
+                      compatible = "marvell,sheeva-88SV131";
+                      clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
+                      clock-names = "cpu_clk", "ddrclk", "powersave";
+                };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index d0051a750587..f8288ea1b530 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -39,16 +39,16 @@ Boards:
 - OMAP3 Tobi with Overo : Commercial expansion board with daughter board
  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
- OMAP4 SDP : Software Developement Board
+- OMAP4 SDP : Software Development Board
  compatible = "ti,omap4-sdp", "ti,omap4430"
 - OMAP4 PandaBoard : Low cost community board
  compatible = "ti,omap4-panda", "ti,omap4430"
- OMAP3 EVM : Software Developement Board for OMAP35x, AM/DM37x
+- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
  compatible = "ti,omap3-evm", "ti,omap3"
- AM335X EVM : Software Developement Board for AM335x
+- AM335X EVM : Software Development Board for AM335x
  compatible = "ti,am335x-evm", "ti,am33xx", "ti,omap3"
 - AM335X Bone : Low cost community board
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
new file mode 100644
index 000000000000..433afe9cb590
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/psci.txt
@@ -0,0 +1,55 @@
+* Power State Coordination Interface (PSCI)
+Firmware implementing the PSCI functions described in ARM document number
+ARM DEN 0022A ("Power State Coordination Interface System Software on ARM
+processors") can be used by Linux to initiate various CPU-centric power
+operations.
+Issue A of the specification describes functions for CPU suspend, hotplug
+and migration of secure software.
+Functions are invoked by trapping to the privilege level of the PSCI
+firmware (specified as part of the binding below) and passing arguments
+in a manner similar to that specified by AAPCS:
+         r0             => 32-bit Function ID / return value
+        {r1 - r3}       => Parameters
+Note that the immediate field of the trapping instruction must be set
+to #0.
+Main node required properties:
+ - compatible    : Must be "arm,psci"
+ - method        : The method of calling the PSCI firmware. Permitted
+                   values are:
+                   "smc" : SMC #0, with the register assignments specified
+                           in this binding.
+                   "hvc" : HVC #0, with the register assignments specified
+                           in this binding.
+Main node optional properties:
+ - cpu_suspend   : Function ID for CPU_SUSPEND operation
+ - cpu_off       : Function ID for CPU_OFF operation
+ - cpu_on        : Function ID for CPU_ON operation
+ - migrate       : Function ID for MIGRATE operation
+Example:
+        psci {
+                compatible      = "arm,psci";
+                method          = "smc";
+                cpu_suspend     = <0x95c10000>;
+                cpu_off         = <0x95c10001>;
+                cpu_on          = <0x95c10002>;
+                migrate         = <0x95c10003>;
+        };
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
new file mode 100644
index 000000000000..5ddb2e9efaaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -0,0 +1,84 @@
+Device tree bindings for OMAP general purpose memory controllers (GPMC)
+The actual devices are instantiated from the child nodes of a GPMC node.
+Required properties:
+ - compatible:          Should be set to one of the following:
+                        ti,omap2420-gpmc (omap2420)
+                        ti,omap2430-gpmc (omap2430)
+                        ti,omap3430-gpmc (omap3430 & omap3630)
+                        ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
+                        ti,am3352-gpmc   (am335x devices)
+ - reg:                 A resource specifier for the register space
+                        (see the example below)
+ - ti,hwmods:           Should be set to "ti,gpmc" until the DT transition is
+                        completed.
+ - #address-cells:      Must be set to 2 to allow memory address translation
+ - #size-cells:         Must be set to 1 to allow CS address passing
+ - gpmc,num-cs:         The maximum number of chip-select lines that controller
+                        can support.
+ - gpmc,num-waitpins:   The maximum number of wait pins that controller can
+                        support.
+ - ranges:              Must be set up to reflect the memory layout with four
+                        integer values for each chip-select line in use:
+                           <cs-number> 0 <physical address of mapping> <size>
+                        Currently, calculated values derived from the contents
+                        of the per-CS register GPMC_CONFIG7 (as set up by the
+                        bootloader) are used for the physical address decoding.
+                        As this will change in the future, filling correct
+                        values here is a requirement.
+Timing properties for child nodes. All are optional and default to 0.
+ - gpmc,sync-clk:       Minimum clock period for synchronous mode, in picoseconds
+ Chip-select signal timings corresponding to GPMC_CONFIG2:
+ - gpmc,cs-on:          Assertion time
+ - gpmc,cs-rd-off:      Read deassertion time
+ - gpmc,cs-wr-off:      Write deassertion time
+ ADV signal timings corresponding to GPMC_CONFIG3:
+ - gpmc,adv-on:         Assertion time
+ - gpmc,adv-rd-off:     Read deassertion time
+ - gpmc,adv-wr-off:     Write deassertion time
+ WE signals timings corresponding to GPMC_CONFIG4:
+ - gpmc,we-on:          Assertion time
+ - gpmc,we-off:         Deassertion time
+ OE signals timings corresponding to GPMC_CONFIG4:
+ - gpmc,oe-on:          Assertion time
+ - gpmc,oe-off:         Deassertion time
+ Access time and cycle time timings corresponding to GPMC_CONFIG5:
+ - gpmc,page-burst-access: Multiple access word delay
+ - gpmc,access:         Start-cycle to first data valid delay
+ - gpmc,rd-cycle:       Total read cycle time
+ - gpmc,wr-cycle:       Total write cycle time
+The following are only applicable to OMAP3+ and AM335x:
+ - gpmc,wr-access
+ - gpmc,wr-data-mux-bus
+Example for an AM33xx board:
+        gpmc: gpmc@50000000 {
+                compatible = "ti,am3352-gpmc";
+                ti,hwmods = "gpmc";
+                reg = <0x50000000 0x2000>;
+                interrupts = <100>;
+                gpmc,num-cs = <8>;
+                gpmc,num-waitpins = <2>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
+                /* child nodes go here */
+        };
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 7337005ef5e1..cffc93d97f54 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -89,7 +89,7 @@ ID	Clock	Peripheral
 16      xor1    XOR DMA 1
 17      crypto  CESA engine
 18      pex1    PCIe Cntrl 1
-19      ge1     Gigabit Ethernet 0
+19      ge1     Gigabit Ethernet 1
 20      tdm     Time Division Mplx
 Required properties:
diff --git a/Documentation/devicetree/bindings/clock/prima2-clock.txt b/Documentation/devicetree/bindings/clock/prima2-clock.txt
new file mode 100644
index 000000000000..5016979c0f78
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/prima2-clock.txt
@@ -0,0 +1,73 @@
+* Clock bindings for CSR SiRFprimaII
+Required properties:
+- compatible: Should be "sirf,prima2-clkc"
+- reg: Address and length of the register set
+- interrupts: Should contain clock controller interrupt
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of prima2
+clocks and IDs.
+        Clock                   ID
+        ---------------------------
+        rtc                     0
+        osc                     1
+        pll1                    2
+        pll2                    3
+        pll3                    4
+        mem                     5
+        sys                     6
+        security                7
+        dsp                     8
+        gps                     9
+        mf                      10
+        io                      11
+        cpu                     12
+        uart0                   13
+        uart1                   14
+        uart2                   15
+        tsc                     16
+        i2c0                    17
+        i2c1                    18
+        spi0                    19
+        spi1                    20
+        pwmc                    21
+        efuse                   22
+        pulse                   23
+        dmac0                   24
+        dmac1                   25
+        nand                    26
+        audio                   27
+        usp0                    28
+        usp1                    29
+        usp2                    30
+        vip                     31
+        gfx                     32
+        mm                      33
+        lcd                     34
+        vpp                     35
+        mmc01                   36
+        mmc23                   37
+        mmc45                   38
+        usbpll                  39
+        usb0                    40
+        usb1                    41
+Examples:
+clks: clock-controller@88000000 {
+        compatible = "sirf,prima2-clkc";
+        reg = <0x88000000 0x1000>;
+        interrupts = <3>;
+        #clock-cells = <1>;
+};
+i2c0: i2c@b00e0000 {
+        cell-index = <0>;
+        compatible = "sirf,prima2-i2c";
+        reg = <0xb00e0000 0x10000>;
+        interrupts = <24>;
+        clocks = <&clks 17>;
+};
diff --git a/Documentation/devicetree/bindings/drm/exynos/g2d.txt b/Documentation/devicetree/bindings/drm/exynos/g2d.txt
new file mode 100644
index 000000000000..1eb124d35a99
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/g2d.txt
@@ -0,0 +1,22 @@
+Samsung 2D Graphic Accelerator using DRM frame work
+Samsung FIMG2D is a graphics 2D accelerator which supports Bit Block Transfer.
+We set the drawing-context registers for configuring rendering parameters and
+then start rendering.
+This driver is for SOCs which contain G2D IPs with version 4.1.
+Required properties:
+        -compatible:
+                should be "samsung,exynos-g2d-41".
+        -reg:
+                physical base address of the controller and length
+                of memory mapped region.
+        -interrupts:
+                interrupt combiner values.
+Example:
+        g2d {
+                compatible = "samsung,exynos-g2d-41";
+                reg = <0x10850000 0x1000>;
+                interrupts = <0 91 0>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/ina209.txt b/Documentation/devicetree/bindings/i2c/ina209.txt
new file mode 100644
index 000000000000..9dd2bee80840
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/ina209.txt
@@ -0,0 +1,18 @@
+ina209 properties
+Required properties:
+- compatible: Must be "ti,ina209"
+- reg: I2C address
+Optional properties:
+- shunt-resistor
+        Shunt resistor value in micro-Ohm
+Example:
+temp-sensor@4c {
+        compatible = "ti,ina209";
+        reg = <0x4c>;
+        shunt-resistor = <5000>;
+};
diff --git a/Documentation/devicetree/bindings/i2c/max6697.txt b/Documentation/devicetree/bindings/i2c/max6697.txt
new file mode 100644
index 000000000000..5f793998e4a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/max6697.txt
@@ -0,0 +1,64 @@
+max6697 properties
+Required properties:
+- compatible:
+        Should be one of
+                maxim,max6581
+                maxim,max6602
+                maxim,max6622
+                maxim,max6636
+                maxim,max6689
+                maxim,max6693
+                maxim,max6694
+                maxim,max6697
+                maxim,max6698
+                maxim,max6699
+- reg: I2C address
+Optional properties:
+- smbus-timeout-disable
+        Set to disable SMBus timeout. If not specified, SMBus timeout will be
+        enabled.
+- extended-range-enable
+        Only valid for MAX6581. Set to enable extended temperature range.
+        Extended temperature will be disabled if not specified.
+- beta-compensation-enable
+        Only valid for MAX6693 and MX6694. Set to enable beta compensation on
+        remote temperature channel 1.
+        Beta compensation will be disabled if not specified.
+- alert-mask
+        Alert bit mask. Alert disabled for bits set.
+        Select bit 0 for local temperature, bit 1..7 for remote temperatures.
+        If not specified, alert will be enabled for all channels.
+- over-temperature-mask
+        Over-temperature bit mask. Over-temperature reporting disabled for
+        bits set.
+        Select bit 0 for local temperature, bit 1..7 for remote temperatures.
+        If not specified, over-temperature reporting will be enabled for all
+        channels.
+- resistance-cancellation
+        Boolean for all chips other than MAX6581. Set to enable resistance
+        cancellation on remote temperature channel 1.
+        For MAX6581, resistance cancellation enabled for all channels if
+        specified as boolean, otherwise as per bit mask specified.
+        Only supported for remote temperatures (bit 1..7).
+        If not specified, resistance cancellation will be disabled for all
+        channels.
+- transistor-ideality
+        For MAX6581 only. Two values; first is bit mask, second is ideality
+        select value as per MAX6581 data sheet. Select bit 1..7 for remote
+        channels.
+        Transistor ideality will be initialized to default (1.008) if not
+        specified.
+Example:
+temp-sensor@1a {
+        compatible = "maxim,max6697";
+        reg = <0x1a>;
+        smbus-timeout-disable;
+        resistance-cancellation;
+        alert-mask = <0x72>;
+        over-temperature-mask = <0x7f>;
+};
diff --git a/Documentation/devicetree/bindings/input/imx-keypad.txt b/Documentation/devicetree/bindings/input/imx-keypad.txt
new file mode 100644
index 000000000000..2ebaf7d26843
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/imx-keypad.txt
@@ -0,0 +1,53 @@
+* Freescale i.MX Keypad Port(KPP) device tree bindings
+The KPP is designed to interface with a keypad matrix with 2-point contact
+or 3-point contact keys. The KPP is designed to simplify the software task
+of scanning a keypad matrix. The KPP is capable of detecting, debouncing,
+and decoding one or multiple keys pressed simultaneously on a keypad.
+Required SoC Specific Properties:
+- compatible: Should be "fsl,<soc>-kpp".
+- reg: Physical base address of the KPP and length of memory mapped
+  region.
+- interrupts: The KPP interrupt number to the CPU(s).
+- clocks: The clock provided by the SoC to the KPP. Some SoCs use dummy
+clock(The clock for the KPP is provided by the SoCs automatically).
+Required Board Specific Properties:
+- pinctrl-names: The definition can be found at
+pinctrl/pinctrl-bindings.txt.
+- pinctrl-0: The definition can be found at
+pinctrl/pinctrl-bindings.txt.
+- linux,keymap: The definition can be found at
+bindings/input/matrix-keymap.txt.
+Example:
+kpp: kpp@73f94000 {
+        compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
+        reg = <0x73f94000 0x4000>;
+        interrupts = <60>;
+        clocks = <&clks 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp_1>;
+        linux,keymap = <0x00000067      /* KEY_UP */
+                        0x0001006c      /* KEY_DOWN */
+                        0x00020072      /* KEY_VOLUMEDOWN */
+                        0x00030066      /* KEY_HOME */
+                        0x0100006a      /* KEY_RIGHT */
+                        0x01010069      /* KEY_LEFT */
+                        0x0102001c      /* KEY_ENTER */
+                        0x01030073      /* KEY_VOLUMEUP */
+                        0x02000040      /* KEY_F6 */
+                        0x02010042      /* KEY_F8 */
+                        0x02020043      /* KEY_F9 */
+                        0x02030044      /* KEY_F10 */
+                        0x0300003b      /* KEY_F1 */
+                        0x0301003c      /* KEY_F2 */
+                        0x0302003d      /* KEY_F3 */
+                        0x03030074>;    /* KEY_POWER */
+};
diff --git a/Documentation/devicetree/bindings/input/lpc32xx-key.txt b/Documentation/devicetree/bindings/input/lpc32xx-key.txt
index 31afd5014c48..bcf62f856358 100644
--- a/Documentation/devicetree/bindings/input/lpc32xx-key.txt
+++ b/Documentation/devicetree/bindings/input/lpc32xx-key.txt
@@ -1,19 +1,22 @@
 NXP LPC32xx Key Scan Interface
+This binding is based on the matrix-keymap binding with the following
+changes:
 Required Properties:
 - compatible: Should be "nxp,lpc3220-key"
 - reg: Physical base address of the controller and length of memory mapped
  region.
 - interrupts: The interrupt number to the cpu.
- keypad,num-rows: Number of rows and columns, e.g. 1: 1x1, 6: 6x6
- keypad,num-columns: Must be equal to keypad,num-rows since LPC32xx only
-  supports square matrices
 - nxp,debounce-delay-ms: Debounce delay in ms
 - nxp,scan-delay-ms: Repeated scan period in ms
 - linux,keymap: the key-code to be reported when the key is pressed
  and released, see also
  Documentation/devicetree/bindings/input/matrix-keymap.txt
+Note: keypad,num-rows and keypad,num-columns are required, and must be equal
+since LPC32xx only supports square matrices
 Example:
        key@40050000 {
diff --git a/Documentation/devicetree/bindings/input/matrix-keymap.txt b/Documentation/devicetree/bindings/input/matrix-keymap.txt
index 3cd8b98ccd2d..c54919fad17e 100644
--- a/Documentation/devicetree/bindings/input/matrix-keymap.txt
+++ b/Documentation/devicetree/bindings/input/matrix-keymap.txt
@@ -9,6 +9,12 @@ Required properties:
        row << 24 | column << 16 | key-code
 Optional properties:
+Properties for the number of rows and columns are optional because some
+drivers will use fixed values for these.
+- keypad,num-rows: Number of row lines connected to the keypad controller.
+- keypad,num-columns: Number of column lines connected to the keypad
+  controller.
 Some users of this binding might choose to specify secondary keymaps for
 cases where there is a modifier key such as a Fn key. Proposed names
 for said properties are "linux,fn-keymap" or with another descriptive
@@ -17,3 +23,5 @@ word for the modifier other from "Fn".
 Example:
        linux,keymap = < 0x00030012
                         0x0102003a >;
+        keypad,num-rows = <2>;
+        keypad,num-columns = <8>;
diff --git a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
index 72683be6de35..2995fae7ee47 100644
--- a/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
+++ b/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt
@@ -1,7 +1,18 @@
 * Tegra keyboard controller
+The key controller has maximum 24 pins to make matrix keypad. Any pin
+can be configured as row or column. The maximum column pin can be 8
+and maximum row pins can be 16 for Tegra20/Tegra30.
 Required properties:
 - compatible: "nvidia,tegra20-kbc"
+- reg: Register base address of KBC.
+- interrupts: Interrupt number for the KBC.
+- nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
+  array of pin numbers which is used as rows.
+- nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
+  array of pin numbers which is used as column.
+- linux,keymap: The keymap for keys as described in the binding document
+  devicetree/bindings/input/matrix-keymap.txt.
 Optional properties, in addition to those specified by the shared
 matrix-keyboard bindings:
@@ -19,5 +30,16 @@ Example:
 keyboard: keyboard {
        compatible = "nvidia,tegra20-kbc";
        reg = <0x7000e200 0x100>;
+        interrupts = <0 85 0x04>;
        nvidia,ghost-filter;
+        nvidia,debounce-delay-ms = <640>;
+        nvidia,kbc-row-pins = <0 1 2>;    /* pin 0, 1, 2 as rows */
+        nvidia,kbc-col-pins = <11 12 13>; /* pin 11, 12, 13 as columns */
+        linux,keymap = <0x00000074
+                        0x00010067
+                        0x00020066
+                        0x01010068
+                        0x02000069
+                        0x02010070
+                        0x02020071>;
 };
diff --git a/Documentation/devicetree/bindings/input/omap-keypad.txt b/Documentation/devicetree/bindings/input/omap-keypad.txt
index f2fa5e10493d..34ed1c60ff95 100644
--- a/Documentation/devicetree/bindings/input/omap-keypad.txt
+++ b/Documentation/devicetree/bindings/input/omap-keypad.txt
@@ -6,19 +6,16 @@ A key can be placed at each intersection of a unique row and a unique column.
 The keypad controller can sense a key-press and key-release and report the
 event using a interrupt to the cpu.
+This binding is based on the matrix-keymap binding with the following
+changes:
+keypad,num-rows and keypad,num-columns are required.
 Required SoC Specific Properties:
 - compatible: should be one of the following
   - "ti,omap4-keypad": For controllers compatible with omap4 keypad
      controller.
-Required Board Specific Properties, in addition to those specified by
-the shared matrix-keyboard bindings:
- keypad,num-rows: Number of row lines connected to the keypad
-  controller.
- keypad,num-columns: Number of column lines connected to the
-  keypad controller.
 Optional Properties specific to linux:
 - linux,keypad-no-autorepeat: do no enable autorepeat feature.
diff --git a/Documentation/devicetree/bindings/input/tca8418_keypad.txt b/Documentation/devicetree/bindings/input/tca8418_keypad.txt
index 2a1538f0053f..255185009167 100644
--- a/Documentation/devicetree/bindings/input/tca8418_keypad.txt
+++ b/Documentation/devicetree/bindings/input/tca8418_keypad.txt
@@ -1,8 +1,10 @@
+This binding is based on the matrix-keymap binding with the following
+changes:
+keypad,num-rows and keypad,num-columns are required.
 Required properties:
 - compatible: "ti,tca8418"
 - reg: the I2C address
 - interrupts: IRQ line number, should trigger on falling edge
- keypad,num-rows: The number of rows
- keypad,num-columns: The number of columns
 - linux,keymap: Keys definitions, see keypad-matrix.
diff --git a/Documentation/devicetree/bindings/gpio/leds-ns2.txt b/Documentation/devicetree/bindings/leds/leds-ns2.txt
index aef3aca34d2d..aef3aca34d2d 100644
--- a/Documentation/devicetree/bindings/gpio/leds-ns2.txt
+++ b/Documentation/devicetree/bindings/leds/leds-ns2.txt
diff --git a/Documentation/devicetree/bindings/mfd/tps6507x.txt b/Documentation/devicetree/bindings/mfd/tps6507x.txt
new file mode 100755
index 000000000000..8fffa3c5ed40
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/tps6507x.txt
@@ -0,0 +1,91 @@
+TPS6507x Power Management Integrated Circuit
+Required properties:
+- compatible: "ti,tps6507x"
+- reg: I2C slave address
+- regulators: This is the list of child nodes that specify the regulator
+  initialization data for defined regulators. Not all regulators for the
+  given device need to be present. The definition for each of these nodes
+  is defined using the standard binding for regulators found at
+  Documentation/devicetree/bindings/regulator/regulator.txt.
+  The regulator is matched with the regulator-compatible.
+  The valid regulator-compatible values are:
+  tps6507x: vdcdc1, vdcdc2, vdcdc3, vldo1, vldo2
+- xxx-supply: Input voltage supply regulator.
+  These entries are required if regulators are enabled for a device.
+  Missing of these properties can cause the regulator registration
+  fails.
+  If some of input supply is powered through battery or always-on
+  supply then also it is require to have these parameters with proper
+  node handle of always on power supply.
+  tps6507x:
+       vindcdc1_2-supply: VDCDC1 and VDCDC2 input.
+       vindcdc3-supply  : VDCDC3 input.
+       vldo1_2-supply   : VLDO1 and VLDO2 input.
+Regulator Optional properties:
+- defdcdc_default: It's property of DCDC2 and DCDC3 regulators.
+                        0: If defdcdc pin of DCDC2/DCDC3 is pulled to GND.
+                        1: If defdcdc pin of DCDC2/DCDC3 is driven HIGH.
+  If this property is not defined, it defaults to 0 (not enabled).
+Example:
+        pmu: tps6507x@48 {
+                compatible = "ti,tps6507x";
+                reg = <0x48>;
+                vindcdc1_2-supply = <&vbat>;
+                vindcdc3-supply = <...>;
+                vinldo1_2-supply = <...>;
+                regulators {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        vdcdc1_reg: regulator@0 {
+                                regulator-compatible = "VDCDC1";
+                                reg = <0>;
+                                regulator-min-microvolt = <3150000>;
+                                regulator-max-microvolt = <3450000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vdcdc2_reg: regulator@1 {
+                                regulator-compatible = "VDCDC2";
+                                reg = <1>;
+                                regulator-min-microvolt = <1710000>;
+                                regulator-max-microvolt = <3450000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                defdcdc_default = <1>;
+                        };
+                        vdcdc3_reg: regulator@2 {
+                                regulator-compatible = "VDCDC3";
+                                reg = <2>;
+                                regulator-min-microvolt = <950000>
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                defdcdc_default = <1>;
+                        };
+                        ldo1_reg: regulator@3 {
+                                regulator-compatible = "LDO1";
+                                reg = <3>;
+                                regulator-min-microvolt = <1710000>;
+                                regulator-max-microvolt = <1890000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo2_reg: regulator@4 {
+                                regulator-compatible = "LDO2";
+                                reg = <4>;
+                                regulator-min-microvolt = <1140000>;
+                                regulator-max-microvolt = <1320000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
index cb4291e3b1d1..a5bdff400002 100644
--- a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
+++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt
@@ -1,7 +1,7 @@
 * DMA Engine.
 The Octeon DMA Engine transfers between the Boot Bus and main memory.
-The DMA Engine will be refered to by phandle by any device that is
+The DMA Engine will be referred to by phandle by any device that is
 connected to it.
 Properties:
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index 792768953330..6d1c0988cfc7 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -4,18 +4,18 @@
 The Synopsis designware mobile storage host controller is used to interface
 a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
 differences between the core Synopsis dw mshc controller properties described
-by synposis-dw-mshc.txt and the properties used by the Samsung Exynos specific
+by synopsis-dw-mshc.txt and the properties used by the Samsung Exynos specific
 extensions to the Synopsis Designware Mobile Storage Host Controller.
 Required Properties:
 * compatible: should be
        - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
-          specific extentions.
+          specific extensions.
        - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
-          specific extentions.
+          specific extensions.
        - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
-          specific extentions.
+          specific extensions.
 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
  unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
index 97e9e315400d..3b3a1ee055ff 100644
--- a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
@@ -55,5 +55,5 @@ Example:
        };
        Note: This example shows both SoC specific and board specific properties
-        in a single device node. The properties can be actually be seperated
+        in a single device node. The properties can be actually be separated
        into SoC specific node and board specific node.
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
new file mode 100644
index 000000000000..e7f8d7ed47eb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -0,0 +1,80 @@
+Device tree bindings for GPMC connected NANDs
+GPMC connected NAND (found on OMAP boards) are represented as child nodes of
+the GPMC controller with a name of "nand".
+All timing relevant properties as well as generic gpmc child properties are
+explained in a separate documents - please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+For NAND specific properties such as ECC modes or bus width, please refer to
+Documentation/devicetree/bindings/mtd/nand.txt
+Required properties:
+ - reg:         The CS line the peripheral is connected to
+Optional properties:
+ - nand-bus-width:              Set this numeric value to 16 if the hardware
+                                is wired that way. If not specified, a bus
+                                width of 8 is assumed.
+ - ti,nand-ecc-opt:             A string setting the ECC layout to use. One of:
+                "sw"            Software method (default)
+                "hw"            Hardware method
+                "hw-romcode"    gpmc hamming mode method & romcode layout
+                "bch4"          4-bit BCH ecc code
+                "bch8"          8-bit BCH ecc code
+ - elm_id:      Specifies elm device node. This is required to support BCH
+                error correction using ELM module.
+For inline partiton table parsing (optional):
+ - #address-cells: should be set to 1
+ - #size-cells: should be set to 1
+Example for an AM33xx board:
+        gpmc: gpmc@50000000 {
+                compatible = "ti,am3352-gpmc";
+                ti,hwmods = "gpmc";
+                reg = <0x50000000 0x1000000>;
+                interrupts = <100>;
+                gpmc,num-cs = <8>;
+                gpmc,num-waitpins = <2>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0x08000000 0x2000>;       /* CS0: NAND */
+                elm_id = <&elm>;
+                nand@0,0 {
+                        reg = <0 0 0>; /* CS0, offset 0 */
+                        nand-bus-width = <16>;
+                        ti,nand-ecc-opt = "bch8";
+                        gpmc,sync-clk = <0>;
+                        gpmc,cs-on = <0>;
+                        gpmc,cs-rd-off = <44>;
+                        gpmc,cs-wr-off = <44>;
+                        gpmc,adv-on = <6>;
+                        gpmc,adv-rd-off = <34>;
+                        gpmc,adv-wr-off = <44>;
+                        gpmc,we-off = <40>;
+                        gpmc,oe-off = <54>;
+                        gpmc,access = <64>;
+                        gpmc,rd-cycle = <82>;
+                        gpmc,wr-cycle = <82>;
+                        gpmc,wr-access = <40>;
+                        gpmc,wr-data-mux-bus = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* partitions go here */
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
new file mode 100644
index 000000000000..deec9da224a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -0,0 +1,43 @@
+Device tree bindings for GPMC connected OneNANDs
+GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of
+the GPMC controller with a name of "onenand".
+All timing relevant properties as well as generic gpmc child properties are
+explained in a separate documents - please refer to
+Documentation/devicetree/bindings/bus/ti-gpmc.txt
+Required properties:
+ - reg:                 The CS line the peripheral is connected to
+Optional properties:
+ - dma-channel:         DMA Channel index
+For inline partiton table parsing (optional):
+ - #address-cells: should be set to 1
+ - #size-cells: should be set to 1
+Example for an OMAP3430 board:
+        gpmc: gpmc@6e000000 {
+                compatible = "ti,omap3430-gpmc";
+                ti,hwmods = "gpmc";
+                reg = <0x6e000000 0x1000000>;
+                interrupts = <20>;
+                gpmc,num-cs = <8>;
+                gpmc,num-waitpins = <4>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                onenand@0 {
+                        reg = <0 0 0>; /* CS0, offset 0 */
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /* partitions go here */
+                };
+        };
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index 6ddd0286a9b7..ecfdf756d10f 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -24,6 +24,8 @@ Required properties:
 Optional properties:
 - ti,hwmods             : Must be "cpgmac0"
 - no_bd_ram             : Must be 0 or 1
+- dual_emac             : Specifies Switch to act as Dual EMAC
+- dual_emac_res_vlan    : Specifies VID to be used to segregate the ports
 Note: "ti,hwmods" field is used to fetch the base address and irq
 resources from TI, omap hwmod data base during device registration.
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
new file mode 100644
index 000000000000..dff0e5f995e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -0,0 +1,60 @@
+* Allwinner A1X Pin Controller
+The pins controlled by sunXi pin controller are organized in banks,
+each bank has 32 pins.  Each pin has 7 multiplexing functions, with
+the first two functions being GPIO in and out. The configuration on
+the pins includes drive strength and pull-up.
+Required properties:
+- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:
+  sun5i-a13.
+- reg: Should contain the register physical address and length for the
+  pin controller.
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices.
+A pinctrl node should contain at least one subnodes representing the
+pinctrl groups available on the machine. Each subnode will list the
+pins it needs, and how they should be configured, with regard to muxer
+configuration, drive strength and pullups. If one of these options is
+not set, its actual value will be unspecified.
+Required subnode-properties:
+- allwinner,pins: List of strings containing the pin name.
+- allwinner,function: Function to mux the pins listed above to.
+Optional subnode-properties:
+- allwinner,drive: Integer. Represents the current sent to the pin
+    0: 10 mA
+    1: 20 mA
+    2: 30 mA
+    3: 40 mA
+- allwinner,pull: Integer.
+    0: No resistor
+    1: Pull-up resistor
+    2: Pull-down resistor
+Examples:
+pinctrl@01c20800 {
+        compatible = "allwinner,sun5i-a13-pinctrl";
+        reg = <0x01c20800 0x400>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        uart1_pins_a: uart1@0 {
+                allwinner,pins = "PE10", "PE11";
+                allwinner,function = "uart1";
+                allwinner,drive = <0>;
+                allwinner,pull = <0>;
+        };
+        uart1_pins_b: uart1@1 {
+                allwinner,pins = "PG3", "PG4";
+                allwinner,function = "uart1";
+                allwinner,drive = <0>;
+                allwinner,pull = <0>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
new file mode 100644
index 000000000000..e204d009f16c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
@@ -0,0 +1,120 @@
+NVIDIA Tegra114 pinmux controller
+The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
+pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
+nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
+a baseline, and only documents the differences between the two bindings.
+Required properties:
+- compatible: "nvidia,tegra114-pinmux"
+- reg: Should contain the register physical address and length for each of
+  the pad control and mux registers. The first bank of address must be the
+  driver strength pad control register address and second bank address must
+  be pinmux register address.
+Tegra114 adds the following optional properties for pin configuration subnodes:
+- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
+- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
+- nvidia,lock: Integer. Lock the pin configuration against further changes
+    until reset. 0: no, 1: yes.
+- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
+- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
+- nvidia,drive-type: Integer. Valid range 0...3.
+As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
+which groups support which functionality.
+Valid values for pin and group names are:
+  per-pin mux groups:
+    These all support nvidia,function, nvidia,tristate, nvidia,pull,
+    nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
+    nvidia,io-reset and nvidia,rcv-sel.
+    ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
+    ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
+    ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
+    dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
+    sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
+    sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
+    ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
+    uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
+    uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
+    gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
+    clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
+    gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
+    gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
+    gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
+    gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+    gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
+    gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
+    gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
+    gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
+    sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+    sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
+    pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
+    pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
+    kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
+    kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
+    kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+    kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
+    cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
+    dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
+    dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
+    gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
+    gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
+    sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
+    sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
+    gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
+    sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
+  drive groups:
+    These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
+    nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
+    support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
+    and nvidia,drive-type.
+    ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
+    dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
+    gmh, owr, uda.
+Example:
+        pinmux: pinmux {
+                compatible = "nvidia,tegra114-pinmux";
+                reg = <0x70000868 0x148         /* Pad control registers */
+                       0x70003000 0x40c>;       /* PinMux registers */
+        };
+Example board file extract:
+        pinctrl {
+                sdmmc4_default: pinmux {
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4",
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+        sdhci@78000400 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sdmmc4_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e97a27856b21..4598a47aa0cd 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -7,9 +7,9 @@ on-chip controllers onto these pads.
 Required Properties:
 - compatible: should be one of the following.
-  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
+  - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
-  - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
+  - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
-  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
+  - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
 - reg: Base address of the pin controller hardware module and length of
  the address space it occupies.
@@ -142,7 +142,7 @@ the following format 'pinctrl{n}' where n is a unique number for the alias.
 Example: A pin-controller node with pin banks:
        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
@@ -185,7 +185,7 @@ Example: A pin-controller node with pin banks:
 Example 1: A pin-controller node with pin groups.
        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
@@ -230,7 +230,7 @@ Example 1: A pin-controller node with pin groups.
 Example 2: A pin-controller node with external wakeup interrupt controller node.
        pinctrl_1: pinctrl@11000000 {
-                compatible = "samsung,pinctrl-exynos4210";
+                compatible = "samsung,exynos4210-pinctrl";
                reg = <0x11000000 0x1000>;
                interrupts = <0 46 0>
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
new file mode 100644
index 000000000000..9a2f3f420526
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt
@@ -0,0 +1,140 @@
+ST Ericsson Nomadik pinmux controller
+Required properties:
+- compatible: "stericsson,nmk-pinctrl", "stericsson,nmk-pinctrl-db8540",
+              "stericsson,nmk-pinctrl-stn8815"
+- reg: Should contain the register physical address and length of the PRCMU.
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as input, output, pull up, pull down...
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+Required subnode-properties:
+- ste,pins : An array of strings. Each string contains the name of a pin or
+    group.
+Optional subnode-properties:
+- ste,function: A string containing the name of the function to mux to the
+  pin or group.
+- ste,config: Handle of pin configuration node (e.g. ste,config = <&slpm_in_wkup_pdis>)
+- ste,input : <0/1/2>
+        0: input with no pull
+        1: input with pull up,
+        2: input with pull down,
+- ste,output: <0/1/2>
+        0: output low,
+        1: output high,
+        2: output (value is not specified).
+- ste,sleep: <0/1>
+        0: sleep mode disable,
+        1: sleep mode enable.
+- ste,sleep-input: <0/1/2/3>
+        0: sleep input with no pull,
+        1: sleep input with pull up,
+        2: sleep input with pull down.
+        3: sleep input and keep last input configuration (no pull, pull up or pull down).
+- ste,sleep-output: <0/1/2>
+        0: sleep output low,
+        1: sleep output high,
+        2: sleep output (value is not specified).
+- ste,sleep-gpio: <0/1>
+        0: disable sleep gpio mode,
+        1: enable sleep gpio mode.
+- ste,sleep-wakeup: <0/1>
+        0: wake-up detection enabled,
+        1: wake-up detection disabled.
+- ste,sleep-pull-disable: <0/1>
+        0: GPIO pull-up or pull-down resistor is enabled, when pin is an input,
+        1: GPIO pull-up and pull-down resistor are disabled.
+Example board file extract:
+        pinctrl@80157000 {
+                compatible = "stericsson,nmk-pinctrl";
+                reg = <0x80157000 0x2000>;
+                pinctrl-names = "default";
+                slpm_in_wkup_pdis: slpm_in_wkup_pdis {
+                        ste,sleep = <1>;
+                        ste,sleep-input = <3>;
+                        ste,sleep-wakeup = <1>;
+                        ste,sleep-pull-disable = <0>;
+                };
+                slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
+                        ste,sleep = <1>;
+                        ste,sleep-output = <1>;
+                        ste,sleep-wakeup = <1>;
+                        ste,sleep-pull-disable = <0>;
+                };
+                slpm_out_wkup_pdis: slpm_out_wkup_pdis {
+                        ste,sleep = <1>;
+                        ste,sleep-output = <2>;
+                        ste,sleep-wakeup = <1>;
+                        ste,sleep-pull-disable = <0>;
+                };
+                uart0 {
+                        uart0_default_mux: uart0_mux {
+                                u0_default_mux {
+                                        ste,function = "u0";
+                                        ste,pins = "u0_a_1";
+                                };
+                        };
+                        uart0_default_mode: uart0_default {
+                                uart0_default_cfg1 {
+                                        ste,pins = "GPIO0", "GPIO2";
+                                        ste,input = <1>;
+                                };
+                                uart0_default_cfg2 {
+                                        ste,pins = "GPIO1", "GPIO3";
+                                        ste,output = <1>;
+                                };
+                        };
+                        uart0_sleep_mode: uart0_sleep {
+                                uart0_sleep_cfg1 {
+                                        ste,pins = "GPIO0", "GPIO2";
+                                        ste,config = <&slpm_in_wkup_pdis>;
+                                };
+                                uart0_sleep_cfg2 {
+                                        ste,pins = "GPIO1";
+                                        ste,config = <&slpm_out_hi_wkup_pdis>;
+                                };
+                                uart0_sleep_cfg3 {
+                                        ste,pins = "GPIO3";
+                                        ste,config = <&slpm_out_wkup_pdis>;
+                                };
+                        };
+                };
+        };
+        uart@80120000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x80120000 0x1000>;
+                interrupts = <0 11 0x4>;
+                pinctrl-names = "default","sleep";
+                pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
+                pinctrl-1 = <&uart0_sleep_mode>;
+        };
diff --git a/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt b/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt
new file mode 100644
index 000000000000..9a599d27bd75
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt
@@ -0,0 +1,13 @@
+* QNAP Power Off
+QNAP NAS devices have a microcontroller controlling the main power
+supply. This microcontroller is connected to UART1 of the Kirkwood and
+Orion5x SoCs. Sending the charactor 'A', at 19200 baud, tells the
+microcontroller to turn the power off. This driver adds a handler to
+pm_power_off which is called to turn the power off.
+Required Properties:
+- compatible: Should be "qnap,power-off"
+- reg: Address and length of the register set for UART1
+- clocks: tclk clock
diff --git a/Documentation/devicetree/bindings/power_supply/restart-poweroff.txt b/Documentation/devicetree/bindings/power_supply/restart-poweroff.txt
new file mode 100644
index 000000000000..5776e684afda
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/restart-poweroff.txt
@@ -0,0 +1,8 @@
+* Restart Power Off
+Buffalo Linkstation LS-XHL and LS-CHLv2, and other devices power off
+by restarting and letting u-boot keep hold of the machine until the
+user presses a button.
+Required Properties:
+- compatible: Should be "restart-poweroff"
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
index b039bcbee134..07abf0f2f440 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
@@ -8,9 +8,9 @@ Properties:
        Definition: Must include "fsl,srio" for IP blocks with IP Block
        Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
-        Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major
+        Optionally, a compatible string of "fsl,srio-vX.Y" where X is Major
        version in IP Block Revision Register and Y is Minor version.  If this
-        compatiable is provided it should be ordered before "fsl,srio".
+        compatible is provided it should be ordered before "fsl,srio".
   - reg
        Usage: required
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
index 357758cb6e92..758eae24082a 100644
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -9,6 +9,11 @@ Required properties:
 - anatop-min-voltage: Minimum voltage of this regulator
 - anatop-max-voltage: Maximum voltage of this regulator
+Optional properties:
+- anatop-delay-reg-offset: Anatop MFD step time register offset
+- anatop-delay-bit-shift: Bit shift for the step time register
+- anatop-delay-bit-width: Number of bits used in the step time register
 Any property defined as part of the core regulator
 binding, defined in regulator.txt, can also be used.
@@ -23,6 +28,9 @@ Example:
                anatop-reg-offset = <0x140>;
                anatop-vol-bit-shift = <9>;
                anatop-vol-bit-width = <5>;
+                anatop-delay-reg-offset = <0x170>;
+                anatop-delay-bit-shift = <24>;
+                anatop-delay-bit-width = <2>;
                anatop-min-bit-val = <1>;
                anatop-min-voltage = <725000>;
                anatop-max-voltage = <1300000>;
diff --git a/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt b/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt
new file mode 100644
index 000000000000..a35ff99003a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt
@@ -0,0 +1,152 @@
+* Samsung S5M8767 Voltage and Current Regulator
+The Samsung S5M8767 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of s5m8767.
+Required properties:
+- compatible: Should be "samsung,s5m8767-pmic".
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+- s5m8767,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+- s5m8767,pmic-buck3-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck3 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+- s5m8767,pmic-buck4-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck4 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+- s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used
+  for selecting GPIO DVS lines. It is one-to-one mapped to dvs gpio lines.
+[1] If none of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
+    property is specified, the 's5m8767,pmic-buck[2/3/4]-dvs-voltage'
+    property should specify atleast one voltage level (which would be a
+    safe operating voltage).
+    If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
+    property is specified, then all the eight voltage values for the
+    's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified.
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from s5m8767 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- s5m8767,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- s5m8767,pmic-buck3-uses-gpio-dvs: 'buck3' can be controlled by gpio dvs.
+- s5m8767,pmic-buck4-uses-gpio-dvs: 'buck4' can be controlled by gpio dvs.
+Additional properties required if either of the optional properties are used:
+- s5m8767,pmic-buck234-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+- s5m8767,pmic-buck-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+Regulators: The regulators of s5m8767 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+        regulator_name {
+                ldo1_reg: LDO1 {
+                        regulator-name = "VDD_ALIVE_1.0V";
+                        regulator-min-microvolt = <1100000>;
+                        regulator-max-microvolt = <1100000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        op_mode = <1>; /* Normal Mode */
+                };
+        };
+The above regulator entries are defined in regulator bindings documentation
+except op_mode description.
+        - op_mode: describes the different operating modes of the LDO's with
+                power mode change in SOC. The different possible values are,
+                0 - always off mode
+                1 - on in normal mode
+                2 - low power mode
+                3 - suspend mode
+The following are the names of the regulators that the s5m8767 pmic block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of s5m8767.
+        - LDOn
+                  - valid values for n are 1 to 28
+                  - Example: LDO0, LD01, LDO28
+        - BUCKn
+                  - valid values for n are 1 to 9.
+                  - Example: BUCK1, BUCK2, BUCK9
+The bindings inside the regulator nodes use the standard regulator bindings
+which are documented elsewhere.
+Example:
+        s5m8767_pmic@66 {
+                compatible = "samsung,s5m8767-pmic";
+                reg = <0x66>;
+                s5m8767,pmic-buck2-uses-gpio-dvs;
+                s5m8767,pmic-buck3-uses-gpio-dvs;
+                s5m8767,pmic-buck4-uses-gpio-dvs;
+                s5m8767,pmic-buck-default-dvs-idx = <0>;
+                s5m8767,pmic-buck-dvs-gpios = <&gpx0 0 1 0 0>, /* DVS1 */
+                                                 <&gpx0 1 1 0 0>, /* DVS2 */
+                                                 <&gpx0 2 1 0 0>; /* DVS3 */
+                s5m8767,pmic-buck-ds-gpios = <&gpx2 3 1 0 0>, /* SET1 */
+                                                <&gpx2 4 1 0 0>, /* SET2 */
+                                                <&gpx2 5 1 0 0>; /* SET3 */
+                s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
+                                                 <1250000>, <1200000>,
+                                                 <1150000>, <1100000>,
+                                                 <1000000>, <950000>;
+                s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
+                                                 <1100000>, <1100000>,
+                                                 <1000000>, <1000000>,
+                                                 <1000000>, <1000000>;
+                s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>;
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VDD_ABB_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                op_mode = <1>; /* Normal Mode */
+                        };
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VDD_ALIVE_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "VDD_MIF_1.2V";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt b/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt
new file mode 100644
index 000000000000..2f7e44a96414
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt
@@ -0,0 +1,27 @@
+TPS51632 Voltage regulators
+Required properties:
+- compatible: Must be "ti,tps51632"
+- reg: I2C slave address
+Optional properties:
+- ti,enable-pwm-dvfs: Enable the DVFS voltage control through the PWM interface.
+- ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this
+        will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage
+        step is 10mV as per datasheet.
+Any property defined as part of the core regulator binding, defined in
+regulator.txt, can also be used.
+Example:
+        tps51632 {
+                compatible = "ti,tps51632";
+                reg =  <0x43>;
+                regulator-name = "tps51632-vout";
+                regulator-min-microvolt = <500000>;
+                regulator-max-microvolt = <1500000>;
+                regulator-boot-on;
+                ti,enable-pwm-dvfs;
+                ti,dvfs-step-20mV;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt b/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt
index c8ca6b8f6582..1b20c3dbcdb8 100644
--- a/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/tps62360-regulator.txt
@@ -17,9 +17,9 @@ Optional properties:
 - ti,vsel1-gpio: Gpio for controlling VSEL1 line.
  If this property is missing, then assume that there is no GPIO
  for vsel1 control.
- ti,vsel0-state-high: Inital state of vsel0 input is high.
+- ti,vsel0-state-high: Initial state of vsel0 input is high.
  If this property is missing, then assume the state as low (0).
- ti,vsel1-state-high: Inital state of vsel1 input is high.
+- ti,vsel1-state-high: Initial state of vsel1 input is high.
  If this property is missing, then assume the state as low (0).
 Any property defined as part of the core regulator binding, defined in
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
index 90ec45fd33ec..7ac7259fe9ea 100644
--- a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
@@ -7,7 +7,7 @@ Required properties:
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: Two interrupt numbers to the cpu should be specified. First
-  interrupt number is the rtc alarm interupt and second interrupt number
+  interrupt number is the rtc alarm interrupt and second interrupt number
  is the rtc tick interrupt. The number of cells representing a interrupt
  depends on the parent interrupt controller.
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
new file mode 100644
index 000000000000..392a4493eebd
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -0,0 +1,24 @@
+NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
+Required properties:
+- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
+- reg: Should contain UART controller registers location and length.
+- interrupts: Should contain UART controller interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this UART controller.
+Optional properties:
+- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
+                only if all 8 lines of UART controller are pinmuxed.
+Example:
+serial@70006000 {
+        compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
+        reg = <0x70006000 0x40>;
+        reg-shift = <2>;
+        interrupts = <0 36 0x04>;
+        nvidia,dma-request-selector = <&apbdma 8>;
+        nvidia,enable-modem-interrupt;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/sound/ak4642.txt b/Documentation/devicetree/bindings/sound/ak4642.txt
new file mode 100644
index 000000000000..623d4e70ae11
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ak4642.txt
@@ -0,0 +1,17 @@
+AK4642 I2C transmitter
+This device supports I2C mode only.
+Required properties:
+  - compatible : "asahi-kasei,ak4642" or "asahi-kasei,ak4643" or "asahi-kasei,ak4648"
+  - reg : The chip select number on the I2C bus
+Example:
+&i2c {
+        ak4648: ak4648@0x12 {
+                compatible = "asahi-kasei,ak4642";
+                reg = <0x12>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt
index a850fb9c88ea..e2cd1d7539e5 100644
--- a/Documentation/devicetree/bindings/sound/cs4271.txt
+++ b/Documentation/devicetree/bindings/sound/cs4271.txt
@@ -20,6 +20,18 @@ Optional properties:
                !RESET pin
 - cirrus,amuteb-eq-bmutec:     When given, the Codec's AMUTEB=BMUTEC flag
                                is enabled.
+ - cirrus,enable-soft-reset:
+        The CS4271 requires its LRCLK and MCLK to be stable before its RESET
+        line is de-asserted. That also means that clocks cannot be changed
+        without putting the chip back into hardware reset, which also requires
+        a complete re-initialization of all registers.
+        One (undocumented) workaround is to assert and de-assert the PDN bit
+        in the MODE2 register. This workaround can be enabled with this DT
+        property.
+        Note that this is not needed in case the clocks are stable
+        throughout the entire runtime of the codec.
 Examples:
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
new file mode 100644
index 000000000000..be35d34e8b26
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
@@ -0,0 +1,51 @@
+NVIDIA Tegra audio complex
+Required properties:
+- compatible : "nvidia,tegra-audio-wm9712"
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the WM9712's pins, and the jacks on the board:
+  WM9712 pins:
+  * MONOOUT
+  * HPOUTL
+  * HPOUTR
+  * LOUT2
+  * ROUT2
+  * OUT3
+  * LINEINL
+  * LINEINR
+  * PHONE
+  * PCBEEP
+  * MIC1
+  * MIC2
+  * Mic Bias
+  Board connectors:
+  * Headphone
+  * LineIn
+  * Mic
+- nvidia,ac97-controller : The phandle of the Tegra AC97 controller
+Example:
+sound {
+        compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
+                         "nvidia,tegra-audio-wm9712";
+        nvidia,model = "Toradex Colibri T20";
+        nvidia,audio-routing =
+                "Headphone", "HPOUTL",
+                "Headphone", "HPOUTR",
+                "LineIn", "LINEINL",
+                "LineIn", "LINEINR",
+                "Mic", "MIC1";
+        nvidia,ac97-controller = <&ac97>;
+};
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
new file mode 100644
index 000000000000..c1454979c1ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra20-ac97.txt
@@ -0,0 +1,22 @@
+NVIDIA Tegra 20 AC97 controller
+Required properties:
+- compatible : "nvidia,tegra20-ac97"
+- reg : Should contain AC97 controller registers location and length
+- interrupts : Should contain AC97 interrupt
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for the AC97 controller
+- nvidia,codec-reset-gpio : The Tegra GPIO controller's phandle and the number
+  of the GPIO used to reset the external AC97 codec
+- nvidia,codec-sync-gpio : The Tegra GPIO controller's phandle and the number
+  of the GPIO corresponding with the AC97 DAP _FS line
+Example:
+ac97@70002000 {
+        compatible = "nvidia,tegra20-ac97";
+        reg = <0x70002000 0x200>;
+        interrupts = <0 81 0x04>;
+        nvidia,dma-request-selector = <&apbdma 12>;
+        nvidia,codec-reset-gpio = <&gpio 170 0>;
+        nvidia,codec-sync-gpio = <&gpio 120 0>;
+};
diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
index 6fae51c7f766..1ab6bc8404d5 100644
--- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt
+++ b/Documentation/devicetree/bindings/sound/omap-twl4030.txt
@@ -6,6 +6,52 @@ Required properties:
 - ti,mcbsp: phandle for the McBSP node
 - ti,codec: phandle for the twl4030 audio node
+Optional properties:
+- ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl
+- ti, jack-det-gpio: Jack detect GPIO
+- ti,audio-routing: List of connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source.
+  If the routing is not provided all possible connection will be available
+Available audio endpoints for the audio-routing table:
+Board connectors:
+ * Headset Stereophone
+ * Earpiece Spk
+ * Handsfree Spk
+ * Ext Spk
+ * Main Mic
+ * Sub Mic
+ * Headset Mic
+ * Carkit Mic
+ * Digital0 Mic
+ * Digital1 Mic
+ * Line In
+twl4030 pins:
+ * HSOL
+ * HSOR
+ * EARPIECE
+ * HFL
+ * HFR
+ * PREDRIVEL
+ * PREDRIVER
+ * CARKITL
+ * CARKITR
+ * MAINMIC
+ * SUBMIC
+ * HSMIC
+ * DIGIMIC0
+ * DIGIMIC1
+ * CARKITMIC
+ * AUXL
+ * AUXR
+ * Headset Mic Bias
+ * Mic Bias 1 /* Used for Main Mic or Digimic0 */
+ * Mic Bias 2 /* Used for Sub Mic or Digimic1 */
 Example:
 sound {
diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.txt b/Documentation/devicetree/bindings/sound/renesas,fsi.txt
new file mode 100644
index 000000000000..c5be003f413e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/renesas,fsi.txt
@@ -0,0 +1,26 @@
+Renesas FSI
+Required properties:
+- compatible                    : "renesas,sh_fsi2" or "renesas,sh_fsi"
+- reg                           : Should contain the register physical address and length
+- interrupts                    : Should contain FSI interrupt
+- fsia,spdif-connection         : FSI is connected by S/PDFI
+- fsia,stream-mode-support      : FSI supports 16bit stream mode.
+- fsia,use-internal-clock       : FSI uses internal clock when master mode.
+- fsib,spdif-connection         : same as fsia
+- fsib,stream-mode-support      : same as fsia
+- fsib,use-internal-clock       : same as fsia
+Example:
+sh_fsi2: sh_fsi2@0xec230000 {
+        compatible = "renesas,sh_fsi2";
+        reg = <0xec230000 0x400>;
+        interrupts = <0 146 0x4>;
+        fsia,spdif-connection;
+        fsia,stream-mode-support;
+        fsia,use-internal-clock;
+};
diff --git a/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt b/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt
new file mode 100644
index 000000000000..4686646fb122
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung,smdk-wm8994.txt
@@ -0,0 +1,14 @@
+Samsung SMDK audio complex
+Required properties:
+- compatible : "samsung,smdk-wm8994"
+- samsung,i2s-controller: The phandle of the Samsung I2S0 controller
+- samsung,audio-codec: The phandle of the WM8994 audio codec
+Example:
+sound {
+                compatible = "samsung,smdk-wm8994";
+                samsung,i2s-controller = <&i2s0>;
+                samsung,audio-codec = <&wm8994>;
+};
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
new file mode 100644
index 000000000000..3070046da2e5
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -0,0 +1,63 @@
+* Samsung I2S controller
+Required SoC Specific Properties:
+- compatible : "samsung,i2s-v5"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- dmas: list of DMA controller phandle and DMA request line ordered pairs.
+- dma-names: identifier string for each DMA request line in the dmas property.
+  These strings correspond 1:1 with the ordered pairs in dmas.
+Optional SoC Specific Properties:
+- samsung,supports-6ch: If the I2S Primary sound source has 5.1 Channel
+  support, this flag is enabled.
+- samsung,supports-rstclr: This flag should be set if I2S software reset bit
+  control is required. When this flag is set I2S software reset bit will be
+  enabled or disabled based on need.
+- samsung,supports-secdai:If I2S block has a secondary FIFO and internal DMA,
+  then this flag is enabled.
+- samsung,idma-addr: Internal DMA register base address of the audio
+  sub system(used in secondary sound source).
+Required Board Specific Properties:
+- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
+  interface lines. The format of the gpio specifier depends on the gpio
+  controller.
+  The syntax of samsung gpio specifier is
+        <[phandle of the gpio controller node]
+         [pin number within the gpio controller]
+         [mux function]
+         [flags and pull up/down]
+         [drive strength]>
+Example:
+- SoC Specific Portion:
+i2s@03830000 {
+        compatible = "samsung,i2s-v5";
+        reg = <0x03830000 0x100>;
+        dmas = <&pdma0 10
+                &pdma0 9
+                &pdma0 8>;
+        dma-names = "tx", "rx", "tx-sec";
+        samsung,supports-6ch;
+        samsung,supports-rstclr;
+        samsung,supports-secdai;
+        samsung,idma-addr = <0x03000000>;
+};
+- Board Specific Portion:
+i2s@03830000 {
+        gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
+                <&gpz 1 2 0 0>, /* I2S_0_CDCLK */
+                <&gpz 2 2 0 0>, /* I2S_0_LRCK */
+                <&gpz 3 2 0 0>, /* I2S_0_SDI */
+                <&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
+                <&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
+                <&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
+};
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
index e7b98f41fa5f..f47c3f589fd0 100644
--- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
+++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
@@ -11,6 +11,12 @@ Optional properties:
 - gpio-reset - gpio pin number used for codec reset
 - ai3x-gpio-func - <array of 2 int> - AIC3X_GPIO1 & AIC3X_GPIO2 Functionality
+- ai3x-micbias-vg - MicBias Voltage required.
+        1 - MICBIAS output is powered to 2.0V,
+        2 - MICBIAS output is powered to 2.5V,
+        3 - MICBIAS output is connected to AVDD,
+        If this node is not mentioned or if the value is incorrect, then MicBias
+        is powered down.
 Example:
diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt
new file mode 100644
index 000000000000..dceb3b1c2bb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8962.txt
@@ -0,0 +1,16 @@
+WM8962 audio CODEC
+This device supports I2C only.
+Required properties:
+  - compatible : "wlf,wm8962"
+  - reg : the I2C address of the device.
+Example:
+codec: wm8962@1a {
+        compatible = "wlf,wm8962";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
new file mode 100644
index 000000000000..e6222106ca36
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -0,0 +1,12 @@
+Renesas MSIOF spi controller
+Required properties:
+- compatible :  "renesas,sh-msiof" for SuperH or
+                "renesas,sh-mobile-msiof" for SH Mobile series
+- reg : Offset and length of the register set for the device
+- interrupts : interrupt line used by MSIOF
+Optional properties:
+- num-cs                : total number of chip-selects
+- renesas,tx-fifo-size  : Overrides the default tx fifo size given in words
+- renesas,rx-fifo-size  : Overrides the default rx fifo size given in words
diff --git a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt b/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
index 801d58cb6d4d..46882058b59b 100644
--- a/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
+++ b/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt
@@ -5,6 +5,12 @@ Required properties:
 - reg: Address and length of the register set for the device
 - interrupts: Should contain the LRADC interrupts
+Optional properties:
+- fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen
+                               to LRADC. Valid value is either 4 or 5. If this
+                               property is not present, then the touchscreen is
+                               disabled.
 Examples:
        lradc@80050000 {
diff --git a/Documentation/devicetree/bindings/tty/serial/arc-uart.txt b/Documentation/devicetree/bindings/tty/serial/arc-uart.txt
new file mode 100644
index 000000000000..5cae2eb686f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/arc-uart.txt
@@ -0,0 +1,26 @@
+* Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
+Required properties:
+- compatible            : "snps,arc-uart"
+- reg                   : offset and length of the register set for the device.
+- interrupts            : device interrupt
+- clock-frequency       : the input clock frequency for the UART
+- current-speed         : baud rate for UART
+e.g.
+arcuart0: serial@c0fc1000 {
+        compatible = "snps,arc-uart";
+        reg = <0xc0fc1000 0x100>;
+        interrupts = <5>;
+        clock-frequency = <80000000>;
+        current-speed = <115200>;
+        status = "okay";
+};
+Note: Each port should have an alias correctly numbered in "aliases" node.
+e.g.
+aliases {
+        serial0 = &arcuart0;
+};
diff --git a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt b/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt
index 6588b6950a7f..8e080b893b49 100644
--- a/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt
+++ b/Documentation/devicetree/bindings/tty/serial/efm32-uart.txt
@@ -5,10 +5,16 @@ Required properties:
 - reg : Address and length of the register set
 - interrupts : Should contain uart interrupt
+Optional properties:
+- location : Decides the location of the USART I/O pins.
+  Allowed range : [0 .. 5]
+  Default: 0
 Example:
 uart@0x4000c400 {
        compatible = "efm32,uart";
        reg = <0x4000c400 0x400>;
        interrupts = <15>;
+        location = <0>;
 };
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
new file mode 100644
index 000000000000..7a95c651ceb3
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -0,0 +1,22 @@
+synopsys DWC3 CORE
+DWC3- USB3 CONTROLLER
+Required properties:
+ - compatible: must be "synopsys,dwc3"
+ - reg : Address and length of the register set for the device
+ - interrupts: Interrupts used by the dwc3 controller.
+ - usb-phy : array of phandle for the PHY device
+Optional properties:
+ - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+This is usually a subnode to DWC3 glue to which it is connected.
+dwc3@4a030000 {
+        compatible = "synopsys,dwc3";
+        reg = <0x4a030000 0xcfff>;
+        interrupts = <0 92 4>
+        usb-phy = <&usb2_phy>, <&usb3,phy>;
+        tx-fifo-resize;
+};
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index 29a043ecda52..1ef0ce71f8fa 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -1,8 +1,11 @@
-OMAP GLUE
+OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
 OMAP MUSB GLUE
 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
 - ti,hwmods : must be "usb_otg_hs"
+ - ti,has-mailbox : to specify that omap uses an external mailbox
+   (in control module) to communicate with the musb core during device connect
+   and disconnect.
 - multipoint : Should be "1" indicating the musb controller supports
   multipoint. This is a MUSB configuration-specific setting.
 - num_eps : Specifies the number of endpoints. This is also a
@@ -16,13 +19,19 @@ OMAP MUSB GLUE
 - power : Should be "50". This signifies the controller can supply upto
   100mA when operating in host mode.
+Optional properties:
+ - ctrl-module : phandle of the control module this glue uses to write to
+   mailbox
 SOC specific device node entry
 usb_otg_hs: usb_otg_hs@4a0ab000 {
        compatible = "ti,omap4-musb";
        ti,hwmods = "usb_otg_hs";
+        ti,has-mailbox;
        multipoint = <1>;
        num_eps = <16>;
        ram_bits = <12>;
+        ctrl-module = <&omap_control_usb>;
 };
 Board specific device node entry
@@ -31,3 +40,26 @@ Board specific device node entry
        mode = <3>;
        power = <50>;
 };
+OMAP CONTROL USB
+Required properties:
+ - compatible: Should be "ti,omap-control-usb"
+ - reg : Address and length of the register set for the device. It contains
+   the address of "control_dev_conf" and "otghs_control" or "phy_power_usb"
+   depending upon omap4 or omap5.
+ - reg-names: The names of the register addresses corresponding to the registers
+   filled in "reg".
+ - ti,type: This is used to differentiate whether the control module has
+   usb mailbox or usb3 phy power. omap4 has usb mailbox in control module to
+   notify events to the musb core and omap5 has usb3 phy power register to
+   power on usb3 phy. Should be "1" if it has mailbox and "2" if it has usb3
+   phy power.
+omap_control_usb: omap-control-usb@4a002300 {
+        compatible = "ti,omap-control-usb";
+        reg = <0x4a002300 0x4>,
+              <0x4a00233c 0x4>;
+        reg-names = "control_dev_conf", "otghs_control";
+        ti,type = <1>;
+};
diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
new file mode 100644
index 000000000000..033194934f64
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -0,0 +1,55 @@
+* Samsung's usb phy transceiver
+The Samsung's phy transceiver is used for controlling usb phy for
+s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
+across Samsung SOCs.
+TODO: Adding the PHY binding with controller(s) according to the under
+developement generic PHY driver.
+Required properties:
+Exynos4210:
+- compatible : should be "samsung,exynos4210-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+        region.
+Exynos5250:
+- compatible : should be "samsung,exynos5250-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+        region.
+Optional properties:
+- #address-cells: should be '1' when usbphy node has a child node with 'reg'
+                  property.
+- #size-cells: should be '1' when usbphy node has a child node with 'reg'
+               property.
+- ranges: allows valid translation between child's address space and parent's
+          address space.
+- The child node 'usbphy-sys' to the node 'usbphy' is for the system controller
+  interface for usb-phy. It should provide the following information required by
+  usb-phy controller to control phy.
+  - reg : base physical address of PHY_CONTROL registers.
+          The size of this register is the total sum of size of all PHY_CONTROL
+          registers that the SoC has. For example, the size will be
+          '0x4' in case we have only one PHY_CONTROL register (e.g.
+          OTHERS register in S3C64XX or USB_PHY_CONTROL register in S5PV210)
+          and, '0x8' in case we have two PHY_CONTROL registers (e.g.
+          USBDEVICE_PHY_CONTROL and USBHOST_PHY_CONTROL registers in exynos4x).
+          and so on.
+Example:
+ - Exynos4210
+        usbphy@125B0000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "samsung,exynos4210-usbphy";
+                reg = <0x125B0000 0x100>;
+                ranges;
+                usbphy-sys {
+                        /* USB device and host PHY_CONTROL registers */
+                        reg = <0x10020704 0x8>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt b/Documentation/devicetree/bindings/usb/usb-phy.txt
index 80d4148cb661..61496f5cb095 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -4,14 +4,39 @@ OMAP USB2 PHY
 Required properties:
 - compatible: Should be "ti,omap-usb2"
- - reg : Address and length of the register set for the device. Also
+ - reg : Address and length of the register set for the device.
-add the address of control module dev conf register until a driver for
-control module is added
+Optional properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+   the PHY.
 This is usually a subnode of ocp2scp to which it is connected.
 usb2phy@4a0ad080 {
        compatible = "ti,omap-usb2";
-        reg = <0x4a0ad080 0x58>,
+        reg = <0x4a0ad080 0x58>;
-              <0x4a002300 0x4>;
+        ctrl-module = <&omap_control_usb>;
+};
+OMAP USB3 PHY
+Required properties:
+ - compatible: Should be "ti,omap-usb3"
+ - reg : Address and length of the register set for the device.
+ - reg-names: The names of the register addresses corresponding to the registers
+   filled in "reg".
+Optional properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+   the PHY.
+This is usually a subnode of ocp2scp to which it is connected.
+usb3phy@4a084400 {
+        compatible = "ti,omap-usb3";
+        reg = <0x4a084400 0x80>,
+              <0x4a084800 0x64>,
+              <0x4a084c00 0x40>;
+        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+        ctrl-module = <&omap_control_usb>;
 };
diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt
new file mode 100644
index 000000000000..6813a715fc7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -0,0 +1,20 @@
+SMSC USB3503 High-Speed Hub Controller
+Required properties:
+- compatible: Should be "smsc,usb3503".
+- reg: Specifies the i2c slave address, it should be 0x08.
+- connect-gpios: Should specify GPIO for connect.
+- intn-gpios: Should specify GPIO for interrupt.
+- reset-gpios: Should specify GPIO for reset.
+- initial-mode: Should specify initial mode.
+                (1 for HUB mode, 2 for STANDBY mode)
+Examples:
+        usb3503@08 {
+                compatible = "smsc,usb3503";
+                reg = <0x08>;
+                connect-gpios = <&gpx3 0 1>;
+                intn-gpios = <&gpx3 4 1>;
+                reset-gpios = <&gpx3 5 1>;
+                initial-mode = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 902b1b1f568e..19e1ef73ab0d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -14,6 +14,7 @@ bosch	Bosch Sensortec GmbH
 brcm    Broadcom Corporation
 cavium  Cavium, Inc.
 chrp    Common Hardware Reference Platform
+cirrus  Cirrus Logic, Inc.
 cortina Cortina Systems, Inc.
 dallas  Maxim Integrated Products (formerly Dallas Semiconductor)
 denx    Denx Software Engineering
@@ -42,6 +43,7 @@ powervr	PowerVR (deprecated, use img)
 qcom    Qualcomm, Inc.
 ramtron Ramtron International
 realtek Realtek Semiconductor Corp.
+renesas Renesas Electronics Corporation
 samsung Samsung Semiconductor
 sbs     Smart Battery System
 schindler       Schindler
@@ -50,8 +52,10 @@ simtek
 sirf    SiRF Technology, Inc.
 snps    Synopsys, Inc.
 st      STMicroelectronics
+ste     ST-Ericsson
 stericsson      ST-Ericsson
 ti      Texas Instruments
+toshiba Toshiba Corporation
 via     VIA Technologies, Inc.
 wlf     Wolfson Microelectronics
 wm      Wondermedia Technologies, Inc.
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
index 79ead8263ae4..ce0d8e78ed8f 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -2,7 +2,7 @@
 The Samsung's Watchdog controller is used for resuming system operation
 after a preset amount of time during which the WDT reset event has not
-occured.
+occurred.
 Required properties:
 - compatible : should be "samsung,s3c2410-wdt"