8 files changed, 116 insertions, 10 deletions

diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index 7eece72b1a35..8fe815046140 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -2,7 +2,9 @@ Amlogic MesonX device tree bindings
 -------------------------------------------
 
 Boards with the Amlogic Meson6 SoC shall have the following properties:
+  Required root node property:
+    compatible: "amlogic,meson6"
 
-Required root node property:
-
-compatible = "amlogic,meson6";
+Boards with the Amlogic Meson8 SoC shall have the following properties:
+  Required root node property:
+    compatible: "amlogic,meson8";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index fc446347ab6d..b2aacbe16ed9 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -227,6 +227,15 @@ nodes to be present and contain the properties described below.
                         # List of phandles to idle state nodes supported
                           by this cpu [3].
 
+        - rockchip,pmu
+                Usage: optional for systems that have an "enable-method"
+                       property value of "rockchip,rk3066-smp"
+                       While optional, it is the preferred way to get access to
+                       the cpu-core power-domains.
+                Value type: <phandle>
+                Definition: Specifies the syscon node controlling the cpu core
+                            power domains.
+
 Example 1 (dual-cluster big.LITTLE system 32-bit):
 
         cpus {
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
new file mode 100644
index 000000000000..42941fdefb11
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -0,0 +1,12 @@
+Allwinner sunXi Platforms Device Tree Bindings
+
+Each device tree must specify which Allwinner SoC it uses,
+using one of the following compatible strings:
+
+  allwinner,sun4i-a10
+  allwinner,sun5i-a10s
+  allwinner,sun5i-a13
+  allwinner,sun6i-a31
+  allwinner,sun7i-a20
+  allwinner,sun8i-a23
+  allwinner,sun9i-a80
diff --git a/Documentation/devicetree/bindings/arm/ux500/power_domain.txt b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt
new file mode 100644
index 000000000000..5679d1742d3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ux500/power_domain.txt
@@ -0,0 +1,35 @@
+* ST-Ericsson UX500 PM Domains
+
+UX500 supports multiple PM domains which are used to gate power to one or
+more peripherals on the SOC.
+
+The implementation of PM domains for UX500 are based upon the generic PM domain
+and use the corresponding DT bindings.
+
+==PM domain providers==
+
+Required properties:
+ - compatible: Must be "stericsson,ux500-pm-domains".
+ - #power-domain-cells : Number of cells in a power domain specifier, must be 1.
+
+Example:
+        pm_domains: pm_domains0 {
+                compatible = "stericsson,ux500-pm-domains";
+                #power-domain-cells = <1>;
+        };
+
+==PM domain consumers==
+
+Required properties:
+ - power-domains: A phandle and PM domain specifier. Below are the list of
+                valid specifiers:
+
+                Index   Specifier
+                -----   ---------
+                0       DOMAIN_VAPE
+
+Example:
+        sdi0_per1@80126000 {
+                compatible = "arm,pl18x", "arm,primecell";
+                power-domains = <&pm_domains DOMAIN_VAPE>
+        };
diff --git a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
index 5fa44f52a0b8..5e16c3ccb061 100644
--- a/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
+++ b/Documentation/devicetree/bindings/bus/mvebu-mbus.txt
@@ -48,9 +48,12 @@ Required properties:
 - compatible:   Should be set to "marvell,mbus-controller".
 
 - reg:          Device's register space.
-                Two entries are expected (see the examples below):
-                the first one controls the devices decoding window and
-                the second one controls the SDRAM decoding window.
+                Two or three entries are expected (see the examples below):
+                the first one controls the devices decoding window,
+                the second one controls the SDRAM decoding window and
+                the third controls the MBus bridge (only with the
+                marvell,armada370-mbus and marvell,armadaxp-mbus
+                compatible strings)
 
 Example:
 
@@ -67,7 +70,7 @@ Example:
 
                         mbusc: mbus-controller@20000 {
                                 compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                                reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
                         };
 
                         /* more children ...*/
@@ -126,7 +129,7 @@ are skipped.
 
                         mbusc: mbus-controller@20000 {
                                 compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                                reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
                         };
 
                         /* more children ...*/
@@ -170,7 +173,7 @@ Using this macro, the above example would be:
 
                         mbusc: mbus-controller@20000 {
                                 compatible = "marvell,mbus-controller";
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                                reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
                         };
 
                         /* other children */
@@ -266,7 +269,7 @@ See the example below, where a more complete device tree is shown:
                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 
                         mbusc: mbus-controller@20000 {
-                                reg = <0x20000 0x100>, <0x20180 0x20>;
+                                reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
                         };
 
                         interrupt-controller@20000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt
new file mode 100644
index 000000000000..89657d1d4cd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-sdram-controller.txt
@@ -0,0 +1,21 @@
+Device Tree bindings for MVEBU SDRAM controllers
+
+The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
+differs from one SoC variant to another, but they also share a number
+of commonalities.
+
+For now, this Device Tree binding documentation only documents the
+Armada XP SDRAM controller.
+
+Required properties:
+
+ - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
+ - reg: a resource specifier for the register space, which should
+   include all SDRAM controller registers as per the datasheet.
+
+Example:
+
+sdramc@1400 {
+        compatible = "marvell,armada-xp-sdram-controller";
+        reg = <0x1400 0x500>;
+};
diff --git a/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt b/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt
new file mode 100644
index 000000000000..dc7c9bad63ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/imx-snvs-poweroff.txt
@@ -0,0 +1,23 @@
+i.mx6 Poweroff Driver
+
+SNVS_LPCR in SNVS module can power off the whole system by pull
+PMIC_ON_REQ low if PMIC_ON_REQ is connected with external PMIC.
+If you don't want to use PMIC_ON_REQ as power on/off control,
+please set status='disabled' to disable this driver.
+
+Required Properties:
+-compatible: "fsl,sec-v4.0-poweroff"
+-reg: Specifies the physical address of the SNVS_LPCR register
+
+Example:
+        snvs@020cc000 {
+                compatible = "fsl,sec-v4.0-mon", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x020cc000 0x4000>;
+                .....
+                snvs_poweroff: snvs-poweroff@38 {
+                        compatible = "fsl,sec-v4.0-poweroff";
+                        reg = <0x38 0x4>;
+                };
+        }
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index a344ec2713a5..ecaf2035c2fe 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -91,6 +91,7 @@ lltc	Linear Technology Corporation
 marvell Marvell Technology Group Ltd.
 maxim   Maxim Integrated Products
 mediatek        MediaTek Inc.
+merrii  Merrii Technology Co., Ltd.
 micrel  Micrel Inc.
 microchip       Microchip Technology Inc.
 micron  Micron Technology Inc.