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diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
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+NVIDIA Tegra20 Clock And Reset Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
+for muxing and gating Tegra's clocks, and setting their rates.
+
+Required properties :
+- compatible : Should be "nvidia,tegra20-car"
+- reg : Should contain CAR registers location and length
+- clocks : Should contain phandle and clock specifiers for two clocks:
+  the 32 KHz "32k_in", and the board-specific oscillator "osc".
+- #clock-cells : Should be 1.
+  In clock consumers, this cell represents the clock ID exposed by the CAR.
+
+  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  registers. These IDs often match those in the CAR's RST_DEVICES registers,
+  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
+  this case, those clocks are assigned IDs above 95 in order to highlight
+  this issue. Implementations that interpret these clock IDs as bit values
+  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
+  explicitly handle these special cases.
+
+  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
+  above.
+
+  0     cpu
+  1     unassigned
+  2     unassigned
+  3     ac97
+  4     rtc
+  5     tmr
+  6     uart1
+  7     unassigned      (register bit affects uart2 and vfir)
+  8     gpio
+  9     sdmmc2
+  10    unassigned      (register bit affects spdif_in and spdif_out)
+  11    i2s1
+  12    i2c1
+  13    ndflash
+  14    sdmmc1
+  15    sdmmc4
+  16    twc
+  17    pwm
+  18    i2s2
+  19    epp
+  20    unassigned      (register bit affects vi and vi_sensor)
+  21    2d
+  22    usbd
+  23    isp
+  24    3d
+  25    ide
+  26    disp2
+  27    disp1
+  28    host1x
+  29    vcp
+  30    unassigned
+  31    cache2
+
+  32    mem
+  33    ahbdma
+  34    apbdma
+  35    unassigned
+  36    kbc
+  37    stat_mon
+  38    pmc
+  39    fuse
+  40    kfuse
+  41    sbc1
+  42    snor
+  43    spi1
+  44    sbc2
+  45    xio
+  46    sbc3
+  47    dvc
+  48    dsi
+  49    unassigned      (register bit affects tvo and cve)
+  50    mipi
+  51    hdmi
+  52    csi
+  53    tvdac
+  54    i2c2
+  55    uart3
+  56    unassigned
+  57    emc
+  58    usb2
+  59    usb3
+  60    mpe
+  61    vde
+  62    bsea
+  63    bsev
+
+  64    speedo
+  65    uart4
+  66    uart5
+  67    i2c3
+  68    sbc4
+  69    sdmmc3
+  70    pcie
+  71    owr
+  72    afi
+  73    csite
+  74    unassigned
+  75    avpucq
+  76    la
+  77    unassigned
+  78    unassigned
+  79    unassigned
+  80    unassigned
+  81    unassigned
+  82    unassigned
+  83    unassigned
+  84    irama
+  85    iramb
+  86    iramc
+  87    iramd
+  88    cram2
+  89    audio_2x        a/k/a audio_2x_sync_clk
+  90    clk_d
+  91    unassigned
+  92    sus
+  93    cdev1
+  94    cdev2
+  95    unassigned
+
+  96    uart2
+  97    vfir
+  98    spdif_in
+  99    spdif_out
+  100   vi
+  101   vi_sensor
+  102   tvo
+  103   cve
+  104   osc
+  105   clk_32k         a/k/a clk_s
+  106   clk_m
+  107   sclk
+  108   cclk
+  109   hclk
+  110   pclk
+  111   blink
+  112   pll_a
+  113   pll_a_out0
+  114   pll_c
+  115   pll_c_out1
+  116   pll_d
+  117   pll_d_out0
+  118   pll_e
+  119   pll_m
+  120   pll_m_out1
+  121   pll_p
+  122   pll_p_out1
+  123   pll_p_out2
+  124   pll_p_out3
+  125   pll_p_out4
+  126   pll_s
+  127   pll_u
+  128   pll_x
+  129   cop             a/k/a avp
+  130   audio           a/k/a audio_sync_clk
+  131   pll_ref
+  132   twd
+
+Example SoC include file:
+
+/ {
+        tegra_car: clock {
+                compatible = "nvidia,tegra20-car";
+                reg = <0x60006000 0x1000>;
+                #clock-cells = <1>;
+        };
+
+        usb@c5004000 {
+                clocks = <&tegra_car 58>; /* usb2 */
+        };
+};
+
+Example board file:
+
+/ {
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                osc: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <12000000>;
+                };
+
+                clk_32k: clock@1 {
+                        compatible = "fixed-clock";
+                        reg = <1>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        &tegra_car {
+                clocks = <&clk_32k> <&osc>;
+        };
+};