134 files changed, 5717 insertions, 992 deletions
diff --git a/Documentation/devicetree/bindings/arm/cci.txt b/Documentation/devicetree/bindings/arm/cci.txt
new file mode 100644
index 000000000000..92d36e2aa877
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cci.txt
@@ -0,0 +1,172 @@
+=======================================================
+ARM CCI cache coherent interconnect binding description
+=======================================================
+ARM multi-cluster systems maintain intra-cluster coherency through a
+cache coherent interconnect (CCI) that is capable of monitoring bus
+transactions and manage coherency, TLB invalidations and memory barriers.
+It allows snooping and distributed virtual memory message broadcast across
+clusters, through memory mapped interface, with a global control register
+space and multiple sets of interface control registers, one per slave
+interface.
+Bindings for the CCI node follow the ePAPR standard, available from:
+www.power.org/documentation/epapr-version-1-1/
+with the addition of the bindings described in this document which are
+specific to ARM.
+* CCI interconnect node
+        Description: Describes a CCI cache coherent Interconnect component
+        Node name must be "cci".
+        Node's parent must be the root node /, and the address space visible
+        through the CCI interconnect is the same as the one seen from the
+        root node (ie from CPUs perspective as per DT standard).
+        Every CCI node has to define the following properties:
+        - compatible
+                Usage: required
+                Value type: <string>
+                Definition: must be set to
+                            "arm,cci-400"
+        - reg
+                Usage: required
+                Value type: <prop-encoded-array>
+                Definition: A standard property. Specifies base physical
+                            address of CCI control registers common to all
+                            interfaces.
+        - ranges:
+                Usage: required
+                Value type: <prop-encoded-array>
+                Definition: A standard property. Follow rules in the ePAPR for
+                            hierarchical bus addressing. CCI interfaces
+                            addresses refer to the parent node addressing
+                            scheme to declare their register bases.
+        CCI interconnect node can define the following child nodes:
+        - CCI control interface nodes
+                Node name must be "slave-if".
+                Parent node must be CCI interconnect node.
+                A CCI control interface node must contain the following
+                properties:
+                - compatible
+                        Usage: required
+                        Value type: <string>
+                        Definition: must be set to
+                                    "arm,cci-400-ctrl-if"
+                - interface-type:
+                        Usage: required
+                        Value type: <string>
+                        Definition: must be set to one of {"ace", "ace-lite"}
+                                    depending on the interface type the node
+                                    represents.
+                - reg:
+                        Usage: required
+                        Value type: <prop-encoded-array>
+                        Definition: the base address and size of the
+                                    corresponding interface programming
+                                    registers.
+* CCI interconnect bus masters
+        Description: masters in the device tree connected to a CCI port
+                     (inclusive of CPUs and their cpu nodes).
+        A CCI interconnect bus master node must contain the following
+        properties:
+        - cci-control-port:
+                Usage: required
+                Value type: <phandle>
+                Definition: a phandle containing the CCI control interface node
+                            the master is connected to.
+Example:
+        cpus {
+                #size-cells = <0>;
+                #address-cells = <1>;
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        cci-control-port = <&cci_control1>;
+                        reg = <0x0>;
+                };
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        cci-control-port = <&cci_control1>;
+                        reg = <0x1>;
+                };
+                CPU2: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        cci-control-port = <&cci_control2>;
+                        reg = <0x100>;
+                };
+                CPU3: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        cci-control-port = <&cci_control2>;
+                        reg = <0x101>;
+                };
+        };
+        dma0: dma@3000000 {
+                compatible = "arm,pl330", "arm,primecell";
+                cci-control-port = <&cci_control0>;
+                reg = <0x0 0x3000000 0x0 0x1000>;
+                interrupts = <10>;
+                #dma-cells = <1>;
+                #dma-channels = <8>;
+                #dma-requests = <32>;
+        };
+        cci@2c090000 {
+                compatible = "arm,cci-400";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x0 0x2c090000 0 0x1000>;
+                ranges = <0x0 0x0 0x2c090000 0x6000>;
+                cci_control0: slave-if@1000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace-lite";
+                        reg = <0x1000 0x1000>;
+                };
+                cci_control1: slave-if@4000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x4000 0x1000>;
+                };
+                cci_control2: slave-if@5000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x5000 0x1000>;
+                };
+        };
+This CCI node corresponds to a CCI component whose control registers sits
+at address 0x000000002c090000.
+CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
+CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
+CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
new file mode 100644
index 000000000000..63c0e6ae5cf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
@@ -0,0 +1,10 @@
+TI Keystone Platforms Device Tree Bindings
+-----------------------------------------------
+Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the
+following properties.
+Required properties:
+ - compatible: All TI specific devices present in Keystone SOC should be in
+   the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
+   type UART should use the specified compatible for those devices.
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index cbef09b5c8a7..69ddf9fad2dc 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -16,6 +16,9 @@ Required properties:
     performs the same operation).
        "marvell,"aurora-outer-cache: Marvell Controller designed to be
         compatible with the ARM one with outer cache mode.
+        "bcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+        offset needs to be added to the address before passing down to the L2
+        cache controller
 - cache-unified : Specifies the cache is a unified cache.
 - cache-level : Should be set to 2 for a level 2 cache.
 - reg : Physical base address and size of cache controller's memory mapped
diff --git a/Documentation/devicetree/bindings/arm/nspire.txt b/Documentation/devicetree/bindings/arm/nspire.txt
new file mode 100644
index 000000000000..4d08518bd176
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/nspire.txt
@@ -0,0 +1,14 @@
+TI-NSPIRE calculators
+Required properties:
+- compatible: Compatible property value should contain "ti,nspire".
+        CX models should have "ti,nspire-cx"
+        Touchpad models should have "ti,nspire-tp"
+        Clickpad models should have "ti,nspire-clp"
+Example:
+/ {
+        model = "TI-NSPIRE CX";
+        compatible = "ti,nspire-cx";
+        ...
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index f8288ea1b530..6d498c758b45 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -56,3 +56,6 @@ Boards:
 - OMAP5 EVM : Evaluation Module
  compatible = "ti,omap5-evm", "ti,omap5"
+- AM43x EPOS EVM
+  compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
diff --git a/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
new file mode 100644
index 000000000000..3b8fbf3c00c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rtsm-dcscb.txt
@@ -0,0 +1,19 @@
+ARM Dual Cluster System Configuration Block
+-------------------------------------------
+The Dual Cluster System Configuration Block (DCSCB) provides basic
+functionality for controlling clocks, resets and configuration pins in
+the Dual Cluster System implemented by the Real-Time System Model (RTSM).
+Required properties:
+- compatible : should be "arm,rtsm,dcscb"
+- reg : physical base address and the size of the registers window
+Example:
+        dcscb@60000000 {
+                compatible = "arm,rtsm,dcscb";
+                reg = <0x60000000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
index f2f2171e530e..9e5f73412cd7 100644
--- a/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/interrupt-combiner.txt
@@ -5,7 +5,7 @@ can combine interrupt sources as a group and provide a single interrupt request
 for the group. The interrupt request from each group are connected to a parent
 interrupt controller, such as GIC in case of Exynos4210.
-The interrupt combiner controller consists of multiple combiners. Upto eight
+The interrupt combiner controller consists of multiple combiners. Up to eight
 interrupt sources can be connected to a combiner. The combiner outputs one
 combined interrupt for its eight interrupt sources. The combined interrupt
 is usually connected to a parent interrupt controller.
@@ -14,8 +14,8 @@ A single node in the device tree is used to describe the interrupt combiner
 controller module (which includes multiple combiners). A combiner in the
 interrupt controller module shares config/control registers with other
 combiners. For example, a 32-bit interrupt enable/disable config register
-can accommodate upto 4 interrupt combiners (with each combiner supporting
+can accommodate up to 4 interrupt combiners (with each combiner supporting
-upto 8 interrupt sources).
+up to 8 interrupt sources).
 Required properties:
 - compatible: should be "samsung,exynos4210-combiner".
diff --git a/Documentation/devicetree/bindings/arm/spear/shirq.txt b/Documentation/devicetree/bindings/arm/spear/shirq.txt
index 13fbb8866bd6..715a013ed4bd 100644
--- a/Documentation/devicetree/bindings/arm/spear/shirq.txt
+++ b/Documentation/devicetree/bindings/arm/spear/shirq.txt
@@ -14,7 +14,7 @@ A single node in the device tree is used to describe the shared
 interrupt multiplexor (one node for all groups). A group in the
 interrupt controller shares config/control registers with other groups.
 For example, a 32-bit interrupt enable/disable config register can
-accommodate upto 4 interrupt groups.
+accommodate up to 4 interrupt groups.
 Required properties:
  - compatible: should be, either of
diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt
index 19bca04b81c9..6256ec31666d 100644
--- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt
+++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt
@@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings
 For various board the "board" node may contain specific properties
 that pertain to this particular board, such as board-specific GPIOs.
+Required root node property: src
+- Nomadik System and reset controller used for basic chip control, clock
+  and reset line control.
+- compatible: must be "stericsson,nomadik,src"
 Boards with the Nomadik SoC include:
 S8815 "MiniKit" manufactured by Calao Systems:
diff --git a/Documentation/devicetree/bindings/arm/ste-u300.txt b/Documentation/devicetree/bindings/arm/ste-u300.txt
new file mode 100644
index 000000000000..69b5ab0b5f4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ste-u300.txt
@@ -0,0 +1,46 @@
+ST-Ericsson U300 Device Tree Bindings
+For various board the "board" node may contain specific properties
+that pertain to this particular board, such as board-specific GPIOs
+or board power regulator supplies.
+Required root node property:
+compatible="stericsson,u300";
+Required node: syscon
+This contains the system controller.
+- compatible: must be "stericsson,u300-syscon".
+- reg: the base address and size of the system controller.
+Boards with the U300 SoC include:
+S365 "Small Board U365":
+Required node: s365
+This contains the board-specific information.
+- compatible: must be "stericsson,s365".
+- vana15-supply: the regulator supplying the 1.5V to drive the
+  board.
+- syscon: a pointer to the syscon node so we can acccess the
+  syscon registers to set the board as self-powered.
+Example:
+/ {
+        model = "ST-Ericsson U300";
+        compatible = "stericsson,u300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        s365 {
+                compatible = "stericsson,s365";
+                vana15-supply = <&ab3100_ldo_d_reg>;
+                syscon = <&syscon>;
+        };
+        syscon: syscon@c0011000 {
+                compatible = "stericsson,u300-syscon";
+                reg = <0xc0011000 0x1000>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index b519f9b699c3..3ec0c5c4f0e9 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -12,6 +12,11 @@ Optional properties:
 - calxeda,port-phys: phandle-combophy and lane assignment, which maps each
                        SATA port to a combophy and a lane within that
                        combophy
+- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
+                        which indicates that the driver supports SGPIO
+                        indicator lights using the indicated GPIOs
+- calxeda,led-order : a u32 array that map port numbers to offsets within the
+                        SGPIO bitstream.
 - dma-coherent      : Present if dma operations are coherent
 Example:
diff --git a/Documentation/devicetree/bindings/ata/atmel-at91_cf.txt b/Documentation/devicetree/bindings/ata/atmel-at91_cf.txt
new file mode 100644
index 000000000000..c1d22b3ae134
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/atmel-at91_cf.txt
@@ -0,0 +1,19 @@
+Atmel AT91RM9200 CompactFlash
+Required properties:
+- compatible : "atmel,at91rm9200-cf".
+- reg : should specify localbus address and size used.
+- gpios : specifies the gpio pins to control the CF device. Detect
+  and reset gpio's are mandatory while irq and vcc gpio's are
+  optional and may be set to 0 if not present.
+Example:
+compact-flash@50000000 {
+        compatible = "atmel,at91rm9200-cf";
+        reg = <0x50000000 0x30000000>;
+        gpios = <&pioC 13 0     /* irq */
+                 &pioC 15 0     /* detect */
+                 0              /* vcc */
+                 &pioC  5 0     /* reset */
+                >;
+};
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
new file mode 100644
index 000000000000..cedc2a9c4785
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -0,0 +1,49 @@
+Device tree bindings for i.MX Wireless External Interface Module (WEIM)
+The term "wireless" does not imply that the WEIM is literally an interface
+without wires. It simply means that this module was originally designed for
+wireless and mobile applications that use low-power technology.
+The actual devices are instantiated from the child nodes of a WEIM node.
+Required properties:
+ - compatible:          Should be set to "fsl,imx6q-weim"
+ - reg:                 A resource specifier for the register space
+                        (see the example below)
+ - clocks:              the clock, see the example below.
+ - #address-cells:      Must be set to 2 to allow memory address translation
+ - #size-cells:         Must be set to 1 to allow CS address passing
+ - ranges:              Must be set up to reflect the memory layout with four
+                        integer values for each chip-select line in use:
+                           <cs-number> 0 <physical address of mapping> <size>
+Timing property for child nodes. It is mandatory, not optional.
+ - fsl,weim-cs-timing:  The timing array, contains 6 timing values for the
+                        child node. We can get the CS index from the child
+                        node's "reg" property. This property contains the values
+                        for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
+                        EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
+Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
+        weim: weim@021b8000 {
+                compatible = "fsl,imx6q-weim";
+                reg = <0x021b8000 0x4000>;
+                clocks = <&clks 196>;
+                #address-cells = <2>;
+                #size-cells = <1>;
+                ranges = <0 0 0x08000000 0x08000000>;
+                nor@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x02000000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        bank-width = <2>;
+                        fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+                                        0x0000c000 0x1404a38e 0x00000000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 4b87ea1194e3..704be9306c9f 100644
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -95,7 +95,6 @@ GPMC chip-select settings properties for child nodes. All are optional.
 - gpmc,burst-wrap       Enables wrap bursting
 - gpmc,burst-read       Enables read page/burst mode
 - gpmc,burst-write      Enables write page/burst mode
- gpmc,device-nand      Device is NAND
 - gpmc,device-width     Total width of device(s) connected to a GPMC
                        chip-select in bytes. The GPMC supports 8-bit
                        and 16-bit devices and so this property must be
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index bd0c8416a5c8..0045433eae1f 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -9,6 +9,9 @@ Required properties:
        "altr,socfpga-pll-clock" - for a PLL clock
        "altr,socfpga-perip-clock" - The peripheral clock divided from the
                PLL clock.
+        "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
+                can get gated.
 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
 - clocks : shall be the input parent clock phandle for the clock. This is
        either an oscillator or a pll output.
@@ -16,3 +19,7 @@ Required properties:
 Optional properties:
 - fixed-divider : If clocks have a fixed divider value, use this property.
+- clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
+        and the bit index.
+- div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
+        and width.
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 000000000000..a1201802f90d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+Required Properties:
+- compatible: should be one of the following:
+  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
+  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
+- reg: physical base address and length of the controller's register set.
+- #clock-cells: should be 1.
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+Provided clocks:
+Clock           ID      SoC (if specific)
+-----------------------------------------------
+mout_audss      0
+mout_i2s        1
+dout_srp        2
+dout_aud_bus    3
+dout_i2s        4
+srp_clk         5
+i2s_bus         6
+sclk_i2s        7
+pcm_bus         8
+sclk_pcm        9
+Example 1: An example of a clock controller node is listed below.
+clock_audss: audss-clock-controller@3810000 {
+        compatible = "samsung,exynos5250-audss-clock";
+        reg = <0x03810000 0x0C>;
+        #clock-cells = <1>;
+};
+Example 2: I2S controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+i2s0: i2s@03830000 {
+        compatible = "samsung,i2s-v5";
+        reg = <0x03830000 0x100>;
+        dmas = <&pdma0 10
+                &pdma0 9
+                &pdma0 8>;
+        dma-names = "tx", "rx", "tx-sec";
+        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                <&clock_audss EXYNOS_I2S_BUS>,
+                <&clock_audss EXYNOS_SCLK_I2S>,
+                <&clock_audss EXYNOS_MOUT_AUDSS>,
+                <&clock_audss EXYNOS_MOUT_I2S>;
+        clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
+        "mout_audss", "mout_i2s";
+};
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index ea5e26f16aec..14d5c2af26f4 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable.
  sclk_spi0_isp       174     Exynos4x12
  sclk_spi1_isp       175     Exynos4x12
  sclk_uart_isp       176     Exynos4x12
+  sclk_fimg2d         177
              [Peripheral Clock Gates]
@@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable.
  smmu_mfcl           274
  smmu_mfcr           275
  g3d                 276
-  g2d                 277     Exynos4210
+  g2d                 277
  rotator             278     Exynos4210
  mdma                279     Exynos4210
  smmu_g2d            280     Exynos4210
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
new file mode 100644
index 000000000000..9bcc4b1bff51
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -0,0 +1,201 @@
+* Samsung Exynos5420 Clock Controller
+The Exynos5420 clock controller generates and supplies clock to various
+controllers within the Exynos5420 SoC.
+Required Properties:
+- comptible: should be one of the following.
+  - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+       [Core Clocks]
+  Clock                 ID
+  ----------------------------
+  fin_pll               1
+  [Clock Gate for Special Clocks]
+  Clock                 ID
+  ----------------------------
+  sclk_uart0            128
+  sclk_uart1            129
+  sclk_uart2            130
+  sclk_uart3            131
+  sclk_mmc0             132
+  sclk_mmc1             133
+  sclk_mmc2             134
+  sclk_spi0             135
+  sclk_spi1             136
+  sclk_spi2             137
+  sclk_i2s1             138
+  sclk_i2s2             139
+  sclk_pcm1             140
+  sclk_pcm2             141
+  sclk_spdif            142
+  sclk_hdmi             143
+  sclk_pixel            144
+  sclk_dp1              145
+  sclk_mipi1            146
+  sclk_fimd1            147
+  sclk_maudio0          148
+  sclk_maupcm0          149
+  sclk_usbd300          150
+  sclk_usbd301          151
+  sclk_usbphy300        152
+  sclk_usbphy301        153
+  sclk_unipro           154
+  sclk_pwm              155
+  sclk_gscl_wa          156
+  sclk_gscl_wb          157
+   [Peripheral Clock Gates]
+  Clock                 ID
+  ----------------------------
+  aclk66_peric          256
+  uart0                 257
+  uart1                 258
+  uart2                 259
+  uart3                 260
+  i2c0                  261
+  i2c1                  262
+  i2c2                  263
+  i2c3                  264
+  i2c4                  265
+  i2c5                  266
+  i2c6                  267
+  i2c7                  268
+  i2c_hdmi              269
+  tsadc                 270
+  spi0                  271
+  spi1                  272
+  spi2                  273
+  keyif                 274
+  i2s1                  275
+  i2s2                  276
+  pcm1                  277
+  pcm2                  278
+  pwm                   279
+  spdif                 280
+  i2c8                  281
+  i2c9                  282
+  i2c10                 283
+  aclk66_psgen          300
+  chipid                301
+  sysreg                302
+  tzpc0                 303
+  tzpc1                 304
+  tzpc2                 305
+  tzpc3                 306
+  tzpc4                 307
+  tzpc5                 308
+  tzpc6                 309
+  tzpc7                 310
+  tzpc8                 311
+  tzpc9                 312
+  hdmi_cec              313
+  seckey                314
+  mct                   315
+  wdt                   316
+  rtc                   317
+  tmu                   318
+  tmu_gpu               319
+  pclk66_gpio           330
+  aclk200_fsys2         350
+  mmc0                  351
+  mmc1                  352
+  mmc2                  353
+  sromc                 354
+  ufs                   355
+  aclk200_fsys          360
+  tsi                   361
+  pdma0                 362
+  pdma1                 363
+  rtic                  364
+  usbh20                365
+  usbd300               366
+  usbd301               377
+  aclk400_mscl          380
+  mscl0                 381
+  mscl1                 382
+  mscl2                 383
+  smmu_mscl0            384
+  smmu_mscl1            385
+  smmu_mscl2            386
+  aclk333               400
+  mfc                   401
+  smmu_mfcl             402
+  smmu_mfcr             403
+  aclk200_disp1         410
+  dsim1                 411
+  dp1                   412
+  hdmi                  413
+  aclk300_disp1         420
+  fimd1                 421
+  smmu_fimd1            422
+  aclk166               430
+  mixer                 431
+  aclk266               440
+  rotator               441
+  mdma1                 442
+  smmu_rotator          443
+  smmu_mdma1            444
+  aclk300_jpeg          450
+  jpeg                  451
+  jpeg2                 452
+  smmu_jpeg             453
+  aclk300_gscl          460
+  smmu_gscl0            461
+  smmu_gscl1            462
+  gscl_wa               463
+  gscl_wb               464
+  gscl0                 465
+  gscl1                 466
+  clk_3aa               467
+  aclk266_g2d           470
+  sss                   471
+  slim_sss              472
+  mdma0                 473
+  aclk333_g2d           480
+  g2d                   481
+  aclk333_432_gscl      490
+  smmu_3aa              491
+  smmu_fimcl0           492
+  smmu_fimcl1           493
+  smmu_fimcl3           494
+  fimc_lite3            495
+  aclk_g3d              500
+  g3d                   501
+Example 1: An example of a clock controller node is listed below.
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5420-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+Example 2: UART controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+                clocks = <&clock 259>, <&clock 130>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
index d71b4b2c077d..f46f5625d8ad 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -184,6 +184,19 @@ clocks and IDs.
        cko2                    170
        srtc_gate               171
        pata_gate               172
+        sata_gate               173
+        spdif_xtal_sel          174
+        spdif0_sel              175
+        spdif1_sel              176
+        spdif0_pred             177
+        spdif0_podf             178
+        spdif1_pred             179
+        spdif1_podf             180
+        spdif0_com_sel          181
+        spdif1_com_sel          182
+        spdif0_gate             183
+        spdif1_gate             184
+        spdif_ipg_gate          185
 Examples (for mx53):
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 6deb6fd1c7cd..a0e104f0527e 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -208,6 +208,7 @@ clocks and IDs.
        pll4_post_div           193
        pll5_post_div           194
        pll5_video_div          195
+        eim_slow                196
 Examples:
diff --git a/Documentation/devicetree/bindings/clock/imx6sl-clock.txt b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
new file mode 100644
index 000000000000..15e40bdf147d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sl-clock.txt
@@ -0,0 +1,10 @@
+* Clock bindings for Freescale i.MX6 SoloLite
+Required properties:
+- compatible: Should be "fsl,imx6sl-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  See include/dt-bindings/clock/imx6sl-clock.h
+for the full list of i.MX6 SoloLite clock IDs.
diff --git a/Documentation/devicetree/bindings/clock/nspire-clock.txt b/Documentation/devicetree/bindings/clock/nspire-clock.txt
new file mode 100644
index 000000000000..7c3bc8bb5b9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nspire-clock.txt
@@ -0,0 +1,24 @@
+TI-NSPIRE Clocks
+Required properties:
+- compatible: Valid compatible properties include:
+        "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
+        "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
+        "lsi,nspire-cx-clock" for the base clock in the CX model
+        "lsi,nspire-classic-clock" for the base clock in the older model
+- reg: Physical base address of the controller and length of memory mapped
+        region.
+Optional:
+- clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
+        clock where it divides the rate from.
+Example:
+ahb_clk {
+        #clock-cells = <0>;
+        compatible = "lsi,nspire-cx-clock";
+        reg = <0x900B0000 0x4>;
+        clocks = <&base_clk>;
+};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
index d6cb083b90a2..0c80c2677104 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -12,253 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
-  The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  <dt-bindings/clock/tegra114-car.h>.
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-  0     unassigned
-  1     unassigned
-  2     unassigned
-  3     unassigned
-  4     rtc
-  5     timer
-  6     uarta
-  7     unassigned      (register bit affects uartb and vfir)
-  8     unassigned
-  9     sdmmc2
-  10    unassigned      (register bit affects spdif_in and spdif_out)
-  11    i2s1
-  12    i2c1
-  13    ndflash
-  14    sdmmc1
-  15    sdmmc4
-  16    unassigned
-  17    pwm
-  18    i2s2
-  19    epp
-  20    unassigned      (register bit affects vi and vi_sensor)
-  21    2d
-  22    usbd
-  23    isp
-  24    3d
-  25    unassigned
-  26    disp2
-  27    disp1
-  28    host1x
-  29    vcp
-  30    i2s0
-  31    unassigned
-  32    unassigned
-  33    unassigned
-  34    apbdma
-  35    unassigned
-  36    kbc
-  37    unassigned
-  38    unassigned
-  39    unassigned      (register bit affects fuse and fuse_burn)
-  40    kfuse
-  41    sbc1
-  42    nor
-  43    unassigned
-  44    sbc2
-  45    unassigned
-  46    sbc3
-  47    i2c5
-  48    dsia
-  49    unassigned
-  50    mipi
-  51    hdmi
-  52    csi
-  53    unassigned
-  54    i2c2
-  55    uartc
-  56    mipi-cal
-  57    emc
-  58    usb2
-  59    usb3
-  60    msenc
-  61    vde
-  62    bsea
-  63    bsev
-  64    unassigned
-  65    uartd
-  66    unassigned
-  67    i2c3
-  68    sbc4
-  69    sdmmc3
-  70    unassigned
-  71    owr
-  72    afi
-  73    csite
-  74    unassigned
-  75    unassigned
-  76    la
-  77    trace
-  78    soc_therm
-  79    dtv
-  80    ndspeed
-  81    i2cslow
-  82    dsib
-  83    tsec
-  84    unassigned
-  85    unassigned
-  86    unassigned
-  87    unassigned
-  88    unassigned
-  89    xusb_host
-  90    unassigned
-  91    msenc
-  92    csus
-  93    unassigned
-  94    unassigned
-  95    unassigned      (bit affects xusb_dev and xusb_dev_src)
-  96    unassigned
-  97    unassigned
-  98    unassigned
-  99    mselect
-  100   tsensor
-  101   i2s3
-  102   i2s4
-  103   i2c4
-  104   sbc5
-  105   sbc6
-  106   d_audio
-  107   apbif
-  108   dam0
-  109   dam1
-  110   dam2
-  111   hda2codec_2x
-  112   unassigned
-  113   audio0_2x
-  114   audio1_2x
-  115   audio2_2x
-  116   audio3_2x
-  117   audio4_2x
-  118   spdif_2x
-  119   actmon
-  120   extern1
-  121   extern2
-  122   extern3
-  123   unassigned
-  124   unassigned
-  125   hda
-  126   unassigned
-  127   se
-  128   hda2hdmi
-  129   unassigned
-  130   unassigned
-  131   unassigned
-  132   unassigned
-  133   unassigned
-  134   unassigned
-  135   unassigned
-  136   unassigned
-  137   unassigned
-  138   unassigned
-  139   unassigned
-  140   unassigned
-  141   unassigned
-  142   unassigned
-  143   unassigned      (bit affects xusb_falcon_src, xusb_fs_src,
-                         xusb_host_src and xusb_ss_src)
-  144   cilab
-  145   cilcd
-  146   cile
-  147   dsialp
-  148   dsiblp
-  149   unassigned
-  150   dds
-  151   unassigned
-  152   dp2
-  153   amx
-  154   adx
-  155   unassigned      (bit affects dfll_ref and dfll_soc)
-  156   xusb_ss
-  192   uartb
-  193   vfir
-  194   spdif_in
-  195   spdif_out
-  196   vi
-  197   vi_sensor
-  198   fuse
-  199   fuse_burn
-  200   clk_32k
-  201   clk_m
-  202   clk_m_div2
-  203   clk_m_div4
-  204   pll_ref
-  205   pll_c
-  206   pll_c_out1
-  207   pll_c2
-  208   pll_c3
-  209   pll_m
-  210   pll_m_out1
-  211   pll_p
-  212   pll_p_out1
-  213   pll_p_out2
-  214   pll_p_out3
-  215   pll_p_out4
-  216   pll_a
-  217   pll_a_out0
-  218   pll_d
-  219   pll_d_out0
-  220   pll_d2
-  221   pll_d2_out0
-  222   pll_u
-  223   pll_u_480M
-  224   pll_u_60M
-  225   pll_u_48M
-  226   pll_u_12M
-  227   pll_x
-  228   pll_x_out0
-  229   pll_re_vco
-  230   pll_re_out
-  231   pll_e_out0
-  232   spdif_in_sync
-  233   i2s0_sync
-  234   i2s1_sync
-  235   i2s2_sync
-  236   i2s3_sync
-  237   i2s4_sync
-  238   vimclk_sync
-  239   audio0
-  240   audio1
-  241   audio2
-  242   audio3
-  243   audio4
-  244   spdif
-  245   clk_out_1
-  246   clk_out_2
-  247   clk_out_3
-  248   blink
-  252   xusb_host_src
-  253   xusb_falcon_src
-  254   xusb_fs_src
-  255   xusb_ss_src
-  256   xusb_dev_src
-  257   xusb_dev
-  258   xusb_hs_src
-  259   sclk
-  260   hclk
-  261   pclk
-  262   cclk_g
-  263   cclk_lp
-  264   dfll_ref
-  265   dfll_soc
 Example SoC include file:
@@ -270,7 +26,7 @@ Example SoC include file:
        };
        usb@c5004000 {
-                clocks = <&tegra_car 58>; /* usb2 */
+                clocks = <&tegra_car TEGRA114_CLK_USB2>;
        };
 };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index e885680f6b45..fcfed5bf73fb 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -12,155 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
-  The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  <dt-bindings/clock/tegra20-car.h>.
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 95 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-  The balance of the clocks controlled by the CAR are assigned IDs of 96 and
-  above.
-  0     cpu
-  1     unassigned
-  2     unassigned
-  3     ac97
-  4     rtc
-  5     tmr
-  6     uart1
-  7     unassigned      (register bit affects uart2 and vfir)
-  8     gpio
-  9     sdmmc2
-  10    unassigned      (register bit affects spdif_in and spdif_out)
-  11    i2s1
-  12    i2c1
-  13    ndflash
-  14    sdmmc1
-  15    sdmmc4
-  16    twc
-  17    pwm
-  18    i2s2
-  19    epp
-  20    unassigned      (register bit affects vi and vi_sensor)
-  21    2d
-  22    usbd
-  23    isp
-  24    3d
-  25    ide
-  26    disp2
-  27    disp1
-  28    host1x
-  29    vcp
-  30    unassigned
-  31    cache2
-  32    mem
-  33    ahbdma
-  34    apbdma
-  35    unassigned
-  36    kbc
-  37    stat_mon
-  38    pmc
-  39    fuse
-  40    kfuse
-  41    sbc1
-  42    snor
-  43    spi1
-  44    sbc2
-  45    xio
-  46    sbc3
-  47    dvc
-  48    dsi
-  49    unassigned      (register bit affects tvo and cve)
-  50    mipi
-  51    hdmi
-  52    csi
-  53    tvdac
-  54    i2c2
-  55    uart3
-  56    unassigned
-  57    emc
-  58    usb2
-  59    usb3
-  60    mpe
-  61    vde
-  62    bsea
-  63    bsev
-  64    speedo
-  65    uart4
-  66    uart5
-  67    i2c3
-  68    sbc4
-  69    sdmmc3
-  70    pcie
-  71    owr
-  72    afi
-  73    csite
-  74    unassigned
-  75    avpucq
-  76    la
-  77    unassigned
-  78    unassigned
-  79    unassigned
-  80    unassigned
-  81    unassigned
-  82    unassigned
-  83    unassigned
-  84    irama
-  85    iramb
-  86    iramc
-  87    iramd
-  88    cram2
-  89    audio_2x        a/k/a audio_2x_sync_clk
-  90    clk_d
-  91    unassigned
-  92    sus
-  93    cdev2
-  94    cdev1
-  95    unassigned
-  96    uart2
-  97    vfir
-  98    spdif_in
-  99    spdif_out
-  100   vi
-  101   vi_sensor
-  102   tvo
-  103   cve
-  104   osc
-  105   clk_32k         a/k/a clk_s
-  106   clk_m
-  107   sclk
-  108   cclk
-  109   hclk
-  110   pclk
-  111   blink
-  112   pll_a
-  113   pll_a_out0
-  114   pll_c
-  115   pll_c_out1
-  116   pll_d
-  117   pll_d_out0
-  118   pll_e
-  119   pll_m
-  120   pll_m_out1
-  121   pll_p
-  122   pll_p_out1
-  123   pll_p_out2
-  124   pll_p_out3
-  125   pll_p_out4
-  126   pll_s
-  127   pll_u
-  128   pll_x
-  129   cop             a/k/a avp
-  130   audio           a/k/a audio_sync_clk
-  131   pll_ref
-  132   twd
 Example SoC include file:
@@ -172,7 +26,7 @@ Example SoC include file:
        };
        usb@c5004000 {
-                clocks = <&tegra_car 58>; /* usb2 */
+                clocks = <&tegra_car TEGRA20_CLK_USB2>;
        };
 };
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index f3da3be5fcad..0f714081e986 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -12,212 +12,9 @@ Required properties :
 - clocks : Should contain phandle and clock specifiers for two clocks:
  the 32 KHz "32k_in", and the board-specific oscillator "osc".
 - #clock-cells : Should be 1.
-  In clock consumers, this cell represents the clock ID exposed by the CAR.
+  In clock consumers, this cell represents the clock ID exposed by the
+  CAR. The assignments may be found in header file
-  The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
+  <dt-bindings/clock/tegra30-car.h>.
-  registers. These IDs often match those in the CAR's RST_DEVICES registers,
-  but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
-  this case, those clocks are assigned IDs above 160 in order to highlight
-  this issue. Implementations that interpret these clock IDs as bit values
-  within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
-  explicitly handle these special cases.
-  The balance of the clocks controlled by the CAR are assigned IDs of 160 and
-  above.
-  0     cpu
-  1     unassigned
-  2     unassigned
-  3     unassigned
-  4     rtc
-  5     timer
-  6     uarta
-  7     unassigned      (register bit affects uartb and vfir)
-  8     gpio
-  9     sdmmc2
-  10    unassigned      (register bit affects spdif_in and spdif_out)
-  11    i2s1
-  12    i2c1
-  13    ndflash
-  14    sdmmc1
-  15    sdmmc4
-  16    unassigned
-  17    pwm
-  18    i2s2
-  19    epp
-  20    unassigned      (register bit affects vi and vi_sensor)
-  21    2d
-  22    usbd
-  23    isp
-  24    3d
-  25    unassigned
-  26    disp2
-  27    disp1
-  28    host1x
-  29    vcp
-  30    i2s0
-  31    cop_cache
-  32    mc
-  33    ahbdma
-  34    apbdma
-  35    unassigned
-  36    kbc
-  37    statmon
-  38    pmc
-  39    unassigned      (register bit affects fuse and fuse_burn)
-  40    kfuse
-  41    sbc1
-  42    nor
-  43    unassigned
-  44    sbc2
-  45    unassigned
-  46    sbc3
-  47    i2c5
-  48    dsia
-  49    unassigned      (register bit affects cve and tvo)
-  50    mipi
-  51    hdmi
-  52    csi
-  53    tvdac
-  54    i2c2
-  55    uartc
-  56    unassigned
-  57    emc
-  58    usb2
-  59    usb3
-  60    mpe
-  61    vde
-  62    bsea
-  63    bsev
-  64    speedo
-  65    uartd
-  66    uarte
-  67    i2c3
-  68    sbc4
-  69    sdmmc3
-  70    pcie
-  71    owr
-  72    afi
-  73    csite
-  74    pciex
-  75    avpucq
-  76    la
-  77    unassigned
-  78    unassigned
-  79    dtv
-  80    ndspeed
-  81    i2cslow
-  82    dsib
-  83    unassigned
-  84    irama
-  85    iramb
-  86    iramc
-  87    iramd
-  88    cram2
-  89    unassigned
-  90    audio_2x        a/k/a audio_2x_sync_clk
-  91    unassigned
-  92    csus
-  93    cdev2
-  94    cdev1
-  95    unassigned
-  96    cpu_g
-  97    cpu_lp
-  98    3d2
-  99    mselect
-  100   tsensor
-  101   i2s3
-  102   i2s4
-  103   i2c4
-  104   sbc5
-  105   sbc6
-  106   d_audio
-  107   apbif
-  108   dam0
-  109   dam1
-  110   dam2
-  111   hda2codec_2x
-  112   atomics
-  113   audio0_2x
-  114   audio1_2x
-  115   audio2_2x
-  116   audio3_2x
-  117   audio4_2x
-  118   audio5_2x
-  119   actmon
-  120   extern1
-  121   extern2
-  122   extern3
-  123   sata_oob
-  124   sata
-  125   hda
-  127   se
-  128   hda2hdmi
-  129   sata_cold
-  160   uartb
-  161   vfir
-  162   spdif_in
-  163   spdif_out
-  164   vi
-  165   vi_sensor
-  166   fuse
-  167   fuse_burn
-  168   cve
-  169   tvo
-  170   clk_32k
-  171   clk_m
-  172   clk_m_div2
-  173   clk_m_div4
-  174   pll_ref
-  175   pll_c
-  176   pll_c_out1
-  177   pll_m
-  178   pll_m_out1
-  179   pll_p
-  180   pll_p_out1
-  181   pll_p_out2
-  182   pll_p_out3
-  183   pll_p_out4
-  184   pll_a
-  185   pll_a_out0
-  186   pll_d
-  187   pll_d_out0
-  188   pll_d2
-  189   pll_d2_out0
-  190   pll_u
-  191   pll_x
-  192   pll_x_out0
-  193   pll_e
-  194   spdif_in_sync
-  195   i2s0_sync
-  196   i2s1_sync
-  197   i2s2_sync
-  198   i2s3_sync
-  199   i2s4_sync
-  200   vimclk
-  201   audio0
-  202   audio1
-  203   audio2
-  204   audio3
-  205   audio4
-  206   audio5
-  207   clk_out_1 (extern1)
-  208   clk_out_2 (extern2)
-  209   clk_out_3 (extern3)
-  210   sclk
-  211   blink
-  212   cclk_g
-  213   cclk_lp
-  214   twd
-  215   cml0
-  216   cml1
-  217   hclk
-  218   pclk
 Example SoC include file:
@@ -229,7 +26,7 @@ Example SoC include file:
        };
        usb@c5004000 {
-                clocks = <&tegra_car 58>; /* usb2 */
+                clocks = <&tegra_car TEGRA30_CLK_USB2>;
        };
 };
diff --git a/Documentation/devicetree/bindings/clock/rockchip.txt b/Documentation/devicetree/bindings/clock/rockchip.txt
new file mode 100644
index 000000000000..a891c823ed44
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip.txt
@@ -0,0 +1,74 @@
+Device Tree Clock bindings for arch-rockchip
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+== Gate clocks ==
+The gate registers form a continuos block which makes the dt node
+structure a matter of taste, as either all gates can be put into
+one gate clock spanning all registers or they can be divided into
+the 10 individual gates containing 16 clocks each.
+The code supports both approaches.
+Required properties:
+- compatible : "rockchip,rk2928-gate-clk"
+- reg : shall be the control register address(es) for the clock.
+- #clock-cells : from common clock binding; shall be set to 1
+- clock-output-names : the corresponding gate names that the clock controls
+- clocks : should contain the parent clock for each individual gate,
+  therefore the number of clocks elements should match the number of
+  clock-output-names
+Example using multiple gate clocks:
+                clk_gates0: gate-clk@200000d0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d0 0x4>;
+                        clocks = <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>;
+                        clock-output-names =
+                                "gate_core_periph", "gate_cpu_gpll",
+                                "gate_ddrphy", "gate_aclk_cpu",
+                                "gate_hclk_cpu", "gate_pclk_cpu",
+                                "gate_atclk_cpu", "gate_i2s0",
+                                "gate_i2s0_frac", "gate_i2s1",
+                                "gate_i2s1_frac", "gate_i2s2",
+                                "gate_i2s2_frac", "gate_spdif",
+                                "gate_spdif_frac", "gate_testclk";
+                        #clock-cells = <1>;
+                };
+                clk_gates1: gate-clk@200000d4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d4 0x4>;
+                        clocks = <&xin24m>, <&xin24m>,
+                                 <&xin24m>, <&dummy>,
+                                 <&dummy>, <&xin24m>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>;
+                        clock-output-names =
+                                "gate_timer0", "gate_timer1",
+                                "gate_timer2", "gate_jtag",
+                                "gate_aclk_lcdc1_src", "gate_otgphy0",
+                                "gate_otgphy1", "gate_ddr_gpll",
+                                "gate_uart0", "gate_frac_uart0",
+                                "gate_uart1", "gate_frac_uart1",
+                                "gate_uart2", "gate_frac_uart2",
+                                "gate_uart3", "gate_frac_uart3";
+                        #clock-cells = <1>;
+                };
diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
index cc374651662c..c40711e8e8f7 100644
--- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt
+++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
@@ -4,7 +4,7 @@ Reference
 [1] Si5351A/B/C Data Sheet
    http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
-The Si5351a/b/c are programmable i2c clock generators with upto 8 output
+The Si5351a/b/c are programmable i2c clock generators with up to 8 output
 clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
 3 output clocks are accessible. The internal structure of the clock
 generators can be found in [1].
@@ -44,6 +44,11 @@ Optional child node properties:
 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
  divider.
 - silabs,pll-master: boolean, multisynth can change pll frequency.
+- silabs,disable-state : clock output disable state, shall be
+  0 = clock output is driven LOW when disabled
+  1 = clock output is driven HIGH when disabled
+  2 = clock output is FLOATING (HIGH-Z) when disabled
+  3 = clock output is NEVER disabled
 ==Example==
diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt
new file mode 100644
index 000000000000..7fc09773de46
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,nomadik.txt
@@ -0,0 +1,104 @@
+ST Microelectronics Nomadik SRC System Reset and Control
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+The Nomadik SRC controller is responsible of controlling chrystals,
+PLLs and clock gates.
+Required properties for the SRC node:
+- compatible: must be "stericsson,nomadik-src"
+- reg: must contain the SRC register base and size
+Optional properties for the SRC node:
+- disable-sxtalo: if present this will disable the SXTALO
+  i.e. the driver output for the slow 32kHz chrystal, if the
+  board has its own circuitry for providing this oscillator
+- disable-mxtal: if present this will disable the MXTALO,
+  i.e. the driver output for the main (~19.2 MHz) chrystal,
+  if the board has its own circuitry for providing this
+  osciallator
+PLL nodes: these nodes represent the two PLLs on the system,
+which should both have the main chrystal, represented as a
+fixed frequency clock, as parent.
+Required properties for the two PLL nodes:
+- compatible: must be "st,nomadik-pll-clock"
+- clock-cells: must be 0
+- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
+- clocks: this clock will have main chrystal as parent
+HCLK nodes: these represent the clock gates on individual
+lines from the HCLK clock tree and the gate for individual
+lines from the PCLK clock tree.
+Requires properties for the HCLK nodes:
+- compatible: must be "st,nomadik-hclk-clock"
+- clock-cells: must be 0
+- clock-id: must be the clock ID from 0 to 63 according to
+  this table:
+        0:  HCLKDMA0
+        1:  HCLKSMC
+        2:  HCLKSDRAM
+        3:  HCLKDMA1
+        4:  HCLKCLCD
+        5:  PCLKIRDA
+        6:  PCLKSSP
+        7:  PCLKUART0
+        8:  PCLKSDI
+        9:  PCLKI2C0
+        10: PCLKI2C1
+        11: PCLKUART1
+        12: PCLMSP0
+        13: HCLKUSB
+        14: HCLKDIF
+        15: HCLKSAA
+        16: HCLKSVA
+        17: PCLKHSI
+        18: PCLKXTI
+        19: PCLKUART2
+        20: PCLKMSP1
+        21: PCLKMSP2
+        22: PCLKOWM
+        23: HCLKHPI
+        24: PCLKSKE
+        25: PCLKHSEM
+        26: HCLK3D
+        27: HCLKHASH
+        28: HCLKCRYP
+        29: PCLKMSHC
+        30: HCLKUSBM
+        31: HCLKRNG
+        (32, 33, 34, 35 RESERVED)
+        36: CLDCLK
+        37: IRDACLK
+        38: SSPICLK
+        39: UART0CLK
+        40: SDICLK
+        41: I2C0CLK
+        42: I2C1CLK
+        43: UART1CLK
+        44: MSPCLK0
+        45: USBCLK
+        46: DIFCLK
+        47: IPI2CCLK
+        48: IPBMCCLK
+        49: HSICLKRX
+        50: HSICLKTX
+        51: UART2CLK
+        52: MSPCLK1
+        53: MSPCLK2
+        54: OWMCLK
+        (55 RESERVED)
+        56: SKECLK
+        (57 RESERVED)
+        58: 3DCLK
+        59: PCLKMSP3
+        60: MSPCLK3
+        61: MSHCCLK
+        62: USBMCLK
+        63: RNGCCLK
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 000000000000..7cafcb98ead7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,80 @@
+Clock bindings for ST-Ericsson U300 System Controller Clocks
+Bindings for the gated system controller clocks:
+Required properties:
+- compatible: must be "stericsson,u300-syscon-clk"
+- #clock-cells: must be <0>
+- clock-type: specifies the type of clock:
+  0 = slow clock
+  1 = fast clock
+  2 = rest/remaining clock
+- clock-id: specifies the clock in the type range
+Optional properties:
+- clocks: parent clock(s)
+The available clocks per type are as follows:
+Type:  ID:   Clock:
+-------------------
+0      0     Slow peripheral bridge clock
+0      1     UART0 clock
+0      4     GPIO clock
+0      6     RTC clock
+0      7     Application timer clock
+0      8     Access timer clock
+1      0     Fast peripheral bridge clock
+1      1     I2C bus 0 clock
+1      2     I2C bus 1 clock
+1      5     MMC interface peripheral (silicon) clock
+1      6     SPI clock
+2      3     CPU clock
+2      4     DMA controller clock
+2      5     External Memory Interface (EMIF) clock
+2      6     NAND flask interface clock
+2      8     XGAM graphics engine clock
+2      9     Shared External Memory Interface (SEMI) clock
+2      10    AHB Subsystem Bridge clock
+2      12    Interrupt controller clock
+Example:
+gpio_clk: gpio_clk@13M {
+        #clock-cells = <0>;
+        compatible = "stericsson,u300-syscon-clk";
+        clock-type = <0>; /* Slow */
+        clock-id = <4>;
+        clocks = <&slow_clk>;
+};
+gpio: gpio@c0016000 {
+        compatible = "stericsson,gpio-coh901";
+        (...)
+        clocks = <&gpio_clk>;
+};
+Bindings for the MMC/SD card clock:
+Required properties:
+- compatible: must be "stericsson,u300-syscon-mclk"
+- #clock-cells: must be <0>
+Optional properties:
+- clocks: parent clock(s)
+mmc_mclk: mmc_mclk {
+        #clock-cells = <0>;
+        compatible = "stericsson,u300-syscon-mclk";
+        clocks = <&mmc_pclk>;
+};
+mmcsd: mmcsd@c0001000 {
+        compatible = "arm,pl18x", "arm,primecell";
+        clocks = <&mmc_pclk>, <&mmc_mclk>;
+        clock-names = "apb_pclk", "mclk";
+        (...)
+};
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index 729f52426fe1..d495521a79d2 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -12,22 +12,30 @@ Required properties:
        "allwinner,sun4i-axi-clk" - for the AXI clock
        "allwinner,sun4i-axi-gates-clk" - for the AXI gates
        "allwinner,sun4i-ahb-clk" - for the AHB clock
-        "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
+        "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
+        "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
        "allwinner,sun4i-apb0-clk" - for the APB0 clock
-        "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
+        "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
+        "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
        "allwinner,sun4i-apb1-clk" - for the APB1 clock
        "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
-        "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
+        "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
+        "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
 - clocks : shall be the input parent clock(s) phandle for the clock
 - #clock-cells : from common clock binding; shall be set to 0 except for
-        "allwinner,sun4i-*-gates-clk" where it shall be set to 1
+        "allwinner,*-gates-clk" where it shall be set to 1
-Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
+Additionally, "allwinner,*-gates-clk" clocks require:
 - clock-output-names : the corresponding gate names that the clock controls
+Clock consumers should specify the desired clocks they use with a
+"clocks" phandle cell. Consumers that are using a gated clock should
+provide an additional ID in their clock property. The values of this
+ID are documented in sunxi/<soc>-gates.txt.
 For example:
 osc24M: osc24M@01c20050 {
@@ -50,102 +58,3 @@ cpu: cpu@01c20054 {
        reg = <0x01c20054 0x4>;
        clocks = <&osc32k>, <&osc24M>, <&pll1>;
 };
-Gate clock outputs
-The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
-their corresponding offsets as present on sun4i are listed below. Note that
-some of these gates are not present on sun5i.
-  * AXI gates ("allwinner,sun4i-axi-gates-clk")
-    DRAM                                                                0
-  * AHB gates ("allwinner,sun4i-ahb-gates-clk")
-    USB0                                                                0
-    EHCI0                                                               1
-    OHCI0                                                               2*
-    EHCI1                                                               3
-    OHCI1                                                               4*
-    SS                                                                  5
-    DMA                                                                 6
-    BIST                                                                7
-    MMC0                                                                8
-    MMC1                                                                9
-    MMC2                                                                10
-    MMC3                                                                11
-    MS                                                                  12**
-    NAND                                                                13
-    SDRAM                                                               14
-    ACE                                                                 16
-    EMAC                                                                17
-    TS                                                                  18
-    SPI0                                                                20
-    SPI1                                                                21
-    SPI2                                                                22
-    SPI3                                                                23
-    PATA                                                                24
-    SATA                                                                25**
-    GPS                                                                 26*
-    VE                                                                  32
-    TVD                                                                 33
-    TVE0                                                                34
-    TVE1                                                                35
-    LCD0                                                                36
-    LCD1                                                                37
-    CSI0                                                                40
-    CSI1                                                                41
-    HDMI                                                                43
-    DE_BE0                                                              44
-    DE_BE1                                                              45
-    DE_FE0                                                              46
-    DE_FE1                                                              47
-    MP                                                                  50
-    MALI400                                                             52
-  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
-    CODEC                                                               0
-    SPDIF                                                               1*
-    AC97                                                                2
-    IIS                                                                 3
-    PIO                                                                 5
-    IR0                                                                 6
-    IR1                                                                 7
-    KEYPAD                                                              10
-  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
-    I2C0                                                                0
-    I2C1                                                                1
-    I2C2                                                                2
-    CAN                                                                 4
-    SCR                                                                 5
-    PS20                                                                6
-    PS21                                                                7
-    UART0                                                               16
-    UART1                                                               17
-    UART2                                                               18
-    UART3                                                               19
-    UART4                                                               20
-    UART5                                                               21
-    UART6                                                               22
-    UART7                                                               23
-Notation:
- [*]:  The datasheet didn't mention these, but they are present on AW code
- [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
new file mode 100644
index 000000000000..6a03475bbfe2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun4i-a10-gates.txt
@@ -0,0 +1,93 @@
+Gate clock outputs
+------------------
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+    DRAM                                        0
+  * AHB gates ("allwinner,sun4i-ahb-gates-clk")
+    USB0                                        0
+    EHCI0                                       1
+    OHCI0                                       2*
+    EHCI1                                       3
+    OHCI1                                       4*
+    SS                                          5
+    DMA                                         6
+    BIST                                        7
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+    MMC3                                        11
+    MS                                          12**
+    NAND                                        13
+    SDRAM                                       14
+    ACE                                         16
+    EMAC                                        17
+    TS                                          18
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+    SPI3                                        23
+    PATA                                        24
+    SATA                                        25**
+    GPS                                         26*
+    VE                                          32
+    TVD                                         33
+    TVE0                                        34
+    TVE1                                        35
+    LCD0                                        36
+    LCD1                                        37
+    CSI0                                        40
+    CSI1                                        41
+    HDMI                                        43
+    DE_BE0                                      44
+    DE_BE1                                      45
+    DE_FE1                                      46
+    DE_FE1                                      47
+    MP                                          50
+    MALI400                                     52
+  * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
+    CODEC                                       0
+    SPDIF                                       1*
+    AC97                                        2
+    IIS                                         3
+    PIO                                         5
+    IR0                                         6
+    IR1                                         7
+    KEYPAD                                      10
+  * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+    CAN                                         4
+    SCR                                         5
+    PS20                                        6
+    PS21                                        7
+    UART0                                       16
+    UART1                                       17
+    UART2                                       18
+    UART3                                       19
+    UART4                                       20
+    UART5                                       21
+    UART6                                       22
+    UART7                                       23
+Notation:
+ [*]:  The datasheet didn't mention these, but they are present on AW code
+ [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
new file mode 100644
index 000000000000..006b6dfc4703
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a13-gates.txt
@@ -0,0 +1,58 @@
+Gate clock outputs
+------------------
+  * AXI gates ("allwinner,sun4i-axi-gates-clk")
+    DRAM                                        0
+  * AHB gates ("allwinner,sun5i-a13-ahb-gates-clk")
+    USBOTG                                      0
+    EHCI                                        1
+    OHCI                                        2
+    SS                                          5
+    DMA                                         6
+    BIST                                        7
+    MMC0                                        8
+    MMC1                                        9
+    MMC2                                        10
+    NAND                                        13
+    SDRAM                                       14
+    SPI0                                        20
+    SPI1                                        21
+    SPI2                                        22
+    STIMER                                      28
+    VE                                          32
+    LCD                                         36
+    CSI                                         40
+    DE_BE                                       44
+    DE_FE                                       46
+    IEP                                         51
+    MALI400                                     52
+  * APB0 gates ("allwinner,sun5i-a13-apb0-gates-clk")
+    CODEC                                       0
+    PIO                                         5
+    IR                                          6
+  * APB1 gates ("allwinner,sun5i-a13-apb1-gates-clk")
+    I2C0                                        0
+    I2C1                                        1
+    I2C2                                        2
+    UART1                                       17
+    UART3                                       19
diff --git a/Documentation/devicetree/bindings/clock/vf610-clock.txt b/Documentation/devicetree/bindings/clock/vf610-clock.txt
new file mode 100644
index 000000000000..c80863d344ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vf610-clock.txt
@@ -0,0 +1,26 @@
+* Clock bindings for Freescale Vybrid VF610 SOC
+Required properties:
+- compatible: Should be "fsl,vf610-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/vf610-clock.h
+for the full list of VF610 clock IDs.
+Examples:
+clks: ccm@4006b000 {
+        compatible = "fsl,vf610-ccm";
+        reg = <0x4006b000 0x1000>;
+        #clock-cells = <1>;
+};
+uart1: serial@40028000 {
+        compatible = "fsl,vf610-uart";
+        reg = <0x40028000 0x1000>;
+        interrupts = <0 62 0x04>;
+        clocks = <&clks VF610_CLK_UART1>;
+        clock-names = "ipg";
+};
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
index a880c70d0047..91d71cc0314a 100644
--- a/Documentation/devicetree/bindings/clock/vt8500.txt
+++ b/Documentation/devicetree/bindings/clock/vt8500.txt
@@ -8,6 +8,8 @@ Required properties:
 - compatible : shall be one of the following:
        "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
        "wm,wm8650-pll-clock" - for a WM8650 PLL clock
+        "wm,wm8750-pll-clock" - for a WM8750 PLL clock
+        "wm,wm8850-pll-clock" - for a WM8850 PLL clock
        "via,vt8500-device-clock" - for a VT/WM device clock
 Required properties for PLL clocks:
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 23ae1db1bc13..d99af878f5d7 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -6,50 +6,99 @@ The purpose of this document is to document their usage.
 See clock_bindings.txt for more information on the generic clock bindings.
 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
-== PLLs ==
+== Clock Controller ==
+The clock controller is a logical abstraction of Zynq's clock tree. It reads
-Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
+required input clock frequencies from the devicetree and acts as clock provider
+for all clock consumers of PS clocks.
 Required properties:
- #clock-cells : shall be 0 (only one clock is output from this node)
+ - #clock-cells : Must be 1
- compatible : "xlnx,zynq-pll"
+ - compatible : "xlnx,ps7-clkc"
- reg : pair of u32 values, which are the address offsets within the SLCR
+ - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
-        of the relevant PLL_CTRL register and PLL_CFG register respectively
+                      (usually 33 MHz oscillators are used for Zynq platforms)
- clocks : phandle for parent clock.  should be the phandle for ps_clk
+ - clock-output-names : List of strings used to name the clock outputs. Shall be
+                        a list of the outputs given below.
 Optional properties:
- clock-output-names : name of the output clock
+ - clocks : as described in the clock bindings
+ - clock-names : as described in the clock bindings
-Example:
-        armpll: armpll {
-                #clock-cells = <0>;
-                compatible = "xlnx,zynq-pll";
-                clocks = <&ps_clk>;
-                reg = <0x100 0x110>;
-                clock-output-names = "armpll";
-        };
-== Peripheral clocks ==
-Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
+Clock inputs:
+The following strings are optional parameters to the 'clock-names' property in
+order to provide an optional (E)MIO clock source.
+ - swdt_ext_clk
+ - gem0_emio_clk
+ - gem1_emio_clk
+ - mio_clk_XX           # with XX = 00..53
+...
-Required properties:
+Clock outputs:
- #clock-cells : shall be 1
+ 0:  armpll
- compatible : "xlnx,zynq-periph-clock"
+ 1:  ddrpll
- reg : a single u32 value, describing the offset within the SLCR where
+ 2:  iopll
-        the CLK_CTRL register is found for this peripheral
+ 3:  cpu_6or4x
- clocks : phandle for parent clocks.  should hold phandles for
+ 4:  cpu_3or2x
-           the IO_PLL, ARM_PLL, and DDR_PLL in order
+ 5:  cpu_2x
- clock-output-names : names of the output clock(s).  For peripherals that have
+ 6:  cpu_1x
-                       two output clocks (for example, the UART), two clocks
+ 7:  ddr2x
-                       should be listed.
+ 8:  ddr3x
+ 9:  dci
+ 10: lqspi
+ 11: smc
+ 12: pcap
+ 13: gem0
+ 14: gem1
+ 15: fclk0
+ 16: fclk1
+ 17: fclk2
+ 18: fclk3
+ 19: can0
+ 20: can1
+ 21: sdio0
+ 22: sdio1
+ 23: uart0
+ 24: uart1
+ 25: spi0
+ 26: spi1
+ 27: dma
+ 28: usb0_aper
+ 29: usb1_aper
+ 30: gem0_aper
+ 31: gem1_aper
+ 32: sdio0_aper
+ 33: sdio1_aper
+ 34: spi0_aper
+ 35: spi1_aper
+ 36: can0_aper
+ 37: can1_aper
+ 38: i2c0_aper
+ 39: i2c1_aper
+ 40: uart0_aper
+ 41: uart1_aper
+ 42: gpio_aper
+ 43: lqspi_aper
+ 44: smc_aper
+ 45: swdt
+ 46: dbg_trc
+ 47: dbg_apb
 Example:
-        uart_clk: uart_clk {
+        clkc: clkc {
                #clock-cells = <1>;
-                compatible = "xlnx,zynq-periph-clock";
+                compatible = "xlnx,ps7-clkc";
-                clocks = <&iopll &armpll &ddrpll>;
+                ps-clk-frequency = <33333333>;
-                reg = <0x154>;
+                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
-                clock-output-names = "uart0_ref_clk",
+                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
-                                     "uart1_ref_clk";
+                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                "dbg_trc", "dbg_apb";
+                # optional props
+                clocks = <&clkc 16>, <&clk_foo>;
+                clock-names = "gem1_emio_clk", "can_mio_clk_23";
        };
diff --git a/Documentation/devicetree/bindings/dma/ste-coh901318.txt b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
new file mode 100644
index 000000000000..091ad057e9cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-coh901318.txt
@@ -0,0 +1,32 @@
+ST-Ericsson COH 901 318 DMA Controller
+This is a DMA controller which has begun as a fork of the
+ARM PL08x PrimeCell VHDL code.
+Required properties:
+- compatible: should be "stericsson,coh901318"
+- reg: register locations and length
+- interrupts: the single DMA IRQ
+- #dma-cells: must be set to <1>, as the channels on the
+  COH 901 318 are simple and identified by a single number
+- dma-channels: the number of DMA channels handled
+Example:
+dmac: dma-controller@c00020000 {
+        compatible = "stericsson,coh901318";
+        reg = <0xc0020000 0x1000>;
+        interrupt-parent = <&vica>;
+        interrupts = <2>;
+        #dma-cells = <1>;
+        dma-channels = <40>;
+};
+Consumers example:
+uart0: serial@c0013000 {
+        compatible = "...";
+        (...)
+        dmas = <&dmac 17 &dmac 18>;
+        dma-names = "tx", "rx";
+};
diff --git a/Documentation/devicetree/bindings/dma/ste-dma40.txt b/Documentation/devicetree/bindings/dma/ste-dma40.txt
new file mode 100644
index 000000000000..bea5b73a7390
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ste-dma40.txt
@@ -0,0 +1,66 @@
+* DMA40 DMA Controller
+Required properties:
+- compatible: "stericsson,dma40"
+- reg: Address range of the DMAC registers
+- reg-names: Names of the above areas to use during resource look-up
+- interrupt: Should contain the DMAC interrupt number
+- #dma-cells: must be <3>
+- memcpy-channels: Channels to be used for memcpy
+Optional properties:
+- dma-channels: Number of channels supported by hardware - if not present
+                the driver will attempt to obtain the information from H/W
+- disabled-channels: Channels which can not be used
+Example:
+        dma: dma-controller@801C0000 {
+                compatible = "stericsson,db8500-dma40", "stericsson,dma40";
+                reg = <0x801C0000 0x1000  0x40010000 0x800>;
+                reg-names = "base", "lcpa";
+                interrupt-parent = <&intc>;
+                interrupts = <0 25 0x4>;
+                #dma-cells = <2>;
+                memcpy-channels  = <56 57 58 59 60>;
+                disabled-channels  = <12>;
+                dma-channels = <8>;
+        };
+Clients
+Required properties:
+- dmas: Comma separated list of dma channel requests
+- dma-names: Names of the aforementioned requested channels
+Each dmas request consists of 4 cells:
+  1. A phandle pointing to the DMA controller
+  2. Device Type
+  3. The DMA request line number (only when 'use fixed channel' is set)
+  4. A 32bit mask specifying; mode, direction and endianess [NB: This list will grow]
+        0x00000001: Mode:
+                Logical channel when unset
+                Physical channel when set
+        0x00000002: Direction:
+                Memory to Device when unset
+                Device to Memory when set
+        0x00000004: Endianess:
+                Little endian when unset
+                Big endian when set
+        0x00000008: Use fixed channel:
+                Use automatic channel selection when unset
+                Use DMA request line number when set
+Example:
+        uart@80120000 {
+                compatible = "arm,pl011", "arm,primecell";
+                reg = <0x80120000 0x1000>;
+                interrupts = <0 11 0x4>;
+                dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+                       <&dma 13 0 0x0>; /* Logical - MemToDev */
+                dma-names = "rx", "rx";
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
new file mode 100644
index 000000000000..9fbbdb783a72
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -0,0 +1,34 @@
+TI EDMA
+Required properties:
+- compatible : "ti,edma3"
+- ti,edma-regions: Number of regions
+- ti,edma-slots: Number of slots
+- #dma-cells: Should be set to <1>
+              Clients should use a single channel number per DMA request.
+- dma-channels: Specify total DMA channels per CC
+- reg: Memory map for accessing module
+- interrupt-parent: Interrupt controller the interrupt is routed through
+- interrupts: Exactly 3 interrupts need to be specified in the order:
+              1. Transfer completion interrupt.
+              2. Memory protection interrupt.
+              3. Error interrupt.
+Optional properties:
+- ti,hwmods: Name of the hwmods associated to the EDMA
+- ti,edma-xbar-event-map: Crossbar event to channel map
+Example:
+edma: edma@49000000 {
+        reg = <0x49000000 0x10000>;
+        interrupt-parent = <&intc>;
+        interrupts = <12 13 14>;
+        compatible = "ti,edma3";
+        ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+        #dma-cells = <1>;
+        dma-channels = <64>;
+        ti,edma-regions = <4>;
+        ti,edma-slots = <256>;
+        ti,edma-xbar-event-map = <1 12
+                                  2 13>;
+};
diff --git a/Documentation/devicetree/bindings/extcon/extcon-twl.txt b/Documentation/devicetree/bindings/extcon/extcon-twl.txt
new file mode 100644
index 000000000000..58f531ab4df3
--- /dev/null
+++ b/Documentation/devicetree/bindings/extcon/extcon-twl.txt
@@ -0,0 +1,15 @@
+EXTCON FOR TWL CHIPS
+PALMAS USB COMPARATOR
+Required Properties:
+ - compatible : Should be "ti,palmas-usb" or "ti,twl6035-usb"
+ - vbus-supply : phandle to the regulator device tree node.
+Optional Properties:
+ - ti,wakeup : To enable the wakeup comparator in probe
+palmas-usb {
+       compatible = "ti,twl6035-usb", "ti,palmas-usb";
+       vbus-supply = <&smps10_reg>;
+       ti,wakeup;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
new file mode 100644
index 000000000000..e0d0446a6b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-clps711x.txt
@@ -0,0 +1,28 @@
+Cirrus Logic CLPS711X GPIO controller
+Required properties:
+- compatible: Should be "cirrus,clps711x-gpio"
+- reg: Physical base GPIO controller registers location and length.
+  There should be two registers, first is DATA register, the second
+  is DIRECTION.
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+    0 = active high
+    1 = active low
+Note: Each GPIO port should have an alias correctly numbered in "aliases"
+node.
+Example:
+aliases {
+        gpio0 = &porta;
+};
+porta: gpio@80000000 {
+        compatible = "cirrus,clps711x-gpio";
+        reg = <0x80000000 0x1>, <0x80000040 0x1>;
+        gpio-controller;
+        #gpio-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-msm.txt b/Documentation/devicetree/bindings/gpio/gpio-msm.txt
new file mode 100644
index 000000000000..ac20e68a004e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-msm.txt
@@ -0,0 +1,26 @@
+MSM GPIO controller bindings
+Required properties:
+- compatible:
+  - "qcom,msm-gpio" for MSM controllers
+- #gpio-cells : Should be two.
+  - first cell is the pin number
+  - second cell is used to specify optional parameters (unused)
+- gpio-controller : Marks the device node as a GPIO controller.
+- #interrupt-cells : Should be 2.
+- interrupt-controller: Mark the device node as an interrupt controller
+- interrupts : Specify the TLMM summary interrupt number
+- ngpio : Specify the number of MSM GPIOs
+Example:
+        msmgpio: gpio@fd510000 {
+                compatible = "qcom,msm-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <0xfd510000 0x4000>;
+                interrupts = <0 208 0>;
+                ngpio = <150>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index f1e5dfecf55d..5375625e8cd2 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,46 +39,3 @@ Example:
                #gpio-cells = <4>;
                gpio-controller;
        };
-Samsung S3C24XX GPIO Controller
-Required properties:
- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
- reg: Physical base address of the controller and length of memory mapped
-  region.
- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
-  should be the following with values derived from the SoC user manual.
-     <[phandle of the gpio controller node]
-      [pin number within the gpio controller]
-      [mux function]
-      [flags and pull up/down]
-  Values for gpio specifier:
-  - Pin number: depending on the controller a number from 0 up to 15.
-  - Mux function: Depending on the SoC and the gpio bank the gpio can be set
-                  as input, output or a special function
-  - Flags and Pull Up/Down: the values to use differ for the individual SoCs
-                    example S3C2416/S3C2450:
-                            0 - Pull Up/Down Disabled.
-                            1 - Pull Down Enabled.
-                            2 - Pull Up Enabled.
-          Bit 16 (0x00010000) - Input is active low.
-  Consult the user manual for the correct values of Mux and Pull Up/Down.
- gpio-controller: Specifies that the node is a gpio controller.
- #address-cells: should be 1.
- #size-cells: should be 1.
-Example:
-        gpa: gpio-controller@56000000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "samsung,s3c24xx-gpio";
-                reg = <0x56000000 0x10>;
-                #gpio-cells = <3>;
-                gpio-controller;
-        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
new file mode 100644
index 000000000000..fd665b44d767
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-stericsson-coh901.txt
@@ -0,0 +1,7 @@
+ST-Ericsson COH 901 571/3 GPIO controller
+Required properties:
+- compatible: Compatible property value should be "stericsson,gpio-coh901"
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+- interrupts: the 0...n interrupts assigned to the different GPIO ports/banks.
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
new file mode 100644
index 000000000000..63bf4becd5f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-xilinx.txt
@@ -0,0 +1,48 @@
+Xilinx plb/axi GPIO controller
+Dual channel GPIO controller with configurable number of pins
+(from 1 to 32 per channel). Every pin can be configured as
+input/output/tristate. Both channels share the same global IRQ but
+local interrupts can be enabled on channel basis.
+Required properties:
+- compatible : Should be "xlnx,xps-gpio-1.00.a"
+- reg : Address and length of the register set for the device
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters (currently unused).
+- gpio-controller : Marks the device node as a GPIO controller.
+Optional properties:
+- interrupts : Interrupt mapping for GPIO IRQ.
+- interrupt-parent : Phandle for the interrupt controller that
+  services interrupts for this device.
+- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input
+- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1
+- xlnx,gpio-width : gpio width
+- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode
+- xlnx,is-dual : if 1, controller also uses the second channel
+- xlnx,all-inputs-2 : as above but for the second channel
+- xlnx,dout-default-2 : as above but the second channel
+- xlnx,gpio2-width : as above but for the second channel
+- xlnx,tri-default-2 : as above but for the second channel
+Example:
+gpio: gpio@40000000 {
+        #gpio-cells = <2>;
+        compatible = "xlnx,xps-gpio-1.00.a";
+        gpio-controller ;
+        interrupt-parent = <&microblaze_0_intc>;
+        interrupts = < 6 2 >;
+        reg = < 0x40000000 0x10000 >;
+        xlnx,all-inputs = <0x0>;
+        xlnx,all-inputs-2 = <0x0>;
+        xlnx,dout-default = <0x0>;
+        xlnx,dout-default-2 = <0x0>;
+        xlnx,gpio-width = <0x2>;
+        xlnx,gpio2-width = <0x2>;
+        xlnx,interrupt-present = <0x1>;
+        xlnx,is-dual = <0x1>;
+        xlnx,tri-default = <0xffffffff>;
+        xlnx,tri-default-2 = <0xffffffff>;
+} ;
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
new file mode 100644
index 000000000000..cb3dc7bcd8e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
@@ -0,0 +1,46 @@
+* Renesas R-Car GPIO Controller
+Required Properties:
+  - compatible: should be one of the following.
+    - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller.
+    - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
+    - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
+    - "renesas,gpio-rcar": for generic R-Car GPIO controller.
+  - reg: Base address and length of each memory resource used by the GPIO
+    controller hardware module.
+  - interrupt-parent: phandle of the parent interrupt controller.
+  - interrupts: Interrupt specifier for the controllers interrupt.
+  - gpio-controller: Marks the device node as a gpio controller.
+  - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+  - gpio-ranges: Range of pins managed by the GPIO controller.
+Please refer to gpio.txt in this directory for details of gpio-ranges property
+and the common GPIO bindings used by client devices.
+Example: R8A7779 (R-Car H1) GPIO controller nodes
+        gpio0: gpio@ffc40000 {
+                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+                reg = <0xffc40000 0x2c>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 141 0x4>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 0 32>;
+        };
+        ...
+        gpio6: gpio@ffc46000 {
+                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
+                reg = <0xffc46000 0x2c>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 147 0x4>;
+                #gpio-cells = <2>;
+                gpio-controller;
+                gpio-ranges = <&pfc 0 192 9>;
+        };
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 2b14a940eb75..3f454ffc654a 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -10,11 +10,16 @@ Required properties:
          mapped region.
  - interrupts : G2D interrupt number to the CPU.
+  - clocks : from common clock binding: handle to G2D clocks.
+  - clock-names : from common clock binding: must contain "sclk_fimg2d" and
+                  "fimg2d", corresponding to entries in the clocks property.
 Example:
        g2d@12800000 {
                compatible = "samsung,s5pv210-g2d";
                reg = <0x12800000 0x1000>;
                interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                status = "disabled";
        };
diff --git a/Documentation/devicetree/bindings/hwmon/g762.txt b/Documentation/devicetree/bindings/hwmon/g762.txt
new file mode 100644
index 000000000000..25cc6d8ee575
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/g762.txt
@@ -0,0 +1,47 @@
+GMT G762/G763 PWM Fan controller
+Required node properties:
+ - "compatible": must be either "gmt,g762" or "gmt,g763"
+ - "reg": I2C bus address of the device
+ - "clocks": a fixed clock providing input clock frequency
+             on CLK pin of the chip.
+Optional properties:
+ - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3.
+               The higher the more.
+ - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty)
+               and 1 (negative duty).
+ - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2.
+If an optional property is not set in .dts file, then current value is kept
+unmodified (e.g. u-boot installed value).
+Additional information on operational parameters for the device is available
+in Documentation/hwmon/g762. A detailed datasheet for the device is available
+at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.
+Example g762 node:
+   clocks {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        g762_clk: fixedclk {
+                 compatible = "fixed-clock";
+                 #clock-cells = <0>;
+                 clock-frequency = <8192>;
+        }
+   }
+   g762: g762@3e {
+        compatible = "gmt,g762";
+        reg = <0x3e>;
+        clocks = <&g762_clk>
+        fan_gear_mode = <0>; /* chip default */
+        fan_startv = <1>;    /* chip default */
+        pwm_polarity = <0>;  /* chip default */
+   };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
index e42a2ee233e6..7fd7fa25e9b0 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
@@ -10,6 +10,10 @@ Recommended properties :
 - clock-frequency : desired I2C bus clock frequency in Hz.
+Optional properties :
+ - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
+   This option is only supported in hardware blocks version 1.11a or newer.
 Example :
        i2c@f0000 {
@@ -20,3 +24,14 @@ Example :
                interrupts = <11>;
                clock-frequency = <400000>;
        };
+        i2c@1120000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,designware-i2c";
+                reg = <0x1120000 0x1000>;
+                interrupt-parent = <&ictl>;
+                interrupts = <12 1>;
+                clock-frequency = <400000>;
+                i2c-sda-hold-time-ns = <300>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
index f46d928aa73d..a1ee681942cc 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
@@ -6,7 +6,11 @@ Required properties :
 - reg             : Offset and length of the register set for the device
 - compatible      : Should be "marvell,mv64xxx-i2c"
 - interrupts      : The interrupt number
- - clock-frequency : Desired I2C bus clock frequency in Hz.
+Optional properties :
+ - clock-frequency : Desired I2C bus clock frequency in Hz. If not set the
+default frequency is 100kHz
 Examples:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
new file mode 100644
index 000000000000..bd81a482634f
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-st-ddci2c.txt
@@ -0,0 +1,15 @@
+ST Microelectronics DDC I2C
+Required properties :
+- compatible : Must be "st,ddci2c"
+- reg: physical base address of the controller and length of memory mapped
+     region.
+- interrupts: interrupt number to the cpu.
+- #address-cells = <1>;
+- #size-cells = <0>;
+Optional properties:
+- Child nodes conforming to i2c bus binding
+Examples :
diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 000000000000..94a425eaa6c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+Required properties :
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+Optional properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+        Valid values are 100000 and 400000.
+        Default to 100000 if not specified, or invalid value.
+Example :
+        i2c_0: i2c@d8280000 {
+                compatible = "wm,wm8505-i2c";
+                reg = <0xd8280000 0x1000>;
+                interrupts = <19>;
+                clocks = <&clki2c0>;
+                clock-frequency = <400000>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/ina2xx.txt b/Documentation/devicetree/bindings/i2c/ina2xx.txt
new file mode 100644
index 000000000000..a2ad85d7e747
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/ina2xx.txt
@@ -0,0 +1,22 @@
+ina2xx properties
+Required properties:
+- compatible: Must be one of the following:
+        - "ti,ina219" for ina219
+        - "ti,ina220" for ina220
+        - "ti,ina226" for ina226
+        - "ti,ina230" for ina230
+- reg: I2C address
+Optional properties:
+- shunt-resistor
+        Shunt resistor value in micro-Ohm
+Example:
+ina220@44 {
+        compatible = "ti,ina220";
+        reg = <0x44>;
+        shunt-resistor = <1000>;
+};
diff --git a/Documentation/devicetree/bindings/iio/dac/ad7303.txt b/Documentation/devicetree/bindings/iio/dac/ad7303.txt
new file mode 100644
index 000000000000..914610f0556e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/dac/ad7303.txt
@@ -0,0 +1,23 @@
+Analog Devices AD7303 DAC device driver
+Required properties:
+        - compatible: Must be "adi,ad7303"
+        - reg: SPI chip select number for the device
+        - spi-max-frequency: Max SPI frequency to use (< 30000000)
+        - Vdd-supply: Phandle to the Vdd power supply
+Optional properties:
+        - REF-supply: Phandle to the external reference voltage supply. This should
+          only be set if there is an external reference voltage connected to the REF
+          pin. If the property is not set Vdd/2 is used as the reference voltage.
+Example:
+                ad7303@4 {
+                        compatible = "adi,ad7303";
+                        reg = <4>;
+                        spi-max-frequency = <10000000>;
+                        Vdd-supply = <&vdd_supply>;
+                        adi,use-external-reference;
+                        REF-supply = <&vref_supply>;
+                };
diff --git a/Documentation/devicetree/bindings/iio/frequency/adf4350.txt b/Documentation/devicetree/bindings/iio/frequency/adf4350.txt
new file mode 100644
index 000000000000..f8c181d81d2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/frequency/adf4350.txt
@@ -0,0 +1,86 @@
+Analog Devices ADF4350/ADF4351 device driver
+Required properties:
+        - compatible: Should be one of
+                * "adi,adf4350": When using the ADF4350 device
+                * "adi,adf4351": When using the ADF4351 device
+        - reg: SPI chip select numbert for the device
+        - spi-max-frequency: Max SPI frequency to use (< 20000000)
+        - clocks: From common clock binding. Clock is phandle to clock for
+                ADF435x Reference Clock (CLKIN).
+Optional properties:
+        - gpios:         GPIO Lock detect - If set with a valid phandle and GPIO number,
+                        pll lock state is tested upon read.
+        - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
+        - adi,power-up-frequency:       If set in Hz the PLL tunes to
+                        the desired frequency on probe.
+        - adi,reference-div-factor: If set the driver skips dynamic calculation
+                        and uses this default value instead.
+        - adi,reference-doubler-enable: Enables reference doubler.
+        - adi,reference-div2-enable: Enables reference divider.
+        - adi,phase-detector-polarity-positive-enable: Enables positive phase
+                        detector polarity. Default = negative.
+        - adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
+                        Default = 10ns.
+        - adi,lock-detect-function-integer-n-enable: Enables lock detect
+                        for integer-N mode. Default = factional-N mode.
+        - adi,charge-pump-current: Charge pump current in mA.
+                        Default = 2500mA.
+        - adi,muxout-select: On chip multiplexer output selection.
+                        Valid values for the multiplexer output are:
+                        0: Three-State Output (default)
+                        1: DVDD
+                        2: DGND
+                        3: R-Counter output
+                        4: N-Divider output
+                        5: Analog lock detect
+                        6: Digital lock detect
+        - adi,low-spur-mode-enable: Enables low spur mode.
+                        Default = Low noise mode.
+        - adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
+        - adi,charge-cancellation-enable: Enabled charge pump
+                        charge cancellation for integer-N modes.
+        - adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
+                         for integer-N modes.
+        - adi,band-select-clock-mode-high-enable: Enables faster band
+                        selection logic.
+        - adi,12bit-clk-divider: Clock divider value used when
+                        adi,12bit-clkdiv-mode != 0
+        - adi,clk-divider-mode:
+                        Valid values for the clkdiv mode are:
+                        0: Clock divider off (default)
+                        1: Fast lock enable
+                        2: Phase resync enable
+        - adi,aux-output-enable: Enables auxiliary RF output.
+        - adi,aux-output-fundamental-enable: Selects fundamental VCO output on
+                        the auxiliary RF output. Default = Output of RF dividers.
+        - adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
+        - adi,output-power: Output power selection.
+                        Valid values for the power mode are:
+                        0: -4dBm (default)
+                        1: -1dBm
+                        2: +2dBm
+                        3: +5dBm
+        - adi,aux-output-power: Auxiliary output power selection.
+                        Valid values for the power mode are:
+                        0: -4dBm (default)
+                        1: -1dBm
+                        2: +2dBm
+                        3: +5dBm
+Example:
+                lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
+                        compatible = "adi,adf4351";
+                        reg = <4>;
+                        spi-max-frequency = <10000000>;
+                        clocks = <&clk0_ad9523 9>;
+                        clock-names = "clkin";
+                        adi,channel-spacing = <10000>;
+                        adi,power-up-frequency = <2400000000>;
+                        adi,phase-detector-polarity-positive-enable;
+                        adi,charge-pump-current = <2500>;
+                        adi,output-power = <3>;
+                        adi,mute-till-lock-enable;
+                };
diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt
new file mode 100644
index 000000000000..011679f1a425
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt
@@ -0,0 +1,18 @@
+* AsahiKASEI AK8975 magnetometer sensor
+Required properties:
+  - compatible : should be "asahi-kasei,ak8975"
+  - reg : the I2C address of the magnetometer
+Optional properties:
+  - gpios : should be device tree identifier of the magnetometer DRDY pin
+Example:
+ak8975@0c {
+        compatible = "asahi-kasei,ak8975";
+        reg = <0x0c>;
+        gpios = <&gpj0 7 0>;
+};
diff --git a/Documentation/devicetree/bindings/input/pxa27x-keypad.txt b/Documentation/devicetree/bindings/input/pxa27x-keypad.txt
new file mode 100644
index 000000000000..f8674f7e5ea5
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/pxa27x-keypad.txt
@@ -0,0 +1,60 @@
+* Marvell PXA Keypad controller
+Required Properties
+- compatible : should be "marvell,pxa27x-keypad"
+- reg : Address and length of the register set for the device
+- interrupts : The interrupt for the keypad controller
+- marvell,debounce-interval : How long time the key will be
+  recognized when it is pressed. It is a u32 value, and bit[31:16]
+  is debounce interval for direct key and bit[15:0] is debounce
+  interval for matrix key. The value is in binary number of 2ms
+Optional Properties For Matrix Keyes
+Please refer to matrix-keymap.txt
+Optional Properties for Direct Keyes
+- marvell,direct-key-count : How many direct keyes are used.
+- marvell,direct-key-mask : The mask indicates which keyes
+  are used. If bit[X] of the mask is set, the direct key X
+  is used.
+- marvell,direct-key-low-active : Direct key status register
+  tells the level of pins that connects to the direct keyes.
+  When this property is set, it means that when the pin level
+  is low, the key is pressed(active).
+- marvell,direct-key-map : It is a u16 array. Each item indicates
+  the linux key-code for the direct key.
+Optional Properties For Rotary
+- marvell,rotary0 : It is a u32 value. Bit[31:16] is the
+  linux key-code for rotary up. Bit[15:0] is the linux key-code
+  for rotary down. It is for rotary 0.
+- marvell,rotary1 : Same as marvell,rotary0. It is for rotary 1.
+- marvell,rotary-rel-key : When rotary is used for relative axes
+  in the device, the value indicates the key-code for relative
+  axes measurement in the device. It is a u32 value. Bit[31:16]
+  is for rotary 1, and Bit[15:0] is for rotary 0.
+Examples:
+        keypad: keypad@d4012000 {
+                keypad,num-rows = <3>;
+                keypad,num-columns = <5>;
+                linux,keymap = <0x0000000e      /* KEY_BACKSPACE */
+                                0x0001006b      /* KEY_END */
+                                0x00020061      /* KEY_RIGHTCTRL */
+                                0x0003000b      /* KEY_0 */
+                                0x00040002      /* KEY_1 */
+                                0x0100008b      /* KEY_MENU */
+                                0x01010066      /* KEY_HOME */
+                                0x010200e7      /* KEY_SEND */
+                                0x01030009      /* KEY_8 */
+                                0x0104000a      /* KEY_9 */
+                                0x02000160      /* KEY_OK */
+                                0x02010003      /* KEY_2 */
+                                0x02020004      /* KEY_3 */
+                                0x02030005      /* KEY_4 */
+                                0x02040006>;    /* KEY_5 */
+                marvell,rotary0 = <0x006c0067>; /* KEY_UP & KEY_DOWN */
+                marvell,direct-key-count = <1>;
+                marvell,direct-key-map = <0x001c>;
+                marvell,debounce-interval = <0x001e001e>;
+        };
diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt
index ce3e394c0e64..942d071baaa5 100644
--- a/Documentation/devicetree/bindings/input/samsung-keypad.txt
+++ b/Documentation/devicetree/bindings/input/samsung-keypad.txt
@@ -25,14 +25,6 @@ Required Board Specific Properties:
 - samsung,keypad-num-columns: Number of column lines connected to the
  keypad controller.
- row-gpios: List of gpios used as row lines. The gpio specifier for
-  this property depends on the gpio controller to which these row lines
-  are connected.
- col-gpios: List of gpios used as column lines. The gpio specifier for
-  this property depends on the gpio controller to which these column
-  lines are connected.
 - Keys represented as child nodes: Each key connected to the keypad
  controller is represented as a child node to the keypad controller
  device node and should include the following properties.
@@ -41,6 +33,9 @@ Required Board Specific Properties:
  - linux,code: the key-code to be reported when the key is pressed
    and released.
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - "default".
 Optional Properties specific to linux:
 - linux,keypad-no-autorepeat: do no enable autorepeat feature.
 - linux,keypad-wakeup: use any event on keypad as wakeup event.
@@ -56,17 +51,8 @@ Example:
                linux,input-no-autorepeat;
                linux,input-wakeup;
-                row-gpios = <&gpx2 0 3 3 0
+                pinctrl-names = "default";
-                             &gpx2 1 3 3 0>;
+                pinctrl-0 = <&keypad_rows &keypad_columns>;
-                col-gpios = <&gpx1 0 3 0 0
-                             &gpx1 1 3 0 0
-                             &gpx1 2 3 0 0
-                             &gpx1 3 3 0 0
-                             &gpx1 4 3 0 0
-                             &gpx1 5 3 0 0
-                             &gpx1 6 3 0 0
-                             &gpx1 7 3 0 0>;
                key_1 {
                        keypad,row = <0>;
diff --git a/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt b/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt
new file mode 100644
index 000000000000..513d94d6e899
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/ti,nspire-keypad.txt
@@ -0,0 +1,60 @@
+TI-NSPIRE Keypad
+Required properties:
+- compatible: Compatible property value should be "ti,nspire-keypad".
+- reg: Physical base address of the peripheral and length of memory mapped
+  region.
+- interrupts: The interrupt number for the peripheral.
+- scan-interval: How often to scan in us. Based on a APB speed of 33MHz, the
+        maximum and minimum delay time is ~2000us and ~500us respectively
+- row-delay: How long to wait before scanning each row.
+- clocks: The clock this peripheral is attached to.
+- linux,keymap: The keymap to use
+        (see Documentation/devicetree/bindings/input/matrix-keymap.txt)
+Optional properties:
+- active-low: Specify that the keypad is active low (i.e. logical low signifies
+        a key press).
+Example:
+input {
+        compatible = "ti,nspire-keypad";
+        reg = <0x900E0000 0x1000>;
+        interrupts = <16>;
+        scan-interval = <1000>;
+        row-delay = <200>;
+        clocks = <&apb_pclk>;
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00040039
+        0x0005002c      0x00060015      0x0007000b
+        0x0008000f      0x0100002d      0x01010011
+        0x0102002f      0x01030004      0x01040016
+        0x01050014      0x0106001f      0x01070002
+        0x010a006a      0x02000013      0x02010010
+        0x02020019      0x02030007      0x02040018
+        0x02050031      0x02060032      0x02070005
+        0x02080028      0x0209006c      0x03000026
+        0x03010025      0x03020024      0x0303000a
+        0x03040017      0x03050023      0x03060022
+        0x03070008      0x03080035      0x03090069
+        0x04000021      0x04010012      0x04020020
+        0x0404002e      0x04050030      0x0406001e
+        0x0407000d      0x04080037      0x04090067
+        0x05010038      0x0502000c      0x0503001b
+        0x05040034      0x0505001a      0x05060006
+        0x05080027      0x0509000e      0x050a006f
+        0x0600002b      0x0602004e      0x06030068
+        0x06040003      0x0605006d      0x06060009
+        0x06070001      0x0609000f      0x0708002a
+        0x0709001d      0x070a0033      >;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt
new file mode 100644
index 000000000000..9d52d5afe3e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/abilis,tb10x-ictl.txt
@@ -0,0 +1,38 @@
+TB10x Top Level Interrupt Controller
+====================================
+The Abilis TB10x SOC contains a custom interrupt controller. It performs
+one-to-one mapping of external interrupt sources to CPU interrupts and
+provides support for reconfigurable trigger modes.
+Required properties
+-------------------
+- compatible: Should be "abilis,tb10x-ictl"
+- reg: specifies physical base address and size of register range.
+- interrupt-congroller: Identifies the node as an interrupt controller.
+- #interrupt cells: Specifies the number of cells used to encode an interrupt
+  source connected to this controller. The value shall be 2.
+- interrupt-parent: Specifies the parent interrupt controller.
+- interrupts: Specifies the list of interrupt lines which are handled by
+  the interrupt controller in the parent controller's notation. Interrupts
+  are mapped one-to-one to parent interrupts.
+Example
+-------
+intc: interrupt-controller {    /* Parent interrupt controller */
+        interrupt-controller;
+        #interrupt-cells = <1>; /* For example below */
+        /* ... */
+};
+tb10x_ictl: pic@2000 {          /* TB10x interrupt controller */
+        compatible = "abilis,tb10x-ictl";
+        reg = <0x2000 0x20>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&intc>;
+        interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
+                        20 21 22 23 24 25 26 27 28 29 30 31>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index e7f4dc14eff2..57edb30dbbca 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -8,91 +8,8 @@ Required properties:
 - #interrupt-cells : Specifies the number of cells needed to encode an
  interrupt source. The value shall be 1.
-The interrupt sources are as follows:
+For the valid interrupt sources for your SoC, see the documentation in
+sunxi/<soc>.txt
-0: ENMI
-1: UART0
-2: UART1
-3: UART2
-4: UART3
-5: IR0
-6: IR1
-7: I2C0
-8: I2C1
-9: I2C2
-10: SPI0
-11: SPI1
-12: SPI2
-13: SPDIF
-14: AC97
-15: TS
-16: I2S
-17: UART4
-18: UART5
-19: UART6
-20: UART7
-21: KEYPAD
-22: TIMER0
-23: TIMER1
-24: TIMER2
-25: TIMER3
-26: CAN
-27: DMA
-28: PIO
-29: TOUCH_PANEL
-30: AUDIO_CODEC
-31: LRADC
-32: SDMC0
-33: SDMC1
-34: SDMC2
-35: SDMC3
-36: MEMSTICK
-37: NAND
-38: USB0
-39: USB1
-40: USB2
-41: SCR
-42: CSI0
-43: CSI1
-44: LCDCTRL0
-45: LCDCTRL1
-46: MP
-47: DEFEBE0
-48: DEFEBE1
-49: PMU
-50: SPI3
-51: TZASC
-52: PATA
-53: VE
-54: SS
-55: EMAC
-56: SATA
-57: GPS
-58: HDMI
-59: TVE
-60: ACE
-61: TVD
-62: PS2_0
-63: PS2_1
-64: USB3
-65: USB4
-66: PLE_PFM
-67: TIMER4
-68: TIMER5
-69: GPU_GP
-70: GPU_GPMMU
-71: GPU_PP0
-72: GPU_PPMMU0
-73: GPU_PMU
-74: GPU_RSV0
-75: GPU_RSV1
-76: GPU_RSV2
-77: GPU_RSV3
-78: GPU_RSV4
-79: GPU_RSV5
-80: GPU_RSV6
-82: SYNC_TIMER0
-83: SYNC_TIMER1
 Example:
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
new file mode 100644
index 000000000000..2c11ac76fac9
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,orion-intc.txt
@@ -0,0 +1,48 @@
+Marvell Orion SoC interrupt controllers
+* Main interrupt controller
+Required properties:
+- compatible: shall be "marvell,orion-intc"
+- reg: base address(es) of interrupt registers starting with CAUSE register
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
+The interrupt sources map to the corresponding bits in the interrupt
+registers, i.e.
+- 0 maps to bit 0 of first base address,
+- 1 maps to bit 1 of first base address,
+- 32 maps to bit 0 of second base address, and so on.
+Example:
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                 /* Dove has 64 first level interrupts */
+                reg = <0x20200 0x10>, <0x20210 0x10>;
+        };
+* Bridge interrupt controller
+Required properties:
+- compatible: shall be "marvell,orion-bridge-intc"
+- reg: base address of bridge interrupt registers starting with CAUSE register
+- interrupts: bridge interrupt of the main interrupt controller
+- interrupt-controller: identifies the node as an interrupt controller
+- #interrupt-cells: number of cells to encode an interrupt source, shall be 1
+Optional properties:
+- marvell,#interrupts: number of interrupts provided by bridge interrupt
+      controller, defaults to 32 if not set
+Example:
+        bridge_intc: interrupt-controller {
+                compatible = "marvell,orion-bridge-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x20110 0x8>;
+                interrupts = <0>;
+                /* Dove bridge provides 5 interrupts */
+                marvell,#interrupts = <5>;
+        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
new file mode 100644
index 000000000000..1f8b0c507c26
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
@@ -0,0 +1,16 @@
+DT bindings for the R-/SH-Mobile irqpin controller
+Required properties:
+- compatible: has to be "renesas,intc-irqpin"
+- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
+  interrupts.txt in this directory
+Optional properties:
+- any properties, listed in interrupts.txt, and any standard resource allocation
+  properties
+- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
+  if different from the default 4 bits
+- control-parent: disable and enable interrupts on the parent interrupt
+  controller, needed for some broken implementations
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
new file mode 100644
index 000000000000..76b98c834499
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
@@ -0,0 +1,89 @@
+Allwinner A10 (sun4i) interrupt sources
+---------------------------------------
+The interrupt sources available for the Allwinner A10 SoC are the
+following one:
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: MMC0
+33: MMC1
+34: MMC2
+35: MMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
new file mode 100644
index 000000000000..2ec3b5ce1a0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
@@ -0,0 +1,55 @@
+Allwinner A13 (sun5i) interrupt sources
+---------------------------------------
+The interrupt sources available for the Allwinner A13 SoC are the
+following one:
+0: ENMI
+2: UART1
+4: UART3
+5: IR
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: MMC0
+33: MMC1
+34: MMC2
+37: NAND
+38: USB OTG
+39: USB EHCI
+40: USB OHCI
+42: CSI
+44: LCDCTRL
+47: DEFEBE
+49: PMU
+53: VE
+54: SS
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.txt b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt
new file mode 100644
index 000000000000..d5176882d8b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.txt
@@ -0,0 +1,147 @@
+Binding for TI/National Semiconductor LP55xx Led Drivers
+Required properties:
+- compatible: "national,lp5521" or "national,lp5523" or "ti,lp5562"
+- reg: I2C slave address
+- clock-mode: Input clock mode, (0: automode, 1: internal, 2: external)
+Each child has own specific current settings
+- led-cur: Current setting at each led channel (mA x10, 0 if led is not connected)
+- max-cur: Maximun current at each led channel.
+Optional properties:
+- label: Used for naming LEDs
+Alternatively, each child can have specific channel name
+- chan-name: Name of each channel name
+example 1) LP5521
+3 LED channels, external clock used. Channel names are 'lp5521_pri:channel0',
+'lp5521_pri:channel1' and 'lp5521_pri:channel2'
+lp5521@32 {
+        compatible = "national,lp5521";
+        reg = <0x32>;
+        label = "lp5521_pri";
+        clock-mode = /bits/ 8 <2>;
+        chan0 {
+                led-cur = /bits/ 8 <0x2f>;
+                max-cur = /bits/ 8 <0x5f>;
+        };
+        chan1 {
+                led-cur = /bits/ 8 <0x2f>;
+                max-cur = /bits/ 8 <0x5f>;
+        };
+        chan2 {
+                led-cur = /bits/ 8 <0x2f>;
+                max-cur = /bits/ 8 <0x5f>;
+        };
+};
+example 2) LP5523
+9 LED channels with specific name. Internal clock used.
+The I2C slave address is configurable with ASEL1 and ASEL0 pins.
+Available addresses are 32/33/34/35h.
+ASEL1    ASEL0    Address
+-------------------------
+ GND      GND       32h
+ GND      VEN       33h
+ VEN      GND       34h
+ VEN      VEN       35h
+lp5523@32 {
+        compatible = "national,lp5523";
+        reg = <0x32>;
+        clock-mode = /bits/ 8 <1>;
+        chan0 {
+                chan-name = "d1";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan1 {
+                chan-name = "d2";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan2 {
+                chan-name = "d3";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan3 {
+                chan-name = "d4";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan4 {
+                chan-name = "d5";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan5 {
+                chan-name = "d6";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan6 {
+                chan-name = "d7";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan7 {
+                chan-name = "d8";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+        chan8 {
+                chan-name = "d9";
+                led-cur = /bits/ 8 <0x14>;
+                max-cur = /bits/ 8 <0x20>;
+        };
+};
+example 3) LP5562
+4 channels are defined.
+lp5562@30 {
+        compatible = "ti,lp5562";
+        reg = <0x30>;
+        clock-mode = /bits/8 <2>;
+        chan0 {
+                chan-name = "R";
+                led-cur = /bits/ 8 <0x20>;
+                max-cur = /bits/ 8 <0x60>;
+        };
+        chan1 {
+                chan-name = "G";
+                led-cur = /bits/ 8 <0x20>;
+                max-cur = /bits/ 8 <0x60>;
+        };
+        chan2 {
+                chan-name = "B";
+                led-cur = /bits/ 8 <0x20>;
+                max-cur = /bits/ 8 <0x60>;
+        };
+        chan3 {
+                chan-name = "W";
+                led-cur = /bits/ 8 <0x20>;
+                max-cur = /bits/ 8 <0x60>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
index bf0182d8da25..df37b0230c75 100644
--- a/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -15,6 +15,9 @@ Required properties:
          mapped region.
  - interrupts : MFC interrupt number to the CPU.
+  - clocks : from common clock binding: handle to mfc clocks.
+  - clock-names : from common clock binding: must contain "sclk_mfc" and "mfc",
+                  corresponding to entries in the clocks property.
  - samsung,mfc-r : Base address of the first memory bank used by MFC
                    for DMA contiguous memory allocation and its size.
@@ -34,6 +37,8 @@ mfc: codec@13400000 {
        reg = <0x13400000 0x10000>;
        interrupts = <0 94 0>;
        samsung,power-domain = <&pd_mfc>;
+        clocks = <&clock 170>, <&clock 273>;
+        clock-names = "sclk_mfc", "mfc";
 };
 Board specific DT entry:
diff --git a/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
new file mode 100644
index 000000000000..653c90c34a71
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mvebu-devbus.txt
@@ -0,0 +1,156 @@
+Device tree bindings for MVEBU Device Bus controllers
+The Device Bus controller available in some Marvell's SoC allows to control
+different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
+The actual devices are instantiated from the child nodes of a Device Bus node.
+Required properties:
+ - compatible:          Currently only Armada 370/XP SoC are supported,
+                        with this compatible string:
+                        marvell,mvebu-devbus
+ - reg:                 A resource specifier for the register space.
+                        This is the base address of a chip select within
+                        the controller's register space.
+                        (see the example below)
+ - #address-cells:      Must be set to 1
+ - #size-cells:         Must be set to 1
+ - ranges:              Must be set up to reflect the memory layout with four
+                        integer values for each chip-select line in use:
+                        0 <physical address of mapping> <size>
+Mandatory timing properties for child nodes:
+Read parameters:
+ - devbus,turn-off-ps:  Defines the time during which the controller does not
+                        drive the AD bus after the completion of a device read.
+                        This prevents contentions on the Device Bus after a read
+                        cycle from a slow device.
+ - devbus,bus-width:    Defines the bus width (e.g. <16>)
+ - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
+                        to read data sample. This parameter is useful for
+                        synchronous pipelined devices, where the address
+                        precedes the read data by one or two cycles.
+ - devbus,acc-first-ps: Defines the time delay from the negation of
+                        ALE[0] to the cycle that the first read data is sampled
+                        by the controller.
+ - devbus,acc-next-ps:  Defines the time delay between the cycle that
+                        samples data N and the cycle that samples data N+1
+                        (in burst accesses).
+ - devbus,rd-setup-ps:  Defines the time delay between DEV_CSn assertion to
+                        DEV_OEn assertion. If set to 0 (default),
+                        DEV_OEn and DEV_CSn are asserted at the same cycle.
+                        This parameter has no affect on <acc-first-ps> parameter
+                        (no affect on first data sample). Set <rd-setup-ps>
+                        to a value smaller than <acc-first-ps>.
+ - devbus,rd-hold-ps:   Defines the time between the last data sample to the
+                        de-assertion of DEV_CSn. If set to 0 (default),
+                        DEV_OEn and DEV_CSn are de-asserted at the same cycle
+                        (the cycle of the last data sample).
+                        This parameter has no affect on DEV_OEn de-assertion.
+                        DEV_OEn is always de-asserted the next cycle after
+                        last data sampled. Also this parameter has no
+                        affect on <turn-off-ps> parameter.
+                        Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
+Write parameters:
+ - devbus,ale-wr-ps:    Defines the time delay from the ALE[0] negation cycle
+                        to the DEV_WEn assertion.
+ - devbus,wr-low-ps:    Defines the time during which DEV_WEn is active.
+                        A[2:0] and Data are kept valid as long as DEV_WEn
+                        is active. This parameter defines the setup time of
+                        address and data to DEV_WEn rise.
+ - devbus,wr-high-ps:   Defines the time during which DEV_WEn is kept
+                        inactive (high) between data beats of a burst write.
+                        DEV_A[2:0] and Data are kept valid (do not toggle) for
+                        <wr-high-ps> - <tick> ps.
+                        This parameter defines the hold time of address and
+                        data after DEV_WEn rise.
+ - devbus,sync-enable: Synchronous device enable.
+                       1: True
+                       0: False
+An example for an Armada XP GP board, with a 16 MiB NOR device as child
+is showed below. Note that the Device Bus driver is in charge of allocating
+the mbus address decoding window for each of its child devices.
+The window is created using the chip select specified in the child
+device node together with the base address and size specified in the ranges
+property. For instance, in the example below the allocated decoding window
+will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
+for chip select 0 (a.k.a DEV_BOOTCS).
+This address window handling is done in this mvebu-devbus only as a temporary
+solution. It will be removed when the support for mbus device tree binding is
+added.
+The reg property implicitly specifies the chip select as this:
+  0x10400: DEV_BOOTCS
+  0x10408: DEV_CS0
+  0x10410: DEV_CS1
+  0x10418: DEV_CS2
+  0x10420: DEV_CS3
+Example:
+        devbus-bootcs@d0010400 {
+                status = "okay";
+                ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* Device Bus parameters are required */
+                /* Read parameters */
+                devbus,bus-width    = <8>;
+                devbus,turn-off-ps  = <60000>;
+                devbus,badr-skew-ps = <0>;
+                devbus,acc-first-ps = <124000>;
+                devbus,acc-next-ps  = <248000>;
+                devbus,rd-setup-ps  = <0>;
+                devbus,rd-hold-ps   = <0>;
+                /* Write parameters */
+                devbus,sync-enable = <0>;
+                devbus,wr-high-ps  = <60000>;
+                devbus,wr-low-ps   = <60000>;
+                devbus,ale-wr-ps   = <60000>;
+                flash@0 {
+                        compatible = "cfi-flash";
+                        /* 16 MiB */
+                        reg = <0 0x1000000>;
+                        bank-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /*
+                         * We split the 16 MiB in two partitions,
+                         * just as an example.
+                         */
+                        partition@0 {
+                                label = "First";
+                                reg = <0 0x800000>;
+                        };
+                        partition@800000 {
+                                label = "Second";
+                                reg = <0x800000 0x800000>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/metag/meta.txt b/Documentation/devicetree/bindings/metag/meta.txt
new file mode 100644
index 000000000000..f4457f57ab08
--- /dev/null
+++ b/Documentation/devicetree/bindings/metag/meta.txt
@@ -0,0 +1,30 @@
+* Meta Processor Binding
+This binding specifies what properties must be available in the device tree
+representation of a Meta Processor Core, which is the root node in the tree.
+Required properties:
+    - compatible: Specifies the compatibility list for the Meta processor.
+      The type shall be <string> and the value shall include "img,meta".
+Optional properties:
+    - clocks: Clock consumer specifiers as described in
+      Documentation/devicetree/bindings/clock/clock-bindings.txt
+    - clock-names: Clock consumer names as described in
+      Documentation/devicetree/bindings/clock/clock-bindings.txt.
+Clocks are identified by name. Valid clocks are:
+    - "core": The Meta core clock from which the Meta timers are derived.
+* Examples
+/ {
+        compatible = "toumaz,tz1090", "img,meta";
+        clocks = <&meta_core_clk>;
+        clock-names = "core";
+};
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
index c3a14e0ad0ad..cd9e90c5d171 100644
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -120,7 +120,7 @@ ab8500 {
                                  "USB_LINK_STATUS",
                                  "USB_ADP_PROBE_PLUG",
                                  "USB_ADP_PROBE_UNPLUG";
-                vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
                v-ape-supply = <&db8500_vape_reg>;
                musb_1v8-supply = <&db8500_vsmps2_reg>;
        };
diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt
new file mode 100644
index 000000000000..0e295c9d8937
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/arizona.txt
@@ -0,0 +1,62 @@
+Wolfson Arizona class audio SoCs
+These devices are audio SoCs with extensive digital capabilites and a range
+of analogue I/O.
+Required properties:
+  - compatible : one of the following chip-specific strings:
+        "wlf,wm5102"
+        "wlf,wm5110"
+  - reg : I2C slave address when connected using I2C, chip select number when
+    using SPI.
+  - interrupts : The interrupt line the /IRQ signal for the device is
+    connected to.
+  - interrupt-controller : Arizona class devices contain interrupt controllers
+    and may provide interrupt services to other devices.
+  - interrupt-parent : The parent interrupt controller.
+  - #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
+    The first cell is the IRQ number.
+    The second cell is the flags, encoded as the trigger masks from
+    Documentation/devicetree/bindings/interrupts.txt
+  - gpio-controller : Indicates this device is a GPIO controller.
+  - #gpio-cells : Must be 2. The first cell is the pin number and the
+    second cell is used to specify optional parameters (currently unused).
+  - AVDD1-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, CPVDD-supply,
+    SPKVDDL-supply, SPKVDDR-supply : power supplies for the device, as covered
+    in Documentation/devicetree/bindings/regulator/regulator.txt
+Optional properties:
+  - wlf,reset : GPIO specifier for the GPIO controlling /RESET
+  - wlf,ldoena : GPIO specifier for the GPIO controlling LDOENA
+  - wlf,gpio-defaults : A list of GPIO configuration register values. If
+    absent, no configuration of these registers is performed. If any
+    entry has a value that is out of range for a 16 bit register then
+    the chip default will be used.  If present exactly five values must
+    be specified.
+Example:
+codec: wm5102@1a {
+        compatible = "wlf,wm5102";
+        reg = <0x1a>;
+        interrupts = <347>;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&gic>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        wlf,gpio-defaults = <
+                0x00000000, /* AIF1TXLRCLK */
+                0xffffffff,
+                0xffffffff,
+                0xffffffff,
+                0xffffffff,
+        >;
+};
diff --git a/Documentation/devicetree/bindings/mfd/max77693.txt b/Documentation/devicetree/bindings/mfd/max77693.txt
new file mode 100644
index 000000000000..11921cc417bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/max77693.txt
@@ -0,0 +1,55 @@
+Maxim MAX77693 multi-function device
+MAX77693 is a Multifunction device with the following submodules:
+- PMIC,
+- CHARGER,
+- LED,
+- MUIC,
+- HAPTIC
+It is interfaced to host controller using i2c.
+This document describes the bindings for the mfd device.
+Required properties:
+- compatible : Must be "maxim,max77693".
+- reg : Specifies the i2c slave address of PMIC block.
+- interrupts : This i2c device has an IRQ line connected to the main SoC.
+- interrupt-parent :  The parent interrupt controller.
+Optional properties:
+- regulators : The regulators of max77693 have to be instantiated under subnod
+  named "regulators" using the following format.
+        regulators {
+                regualtor-compatible = ESAFEOUT1/ESAFEOUT2/CHARGER
+                standard regulator constratints[*].
+        };
+        [*] refer Documentation/devicetree/bindings/regulator/regulator.txt
+Example:
+        max77693@66 {
+                compatible = "maxim,max77693";
+                reg = <0x66>;
+                interrupt-parent = <&gpx1>;
+                interrupts = <5 2>;
+                regulators {
+                        esafeout@1 {
+                                regulator-compatible = "ESAFEOUT1";
+                                regulator-name = "ESAFEOUT1";
+                                regulator-boot-on;
+                        };
+                        esafeout@2 {
+                                regulator-compatible = "ESAFEOUT2";
+                                regulator-name = "ESAFEOUT2";
+                                };
+                        charger@0 {
+                                regulator-compatible = "CHARGER";
+                                regulator-name = "CHARGER";
+                                regulator-min-microamp = <60000>;
+                                regulator-max-microamp = <2580000>;
+                                        regulator-boot-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
new file mode 100644
index 000000000000..892537d1a48f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/palmas.txt
@@ -0,0 +1,49 @@
+* palmas device tree bindings
+The TI palmas family current members :-
+twl6035 (palmas)
+twl6037 (palmas)
+tps65913 (palmas)
+tps65914 (palmas)
+Required properties:
+- compatible : Should be from the list
+  ti,twl6035
+  ti,twl6036
+  ti,twl6037
+  ti,tps65913
+  ti,tps65914
+  ti,tps80036
+and also the generic series names
+  ti,palmas
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+  The first cell is the IRQ number.
+  The second cell is the flags, encoded as the trigger masks from
+  Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+Optional properties:
+  ti,mux-padX : set the pad register X (1-2) to the correct muxing for the
+                hardware, if not set will use muxing in OTP.
+Example:
+palmas {
+        compatible = "ti,twl6035", "ti,palmas";
+        reg = <0x48>
+        interrupt-parent = <&intc>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        ti,mux-pad1 = <0>;
+        ti,mux-pad2 = <0>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pmic {
+                compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+                ....
+        };
+}
diff --git a/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
new file mode 100644
index 000000000000..094ae010f2fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/bcm,kona-sdhci.txt
@@ -0,0 +1,16 @@
+Broadcom BCM281xx SDHCI
+This file documents differences between the core properties in mmc.txt
+and the properties present in the bcm281xx SDHCI
+Required properties:
+- compatible : Should be "bcm,kona-sdhci"
+Example:
+sdio2: sdio@0x3f1a0000 {
+        compatible = "bcm,kona-sdhci";
+        reg = <0x3f1a0000 0x10000>;
+        interrupts = <0x0 74 0x4>;
+};
diff --git a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
index 726fd2122a13..1180d7814af8 100644
--- a/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
@@ -51,7 +51,7 @@ Optional properties:
 * card-detect-delay: Delay in milli-seconds before detecting card after card
  insert event. The default value is 0.
-* supports-highspeed: Enables support for high speed cards (upto 50MHz)
+* supports-highspeed: Enables support for high speed cards (up to 50MHz)
 * broken-cd: as documented in mmc core bindings.
diff --git a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
index 6a983c1d87cd..df338cb5059c 100644
--- a/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
@@ -29,6 +29,13 @@ Optional properties:
                "bch4"          4-bit BCH ecc code
                "bch8"          8-bit BCH ecc code
+ - ti,nand-xfer-type:           A string setting the data transfer type. One of:
+                "prefetch-polled"       Prefetch polled mode (default)
+                "polled"                Polled mode, without prefetch
+                "prefetch-dma"          Prefetch enabled sDMA mode
+                "prefetch-irq"          Prefetch enabled irq mode
 - elm_id:      Specifies elm device node. This is required to support BCH
                error correction using ELM module.
@@ -55,6 +62,7 @@ Example for an AM33xx board:
                        reg = <0 0 0>; /* CS0, offset 0 */
                        nand-bus-width = <16>;
                        ti,nand-ecc-opt = "bch8";
+                        ti,nand-xfer-type = "polled";
                        gpmc,sync-clk-ps = <0>;
                        gpmc,cs-on-ns = <0>;
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
new file mode 100644
index 000000000000..e2371f5cdebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -0,0 +1,73 @@
+* Synopsis Designware PCIe interface
+Required properties:
+- compatible: should contain "snps,dw-pcie" to identify the
+        core, plus an identifier for the specific instance, such
+        as "samsung,exynos5440-pcie".
+- reg: base addresses and lengths of the pcie controller,
+        the phy controller, additional register for the phy controller.
+- interrupts: interrupt values for level interrupt,
+        pulse interrupt, special interrupt.
+- clocks: from common clock binding: handle to pci clock.
+- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map: standard PCI properties
+        to define the mapping of the PCIe interface to interrupt
+        numbers.
+- reset-gpio: gpio pin number of power good signal
+Example:
+SoC specific DT Entry:
+        pcie@290000 {
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                reg = <0x290000 0x1000
+                        0x270000 0x1000
+                        0x271000 0x40>;
+                interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+                clocks = <&clock 28>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
+                          0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0x0 0 &gic 53>;
+        };
+        pcie@2a0000 {
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                reg = <0x2a0000 0x1000
+                        0x272000 0x1000
+                        0x271040 0x40>;
+                interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+                clocks = <&clock 29>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
+                          0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0x0 0 &gic 56>;
+        };
+Board specific DT Entry:
+        pcie@290000 {
+                reset-gpio = <&pin_ctrl 5 0>;
+        };
+        pcie@2a0000 {
+                reset-gpio = <&pin_ctrl 22 0>;
+        };
diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
new file mode 100644
index 000000000000..f8d405897a94
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
@@ -0,0 +1,221 @@
+* Marvell EBU PCIe interfaces
+Mandatory properties:
+- compatible: one of the following values:
+    marvell,armada-370-pcie
+    marvell,armada-xp-pcie
+    marvell,kirkwood-pcie
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- bus-range: PCI bus numbers covered
+- device_type, set to "pci"
+- ranges: ranges for the PCI memory and I/O regions, as well as the
+  MMIO registers to control the PCIe interfaces.
+In addition, the Device Tree node must have sub-nodes describing each
+PCIe interface, having the following mandatory properties:
+- reg: used only for interrupt mapping, so only the first four bytes
+  are used to refer to the correct bus number and device number.
+- assigned-addresses: reference to the MMIO registers used to control
+  this PCIe interface.
+- clocks: the clock associated to this PCIe interface
+- marvell,pcie-port: the physical PCIe port number
+- status: either "disabled" or "okay"
+- device_type, set to "pci"
+- #address-cells, set to <3>
+- #size-cells, set to <2>
+- #interrupt-cells, set to <1>
+- ranges, empty property.
+- interrupt-map-mask and interrupt-map, standard PCI properties to
+  define the mapping of the PCIe interface to interrupt numbers.
+and the following optional properties:
+- marvell,pcie-lane: the physical PCIe lane number, for ports having
+  multiple lanes. If this property is not found, we assume that the
+  value is 0.
+Example:
+pcie-controller {
+        compatible = "marvell,armada-xp-pcie";
+        status = "disabled";
+        device_type = "pci";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        bus-range = <0x00 0xff>;
+        ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
+                  0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
+                  0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
+                  0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
+                  0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
+                  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
+                  0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
+                  0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
+                  0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
+                  0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
+                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+        pcie@1,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
+                reg = <0x0800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 58>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 5>;
+                status = "disabled";
+        };
+        pcie@2,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
+                reg = <0x1000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 59>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <1>;
+                clocks = <&gateclk 6>;
+                status = "disabled";
+        };
+        pcie@3,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
+                reg = <0x1800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 60>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <2>;
+                clocks = <&gateclk 7>;
+                status = "disabled";
+        };
+        pcie@4,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
+                reg = <0x2000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 61>;
+                marvell,pcie-port = <0>;
+                marvell,pcie-lane = <3>;
+                clocks = <&gateclk 8>;
+                status = "disabled";
+        };
+        pcie@5,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
+                reg = <0x2800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 62>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 9>;
+                status = "disabled";
+        };
+        pcie@6,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
+                reg = <0x3000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 63>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <1>;
+                clocks = <&gateclk 10>;
+                status = "disabled";
+        };
+        pcie@7,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
+                reg = <0x3800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 64>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <2>;
+                clocks = <&gateclk 11>;
+                status = "disabled";
+        };
+        pcie@8,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
+                reg = <0x4000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 65>;
+                marvell,pcie-port = <1>;
+                marvell,pcie-lane = <3>;
+                clocks = <&gateclk 12>;
+                status = "disabled";
+        };
+        pcie@9,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
+                reg = <0x4800 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 99>;
+                marvell,pcie-port = <2>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 26>;
+                status = "disabled";
+        };
+        pcie@10,0 {
+                device_type = "pci";
+                assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
+                reg = <0x5000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                #interrupt-cells = <1>;
+                ranges;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &mpic 103>;
+                marvell,pcie-port = <3>;
+                marvell,pcie-lane = <0>;
+                clocks = <&gateclk 27>;
+                status = "disabled";
+        };
+};
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
new file mode 100644
index 000000000000..41aeed38926d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -0,0 +1,9 @@
+PCI bus bridges have standardized Device Tree bindings:
+PCI Bus Binding to: IEEE Std 1275-1994
+http://www.openfirmware.org/ofwg/bindings/pci/pci2_1.pdf
+And for the interrupt mapping part:
+Open Firmware Recommended Practice: Interrupt Mapping
+http://www.openfirmware.org/1275/practice/imap/imap0_9d.pdf
diff --git a/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
new file mode 100644
index 000000000000..30b364e504ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/v3-v360epc-pci.txt
@@ -0,0 +1,15 @@
+V3 Semiconductor V360 EPC PCI bridge
+This bridge is found in the ARM Integrator/AP (Application Platform)
+Integrator-specific notes:
+- syscon: should contain a link to the syscon device node (since
+  on the Integrator, some registers in the syscon are required to
+  operate the V3).
+V360 EPC specific notes:
+- reg: should contain the base address of the V3 adapter.
+- interrupts: should contain a reference to the V3 error interrupt
+  as routed on the system.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
index bcfdab5d442e..3a7caf7a744a 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
@@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding:
 Examples:
 usdhc@0219c000 { /* uSDHC4 */
-        fsl,card-wired;
+        non-removable;
        vmmc-supply = <&reg_3p3v>;
        status = "okay";
        pinctrl-names = "default";
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
new file mode 100644
index 000000000000..ddcdeb697c29
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
@@ -0,0 +1,41 @@
+Freescale Vybrid VF610 IOMUX Controller
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+Required properties:
+- compatible: "fsl,vf610-iomuxc"
+- fsl,pins: two integers array, represents a group of pins mux and config
+  setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
+  a pin working on a specific function, CONFIG is the pad setting value
+  such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
+  datasheet for the valid pad config settings.
+CONFIG bits definition:
+PAD_CTL_SPEED_LOW               (1 << 12)
+PAD_CTL_SPEED_MED               (2 << 12)
+PAD_CTL_SPEED_HIGH              (3 << 12)
+PAD_CTL_SRE_FAST                (1 << 11)
+PAD_CTL_SRE_SLOW                (0 << 11)
+PAD_CTL_ODE                     (1 << 10)
+PAD_CTL_HYS                     (1 << 9)
+PAD_CTL_DSE_DISABLE             (0 << 6)
+PAD_CTL_DSE_150ohm              (1 << 6)
+PAD_CTL_DSE_75ohm               (2 << 6)
+PAD_CTL_DSE_50ohm               (3 << 6)
+PAD_CTL_DSE_37ohm               (4 << 6)
+PAD_CTL_DSE_30ohm               (5 << 6)
+PAD_CTL_DSE_25ohm               (6 << 6)
+PAD_CTL_DSE_20ohm               (7 << 6)
+PAD_CTL_PUS_100K_DOWN           (0 << 4)
+PAD_CTL_PUS_47K_UP              (1 << 4)
+PAD_CTL_PUS_100K_UP             (2 << 4)
+PAD_CTL_PUS_22K_UP              (3 << 4)
+PAD_CTL_PKE                     (1 << 3)
+PAD_CTL_PUE                     (1 << 2)
+PAD_CTL_OBE_ENABLE              (1 << 1)
+PAD_CTL_IBE_ENABLE              (1 << 0)
+PAD_CTL_OBE_IBE_ENABLE          (3 << 0)
+Please refer to vf610-pinfunc.h in device tree source folder
+for all available PIN_FUNC_ID for Vybrid VF610.
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
new file mode 100644
index 000000000000..a186181c402b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
@@ -0,0 +1,127 @@
+ImgTec TZ1090 PDC pin controller
+Required properties:
+- compatible: "img,tz1090-pdc-pinctrl"
+- reg: Should contain the register physical address and length of the
+  SOC_GPIO_CONTROL registers in the PDC register region.
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+TZ1090-PDC's pin configuration nodes act as a container for an abitrary number
+of subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function. For this reason, even seemingly boolean
+values are actually tristates in this binding: unspecified, off, or on.
+Unspecified is represented as an absent property, and off/on are represented as
+integer values 0 and 1.
+Required subnode-properties:
+- tz1090,pins : An array of strings. Each string contains the name of a pin or
+  group. Valid values for these names are listed below.
+Optional subnode-properties:
+- tz1090,function: A string containing the name of the function to mux to the
+  pin or group. Valid values for function names are listed below, including
+  which pingroups can be muxed to them.
+- supported generic pinconfig properties (for further details see
+  Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
+  - bias-disable
+  - bias-high-impedance
+  - bias-bus-hold
+  - bias-pull-up
+  - bias-pull-down
+  - input-schmitt-enable
+  - input-schmitt-disable
+  - drive-strength: Integer, control drive strength of pins in mA.
+      2: 2mA
+      4: 4mA
+      8: 8mA
+      12: 12mA
+  - low-power-enable: Flag, power-on-start weak pull-down for invalid power.
+  - low-power-disable: Flag, power-on-start weak pull-down disabled.
+Note that many of these properties are only valid for certain specific pins
+or groups. See the TZ1090 TRM for complete details regarding which groups
+support which functionality. The Linux pinctrl driver may also be a useful
+reference.
+Valid values for pin and group names are:
+  pins:
+    These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
+    bias-bus-hold (which can also be provided to any of the groups below to set
+    it for all gpio pins in that group).
+    gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
+  mux groups:
+    These all support function.
+    gpio0
+        pins:       gpio0.
+        function:   ir_mod_stable_out.
+    gpio1
+        pins:       gpio1.
+        function:   ir_mod_power_out.
+  drive groups:
+    These support input-schmitt-enable, input-schmitt-disable,
+    drive-strength, low-power-enable, and low-power-disable.
+    pdc
+        pins:   gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
+                ext_power.
+Example:
+        pinctrl_pdc: pinctrl@02006500 {
+                #gpio-range-cells = <3>;
+                compatible = "img,tz1090-pdc-pinctrl";
+                reg = <0x02006500 0x100>;
+        };
+Example board file extracts:
+        &pinctrl_pdc {
+                pinctrl-names = "default";
+                pinctrl-0 = <&syswake_default>;
+                syswake_default: syswakes {
+                        syswake_cfg {
+                                tz1090,pins =   "sys_wake0",
+                                                "sys_wake1",
+                                                "sys_wake2";
+                                pull-up;
+                        };
+                };
+                irmod_default: irmod {
+                        gpio0_cfg {
+                                tz1090,pins =   "gpio0";
+                                tz1090,function = "ir_mod_stable_out";
+                        };
+                        gpio1_cfg {
+                                tz1090,pins =   "gpio1";
+                                tz1090,function = "ir_mod_power_out";
+                        };
+                };
+        };
+        ir: ir@02006200 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&irmod_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
new file mode 100644
index 000000000000..4b27c99f7f9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
@@ -0,0 +1,227 @@
+ImgTec TZ1090 pin controller
+Required properties:
+- compatible: "img,tz1090-pinctrl"
+- reg: Should contain the register physical address and length of the pad
+  configuration registers (CR_PADS_* and CR_IF_CTL0).
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+TZ1090's pin configuration nodes act as a container for an abitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function. For this reason, even seemingly boolean
+values are actually tristates in this binding: unspecified, off, or on.
+Unspecified is represented as an absent property, and off/on are represented as
+integer values 0 and 1.
+Required subnode-properties:
+- tz1090,pins : An array of strings. Each string contains the name of a pin or
+  group. Valid values for these names are listed below.
+Optional subnode-properties:
+- tz1090,function: A string containing the name of the function to mux to the
+  pin or group. Valid values for function names are listed below, including
+  which pingroups can be muxed to them.
+- supported generic pinconfig properties (for further details see
+  Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
+  - bias-disable
+  - bias-high-impedance
+  - bias-bus-hold
+  - bias-pull-up
+  - bias-pull-down
+  - input-schmitt-enable
+  - input-schmitt-disable
+  - drive-strength: Integer, control drive strength of pins in mA.
+      2: 2mA
+      4: 4mA
+      8: 8mA
+      12: 12mA
+Note that many of these properties are only valid for certain specific pins
+or groups. See the TZ1090 TRM for complete details regarding which groups
+support which functionality. The Linux pinctrl driver may also be a useful
+reference.
+Valid values for pin and group names are:
+  gpio pins:
+    These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
+    bias-bus-hold (which can also be provided to any of the groups below to set
+    it for all pins in that group).
+    They also all support the some form of muxing. Any pins which are contained
+    in one of the mux groups (see below) can be muxed only to the functions
+    supported by the mux group. All other pins can be muxed to the "perip"
+    function which which enables them with their intended peripheral.
+    Different pins in the same mux group cannot be muxed to different functions,
+    however it is possible to mux only a subset of the pins in a mux group to a
+    particular function and leave the remaining pins unmuxed. This is useful if
+    the board connects certain pins in a group to other devices to be controlled
+    by GPIO, and you don't want the usual peripheral to have any control of the
+    pin.
+    ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
+    i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
+    i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
+    scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
+    sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
+    spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
+    spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
+    tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
+    tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
+    tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
+    tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
+    tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
+    uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
+        bias-high-impediance:  supported.
+        bias-pull-up:          supported.
+        bias-pull-down:        supported.
+        bias-bus-hold:         supported.
+        function:              perip or those supported by pin's mux group.
+  other pins:
+    These other pins are part of various pin groups below, but can't be
+    controlled as GPIOs. They do however support bias-high-impediance,
+    bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
+    to any of the groups below to set it for all pins in that group).
+    clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
+        bias-high-impediance:  supported.
+        bias-pull-up:          supported.
+        bias-pull-down:        supported.
+        bias-bus-hold:         supported.
+  mux groups:
+    These all support function, and some support drive configs.
+    afe
+        pins:                  tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
+                               ant_sel1, gain0, gain1, gain2, gain3, gain4,
+                               gain5, gain6, gain7.
+        function:              afe, ts_out_0.
+        input-schmitt-enable:  supported.
+        input-schmitt-disable: supported.
+        drive-strength:        supported.
+    pdm_d
+        pins:                  pdm_d.
+        function:              pdm_dac, usb_vbus.
+    sdh
+        pins:                  sdh_cd, sdh_wp, sdh_clk_in.
+        function:              sdh, sdio.
+    sdio
+        pins:                  sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
+                               sdio_d3.
+        function:              sdio, sdh.
+    spi1_cs2
+        pins:                  spi1_cs2.
+        function:              spi1_cs2, usb_vbus.
+    tft
+        pins:                  tft_red0, tft_red1, tft_red2, tft_red3,
+                               tft_red4, tft_red5, tft_red6, tft_red7,
+                               tft_green0, tft_green1, tft_green2, tft_green3,
+                               tft_green4, tft_green5, tft_green6, tft_green7,
+                               tft_blue0, tft_blue1, tft_blue2, tft_blue3,
+                               tft_blue4, tft_blue5, tft_blue6, tft_blue7,
+                               tft_vdden_gd, tft_panelclk, tft_blank_ls,
+                               tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
+                               tft_pwrsave.
+        function:              tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
+                               lcd_trace, phy_ringosc.
+        input-schmitt-enable:  supported.
+        input-schmitt-disable: supported.
+        drive-strength:        supported.
+  drive groups:
+    These all support input-schmitt-enable, input-schmitt-disable,
+    and drive-strength.
+    jtag
+        pins:   tck, trst, tdi, tdo, tms.
+    scb1
+        pins:   scb1_sdat, scb1_sclk.
+    scb2
+        pins:   scb2_sdat, scb2_sclk.
+    spi0
+        pins:   spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
+    spi1
+        pins:   spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
+    uart
+        pins:   uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
+                uart1_txd, uart1_rxd.
+    drive_i2s
+        pins:   clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
+                i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
+    drive_pdm
+        pins:   clk_out0, pdm_b, pdm_a.
+    drive_scb0
+        pins:   scb0_sclk, scb0_sdat, pdm_d, pdm_c.
+    drive_sdio
+        pins:   sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
+                sdh_wp, sdh_cd, sdh_clk_in.
+  convenience groups:
+    These are just convenient groupings of pins and don't support any drive
+    configs.
+    uart0
+        pins:   uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
+    uart1
+        pins:   uart1_rxd, uart1_txd.
+    scb0
+        pins:   scb0_sclk, scb0_sdat.
+    i2s
+        pins:   i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
+                i2s_lrclk_out, i2s_mclk.
+Example:
+        pinctrl: pinctrl@02005800 {
+                #gpio-range-cells = <3>;
+                compatible = "img,tz1090-pinctrl";
+                reg = <0x02005800 0xe4>;
+        };
+Example board file extract:
+        &pinctrl {
+                uart0_default: uart0 {
+                        uart0_cfg {
+                                tz1090,pins =   "uart0_rxd",
+                                                "uart0_txd";
+                                tz1090,function = "perip";
+                        };
+                };
+                tft_default: tft {
+                        tft_cfg {
+                                tz1090,pins =   "tft";
+                                tz1090,function = "tft";
+                        };
+                };
+        };
+        uart@02004b00 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_default>;
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index a648aaad6110..50ec3512a292 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -10,29 +10,31 @@ Required properties:
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
 only for more detailed description in this document.
+Note: pmu* also allows for Power Management functions listed below
 name          pins     functions
 ================================================================================
-mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
-mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
 mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
-                       uart1(rts)
+                       uart1(rts), pmu*
 mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
-                       uart1(cts), lcd-spi(cs1)
+                       uart1(cts), lcd-spi(cs1), pmu*
-mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
-mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
-mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
-mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
-mpp8          8        gpio, pmu, watchdog(rstout)
+mpp8          8        gpio, pmu, watchdog(rstout), pmu*
-mpp9          9        gpio, pmu, pex1(clkreq)
+mpp9          9        gpio, pmu, pex1(clkreq), pmu*
-mpp10         10       gpio, pmu, ssp(sclk)
+mpp10         10       gpio, pmu, ssp(sclk), pmu*
 mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
-                       sdio1(ledctrl), pex0(clkreq)
+                       sdio1(ledctrl), pex0(clkreq), pmu*
-mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
+                       sata(act), pmu*
 mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
-                       ssp(extclk)
+                       ssp(extclk), pmu*
-mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
-mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
 mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
 mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
                       ac97-1(sysclko)
@@ -57,6 +59,21 @@ mpp_nand      64-71    gpo, nand
 audio0        -        i2s, ac97
 twsi          -        none, opt1, opt2, opt3
+Power Management functions (pmu*):
+pmu-nc               Pin not driven by any PM function
+pmu-low              Pin driven low (0)
+pmu-high             Pin driven high (1)
+pmic(sdi)            Pin is used for PMIC SDI
+cpu-pwr-down         Pin is used for CPU_PWRDWN
+standby-pwr-down     Pin is used for STBY_PWRDWN
+core-pwr-good        Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
+cpu-pwr-good         Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
+bat-fault            Pin is used for BATTERY_FAULT
+ext0-wakeup          Pin is used for EXT0_WU
+ext1-wakeup          Pin is used for EXT0_WU
+ext2-wakeup          Pin is used for EXT0_WU
+pmu-blink            Pin is used for blink function
 Notes:
 * group "mpp_audio1" allows the following functions and gpio pins:
  - gpio          : gpio on pins 52-57
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index c95ea8278f87..aeb3c995cc04 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -126,3 +126,51 @@ device; they may be grandchildren, for example. Whether this is legal, and
 whether there is any interaction between the child and intermediate parent
 nodes, is again defined entirely by the binding for the individual pin
 controller device.
+== Using generic pinconfig options ==
+Generic pinconfig parameters can be used by defining a separate node containing
+the applicable parameters (and optional values), like:
+pcfg_pull_up: pcfg_pull_up {
+        bias-pull-up;
+        drive-strength = <20>;
+};
+This node should then be referenced in the appropriate pinctrl node as a phandle
+and parsed in the driver using the pinconf_generic_parse_dt_config function.
+Supported configuration parameters are:
+bias-disable            - disable any pin bias
+bias-high-impedance     - high impedance mode ("third-state", "floating")
+bias-bus-hold           - latch weakly
+bias-pull-up            - pull up the pin
+bias-pull-down          - pull down the pin
+bias-pull-pin-default   - use pin-default pull state
+drive-push-pull         - drive actively high and low
+drive-open-drain        - drive with open drain
+drive-open-source       - drive with open source
+drive-strength          - sink or source at most X mA
+input-schmitt-enable    - enable schmitt-trigger mode
+input-schmitt-disable   - disable schmitt-trigger mode
+input-debounce          - debounce mode with debound time X
+low-power-enable        - enable low power mode
+low-power-disable       - disable low power mode
+output-low              - set the pin to output mode with low level
+output-high             - set the pin to output mode with high level
+Arguments for parameters:
+- bias-pull-up, -down and -pin-default take as optional argument on hardware
+  supporting it the pull strength in Ohm. bias-disable will disable the pull.
+- drive-strength takes as argument the target strength in mA.
+- input-debounce takes the debounce time in usec as argument
+  or 0 to disable debouncing
+All parameters not listed here, do not take an argument.
+More in-depth documentation on these parameters can be found in
+<include/linux/pinctrl/pinconfig-generic.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 08f0c3d01575..5a02e30dd262 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -18,7 +18,8 @@ Optional properties:
  pin functions is ignored
 - pinctrl-single,bit-per-mux : boolean to indicate that one register controls
-  more than one pin
+  more than one pin, for which "pinctrl-single,function-mask" property specifies
+ position mask of pin.
 - pinctrl-single,drive-strength : array of value that are used to configure
  drive strength in the pinmux register. They're value of drive strength
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
new file mode 100644
index 000000000000..05bf82a07dfd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -0,0 +1,110 @@
+*ST pin controller.
+Each multi-function pin is controlled, driven and routed through the
+PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
+and multiple alternate functions(ALT1 - ALTx) that directly connect
+the pin to different hardware blocks.
+When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
+Pull Up (PU) are driven by the related PIO block.
+ST pinctrl driver controls PIO multiplexing block and also interacts with
+gpio driver to configure a pin.
+Required properties: (PIO multiplexing block)
+- compatible    : should be "st,<SOC>-<pio-block>-pinctrl"
+        like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
+- gpio-controller : Indicates this device is a GPIO controller
+- #gpio-cells     : Should be one. The first cell is the pin number.
+- st,retime-pin-mask    : Should be mask to specify which pins can be retimed.
+        If the property is not present, it is assumed that all the pins in the
+        bank are capable of retiming. Retiming is mainly used to improve the
+        IO timing margins of external synchronous interfaces.
+- st,bank-name          : Should be a name string for this bank as
+                        specified in datasheet.
+- st,syscfg             : Should be a phandle of the syscfg node.
+Example:
+        pin-controller-sbc {
+                #address-cells  = <1>;
+                #size-cells     = <1>;
+                compatible      = "st,stih415-sbc-pinctrl";
+                st,syscfg       = <&syscfg_sbc>;
+                ranges          = <0 0xfe610000 0x5000>;
+                PIO0: gpio@fe610000 {
+                        gpio-controller;
+                        #gpio-cells     = <1>;
+                        reg             = <0 0x100>;
+                        st,bank-name    = "PIO0";
+                };
+                ...
+                pin-functions nodes follow...
+        };
+Contents of function subnode node:
+----------------------
+Required properties for pin configuration node:
+- st,pins       : Child node with list of pins with configuration.
+Below is the format of how each pin conf should look like.
+<bank offset mux mode rt_type rt_delay rt_clk>
+Every PIO is represented with 4-7 parameters depending on retime configuration.
+Each parameter is explained as below.
+-bank           : Should be bank phandle to which this PIO belongs.
+-offset         : Offset in the PIO bank.
+-mux            : Should be alternate function number associated this pin.
+                Use same numbers from datasheet.
+-mode           :pin configuration is selected from one of the below values.
+                IN
+                IN_PU
+                OUT
+                BIDIR
+                BIDIR_PU
+-rt_type        Retiming Configuration for the pin.
+                Possible retime configuration are:
+                -------         -------------
+                value           args
+                -------         -------------
+                NICLK           <delay> <clk>
+                ICLK_IO         <delay> <clk>
+                BYPASS          <delay>
+                DE_IO           <delay> <clk>
+                SE_ICLK_IO      <delay> <clk>
+                SE_NICLK_IO     <delay> <clk>
+- delay is retime delay in pico seconds as mentioned in data sheet.
+- rt_clk        :clk to be use for retime.
+                Possible values are:
+                CLK_A
+                CLK_B
+                CLK_C
+                CLK_D
+Example of mmcclk pin which is a bi-direction pull pu with retime config
+as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
+pin-controller {
+        ...
+        mmc0 {
+                pinctrl_mmc: mmc {
+                        st,pins {
+                                mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
+                                ...
+                        };
+                };
+        ...
+        };
+};
+sdhci0:sdhci@fe810000{
+        ...
+        pinctrl-names = "default";
+        pinctrl-0       = <&pinctrl_mmc>;
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 000000000000..d5dac7b843a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,153 @@
+* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
+The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
+SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
+Pin Control
+-----------
+Required Properties:
+  - compatible: should be one of the following.
+    - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
+    - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
+    - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
+    - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
+    - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
+    - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
+    - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
+  - reg: Base address and length of each memory resource used by the pin
+    controller hardware module.
+Optional properties:
+  - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
+    otherwise. Should be 3.
+The PFC node also acts as a container for pin configuration nodes. Please refer
+to pinctrl-bindings.txt in this directory for the definition of the term "pin
+configuration node" and for the common pinctrl bindings used by client devices.
+Each pin configuration node represents a desired configuration for a pin, a
+pin group, or a list of pins or pin groups. The configuration can include the
+function to select on those pin(s) and pin configuration parameters (such as
+pull-up and pull-down).
+Pin configuration nodes contain pin configuration properties, either directly
+or grouped in child subnodes. Both pin muxing and configuration parameters can
+be grouped in that way and referenced as a single pin configuration node by
+client devices.
+A configuration node or subnode must reference at least one pin (through the
+pins or pin groups properties) and contain at least a function or one
+configuration parameter. When the function is present only pin groups can be
+used to reference pins.
+All pin configuration nodes and subnodes names are ignored. All of those nodes
+are parsed through phandles and processed purely based on their content.
+Pin Configuration Node Properties:
+- renesas,pins : An array of strings, each string containing the name of a pin.
+- renesas,groups : An array of strings, each string containing the name of a pin
+  group.
+- renesas,function: A string containing the name of the function to mux to the
+  pin group(s) specified by the renesas,groups property
+  Valid values for pin, group and function names can be found in the group and
+  function arrays of the PFC data file corresponding to the SoC
+  (drivers/pinctrl/sh-pfc/pfc-*.c)
+The pin configuration parameters use the generic pinconf bindings defined in
+pinctrl-bindings.txt in this directory. The supported parameters are
+bias-disable, bias-pull-up and bias-pull-down.
+GPIO
+----
+On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
+node.
+Required Properties:
+  - gpio-controller: Marks the device node as a gpio controller.
+  - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
+    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
+    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
+The syntax of the gpio specifier used by client nodes should be the following
+with values derived from the SoC user manual.
+  <[phandle of the gpio controller node]
+   [pin number within the gpio controller]
+   [flags]>
+On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
+Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
+for documentation of the GPIO device tree bindings on those platforms.
+Examples
+--------
+Example 1: SH73A0 (SH-Mobile AG5) pin controller node
+        pfc: pfc@e6050000 {
+                compatible = "renesas,pfc-sh73a0";
+                reg = <0xe6050000 0x8000>,
+                      <0xe605801c 0x1c>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+Example 2: A GPIO LED node that references a GPIO
+        #include <dt-bindings/gpio/gpio.h>
+        leds {
+                compatible = "gpio-leds";
+                led1 {
+                        gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
+                };
+        };
+Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
+           for the MMCIF and SCIFA4 devices
+        &pfc {
+                pinctrl-0 = <&scifa4_pins>;
+                pinctrl-names = "default";
+                mmcif_pins: mmcif {
+                        mux {
+                                renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
+                                renesas,function = "mmc0";
+                        };
+                        cfg {
+                                renesas,groups = "mmc0_data8_0";
+                                renesas,pins = "PORT279";
+                                bias-pull-up;
+                        };
+                };
+                scifa4_pins: scifa4 {
+                        renesas,groups = "scifa4_data", "scifa4_ctrl";
+                        renesas,function = "scifa4";
+                };
+        };
+Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
+        &mmcif {
+                pinctrl-0 = <&mmcif_pins>;
+                pinctrl-names = "default";
+                bus-width = <8>;
+                vmmc-supply = <&reg_1p8v>;
+                status = "okay";
+        };
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
new file mode 100644
index 000000000000..b0fb1018d7ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -0,0 +1,97 @@
+* Rockchip Pinmux Controller
+The Rockchip Pinmux Controller, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+4 muxing options with option 0 being the use as a GPIO.
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+The Rockchip pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and
+config of the pins in that group. The 'pins' selects the function mode(also
+named pin mode) this pin can work on and the 'config' configures various pad
+settings such as pull-up, etc.
+The pins are grouped into up to 5 individual pin banks which need to be
+defined as gpio sub-nodes of the pinmux controller.
+Required properties for iomux controller:
+  - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
+                       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
+Required properties for gpio sub nodes:
+  - compatible: "rockchip,gpio-bank"
+  - reg: register of the gpio bank (different than the iomux registerset)
+  - interrupts: base interrupt of the gpio bank in the interrupt controller
+  - clocks: clock that drives this bank
+  - gpio-controller: identifies the node as a gpio controller and pin bank.
+  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
+    binding is used, the amount of cells must be specified as 2. See generic
+    GPIO binding documentation for description of particular cells.
+  - interrupt-controller: identifies the controller node as interrupt-parent.
+  - #interrupt-cells: the value of this property should be 2 and the interrupt
+    cells should use the standard two-cell scheme described in
+    bindings/interrupt-controller/interrupts.txt
+Required properties for pin configuration node:
+  - rockchip,pins: 3 integers array, represents a group of pins mux and config
+    setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
+    The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
+    The phandle of a node containing the generic pinconfig options
+    to use, as described in pinctrl-bindings.txt in this directory.
+Examples:
+#include <dt-bindings/pinctrl/rockchip.h>
+...
+pinctrl@20008000 {
+        compatible = "rockchip,rk3066a-pinctrl";
+        reg = <0x20008000 0x150>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        gpio0: gpio0@20034000 {
+                compatible = "rockchip,gpio-bank";
+                reg = <0x20034000 0x100>;
+                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clk_gates8 9>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        ...
+        pcfg_pull_default: pcfg_pull_default {
+                bias-pull-pin-default
+        };
+        uart2 {
+                uart2_xfer: uart2-xfer {
+                        rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
+                                        <RK_GPIO1 9 1 &pcfg_pull_default>;
+                };
+        };
+};
+uart2: serial@20064000 {
+        compatible = "snps,dw-apb-uart";
+        reg = <0x20064000 0x400>;
+        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+        reg-shift = <2>;
+        reg-io-width = <1>;
+        clocks = <&mux_uart2>;
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_xfer>;
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index c70fca146e91..36281e7a2a46 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -7,10 +7,15 @@ on-chip controllers onto these pads.
 Required Properties:
 - compatible: should be one of the following.
+  - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
+  - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
+  - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
+  - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
  - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
  - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
  - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
  - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+  - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
 - reg: Base address of the pin controller hardware module and length of
  the address space it occupies.
@@ -21,8 +26,18 @@ Required Properties:
  - gpio-controller: identifies the node as a gpio controller and pin bank.
  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
-    binding is used, the amount of cells must be specified as 2. See generic
+    binding is used, the amount of cells must be specified as 2. See the below
-    GPIO binding documentation for description of particular cells.
+    mentioned gpio binding representation for description of particular cells.
+        Eg: <&gpx2 6 0>
+        <[phandle of the gpio controller node]
+        [pin number within the gpio controller]
+        [flags]>
+        Values for gpio specifier:
+        - Pin number: is a value between 0 to 7.
+        - Flags: 0 - Active High
+                 1 - Active Low
 - Pin mux/config groups as child nodes: The pin mux (selecting pin function
  mode) and pin config (pull up/down, driver strength) settings are represented
@@ -106,6 +121,10 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
   - compatible: identifies the type of the external wakeup interrupt controller
     The possible values are:
+     - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller
+       found on Samsung S3C24xx SoCs except S3C2412 and S3C2413,
+     - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller
+       found on Samsung S3C2412 and S3C2413 SoCs,
     - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
       found on Samsung S3C64xx SoCs,
     - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
@@ -266,3 +285,33 @@ Example 4: Set up the default pin state for uart controller.
                pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
        }
+Example 5: A display port client node that supports 'default' pinctrl state
+           and gpio binding.
+        display-port-controller {
+                /* ... */
+                samsung,hpd-gpio = <&gpx2 6 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&dp_hpd>;
+        };
+Example 6: Request the gpio for display port controller
+        static int exynos_dp_probe(struct platform_device *pdev)
+        {
+                int hpd_gpio, ret;
+                struct device *dev = &pdev->dev;
+                struct device_node *dp_node = dev->of_node;
+                /* ... */
+                hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
+                /* ... */
+                ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
+                                            "hpd_gpio");
+                /* ... */
+        }
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt
new file mode 100644
index 000000000000..e3865e136067
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt
@@ -0,0 +1,352 @@
+ST Ericsson abx500 pinmux controller
+Required properties:
+- compatible: "stericsson,ab8500-gpio",  "stericsson,ab8540-gpio",
+              "stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as input, output, pull up, pull down...
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+Required subnode-properties:
+- ste,pins : An array of strings. Each string contains the name of a pin or
+    group.
+Optional subnode-properties:
+- ste,function: A string containing the name of the function to mux to the
+  pin or group.
+- generic pin configuration option to use. Example :
+        default_cfg {
+                ste,pins = "GPIO1";
+                bias-disable;
+        };
+- ste,config: Handle of pin configuration node containing the generic
+  pinconfig options to use, as described in pinctrl-bindings.txt in
+  this directory. Example :
+        pcfg_bias_disable: pcfg_bias_disable {
+                bias-disable;
+        };
+        default_cfg {
+                ste,pins = "GPIO1";
+                ste.config = <&pcfg_bias_disable>;
+        };
+Example board file extract:
+&pinctrl_abx500 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>;
+        sysclkreq2 {
+                sysclkreq2_default_mode: sysclkreq2_default {
+                        default_mux {
+                                ste,function = "sysclkreq";
+                                ste,pins = "sysclkreq2_d_1";
+                        };
+                        default_cfg {
+                                ste,pins = "GPIO1";
+                                bias-disable;
+                        };
+                };
+        };
+        sysclkreq3 {
+                sysclkreq3_default_mode: sysclkreq3_default {
+                        default_mux {
+                                ste,function = "sysclkreq";
+                                ste,pins = "sysclkreq3_d_1";
+                        };
+                        default_cfg {
+                                ste,pins = "GPIO2";
+                                output-low;
+                        };
+                };
+        };
+        gpio3 {
+                gpio3_default_mode: gpio3_default {
+                        default_mux {
+                                ste,function = "gpio";
+                                ste,pins = "gpio3_a_1";
+                        };
+                        default_cfg {
+                                ste,pins = "GPIO3";
+                                output-low;
+                        };
+                };
+        };
+        sysclkreq6 {
+                sysclkreq6_default_mode: sysclkreq6_default {
+                        default_mux {
+                                ste,function = "sysclkreq";
+                                ste,pins = "sysclkreq6_d_1";
+                        };
+                        default_cfg {
+                                ste,pins = "GPIO4";
+                                bias-disable;
+                        };
+                };
+        };
+        pwmout1 {
+                pwmout1_default_mode: pwmout1_default {
+                        default_mux {
+                                ste,function = "pwmout";
+                                ste,pins = "pwmout1_d_1";
+                        };
+                        default_cfg {
+                                ste,pins = "GPIO14";
+                                output-low;
+                        };
+                };
+        };
+        pwmout2 {
+                pwmout2_default_mode: pwmout2_default {
+                        pwmout2_default_mux {
+                                ste,function = "pwmout";
+                                ste,pins = "pwmout2_d_1";
+                        };
+                        pwmout2_default_cfg {
+                                ste,pins = "GPIO15";
+                                output-low;
+                        };
+                };
+        };
+        pwmout3 {
+                pwmout3_default_mode: pwmout3_default {
+                        pwmout3_default_mux {
+                                ste,function = "pwmout";
+                                ste,pins = "pwmout3_d_1";
+                        };
+                        pwmout3_default_cfg {
+                                ste,pins = "GPIO16";
+                                output-low;
+                        };
+                };
+        };
+        adi1 {
+                adi1_default_mode: adi1_default {
+                        adi1_default_mux {
+                                ste,function = "adi1";
+                                ste,pins = "adi1_d_1";
+                        };
+                        adi1_default_cfg1 {
+                                ste,pins = "GPIO17","GPIO19","GPIO20";
+                                bias-disable;
+                        };
+                        adi1_default_cfg2 {
+                                ste,pins = "GPIO18";
+                                output-low;
+                        };
+                };
+        };
+        dmic12 {
+                dmic12_default_mode: dmic12_default {
+                        dmic12_default_mux {
+                                ste,function = "dmic";
+                                ste,pins = "dmic12_d_1";
+                        };
+                        dmic12_default_cfg1 {
+                                ste,pins = "GPIO27";
+                                output-low;
+                        };
+                        dmic12_default_cfg2 {
+                                ste,pins = "GPIO28";
+                                bias-disable;
+                        };
+                };
+        };
+        dmic34 {
+                dmic34_default_mode: dmic34_default {
+                        dmic34_default_mux {
+                                ste,function = "dmic";
+                                ste,pins = "dmic34_d_1";
+                        };
+                        dmic34_default_cfg1 {
+                                ste,pins = "GPIO29";
+                                output-low;
+                        };
+                        dmic34_default_cfg2 {
+                                ste,pins = "GPIO30";
+                                bias-disable;{
+                        };
+                };
+        };
+        dmic56 {
+                dmic56_default_mode: dmic56_default {
+                        dmic56_default_mux {
+                                ste,function = "dmic";
+                                ste,pins = "dmic56_d_1";
+                        };
+                        dmic56_default_cfg1 {
+                                ste,pins = "GPIO31";
+                                output-low;
+                        };
+                        dmic56_default_cfg2 {
+                                ste,pins = "GPIO32";
+                                bias-disable;
+                        };
+                };
+        };
+        sysclkreq5 {
+                sysclkreq5_default_mode: sysclkreq5_default {
+                        sysclkreq5_default_mux {
+                                ste,function = "sysclkreq";
+                                ste,pins = "sysclkreq5_d_1";
+                        };
+                        sysclkreq5_default_cfg {
+                                ste,pins = "GPIO42";
+                                output-low;
+                        };
+                };
+        };
+        batremn {
+                batremn_default_mode: batremn_default {
+                        batremn_default_mux {
+                                ste,function = "batremn";
+                                ste,pins = "batremn_d_1";
+                        };
+                        batremn_default_cfg {
+                                ste,pins = "GPIO43";
+                                bias-disable;
+                        };
+                };
+        };
+        service {
+                service_default_mode: service_default {
+                        service_default_mux {
+                                ste,function = "service";
+                                ste,pins = "service_d_1";
+                        };
+                        service_default_cfg {
+                                ste,pins = "GPIO44";
+                                bias-disable;
+                        };
+                };
+        };
+        pwrctrl0 {
+                pwrctrl0_default_mux: pwrctrl0_mux {
+                        pwrctrl0_default_mux {
+                                ste,function = "pwrctrl";
+                                ste,pins = "pwrctrl0_d_1";
+                        };
+                };
+                pwrctrl0_default_mode: pwrctrl0_default {
+                        pwrctrl0_default_cfg {
+                                ste,pins = "GPIO45";
+                                bias-disable;
+                        };
+                };
+        };
+        pwrctrl1 {
+                pwrctrl1_default_mux: pwrctrl1_mux {
+                        pwrctrl1_default_mux {
+                                ste,function = "pwrctrl";
+                                ste,pins = "pwrctrl1_d_1";
+                        };
+                };
+                pwrctrl1_default_mode: pwrctrl1_default {
+                        pwrctrl1_default_cfg {
+                                ste,pins = "GPIO46";
+                                bias-disable;
+                        };
+                };
+        };
+        pwmextvibra1 {
+                pwmextvibra1_default_mode: pwmextvibra1_default {
+                        pwmextvibra1_default_mux {
+                                ste,function = "pwmextvibra";
+                                ste,pins = "pwmextvibra1_d_1";
+                        };
+                        pwmextvibra1_default_cfg {
+                                ste,pins = "GPIO47";
+                                bias-disable;
+                        };
+                };
+        };
+        pwmextvibra2 {
+                pwmextvibra2_default_mode: pwmextvibra2_default {
+                        pwmextvibra2_default_mux {
+                                ste,function = "pwmextvibra";
+                                ste,pins = "pwmextvibra2_d_1";
+                        };
+                        pwmextvibra1_default_cfg {
+                                ste,pins = "GPIO48";
+                                bias-disable;
+                        };
+                };
+        };
+        gpio51 {
+                gpio51_default_mode: gpio51_default {
+                                gpio51_default_mux {
+                                ste,function = "gpio";
+                                ste,pins = "gpio51_a_1";
+                        };
+                        gpio51_default_cfg {
+                                ste,pins = "GPIO51";
+                                output-low;
+                        };
+                };
+        };
+        gpio52 {
+                gpio52_default_mode: gpio52_default {
+                        gpio52_default_mux {
+                                ste,function = "gpio";
+                                ste,pins = "gpio52_a_1";
+                        };
+                        gpio52_default_cfg {
+                                ste,pins = "GPIO52";
+                                bias-pull-down;
+                        };
+                };
+        };
+        gpio53 {
+                gpio53_default_mode: gpio53_default {
+                        gpio53_default_mux {
+                                ste,function = "gpio";
+                                ste,pins = "gpio53_a_1";
+                        };
+                        gpio53_default_cfg {
+                                ste,pins = "GPIO53";
+                                bias-pull-down;
+                        };
+                };
+        };
+        gpio54 {
+                gpio54_default_mode: gpio54_default {
+                        gpio54_default_mux {
+                                ste,function = "gpio";
+                                ste,pins = "gpio54_a_1";
+                        };
+                        gpio54_default_cfg {
+                                ste,pins = "GPIO54";
+                                output-low;
+                        };
+                };
+        };
+        pdmclkdat {
+                pdmclkdat_default_mode: pdmclkdat_default {
+                        pdmclkdat_default_mux {
+                                ste,function = "pdm";
+                                ste,pins = "pdmclkdat_d_1";
+                        };
+                        pdmclkdat_default_cfg {
+                                ste,pins = "GPIO55", "GPIO56";
+                                bias-disable;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
index 2161334a7ca5..712baf6c3e24 100644
--- a/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
+++ b/Documentation/devicetree/bindings/powerpc/4xx/emac.txt
@@ -1,7 +1,7 @@
    4xx/Axon EMAC ethernet nodes
    The EMAC ethernet controller in IBM and AMCC 4xx chips, and also
-    the Axon bridge.  To operate this needs to interact with a ths
+    the Axon bridge.  To operate this needs to interact with a this
    special McMAL DMA controller, and sometimes an RGMII or ZMII
    interface.  In addition to the nodes and properties described
    below, the node for the OPB bus on which the EMAC sits must have a
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt b/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt
new file mode 100644
index 000000000000..641bc13983e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/interlaken-lac.txt
@@ -0,0 +1,309 @@
+===============================================================================
+Freescale Interlaken Look-Aside Controller Device Bindings
+Copyright 2012 Freescale Semiconductor Inc.
+CONTENTS
+  - Interlaken Look-Aside Controller (LAC) Node
+  - Example LAC Node
+  - Interlaken Look-Aside Controller (LAC) Software Portal Node
+  - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
+  - Example LAC SWP Node with Child Nodes
+==============================================================================
+Interlaken Look-Aside Controller (LAC) Node
+DESCRIPTION
+The Interlaken is a narrow, high speed channelized chip-to-chip interface. To
+facilitate interoperability between a data path device and a look-aside
+co-processor, the Interlaken Look-Aside protocol is defined for short
+transaction-related transfers. Although based on the Interlaken protocol,
+Interlaken Look-Aside is not directly compatible with Interlaken and can be
+considered a different operation mode.
+The Interlaken LA controller connects internal platform to Interlaken serial
+interface. It accepts LA command through software portals, which are system
+memory mapped 4KB spaces. The LA commands are then translated into the
+Interlaken control words and data words, which are sent on TX side to TCAM
+through SerDes lanes.
+There are two 4KiB spaces defined within the LAC global register memory map.
+There is a full register set at 0x0000-0x0FFF (also known as the "hypervisor"
+version), and a subset at 0x1000-0x1FFF.  The former is a superset of the
+latter, and includes certain registers that should not be accessible to
+partitioned software.  Separate nodes are used for each region, with a phandle
+linking the hypervisor node to the normal operating node.
+PROPERTIES
+  - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,interlaken-lac". This represents only
+                those LAC CCSR registers not protected in partitioned
+                software. The version of the device is determined by the LAC
+                IP Block Revision Register (IPBRR0) at offset 0x0BF8.
+                Table of correspondences between IPBRR0 values and example
+                chips:
+                        Value           Device
+                        -----------     -------
+                        0x02000100      T4240
+                The Hypervisor node has a different compatible. It must include
+                "fsl,interlaken-lac-hv". This node represents the protected
+                LAC register space and is required except inside a partition
+                where access to the hypervisor node is to be denied.
+  - fsl,non-hv-node
+        Usage: required in "fsl,interlaken-lac-hv"
+        Value type: <phandle>
+        Definition: Points to the non-protected LAC CCSR mapped register space
+                node.
+  - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property. The first resource represents the
+                Interlaken LAC configuration registers.
+  - interrupts:
+        Usage: required in non-hv node only
+        Value type: <prop-encoded-array>
+        Definition: Interrupt mapping for Interlaken LAC error IRQ.
+EXAMPLE
+        lac: lac@229000 {
+                compatible = "fsl,interlaken-lac"
+                reg = <0x229000 0x1000>;
+                interrupts = <16 2 1 18>;
+        };
+        lac-hv@228000 {
+                compatible = "fsl,interlaken-lac-hv"
+                reg = <0x228000 0x1000>;
+                fsl,non-hv-node = <&lac>;
+        };
+===============================================================================
+Interlaken Look-Aside Controller (LAC) Software Portal Container Node
+DESCRIPTION
+The Interlaken Look-Aside Controller (LAC) utilizes Software Portals to accept
+Interlaken Look-Aside (ILA) commands. The Interlaken LAC software portal
+memory map occupies 128KB of memory space. The software portal memory space is
+intended to be cache-enabled. WIMG for each software space is required to be
+0010 if stashing is enabled; otherwise, WIMG can be 0000 or 0010.
+PROPERTIES
+  - #address-cells
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property. Must have a value of 1.
+  - #size-cells
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property. Must have a value of 1.
+  - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,interlaken-lac-portals"
+  - ranges
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property. Specifies the address and length
+                of the LAC portal memory space.
+===============================================================================
+Interlaken Look-Aside Controller (LAC) Software Portals Child Nodes
+DESCRIPTION
+There are up to 24 available software portals with each software portal
+requiring 4KB of consecutive memory within the software portal memory mapped
+space.
+PROPERTIES
+  - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,interlaken-lac-portal-vX.Y" where X is
+                the Major version (IP_MJ) found in the LAC IP Block Revision
+                Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
+                (IP_MN).
+                Table of correspondences between version values and example chips:
+                    Value       Device
+                    ------      -------
+                      1.0       T4240
+  - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  The first resource represents the
+                Interlaken LAC software portal registers.
+  - fsl,liodn
+        Value type: <u32>
+        Definition: The logical I/O device number (LIODN) for this device.  The
+                LIODN is a number expressed by this device and used to perform
+                look-ups in the IOMMU (PAMU) address table when performing
+                DMAs. This property is automatically added by u-boot.
+===============================================================================
+EXAMPLE
+lac-portals {
+        #address-cells = <0x1>;
+        #size-cells = <0x1>;
+        compatible = "fsl,interlaken-lac-portals";
+        ranges = <0x0 0xf 0xf4400000 0x20000>;
+        lportal0: lac-portal@0 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x204>;
+                reg = <0x0 0x1000>;
+        };
+        lportal1: lac-portal@1000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x205>;
+                reg = <0x1000 0x1000>;
+        };
+        lportal2: lac-portal@2000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x206>;
+                reg = <0x2000 0x1000>;
+        };
+        lportal3: lac-portal@3000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x207>;
+                reg = <0x3000 0x1000>;
+        };
+        lportal4: lac-portal@4000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x208>;
+                reg = <0x4000 0x1000>;
+        };
+        lportal5: lac-portal@5000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x209>;
+                reg = <0x5000 0x1000>;
+        };
+        lportal6: lac-portal@6000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x20A>;
+                reg = <0x6000 0x1000>;
+        };
+        lportal7: lac-portal@7000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x20B>;
+                reg = <0x7000 0x1000>;
+        };
+        lportal8: lac-portal@8000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x20C>;
+                reg = <0x8000 0x1000>;
+        };
+        lportal9: lac-portal@9000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x20D>;
+                reg = <0x9000 0x1000>;
+        };
+        lportal10: lac-portal@A000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x20E>;
+                reg = <0xA000 0x1000>;
+        };
+        lportal11: lac-portal@B000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x20F>;
+                reg = <0xB000 0x1000>;
+        };
+        lportal12: lac-portal@C000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x210>;
+                reg = <0xC000 0x1000>;
+        };
+        lportal13: lac-portal@D000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x211>;
+                reg = <0xD000 0x1000>;
+        };
+        lportal14: lac-portal@E000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x212>;
+                reg = <0xE000 0x1000>;
+        };
+        lportal15: lac-portal@F000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x213>;
+                reg = <0xF000 0x1000>;
+        };
+        lportal16: lac-portal@10000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x214>;
+                reg = <0x10000 0x1000>;
+        };
+        lportal17: lac-portal@11000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x215>;
+                reg = <0x11000 0x1000>;
+        };
+        lportal8: lac-portal@1200 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x216>;
+                reg = <0x12000 0x1000>;
+        };
+        lportal19: lac-portal@13000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x217>;
+                reg = <0x13000 0x1000>;
+        };
+        lportal20: lac-portal@14000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x218>;
+                reg = <0x14000 0x1000>;
+        };
+        lportal21: lac-portal@15000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x219>;
+                reg = <0x15000 0x1000>;
+        };
+        lportal22: lac-portal@16000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x21A>;
+                reg = <0x16000 0x1000>;
+        };
+        lportal23: lac-portal@17000 {
+                compatible = "fsl,interlaken-lac-portal-v1.0";
+                fsl,liodn = <0x21B>;
+                reg = <0x17000 0x1000>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/pps/pps-gpio.txt b/Documentation/devicetree/bindings/pps/pps-gpio.txt
new file mode 100644
index 000000000000..40bf9c3564a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pps/pps-gpio.txt
@@ -0,0 +1,20 @@
+Device-Tree Bindings for a PPS Signal on GPIO
+These properties describe a PPS (pulse-per-second) signal connected to
+a GPIO pin.
+Required properties:
+- compatible: should be "pps-gpio"
+- gpios: one PPS GPIO in the format described by ../gpio/gpio.txt
+Optional properties:
+- assert-falling-edge: when present, assert is indicated by a falling edge
+                       (instead of by a rising edge)
+Example:
+        pps {
+                compatible = "pps-gpio";
+                gpios = <&gpio2 6 0>;
+                assert-falling-edge;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/lp872x.txt b/Documentation/devicetree/bindings/regulator/lp872x.txt
new file mode 100644
index 000000000000..78183182dad9
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/lp872x.txt
@@ -0,0 +1,160 @@
+Binding for TI/National Semiconductor LP872x Driver
+Required properties:
+  - compatible: "ti,lp8720" or "ti,lp8725"
+  - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
+Optional properties:
+  - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
+    (LP8720)
+    bit[2]: BUCK output voltage control by external DVS pin or register
+            1 = external pin, 0 = bit7 of register 08h
+    bit[1]: sleep control by external DVS pin or register
+            1 = external pin, 0 = bit6 of register 08h
+    bit[0]: time step unit(usec). 1 = 25, 0 = 50
+    (LP8725)
+    bit[7:6]: time step unit(usec). 00 = 32, 01 = 64, 10 = 128, 11 = 256
+    bit[4]:   BUCK2 enable control. 1 = enable, 0 = disable
+    bit[3]:   BUCK2 output voltage register address. 1 = 0Ah, 0 = 0Bh
+    bit[2]:   BUCK1 output voltage control by external DVS pin or register
+              1 = register 08h, 0 = DVS
+    bit[1]:   LDO sleep control. 1 = sleep mode, 0 = normal
+    bit[0]:   BUCK1 enable control, 1 = enable, 0 = disable
+    For more details, please see the datasheet.
+  - ti,update-config: define it when LP872X_GENERAL_CFG register should be set
+  - ti,dvs-gpio: GPIO specifier for external DVS pin control of LP872x devices.
+  - ti,dvs-vsel: DVS selector. 0 = SEL_V1, 1 = SEL_V2.
+  - ti,dvs-state: initial DVS pin state. 0 = DVS_LOW, 1 = DVS_HIGH.
+  Sub nodes for regulator_init_data
+    LP8720 has maximum 6 nodes. (child name: ldo1 ~ 5 and buck)
+    LP8725 has maximum 9 nodes. (child name: ldo1 ~ 5, lilo1,2 and buck1,2)
+    For more details, please see the following binding document.
+    (Documentation/devicetree/bindings/regulator/regulator.txt)
+Datasheet
+  - LP8720: http://www.ti.com/lit/ds/symlink/lp8720.pdf
+  - LP8725: http://www.ti.com/lit/ds/symlink/lp8725.pdf
+Example 1) LP8720
+lp8720@7d {
+        compatible = "ti,lp8720";
+        reg = <0x7d>;
+        /* external DVS pin used, timestep is 25usec */
+        ti,general-config = /bits/ 8 <0x03>;
+        ti,update-config;
+        /*
+         * The dvs-gpio depends on the processor environment.
+         * For example, following GPIO specifier means GPIO134 in OMAP4.
+         */
+        ti,dvs-gpio = <&gpio5 6 0>;
+        ti,dvs-vsel = /bits/ 8 <1>;             /* SEL_V2 */
+        ti,dvs-state = /bits/ 8 <1>;            /* DVS_HIGH */
+        vaf: ldo1 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vmmc: ldo2 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vcam_io: ldo3 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+        vcam_core: ldo4 {
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <2850000>;
+                regulator-boot-on;
+        };
+        vcam: ldo5 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vcc: buck {
+                regulator-name = "VBUCK";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <2300000>;
+        };
+};
+Example 2) LP8725
+lp8725@7a {
+        compatible = "ti,lp8725";
+        reg = <0x7a>;
+        /* Enable BUCK1,2, no DVS, normal LDO mode, timestep is 256usec */
+        ti,general-config = /bits/ 8 <0xdd>;
+        ti,update-config;
+        vcam_io: ldo1 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vcam_core: ldo2 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vcam: ldo3 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vcmmb_io: ldo4 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+        vcmmb_core: ldo5 {
+                regulator-min-microvolt = <1200000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+        };
+        vaux1: lilo1 {
+                regulator-name = "VAUX1";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vaux2: lilo2 {
+                regulator-name = "VAUX2";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vcc1: buck1 {
+                regulator-name = "VBUCK1";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <3000000>;
+                regulator-min-microamp  = <460000>;
+                regulator-max-microamp  = <1370000>;
+                regulator-boot-on;
+        };
+        vcc2: buck2 {
+                regulator-name = "VBUCK2";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <3000000>;
+                regulator-min-microamp  = <460000>;
+                regulator-max-microamp  = <1370000>;
+                regulator-boot-on;
+        };
+};
diff --git a/Documentation/devicetree/bindings/regulator/max8973-regulator.txt b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
new file mode 100644
index 000000000000..4f15d8a1bfd0
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8973-regulator.txt
@@ -0,0 +1,21 @@
+* Maxim MAX8973 Voltage Regulator
+Required properties:
+- compatible:   must be "maxim,max8973"
+- reg:          the i2c slave address of the regulator. It should be 0x1b.
+Any standard regulator properties can be used to configure the single max8973
+DCDC.
+Example:
+        max8973@1b {
+                compatible = "maxim,max8973";
+                reg = <0x1b>;
+                regulator-min-microvolt = <935000>;
+                regulator-max-microvolt = <1200000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
new file mode 100644
index 000000000000..d5a308629c57
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
@@ -0,0 +1,72 @@
+* palmas regulator IP block devicetree bindings
+Required properties:
+- compatible : Should be from the list
+  ti,twl6035-pmic
+  ti,twl6036-pmic
+  ti,twl6037-pmic
+  ti,tps65913-pmic
+  ti,tps65914-pmic
+and also the generic series names
+  ti,palmas-pmic
+- interrupt-parent : The parent interrupt controller which is palmas.
+- interrupts : The interrupt number and the type which can be looked up here:
+               arch/arm/boot/dts/include/dt-bindings/interrupt-controller/irq.h
+- interrupts-name: The names of the individual interrupts.
+Optional properties:
+- ti,ldo6-vibrator : ldo6 is in vibrator mode
+Optional nodes:
+- regulators : Must contain a sub-node per regulator from the list below.
+               Each sub-node should contain the constraints and initialization
+               information for that regulator. See regulator.txt for a
+               description of standard properties for these sub-nodes.
+               Additional custom properties  are listed below.
+               For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
+               smps45, smps457, smps7 depending on variant, smps6, smps[8-10],
+               ldo[1-9], ldoln, ldousb.
+               Optional sub-node properties:
+               ti,warm-reset - maintain voltage during warm reset(boolean)
+               ti,roof-floor - control voltage selection by pin(boolean)
+               ti,sleep-mode - mode to adopt in pmic sleep 0 - off, 1 - auto,
+               2 - eco, 3 - forced pwm
+               ti,tstep - slope control 0 - Jump, 1 10mV/us, 2 5mV/us, 3 2.5mV/us
+               ti,smps-range - OTP has the wrong range set for the hardware so override
+               0 - low range, 1 - high range.
+Example:
+#include <dt-bindings/interrupt-controller/irq.h>
+pmic {
+        compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+        interrupt-parent = <&palmas>;
+        interrupts = <14 IRQ_TYPE_NONE>;
+        interrupts-name = "short-irq";
+        ti,ldo6-vibrator;
+        regulators {
+                smps12_reg : smps12 {
+                        regulator-name = "smps12";
+                        regulator-min-microvolt = < 600000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        ti,warm-reset;
+                        ti,roof-floor;
+                        ti,mode-sleep = <0>;
+                        ti,tstep = <0>;
+                        ti,smps-range = <1>;
+                };
+                ldo1_reg: ldo1 {
+                        regulator-name = "ldo1";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt
index ecfc6ccd67ef..48a3b8e5d6bd 100644
--- a/Documentation/devicetree/bindings/regulator/regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/regulator.txt
@@ -9,6 +9,7 @@ Optional properties:
 - regulator-max-microamp: largest current consumers may set
 - regulator-always-on: boolean, regulator should never be disabled
 - regulator-boot-on: bootloader/firmware enabled regulator
+- regulator-allow-bypass: allow the regulator to go into bypass mode
 - <name>-supply: phandle to the parent supply/regulator node
 - regulator-ramp-delay: ramp delay for regulator(in uV/uS)
diff --git a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
new file mode 100644
index 000000000000..2e57a33e9029
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
@@ -0,0 +1,128 @@
+Adaptive Body Bias(ABB) SoC internal LDO regulator for Texas Instruments SoCs
+Required Properties:
+- compatible: Should be one of:
+  - "ti,abb-v1" for older SoCs like OMAP3
+  - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  - "base-address"      - contains base address of ABB module
+  - "int-address"       - contains address of interrupt register for ABB module
+  (also see Optional properties)
+- #address-cell: should be 0
+- #size-cell: should be 0
+- clocks: should point to the clock node used by ABB module
+- ti,settling-time: Settling time in uSecs from SoC documentation for ABB module
+        to settle down(target time for SR2_WTCNT_VALUE).
+- ti,clock-cycles: SoC specific data about count of system ti,clock-cycles used for
+        computing settling time from SoC Documentation for ABB module(clock
+        cycles for SR2_WTCNT_VALUE).
+- ti,tranxdone-status-mask: Mask to the int-register to write-to-clear mask
+        indicating LDO tranxdone (operation complete).
+- ti,abb_info: An array of 6-tuples u32 items providing information about ABB
+        configuration needed per operational voltage of the device.
+        Each item consists of the following in the same order:
+        volt: voltage in uV - Only used to index ABB information.
+        ABB mode: one of the following:
+                0-bypass
+                1-Forward Body Bias(FBB)
+                3-Reverse Body Bias(RBB)
+        efuse:  (see Optional properties)
+        RBB enable efuse Mask:  (See Optional properties)
+        FBB enable efuse Mask:  (See Optional properties)
+        Vset value efuse Mask:  (See Optional properties)
+        NOTE: If more than 1 entry is present, then regulator is setup to change
+              voltage, allowing for various modes to be selected indexed off
+              the regulator. Further, ABB LDOs are considered always-on by
+              default.
+Optional Properties:
+- reg-names: In addition to the required properties, the following are optional
+  - "efuse-address"     - Contains efuse base address used to pick up ABB info.
+  - "ldo-address"       - Contains address of ABB LDO overide register address.
+        "efuse-address" is required for this.
+- ti,ldovbb-vset-mask   - Required if ldo-address is set, mask for LDO override
+        register to provide override vset value.
+- ti,ldovbb-override-mask - Required if ldo-address is set, mask for LDO
+        override register to enable override vset value.
+- ti,abb_opp_sel: Addendum to the description in required properties
+        efuse: Mandatory if 'efuse-address' register is defined. Provides offset
+               from efuse-address to pick up ABB characteristics. Set to 0 if
+               'efuse-address' is not defined.
+        RBB enable efuse Mask:  Optional if 'efuse-address' register is defined.
+                'ABB mode' is force set to RBB mode if value at "efuse-address"
+                + efuse maps to RBB mask. Set to 0 to ignore this.
+        FBB enable efuse Mask:  Optional if 'efuse-address' register is defined.
+                'ABB mode' is force set to FBB mode if value at "efuse-address"
+                + efuse maps to FBB mask (valid only if RBB mask does not match)
+                Set to 0 to ignore this.
+        Vset value efuse Mask:  Mandatory if ldo-address is set. Picks up from
+                efuse the value to set in 'ti,ldovbb-vset-mask' at ldo-address.
+Example #1: Simplest configuration (no efuse data, hard coded ABB table):
+abb_x: regulator-abb-x {
+        compatible = "ti,abb-v1";
+        regulator-name = "abb_x";
+        #address-cell = <0>;
+        #size-cells = <0>;
+        reg = <0x483072f0 0x8>, <0x48306818 0x4>;
+        reg-names = "base-address", "int-address";
+        ti,tranxdone-status-mask = <0x4000000>;
+        clocks = <&sysclk>;
+        ti,settling-time = <30>;
+        ti,clock-cycles = <8>;
+        ti,abb_info = <
+        /* uV           ABB     efuse   rbb_m   fbb_m   vset_m */
+        1012500         0       0       0       0       0 /* Bypass */
+        1200000         3       0       0       0       0 /* RBB mandatory */
+        1320000         1       0       0       0       0 /* FBB mandatory */
+        >;
+};
+Example #2: Efuse bits contain ABB mode setting (no LDO override capability)
+abb_y: regulator-abb-y {
+        compatible = "ti,abb-v2";
+        regulator-name = "abb_y";
+        #address-cell = <0>;
+        #size-cells = <0>;
+        reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>, <0x4A002268 0x8>;
+        reg-names = "base-address", "int-address", "efuse-address";
+        ti,tranxdone-status-mask = <0x4000000>;
+        clocks = <&sysclk>;
+        ti,settling-time = <50>;
+        ti,clock-cycles = <16>;
+        ti,abb_info = <
+        /* uV           ABB     efuse   rbb_m   fbb_m   vset_m */
+        975000          0       0       0       0       0 /* Bypass */
+        1012500         0       0       0x40000 0       0 /* RBB optional */
+        1200000         0       0x4     0       0x40000 0 /* FBB optional */
+        1320000         1       0       0       0       0 /* FBB mandatory */
+        >;
+};
+Example #3: Efuse bits contain ABB mode setting and LDO override capability
+abb_z: regulator-abb-z {
+        compatible = "ti,abb-v2";
+        regulator-name = "abb_z";
+        #address-cell = <0>;
+        #size-cells = <0>;
+        reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
+              <0x4a002194 0x8>, <0x4ae0C314 0x4>;
+        reg-names = "base-address", "int-address",
+                    "efuse-address", "ldo-address";
+        ti,tranxdone-status-mask = <0x8000000>;
+        /* LDOVBBMM_MUX_CTRL */
+        ti,ldovbb-override-mask = <0x400>;
+        /* LDOVBBMM_VSET_OUT */
+        ti,ldovbb-vset-mask = <0x1F>;
+        clocks = <&sysclk>;
+        ti,settling-time = <50>;
+        ti,clock-cycles = <16>;
+        ti,abb_info = <
+        /* uV   ABB     efuse   rbb_m   fbb_m   vset_m */
+        975000  0       0       0       0       0       /* Bypass */
+        1200000 0       0x4     0       0x40000 0x1f00  /* FBB optional, vset */
+        >;
+};
diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
index 93e2b0f048e6..eb2327b2bdb3 100644
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt
@@ -5,9 +5,20 @@ Required properties:
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: IRQ line for the timer.
+- either clocks+clock-names or clock-frequency properties
+Optional properties:
+- clocks        : list of clock specifiers, corresponding to entries in
+                  the clock-names property;
+- clock-names   : should contain "timer" and "pclk" entries, matching entries
+                  in the clocks property.
 - clock-frequency: The frequency in HZ of the timer.
 - clock-freq: For backwards compatibility with picoxcell
+If using the clock specifiers, the pclk clock is optional, as not all
+systems may use one.
 Example:
                timer1: timer@ffc09000 {
@@ -23,3 +34,11 @@ Example:
                                clock-frequency = <200000000>;
                                reg = <0xffd00000 0x1000>;
                        };
+                timer3: timer@ffe00000 {
+                                compatible = "snps,dw-apb-timer-osc";
+                                interrupts = <0 170 4>;
+                                reg = <0xffe00000 0x1000>;
+                                clocks = <&timer_clk>, <&timer_pclk>;
+                                clock-names = "timer", "pclk";
+                        };
diff --git a/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt b/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt
new file mode 100644
index 000000000000..0e72183f52bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/serio/olpc,ap-sp.txt
@@ -0,0 +1,13 @@
+OLPC AP-SP serio interface
+Required properties:
+- compatible : "olpc,ap-sp"
+- reg : base address and length of SoC's WTM registers
+- interrupts : SP-AP interrupt
+Example:
+        ap-sp@d4290000 {
+                compatible = "olpc,ap-sp";
+                reg = <0xd4290000 0x1000>;
+                interrupts = <40>;
+        }
diff --git a/Documentation/devicetree/bindings/sound/adi,adau1701.txt b/Documentation/devicetree/bindings/sound/adi,adau1701.txt
new file mode 100644
index 000000000000..547a49b56a62
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/adi,adau1701.txt
@@ -0,0 +1,35 @@
+Analog Devices ADAU1701
+Required properties:
+ - compatible:          Should contain "adi,adau1701"
+ - reg:                 The i2c address. Value depends on the state of ADDR0
+                        and ADDR1, as wired in hardware.
+Optional properties:
+ - reset-gpio:          A GPIO spec to define which pin is connected to the
+                        chip's !RESET pin. If specified, the driver will
+                        assert a hardware reset at probe time.
+ - adi,pll-mode-gpios:  An array of two GPIO specs to describe the GPIOs
+                        the ADAU's PLL config pins are connected to.
+                        The state of the pins are set according to the
+                        configured clock divider on ASoC side before the
+                        firmware is loaded.
+ - adi,pin-config:      An array of 12 numerical values selecting one of the
+                        pin configurations as described in the datasheet,
+                        table 53. Note that the value of this property has
+                        to be prefixed with '/bits/ 8'.
+Examples:
+        i2c_bus {
+                adau1701@34 {
+                        compatible = "adi,adau1701";
+                        reg = <0x34>;
+                        reset-gpio = <&gpio 23 0>;
+                        adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
+                        adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
+                                                   0x4 0x4 0x4 0x4 0x4 0x4>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt
new file mode 100644
index 000000000000..f49450a87890
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt
@@ -0,0 +1,46 @@
+Freescale i.MX audio complex with WM8962 codec
+Required properties:
+- compatible : "fsl,imx-audio-wm8962"
+- model : The user-visible name of this sound complex
+- ssi-controller : The phandle of the i.MX SSI controller
+- audio-codec : The phandle of the WM8962 audio codec
+- audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names could be power
+  supplies, WM8962 pins, and the jacks on the board:
+  Power supplies:
+   * Mic Bias
+  Board connectors:
+   * Mic Jack
+   * Headphone Jack
+   * Ext Spk
+- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
+- mux-ext-port : The external port of the i.MX audio muxer
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+Example:
+sound {
+        compatible = "fsl,imx6q-sabresd-wm8962",
+                     "fsl,imx-audio-wm8962";
+        model = "wm8962-audio";
+        ssi-controller = <&ssi2>;
+        audio-codec = <&codec>;
+                audio-routing =
+                "Headphone Jack", "HPOUTL",
+                "Headphone Jack", "HPOUTR",
+                "Ext Spk", "SPKOUTL",
+                "Ext Spk", "SPKOUTR",
+                "MICBIAS", "AMIC",
+                "IN3R", "MICBIAS",
+                "DMIC", "MICBIAS",
+                "DMICDAT", "DMIC";
+        mux-int-port = <2>;
+        mux-ext-port = <3>;
+};
diff --git a/Documentation/devicetree/bindings/sound/mxs-saif.txt b/Documentation/devicetree/bindings/sound/mxs-saif.txt
index c37ba6143d9b..7ba07a118e37 100644
--- a/Documentation/devicetree/bindings/sound/mxs-saif.txt
+++ b/Documentation/devicetree/bindings/sound/mxs-saif.txt
@@ -3,8 +3,11 @@
 Required properties:
 - compatible: Should be "fsl,<chip>-saif"
 - reg: Should contain registers location and length
- interrupts: Should contain ERROR and DMA interrupts
+- interrupts: Should contain ERROR interrupt number
- fsl,saif-dma-channel: APBX DMA channel for the SAIF
+- dmas: DMA specifier, consisting of a phandle to DMA controller node
+  and SAIF DMA channel ID.
+  Refer to dma.txt and fsl-mxs-dma.txt for details.
+- dma-names: Must be "rx-tx".
 Optional properties:
 - fsl,saif-master: phandle to the master SAIF.  It's only required for
@@ -23,14 +26,16 @@ aliases {
 saif0: saif@80042000 {
        compatible = "fsl,imx28-saif";
        reg = <0x80042000 2000>;
-        interrupts = <59 80>;
+        interrupts = <59>;
-        fsl,saif-dma-channel = <4>;
+        dmas = <&dma_apbx 4>;
+        dma-names = "rx-tx";
 };
 saif1: saif@80046000 {
        compatible = "fsl,imx28-saif";
        reg = <0x80046000 2000>;
-        interrupts = <58 81>;
+        interrupts = <58>;
-        fsl,saif-dma-channel = <5>;
+        dmas = <&dma_apbx 5>;
+        dma-names = "rx-tx";
        fsl,saif-master = <&saif0>;
 };
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
new file mode 100644
index 000000000000..d130818700b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-rt5640.txt
@@ -0,0 +1,71 @@
+NVIDIA Tegra audio complex, with RT5640 CODEC
+Required properties:
+- compatible : "nvidia,tegra-audio-rt5640"
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Must include the following entries:
+  "pll_a" (The Tegra clock of that name),
+  "pll_a_out0" (The Tegra clock of that name),
+  "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the RT5640's pins, and the jacks on the board:
+  RT5640 pins:
+  * DMIC1
+  * DMIC2
+  * MICBIAS1
+  * IN1P
+  * IN1R
+  * IN2P
+  * IN2R
+  * HPOL
+  * HPOR
+  * LOUTL
+  * LOUTR
+  * MONOP
+  * MONON
+  * SPOLP
+  * SPOLN
+  * SPORP
+  * SPORN
+  Board connectors:
+  * Headphones
+  * Speakers
+- nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
+  connected to the CODEC.
+- nvidia,audio-codec : The phandle of the RT5640 audio codec. This binding
+  assumes that AIF1 on the CODEC is connected to Tegra.
+Optional properties:
+- nvidia,hp-det-gpios : The GPIO that detects headphones are plugged in
+Example:
+sound {
+        compatible = "nvidia,tegra-audio-rt5640-dalmore",
+                        "nvidia,tegra-audio-rt5640";
+        nvidia,model = "NVIDIA Tegra Dalmore";
+        nvidia,audio-routing =
+                "Headphones", "HPOR",
+                "Headphones", "HPOL",
+                "Speakers", "SPORP",
+                "Speakers", "SPORN",
+                "Speakers", "SPOLP",
+                "Speakers", "SPOLN";
+        nvidia,i2s-controller = <&tegra_i2s1>;
+        nvidia,audio-codec = <&rt5640>;
+        nvidia,hp-det-gpios = <&gpio 143 0>; /* GPIO PR7 */
+        clocks = <&tegra_car 216>, <&tegra_car 217>, <&tegra_car 120>;
+        clock-names = "pll_a", "pll_a_out0", "mclk";
+};
diff --git a/Documentation/devicetree/bindings/sound/rt5640.txt b/Documentation/devicetree/bindings/sound/rt5640.txt
new file mode 100644
index 000000000000..005bcb24d72d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rt5640.txt
@@ -0,0 +1,30 @@
+RT5640 audio CODEC
+This device supports I2C only.
+Required properties:
+- compatible : "realtek,rt5640".
+- reg : The I2C address of the device.
+- interrupts : The CODEC's interrupt output.
+Optional properties:
+- realtek,in1-differential
+- realtek,in2-differential
+  Boolean. Indicate MIC1/2 input are differential, rather than single-ended.
+- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin.
+Example:
+rt5640 {
+        compatible = "realtek,rt5640";
+        reg = <0x1c>;
+        interrupt-parent = <&gpio>;
+        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+        realtek,ldo1-en-gpios =
+                <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+};
diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046da2e5..025e66b85a43 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,16 @@ Required SoC Specific Properties:
 - dmas: list of DMA controller phandle and DMA request line ordered pairs.
 - dma-names: identifier string for each DMA request line in the dmas property.
  These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: Handle to iis clock and RCLK source clk.
+- clock-names:
+  i2s0 uses some base clks from CMU and some are from audio subsystem internal
+  clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
+  "i2s_opclk1" as shown in the example below.
+  i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
+  be "iis" and "i2s_opclk0".
+  "iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
+  clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
+  doesn't have any such mux.
 Optional SoC Specific Properties:
@@ -20,44 +30,26 @@ Optional SoC Specific Properties:
  then this flag is enabled.
 - samsung,idma-addr: Internal DMA register base address of the audio
  sub system(used in secondary sound source).
+- pinctrl-0: Should specify pin control groups used for this controller.
-Required Board Specific Properties:
+- pinctrl-names: Should contain only one value - "default".
- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
-  interface lines. The format of the gpio specifier depends on the gpio
-  controller.
-  The syntax of samsung gpio specifier is
-        <[phandle of the gpio controller node]
-         [pin number within the gpio controller]
-         [mux function]
-         [flags and pull up/down]
-         [drive strength]>
 Example:
- SoC Specific Portion:
+i2s0: i2s@03830000 {
-i2s@03830000 {
        compatible = "samsung,i2s-v5";
        reg = <0x03830000 0x100>;
        dmas = <&pdma0 10
                &pdma0 9
                &pdma0 8>;
        dma-names = "tx", "rx", "tx-sec";
+        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                <&clock_audss EXYNOS_I2S_BUS>,
+                <&clock_audss EXYNOS_SCLK_I2S>;
+        clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
        samsung,supports-6ch;
        samsung,supports-rstclr;
        samsung,supports-secdai;
        samsung,idma-addr = <0x03000000>;
-};
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2s0_bus>;
- Board Specific Portion:
-i2s@03830000 {
-        gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
-                <&gpz 1 2 0 0>, /* I2S_0_CDCLK */
-                <&gpz 2 2 0 0>, /* I2S_0_LRCK */
-                <&gpz 3 2 0 0>, /* I2S_0_SDI */
-                <&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
-                <&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
-                <&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
 };
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
index 9cc44449508d..955df60a118c 100644
--- a/Documentation/devicetree/bindings/sound/sgtl5000.txt
+++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt
@@ -5,9 +5,12 @@ Required properties:
 - reg : the I2C address of the device
+- clocks : the clock provider of SYS_MCLK
 Example:
 codec: sgtl5000@0a {
        compatible = "fsl,sgtl5000";
        reg = <0x0a>;
+        clocks = <&clks 150>;
 };
diff --git a/Documentation/devicetree/bindings/sound/spdif-receiver.txt b/Documentation/devicetree/bindings/sound/spdif-receiver.txt
new file mode 100644
index 000000000000..80f807bf8a1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/spdif-receiver.txt
@@ -0,0 +1,10 @@
+Device-Tree bindings for dummy spdif receiver
+Required properties:
+        - compatible: should be "linux,spdif-dir".
+Example node:
+        codec: spdif-receiver {
+                compatible = "linux,spdif-dir";
+        };
diff --git a/Documentation/devicetree/bindings/sound/spdif-transmitter.txt b/Documentation/devicetree/bindings/sound/spdif-transmitter.txt
new file mode 100644
index 000000000000..55a85841dd85
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/spdif-transmitter.txt
@@ -0,0 +1,10 @@
+Device-Tree bindings for dummy spdif transmitter
+Required properties:
+        - compatible: should be "linux,spdif-dit".
+Example node:
+        codec: spdif-transmitter {
+                compatible = "linux,spdif-dit";
+        };
diff --git a/Documentation/devicetree/bindings/sound/ssm2518.txt b/Documentation/devicetree/bindings/sound/ssm2518.txt
new file mode 100644
index 000000000000..59381a778c79
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ssm2518.txt
@@ -0,0 +1,20 @@
+SSM2518 audio amplifier
+This device supports I2C only.
+Required properties:
+  - compatible : Must be "adi,ssm2518"
+  - reg : the I2C address of the device. This will either be 0x34 (ADDR pin low)
+        or 0x35 (ADDR pin high)
+Optional properties:
+  - gpios : GPIO connected to the nSD pin. If the property is not present it is
+                assumed that the nSD pin is hardwired to always on.
+Example:
+        ssm2518: ssm2518@34 {
+                compatible = "adi,ssm2518";
+                reg = <0x34>;
+                gpios = <&gpio 5 0>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/ti,tas5086.txt b/Documentation/devicetree/bindings/sound/ti,tas5086.txt
index 8ea4f5b4818d..d2866a0d6a26 100644
--- a/Documentation/devicetree/bindings/sound/ti,tas5086.txt
+++ b/Documentation/devicetree/bindings/sound/ti,tas5086.txt
@@ -20,6 +20,17 @@ Optional properties:
                        When not specified, the hardware default of 1300ms
                        is retained.
+ - ti,mid-z-channel-X:  Boolean properties, X being a number from 1 to 6.
+                        If given, channel X will start with the Mid-Z start
+                        sequence, otherwise the default Low-Z scheme is used.
+                        The correct configuration depends on how the power
+                        stages connected to the PWM output pins work. Not all
+                        power stages are compatible to Mid-Z - please refer
+                        to the datasheets for more details.
+                        Most systems should not set any of these properties.
 Examples:
        i2c_bus {
diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt
index dceb3b1c2bb7..7f82b59ec8f9 100644
--- a/Documentation/devicetree/bindings/sound/wm8962.txt
+++ b/Documentation/devicetree/bindings/sound/wm8962.txt
@@ -8,9 +8,32 @@ Required properties:
  - reg : the I2C address of the device.
+Optional properties:
+  - spk-mono: This is a boolean property. If present, the SPK_MONO bit
+    of R51 (Class D Control 2) gets set, indicating that the speaker is
+    in mono mode.
+  - mic-cfg : Default register value for R48 (Additional Control 4).
+    If absent, the default should be the register default.
+  - gpio-cfg : A list of GPIO configuration register values. The list must
+    be 6 entries long. If absent, no configuration of these registers is
+    performed. And note that only the value within [0x0, 0xffff] is valid.
+    Any other value is regarded as setting the GPIO register by its reset
+    value 0x0.
 Example:
 codec: wm8962@1a {
        compatible = "wlf,wm8962";
        reg = <0x1a>;
+        gpio-cfg = <
+                0x0000 /* 0:Default */
+                0x0000 /* 1:Default */
+                0x0013 /* 2:FN_DMICCLK */
+                0x0000 /* 3:Default */
+                0x8014 /* 4:FN_DMICCDAT */
+                0x0000 /* 5:Default */
+        >;
 };
diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
index 8bf89c643640..f11f295c8450 100644
--- a/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
+++ b/Documentation/devicetree/bindings/spi/brcm,bcm2835-spi.txt
@@ -2,7 +2,7 @@ Broadcom BCM2835 SPI0 controller
 The BCM2835 contains two forms of SPI master controller, one known simply as
 SPI0, and the other known as the "Universal SPI Master"; part of the
-auxilliary block. This binding applies to the SPI0 controller.
+auxiliary block. This binding applies to the SPI0 controller.
 Required properties:
 - compatible: Should be "brcm,bcm2835-spi".
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt
index 938809c6829b..4c85c4c69584 100644
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
@@ -10,7 +10,18 @@ Required properties:
                          input. The default is D0 as input and
                          D1 as output.
-Example:
+Optional properties:
+- dmas: List of DMA specifiers with the controller specific format
+        as described in the generic DMA client binding. A tx and rx
+        specifier is required for each chip select.
+- dma-names: List of DMA request names. These strings correspond
+        1:1 with the DMA specifiers listed in dmas. The string naming
+        is to be "rxN" and "txN" for RX and TX requests,
+        respectively, where N equals the chip select number.
+Examples:
+[hwmod populated DMA resources]
 mcspi1: mcspi@1 {
    #address-cells = <1>;
@@ -20,3 +31,17 @@ mcspi1: mcspi@1 {
    ti,spi-num-cs = <4>;
 };
+[generic DMA request binding]
+mcspi1: mcspi@1 {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    compatible = "ti,omap4-mcspi";
+    ti,hwmods = "mcspi1";
+    ti,spi-num-cs = <2>;
+    dmas = <&edma 42
+            &edma 43
+            &edma 44
+            &edma 45>;
+    dma-names = "tx0", "rx0", "tx1", "rx1";
+};
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
new file mode 100644
index 000000000000..ed9377811ee2
--- /dev/null
+++ b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
@@ -0,0 +1,99 @@
+Device-Tree bindings for LVDS Display Bridge (ldb)
+LVDS Display Bridge
+===================
+The LVDS Display Bridge device tree node contains up to two lvds-channel
+nodes describing each of the two LVDS encoder channels of the bridge.
+Required properties:
+ - #address-cells : should be <1>
+ - #size-cells : should be <0>
+ - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
+                Both LDB versions are similar, but i.MX6 has an additional
+                multiplexer in the front to select any of the four IPU display
+                interfaces as input for each LVDS channel.
+ - gpr : should be <&gpr> on i.MX53 and i.MX6q.
+         The phandle points to the iomuxc-gpr region containing the LVDS
+         control register.
+- clocks, clock-names : phandles to the LDB divider and selector clocks and to
+                        the display interface selector clocks, as described in
+                        Documentation/devicetree/bindings/clock/clock-bindings.txt
+        The following clocks are expected on i.MX53:
+                "di0_pll" - LDB LVDS channel 0 mux
+                "di1_pll" - LDB LVDS channel 1 mux
+                "di0" - LDB LVDS channel 0 gate
+                "di1" - LDB LVDS channel 1 gate
+                "di0_sel" - IPU1 DI0 mux
+                "di1_sel" - IPU1 DI1 mux
+        On i.MX6q the following additional clocks are needed:
+                "di2_sel" - IPU2 DI0 mux
+                "di3_sel" - IPU2 DI1 mux
+        The needed clock numbers for each are documented in
+        Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
+        Documentation/devicetree/bindings/clock/imx6q-clock.txt.
+Optional properties:
+ - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
+ - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
+               not used on i.MX6q
+ - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
+   be configured - one input will be distributed on both outputs in dual
+   channel mode
+LVDS Channel
+============
+Each LVDS Channel has to contain a display-timings node that describes the
+video timings for the connected LVDS display. For detailed information, also
+have a look at Documentation/devicetree/bindings/video/display-timing.txt.
+Required properties:
+ - reg : should be <0> or <1>
+ - crtcs : a list of phandles with index pointing to the IPU display interfaces
+           that can be used as video source for this channel.
+ - fsl,data-mapping : should be "spwg" or "jeida"
+                      This describes how the color bits are laid out in the
+                      serialized LVDS signal.
+ - fsl,data-width : should be <18> or <24>
+example:
+gpr: iomuxc-gpr@53fa8000 {
+        /* ... */
+};
+ldb: ldb@53fa8008 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "fsl,imx53-ldb";
+        gpr = <&gpr>;
+        clocks = <&clks 122>, <&clks 120>,
+                 <&clks 115>, <&clks 116>,
+                 <&clks 123>, <&clks 85>;
+        clock-names = "di0_pll", "di1_pll",
+                      "di0_sel", "di1_sel",
+                      "di0", "di1";
+        lvds-channel@0 {
+                reg = <0>;
+                crtcs = <&ipu 0>;
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <24>;
+                display-timings {
+                        /* ... */
+                };
+        };
+        lvds-channel@1 {
+                reg = <1>;
+                crtcs = <&ipu 1>;
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <24>;
+                display-timings {
+                        /* ... */
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
index cb47bfbcaeea..b5a86d20ee36 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
@@ -44,7 +44,7 @@ Example 1: In this example, the system uses only the first global timer
        };
 Example 2: In this example, the MCT global and local timer interrupts are
-           connected to two seperate interrupt controllers. Hence, an
+           connected to two separate interrupt controllers. Hence, an
           interrupt-map is created to map the interrupts to the respective
           interrupt controllers.
diff --git a/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
new file mode 100644
index 000000000000..9499bc8ee9e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/stericsson-u300-apptimer.txt
@@ -0,0 +1,18 @@
+ST-Ericsson U300 apptimer
+Required properties:
+- compatible : should be "stericsson,u300-apptimer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupts; one for each subtimer. These
+  are, in order: OS (operating system), DD (device driver) both
+  adopted for EPOC/Symbian with two specific IRQs for these tasks,
+  then GP1 and GP2, which are general-purpose timers.
+Example:
+timer {
+        compatible = "stericsson,u300-apptimer";
+        reg = <0xc0014000 0x1000>;
+        interrupts = <24 25 26 27>;
+};
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
index b462d0c54823..c662eb36be29 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-imx-uart.txt
@@ -8,6 +8,8 @@ Required properties:
 Optional properties:
 - fsl,uart-has-rtscts : Indicate the uart has rts and cts
 - fsl,irda-mode : Indicate the uart supports irda mode
+- fsl,dte-mode : Indicate the uart works in DTE mode. The uart works
+                  is DCE mode by default.
 Example:
@@ -16,4 +18,5 @@ serial@73fbc000 {
        reg = <0x73fbc000 0x4000>;
        interrupts = <31>;
        fsl,uart-has-rtscts;
+        fsl,dte-mode;
 };
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
new file mode 100644
index 000000000000..6fd1dd1638dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-lpuart.txt
@@ -0,0 +1,14 @@
+* Freescale low power universal asynchronous receiver/transmitter (lpuart)
+Required properties:
+- compatible : Should be "fsl,<soc>-lpuart"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain uart interrupt
+Example:
+uart0: serial@40027000 {
+               compatible = "fsl,vf610-lpuart";
+               reg = <0x40027000 0x1000>;
+               interrupts = <0 61 0x00>;
+       };
diff --git a/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
new file mode 100644
index 000000000000..20468b2a7516
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt
@@ -0,0 +1,16 @@
+* Universal Flash Storage (UFS) Host Controller
+UFSHC nodes are defined to describe on-chip UFS host controllers.
+Each UFS controller instance should have its own node.
+Required properties:
+- compatible        : compatible list, contains "jedec,ufs-1.1"
+- interrupts        : <interrupt mapping for UFS host controller IRQ>
+- reg               : <registers mapping>
+Example:
+        ufshc@0xfc598000 {
+                compatible = "jedec,ufs-1.1";
+                reg = <0xfc598000 0x800>;
+                interrupts = <0 28 0>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
index ea840f7f9258..dc9dc8c87f15 100644
--- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt
+++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
@@ -12,7 +12,7 @@ AM33XX MUSB GLUE
   represents PERIPHERAL.
 - port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
   represents PERIPHERAL.
- - power : Should be "250". This signifies the controller can supply upto
+ - power : Should be "250". This signifies the controller can supply up to
   500mA when operating in host mode.
 Example:
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 60bd2150a3e6..55f51af08bc7 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -47,3 +47,85 @@ usb1: gadget@fffa4000 {
        interrupts = <10 4>;
        atmel,vbus-gpio = <&pioC 5 0>;
 };
+Atmel High-Speed USB device controller
+Required properties:
+ - compatible: Should be "atmel,at91sam9rl-udc"
+ - reg: Address and length of the register set for the device
+ - interrupts: Should contain usba interrupt
+ - ep childnode: To specify the number of endpoints and their properties.
+Optional properties:
+ - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
+Required child node properties:
+ - name: Name of the endpoint.
+ - reg: Num of the endpoint.
+ - atmel,fifo-size: Size of the fifo.
+ - atmel,nb-banks: Number of banks.
+ - atmel,can-dma: Boolean to specify if the endpoint support DMA.
+ - atmel,can-isoc: Boolean to specify if the endpoint support ISOC.
+usb2: gadget@fff78000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        compatible = "atmel,at91sam9rl-udc";
+        reg = <0x00600000 0x80000
+               0xfff78000 0x400>;
+        interrupts = <27 4 0>;
+        atmel,vbus-gpio = <&pioB 19 0>;
+        ep0 {
+                reg = <0>;
+                atmel,fifo-size = <64>;
+                atmel,nb-banks = <1>;
+        };
+        ep1 {
+                reg = <1>;
+                atmel,fifo-size = <1024>;
+                atmel,nb-banks = <2>;
+                atmel,can-dma;
+                atmel,can-isoc;
+        };
+        ep2 {
+                reg = <2>;
+                atmel,fifo-size = <1024>;
+                atmel,nb-banks = <2>;
+                atmel,can-dma;
+                atmel,can-isoc;
+        };
+        ep3 {
+                reg = <3>;
+                atmel,fifo-size = <1024>;
+                atmel,nb-banks = <3>;
+                atmel,can-dma;
+        };
+        ep4 {
+                reg = <4>;
+                atmel,fifo-size = <1024>;
+                atmel,nb-banks = <3>;
+                atmel,can-dma;
+        };
+        ep5 {
+                reg = <5>;
+                atmel,fifo-size = <1024>;
+                atmel,nb-banks = <3>;
+                atmel,can-dma;
+                atmel,can-isoc;
+        };
+        ep6 {
+                reg = <6>;
+                atmel,fifo-size = <1024>;
+                atmel,nb-banks = <3>;
+                atmel,can-dma;
+                atmel,can-isoc;
+        };
+};
diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
index 1c04a4c9515f..b4b5b7906c88 100644
--- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
@@ -5,6 +5,12 @@ Required properties:
 - reg: Should contain registers location and length
 - interrupts: Should contain controller interrupt
+Recommended properies:
+- phy_type: the type of the phy connected to the core. Should be one
+  of "utmi", "utmi_wide", "ulpi", "serial" or "hsic". Without this
+  property the PORTSC register won't be touched
+- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
 Optional properties:
 - fsl,usbphy: phandler of usb phy that connects to the only one port
 - fsl,usbmisc: phandler of non-core register device, with one argument
diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt
index b3abde736017..d967ba16de60 100644
--- a/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt
@@ -48,3 +48,37 @@ Example:
                clocks = <&clock 285>;
                clock-names = "usbhost";
        };
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwusb3" for USB 3.0 DWC3
+               controller.
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+                                 with 'reg' property.
+ - ranges: allows valid 1:1 translation between child's address space and
+           parent's address space
+ - clocks: Clock IDs array as required by the controller.
+ - clock-names: names of clocks correseponding to IDs in the clock property
+Sub-nodes:
+The dwc3 core should be added as subnode to Exynos dwc3 glue.
+- dwc3 :
+   The binding details of dwc3 can be found in:
+   Documentation/devicetree/bindings/usb/dwc3.txt
+Example:
+        usb@12000000 {
+                compatible = "samsung,exynos5250-dwusb3";
+                clocks = <&clock 286>;
+                clock-names = "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                dwc3 {
+                        compatible = "synopsys,dwc3";
+                        reg = <0x12000000 0x10000>;
+                        interrupts = <0 72 0>;
+                        usb-phy = <&usb2_phy &usb3_phy>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
index 34c952883276..df0933043a5b 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt
@@ -6,27 +6,10 @@ Practice : Universal Serial Bus" with the following modifications
 and additions :
 Required properties :
- - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
+ - compatible : Should be "nvidia,tegra20-ehci".
-   used in host mode.
+ - nvidia,phy : phandle of the PHY that the controller is connected to.
- - phy_type : Should be one of "ulpi" or "utmi".
+ - clocks : Contains a single entry which defines the USB controller's clock.
- - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
-   activated for the bus to be powered.
- - nvidia,phy : phandle of the PHY instance, the controller is connected to.
-Required properties for phy_type == ulpi:
-  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
 Optional properties:
-  - dr_mode : dual role mode. Indicates the working mode for
+ - nvidia,needs-double-reset : boolean is to be set for some of the Tegra20
-   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
+   USB ports, which need reset twice due to hardware issues.
-   or "otg".  Default to "host" if not defined for backward compatibility.
-      host means this is a host controller
-      peripheral means it is device controller
-      otg means it can operate as either ("on the go")
-  - nvidia,has-legacy-mode : boolean indicates whether this controller can
-    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
-    registers are accessed through the APB_MISC base address instead of
-    the USB controller. Since this is a legacy issue it probably does not
-    warrant a compatible string of its own.
-  - nvidia,needs-double-reset : boolean is to be set for some of the Tegra2
-    USB ports, which need reset twice due to hardware issues.
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
index 6bdaba2f0aa1..c4c9e9e664aa 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -4,14 +4,49 @@ The device node for Tegra SOC USB PHY:
 Required properties :
 - compatible : Should be "nvidia,tegra20-usb-phy".
- - reg : Address and length of the register set for the USB PHY interface.
+ - reg : Defines the following set of registers, in the order listed:
- - phy_type : Should be one of "ulpi" or "utmi".
+   - The PHY's own register set.
+     Always present.
+   - The register set of the PHY containing the UTMI pad control registers.
+     Present if-and-only-if phy_type == utmi.
+ - phy_type : Should be one of "utmi", "ulpi" or "hsic".
+ - clocks : Defines the clocks listed in the clock-names property.
+ - clock-names : The following clock names must be present:
+   - reg: The clock needed to access the PHY's own registers. This is the
+     associated EHCI controller's clock. Always present.
+   - pll_u: PLL_U. Always present.
+   - timer: The timeout clock (clk_m). Present if phy_type == utmi.
+   - utmi-pads: The clock needed to access the UTMI pad control registers.
+     Present if phy_type == utmi.
+   - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
+     Present if phy_type == ulpi, and ULPI link mode is in use.
 Required properties for phy_type == ulpi:
  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
+Required PHY timing params for utmi phy:
+  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
+    start of sync launches RxActive
+  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
+  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
+    before declare IDLE.
+  - nvidia,term-range-adj : Range adjusment on terminations
+  - nvidia,xcvr-setup : HS driver output control
+  - nvidia,xcvr-lsfslew : LS falling slew rate control.
+  - nvidia,xcvr-lsrslew :  LS rising slew rate control.
 Optional properties:
  - nvidia,has-legacy-mode : boolean indicates whether this controller can
    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
    registers are accessed through the APB_MISC base address instead of
-    the USB controller.
-\ No newline at end of file
+    the USB controller.
+  - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power
+    optimizations for the devices that are always connected. e.g. modem.
+  - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be
+    "host", "peripheral", or "otg". Defaults to "host" if not defined.
+      host means this is a host controller
+      peripheral means it is device controller
+      otg means it can operate as either ("on the go")
+Required properties for dr_mode == otg:
+  - vbus-supply: regulator for VBUS
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index d4769f343d6c..57e71f6817d0 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -16,7 +16,7 @@ OMAP MUSB GLUE
   specifying ULPI and UTMI respectively.
 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
   represents PERIPHERAL.
- - power : Should be "50". This signifies the controller can supply upto
+ - power : Should be "50". This signifies the controller can supply up to
   100mA when operating in host mode.
 - usb-phy : the phandle for the PHY device
diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt
index 6813a715fc7d..8c5be48b43c8 100644
--- a/Documentation/devicetree/bindings/usb/usb3503.txt
+++ b/Documentation/devicetree/bindings/usb/usb3503.txt
@@ -4,6 +4,10 @@ Required properties:
 - compatible: Should be "smsc,usb3503".
 - reg: Specifies the i2c slave address, it should be 0x08.
 - connect-gpios: Should specify GPIO for connect.
+- disabled-ports: Should specify the ports unused.
+        '1' or '2' or '3' are availe for this property to describe the port
+        number. 1~3 property values are possible to be desribed.
+        Do not describe this property if all ports have to be enabled.
 - intn-gpios: Should specify GPIO for interrupt.
 - reset-gpios: Should specify GPIO for reset.
 - initial-mode: Should specify initial mode.
@@ -14,6 +18,7 @@ Examples:
                compatible = "smsc,usb3503";
                reg = <0x08>;
                connect-gpios = <&gpx3 0 1>;
+                disabled-ports = <2 3>;
                intn-gpios = <&gpx3 4 1>;
                reset-gpios = <&gpx3 5 1>;
                initial-mode = <1>;
diff --git a/Documentation/devicetree/bindings/usb/ux500-usb.txt b/Documentation/devicetree/bindings/usb/ux500-usb.txt
new file mode 100644
index 000000000000..330d6ec15401
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ux500-usb.txt
@@ -0,0 +1,50 @@
+Ux500 MUSB
+Required properties:
+ - compatible : Should be "stericsson,db8500-musb"
+ - reg        : Offset and length of registers
+ - interrupts : Interrupt; mode, number and trigger
+ - dr_mode    : Dual-role; either host mode "host", peripheral mode "peripheral"
+                or both "otg"
+Optional properties:
+ - dmas       : A list of dma channels;
+                dma-controller, event-line, fixed-channel, flags
+ - dma-names  : An ordered list of channel names affiliated to the above
+Example:
+usb_per5@a03e0000 {
+        compatible = "stericsson,db8500-musb", "mentor,musb";
+        reg = <0xa03e0000 0x10000>;
+        interrupts = <0 23 0x4>;
+        interrupt-names = "mc";
+        dr_mode = "otg";
+        dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+               <&dma 38 0 0x0>, /* Logical - MemToDev */
+               <&dma 37 0 0x2>, /* Logical - DevToMem */
+               <&dma 37 0 0x0>, /* Logical - MemToDev */
+               <&dma 36 0 0x2>, /* Logical - DevToMem */
+               <&dma 36 0 0x0>, /* Logical - MemToDev */
+               <&dma 19 0 0x2>, /* Logical - DevToMem */
+               <&dma 19 0 0x0>, /* Logical - MemToDev */
+               <&dma 18 0 0x2>, /* Logical - DevToMem */
+               <&dma 18 0 0x0>, /* Logical - MemToDev */
+               <&dma 17 0 0x2>, /* Logical - DevToMem */
+               <&dma 17 0 0x0>, /* Logical - MemToDev */
+               <&dma 16 0 0x2>, /* Logical - DevToMem */
+               <&dma 16 0 0x0>, /* Logical - MemToDev */
+               <&dma 39 0 0x2>, /* Logical - DevToMem */
+               <&dma 39 0 0x0>; /* Logical - MemToDev */
+        dma-names = "iep_1_9",  "oep_1_9",
+                    "iep_2_10", "oep_2_10",
+                    "iep_3_11", "oep_3_11",
+                    "iep_4_12", "oep_4_12",
+                    "iep_5_13", "oep_5_13",
+                    "iep_6_14", "oep_6_14",
+                    "iep_7_15", "oep_7_15",
+                    "iep_8",    "oep_8";
+};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 6931c4348d24..948f61561ffa 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -31,6 +31,7 @@ idt	Integrated Device Technologies, Inc.
 img     Imagination Technologies Ltd.
 intercontrol    Inter Control Group
 linux   Linux-specific binding
+lsi     LSI Corp. (LSI Logic)
 marvell Marvell Technology Group Ltd.
 maxim   Maxim Integrated Products
 mosaixtech      Mosaix Technologies, Inc.
@@ -57,8 +58,10 @@ snps 	Synopsys, Inc.
 st      STMicroelectronics
 ste     ST-Ericsson
 stericsson      ST-Ericsson
+toumaz  Toumaz
 ti      Texas Instruments
 toshiba Toshiba Corporation
+v3      V3 Semiconductor
 via     VIA Technologies, Inc.
 wlf     Wolfson Microelectronics
 wm      Wondermedia Technologies, Inc.
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index c60da67a5d76..84f10c16cb38 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -21,6 +21,10 @@ Required properties for dp-controller:
                of memory mapped region.
        -interrupts:
                interrupt combiner values.
+        -clocks:
+                from common clock binding: handle to dp clock.
+        -clock-names:
+                from common clock binding: Shall be "dp".
        -interrupt-parent:
                phandle to Interrupt combiner node.
        -samsung,color-space:
@@ -61,6 +65,8 @@ SOC specific portion:
                reg = <0x145b0000 0x10000>;
                interrupts = <10 3>;
                interrupt-parent = <&combiner>;
+                clocks = <&clock 342>;
+                clock-names = "dp";
                dptx-phy {
                        reg = <0x10040720>;
diff --git a/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
new file mode 100644
index 000000000000..8ffb88e39e76
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/stericsson-coh901327.txt
@@ -0,0 +1,19 @@
+ST-Ericsson COH 901 327 Watchdog timer
+Required properties:
+- compatible: must be "stericsson,coh901327".
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: the interrupt used for the watchdog timeout warning.
+Optional properties:
+- timeout-sec: contains the watchdog timeout in seconds.
+Example:
+watchdog: watchdog@c0012000 {
+        compatible = "stericsson,coh901327";
+        reg = <0xc0012000 0x1000>;
+        interrupts = <3>;
+        timeout-sec = <60>;
+};
diff --git a/Documentation/devicetree/usage-model.txt b/Documentation/devicetree/usage-model.txt
index 0efedaad5165..2b6b3d3f0388 100644
--- a/Documentation/devicetree/usage-model.txt
+++ b/Documentation/devicetree/usage-model.txt
@@ -106,17 +106,18 @@ In the majority of cases, the machine identity is irrelevant, and the
 kernel will instead select setup code based on the machine's core
 CPU or SoC.  On ARM for example, setup_arch() in
 arch/arm/kernel/setup.c will call setup_machine_fdt() in
-arch/arm/kernel/devicetree.c which searches through the machine_desc
+arch/arm/kernel/devtree.c which searches through the machine_desc
 table and selects the machine_desc which best matches the device tree
 data.  It determines the best match by looking at the 'compatible'
 property in the root device tree node, and comparing it with the
-dt_compat list in struct machine_desc.
+dt_compat list in struct machine_desc (which is defined in
+arch/arm/include/asm/mach/arch.h if you're curious).
 The 'compatible' property contains a sorted list of strings starting
 with the exact name of the machine, followed by an optional list of
 boards it is compatible with sorted from most compatible to least.  For
 example, the root compatible properties for the TI BeagleBoard and its
-successor, the BeagleBoard xM board might look like:
+successor, the BeagleBoard xM board might look like, respectively:
        compatible = "ti,omap3-beagleboard", "ti,omap3450", "ti,omap3";
        compatible = "ti,omap3-beagleboard-xm", "ti,omap3450", "ti,omap3";
@@ -161,7 +162,7 @@ cases.
 Instead, the compatible list allows a generic machine_desc to provide
 support for a wide common set of boards by specifying "less
-compatible" value in the dt_compat list.  In the example above,
+compatible" values in the dt_compat list.  In the example above,
 generic board support can claim compatibility with "ti,omap3" or
 "ti,omap3450".  If a bug was discovered on the original beagleboard
 that required special workaround code during early boot, then a new
@@ -377,7 +378,7 @@ platform_devices as more platform_devices is a common pattern, and the
 device tree support code reflects that and makes the above example
 simpler.  The second argument to of_platform_populate() is an
 of_device_id table, and any node that matches an entry in that table
-will also get its child nodes registered.  In the tegra case, the code
+will also get its child nodes registered.  In the Tegra case, the code
 can look something like this:
 static void __init harmony_init_machine(void)