diff options
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/imx-pwm.txt | 17 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 |
3 files changed, 19 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt new file mode 100644 index 000000000000..8522bfbccfd7 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/imx-pwm.txt | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | Freescale i.MX PWM controller | ||
| 2 | |||
| 3 | Required properties: | ||
| 4 | - compatible: should be "fsl,<soc>-pwm" | ||
| 5 | - reg: physical base address and length of the controller's registers | ||
| 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | ||
| 7 | of the PWM to use and the second cell is the period in nanoseconds. | ||
| 8 | - interrupts: The interrupt for the pwm controller | ||
| 9 | |||
| 10 | Example: | ||
| 11 | |||
| 12 | pwm1: pwm@53fb4000 { | ||
| 13 | #pwm-cells = <2>; | ||
| 14 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; | ||
| 15 | reg = <0x53fb4000 0x4000>; | ||
| 16 | interrupts = <61>; | ||
| 17 | }; | ||
diff --git a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt index 11963e4d6bc4..9e3f8f1d46a2 100644 --- a/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/mxs-pwm.txt | |||
| @@ -4,7 +4,7 @@ Required properties: | |||
| 4 | - compatible: should be "fsl,imx23-pwm" | 4 | - compatible: should be "fsl,imx23-pwm" |
| 5 | - reg: physical base address and length of the controller's registers | 5 | - reg: physical base address and length of the controller's registers |
| 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index | 6 | - #pwm-cells: should be 2. The first cell specifies the per-chip index |
| 7 | of the PWM to use and the second cell is the duty cycle in nanoseconds. | 7 | of the PWM to use and the second cell is the period in nanoseconds. |
| 8 | - fsl,pwm-number: the number of PWM devices | 8 | - fsl,pwm-number: the number of PWM devices |
| 9 | 9 | ||
| 10 | Example: | 10 | Example: |
diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index bbbeedb4ec05..01438ecd6628 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | |||
| @@ -7,7 +7,7 @@ Required properties: | |||
| 7 | - reg: physical base address and length of the controller's registers | 7 | - reg: physical base address and length of the controller's registers |
| 8 | - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The | 8 | - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The |
| 9 | first cell specifies the per-chip index of the PWM to use and the second | 9 | first cell specifies the per-chip index of the PWM to use and the second |
| 10 | cell is the duty cycle in nanoseconds. | 10 | cell is the period in nanoseconds. |
| 11 | 11 | ||
| 12 | Example: | 12 | Example: |
| 13 | 13 | ||
