61 files changed, 1431 insertions, 123 deletions

diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 832fe8cc24d7..adc61b095bd1 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -14,14 +14,21 @@ Required properties:
                                 for exynos4412/5250 controllers.
                         Must be "samsung,exynos-adc-v2" for
                                 future controllers.
+                        Must be "samsung,exynos3250-adc" for
+                                controllers compatible with ADC of Exynos3250.
 - reg:                  Contains ADC register address range (base address and
                         length) and the address of the phy enable register.
 - interrupts:           Contains the interrupt information for the timer. The
                         format is being dependent on which interrupt controller
                         the Samsung device uses.
 - #io-channel-cells = <1>; As ADC has multiple outputs
-- clocks                From common clock binding: handle to adc clock.
-- clock-names           From common clock binding: Shall be "adc".
+- clocks                From common clock bindings: handles to clocks specified
+                        in "clock-names" property, in the same order.
+- clock-names           From common clock bindings: list of clock input names
+                        used by ADC block:
+                        - "adc" : ADC bus clock
+                        - "sclk" : ADC special clock (only for Exynos3250 and
+                                   compatible ADC block)
 - vdd-supply            VDD input supply.
 
 Note: child nodes can be added for auto probing from device tree.
@@ -41,6 +48,20 @@ adc: adc@12D10000 {
         vdd-supply = <&buck5_reg>;
 };
 
+Example: adding device info in dtsi file for Exynos3250 with additional sclk
+
+adc: adc@126C0000 {
+        compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
+        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+        interrupts = <0 137 0>;
+        #io-channel-cells = <1>;
+        io-channel-ranges;
+
+        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+        clock-names = "adc", "sclk";
+
+        vdd-supply = <&buck5_reg>;
+};
 
 Example: Adding child nodes in dts file
 
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 2a4ab046a8a1..f9865e77e0b0 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -12,8 +12,38 @@ Properties:
 
  - reg : offset and length of the register set.
 
+ - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
+                The single specifier cell is used as index to list of clocks
+                provided by PMU, which is currently:
+                        0 : SoC clock output (CLKOUT pin)
+
+ - clock-names : list of clock names for particular CLKOUT mux inputs in
+                following format:
+                        "clkoutN", where N is a decimal number corresponding to
+                        CLKOUT mux control bits value for given input, e.g.
+                                "clkout0", "clkout7", "clkout15".
+
+ - clocks : list of phandles and specifiers to all input clocks listed in
+                clock-names property.
+
 Example :
 pmu_system_controller: system-controller@10040000 {
         compatible = "samsung,exynos5250-pmu", "syscon";
         reg = <0x10040000 0x5000>;
+        #clock-cells = <1>;
+        clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
+                        "clkout4", "clkout8", "clkout9";
+        clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
+                <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
+                <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
+                <&clock CLK_XUSBXTI>;
+};
+
+Example of clock consumer :
+
+usb3503: usb3503@08 {
+        /* ... */
+        clock-names = "refclk";
+        clocks = <&pmu_system_controller 0>;
+        /* ... */
 };
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c96d8dcf98fd..4ab09f2202d4 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -3,28 +3,43 @@
 SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 
+It is possible, but not required, to represent each port as a sub-node.
+It allows to enable each port independently when dealing with multiple
+PHYs.
+
 Required properties:
 - compatible        : compatible string, one of:
   - "allwinner,sun4i-a10-ahci"
-  - "fsl,imx53-ahci"
-  - "fsl,imx6q-ahci"
   - "hisilicon,hisi-ahci"
   - "ibm,476gtr-ahci"
   - "marvell,armada-380-ahci"
   - "snps,dwc-ahci"
   - "snps,exynos5440-ahci"
   - "snps,spear-ahci"
+  - "generic-ahci"
 - interrupts        : <interrupt mapping for SATA IRQ>
 - reg               : <registers mapping>
 
+Please note that when using "generic-ahci" you must also specify a SoC specific
+compatible:
+        compatible = "manufacturer,soc-model-ahci", "generic-ahci";
+
 Optional properties:
 - dma-coherent      : Present if dma operations are coherent
 - clocks            : a list of phandle + clock specifier pairs
 - target-supply     : regulator for SATA target power
+- phys              : reference to the SATA PHY node
+- phy-names         : must be "sata-phy"
+
+Required properties when using sub-nodes:
+- #address-cells    : number of cells to encode an address
+- #size-cells       : number of cells representing the size of an address
+
+
+Sub-nodes required properties:
+- reg               : the port number
+- phys              : reference to the SATA PHY node
 
-"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
-- clocks            : must contain the sata, sata_ref and ahb clocks
-- clock-names       : must contain "ahb" for the ahb clock
 
 Examples:
         sata@ffe08000 {
@@ -40,3 +55,23 @@ Examples:
                 clocks = <&pll6 0>, <&ahb_gates 25>;
                 target-supply = <&reg_ahci_5v>;
         };
+
+With sub-nodes:
+        sata@f7e90000 {
+                compatible = "marvell,berlin2q-achi", "generic-ahci";
+                reg = <0xe90000 0x1000>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&chip CLKID_SATA>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sata0: sata-port@0 {
+                        reg = <0>;
+                        phys = <&sata_phy 0>;
+                };
+
+                sata1: sata-port@1 {
+                        reg = <1>;
+                        phys = <&sata_phy 1>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt
new file mode 100644
index 000000000000..0574a77a0b9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-st.txt
@@ -0,0 +1,31 @@
+STMicroelectronics STi SATA controller
+
+This binding describes a SATA device.
+
+Required properties:
+ - compatible      : Must be "st,sti-ahci"
+ - reg             : Physical base addresses and length of register sets
+ - interrupts      : Interrupt associated with the SATA device
+ - interrupt-names :   Associated name must be; "hostc"
+ - resets          : The power-down and soft-reset lines of SATA IP
+ - reset-names     :   Associated names must be; "pwr-dwn" and "sw-rst"
+ - clocks          : The phandle for the clock
+ - clock-names     :   Associated name must be; "ahci_clk"
+ - phys            : The phandle for the PHY device
+ - phy-names       :   Associated name must be; "ahci_phy"
+
+Example:
+
+        sata0: sata@fe380000 {
+                compatible      = "st,sti-ahci";
+                reg             = <0xfe380000 0x1000>;
+                interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;
+                interrupt-names = "hostc";
+                phys            = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
+                phy-names       = "ahci_phy";
+                resets          = <&powerdown STIH416_SATA0_POWERDOWN>,
+                                  <&softreset STIH416_SATA0_SOFTRESET>;
+                reset-names     = "pwr-dwn", "sw-rst";
+                clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
+                clock-names     = "ahci_clk";
+        };
diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt
new file mode 100644
index 000000000000..fa511db18408
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/imx-sata.txt
@@ -0,0 +1,36 @@
+* Freescale i.MX AHCI SATA Controller
+
+The Freescale i.MX SATA controller mostly conforms to the AHCI interface
+with some special extensions at integration level.
+
+Required properties:
+- compatible : should be one of the following:
+   - "fsl,imx53-ahci" for i.MX53 SATA controller
+   - "fsl,imx6q-ahci" for i.MX6Q SATA controller
+- interrupts : interrupt mapping for SATA IRQ
+- reg : registers mapping
+- clocks : list of clock specifiers, must contain an entry for each
+  required entry in clock-names
+- clock-names : should include "sata", "sata_ref" and "ahb" entries
+
+Optional properties:
+- fsl,transmit-level-mV : transmit voltage level, in millivolts.
+- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels
+- fsl,transmit-atten-16ths : transmit attenuation, in 16ths
+- fsl,receive-eq-mdB : receive equalisation, in milli-decibels
+  Please refer to the technical documentation or the driver source code
+  for the list of legal values for these options.
+- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
+  link.
+
+Examples:
+
+sata@02200000 {
+        compatible = "fsl,imx6q-ahci";
+        reg = <0x02200000 0x4000>;
+        interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clks IMX6QDL_CLK_SATA>,
+                 <&clks IMX6QDL_CLK_SATA_REF_100M>,
+                 <&clks IMX6QDL_CLK_AHB>;
+        clock-names = "sata", "sata_ref", "ahb";
+};
diff --git a/Documentation/devicetree/bindings/ata/tegra-sata.txt b/Documentation/devicetree/bindings/ata/tegra-sata.txt
new file mode 100644
index 000000000000..946f2072570b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/tegra-sata.txt
@@ -0,0 +1,30 @@
+Tegra124 SoC SATA AHCI controller
+
+Required properties :
+- compatible : "nvidia,tegra124-ahci".
+- reg : Should contain 2 entries:
+  - AHCI register set (SATA BAR5)
+  - SATA register set
+- interrupts : Defines the interrupt used by SATA
+- clocks : Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names : Must include the following entries:
+  - sata
+  - sata-oob
+  - cml1
+  - pll_e
+- resets : Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names : Must include the following entries:
+  - sata
+  - sata-oob
+  - sata-cold
+- phys : Must contain an entry for each entry in phy-names.
+  See ../phy/phy-bindings.txt for details.
+- phy-names : Must include the following entries:
+  - sata-phy : XUSB PADCTL SATA PHY
+- hvdd-supply : Defines the SATA HVDD regulator
+- vddio-supply : Defines the SATA VDDIO regulator
+- avdd-supply : Defines the SATA AVDD regulator
+- target-5v-supply : Defines the SATA 5V power regulator
+- target-12v-supply : Defines the SATA 12V power regulator
diff --git a/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt b/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt
new file mode 100644
index 000000000000..4208886d834a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-palmas-clk32kg-clocks.txt
@@ -0,0 +1,35 @@
+* Palmas 32KHz clocks *
+
+Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
+
+This binding uses the common clock binding ./clock-bindings.txt.
+
+Required properties:
+- compatible :  "ti,palmas-clk32kg" for clk32kg clock
+                "ti,palmas-clk32kgaudio" for clk32kgaudio clock
+- #clock-cells : shall be set to 0.
+
+Optional property:
+- ti,external-sleep-control: The external enable input pins controlled the
+        enable/disable of clocks.  The external enable input pins ENABLE1,
+        ENABLE2 and NSLEEP. The valid values for the external pins are:
+                PALMAS_EXT_CONTROL_PIN_ENABLE1 for ENABLE1 pin
+                PALMAS_EXT_CONTROL_PIN_ENABLE2 for ENABLE2 pin
+                PALMAS_EXT_CONTROL_PIN_NSLEEP for NSLEEP pin
+        Option 0 or missing this property means the clock is enabled/disabled
+        via register access and these pins do not have any control.
+        The macros of external control pins for DTS is defined at
+        dt-bindings/mfd/palmas.h
+
+Example:
+        #include <dt-bindings/mfd/palmas.h>
+        ...
+        palmas: tps65913@58 {
+                ...
+                clk32kg: palmas_clk32k@0 {
+                        compatible = "ti,palmas-clk32kg";
+                        #clock-cells = <0>;
+                        ti,external-sleep-control = <PALMAS_EXT_CONTROL_PIN_NSLEEP>;
+                };
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index f15787817d6b..06fc6d541c89 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -131,3 +131,39 @@ clock signal, and a UART.
   ("pll" and "pll-switched").
 * The UART has its baud clock connected the external oscillator and its
   register clock connected to the PLL clock (the "pll-switched" signal)
+
+==Assigned clock parents and rates==
+
+Some platforms may require initial configuration of default parent clocks
+and clock frequencies. Such a configuration can be specified in a device tree
+node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
+properties. The assigned-clock-parents property should contain a list of parent
+clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
+property the list of assigned clock frequency values - corresponding to clocks
+listed in the assigned-clocks property.
+
+To skip setting parent or rate of a clock its corresponding entry should be
+set to 0, or can be omitted if it is not followed by any non-zero entry.
+
+    uart@a000 {
+        compatible = "fsl,imx-uart";
+        reg = <0xa000 0x1000>;
+        ...
+        clocks = <&osc 0>, <&pll 1>;
+        clock-names = "baud", "register";
+
+        assigned-clocks = <&clkcon 0>, <&pll 2>;
+        assigned-clock-parents = <&pll 2>;
+        assigned-clock-rates = <0>, <460800>;
+    };
+
+In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
+the <&pll 2> clock is assigned a frequency value of 460800 Hz.
+
+Configuring a clock's parent and rate through the device node that consumes
+the clock can be done only for clocks that have a single user. Specifying
+conflicting parent or rate configuration in multiple consumer nodes for
+a shared clock is forbidden.
+
+Configuration of common clocks, which affect multiple consumer devices can
+be similarly specified in the clock provider node.
diff --git a/Documentation/devicetree/bindings/clock/clps711x-clock.txt b/Documentation/devicetree/bindings/clock/clps711x-clock.txt
new file mode 100644
index 000000000000..ce5a7476f05d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clps711x-clock.txt
@@ -0,0 +1,19 @@
+* Clock bindings for the Cirrus Logic CLPS711X CPUs
+
+Required properties:
+- compatible       : Shall contain "cirrus,clps711x-clk".
+- reg              : Address of the internal register set.
+- startup-frequency: Factory set CPU startup frequency in HZ.
+- #clock-cells     : Should be <1>.
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
+for the full list of CLPS711X clock IDs.
+
+Example:
+        clks: clks@80000000 {
+                #clock-cells = <1>;
+                compatible = "cirrus,ep7312-clk", "cirrus,clps711x-clk";
+                reg = <0x80000000 0xc000>;
+                startup-frequency = <73728000>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 9cfcb4f2bc97..aba3d254e037 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -5,6 +5,8 @@ Required properties :
 - compatible : shall contain only one of the following:
 
                         "qcom,gcc-apq8064"
+                        "qcom,gcc-apq8084"
+                        "qcom,gcc-ipq8064"
                         "qcom,gcc-msm8660"
                         "qcom,gcc-msm8960"
                         "qcom,gcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
index d572e9964c54..29ebf84d25af 100644
--- a/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,mmcc.txt
@@ -4,6 +4,8 @@ Qualcomm Multimedia Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain only one of the following:
 
+                        "qcom,mmcc-apq8064"
+                        "qcom,mmcc-apq8084"
                         "qcom,mmcc-msm8660"
                         "qcom,mmcc-msm8960"
                         "qcom,mmcc-msm8974"
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
new file mode 100644
index 000000000000..0c2bf5eba43e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt
@@ -0,0 +1,61 @@
+* Rockchip RK3188/RK3066 Clock and Reset Unit
+
+The RK3188/RK3066 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
+                        "rockchip,rk3066a-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
+dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
+Similar macros exist for the reset sources in these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "xin27m" - 27mhz crystal input on rk3066 - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_cif0" - external camera clock - optional,
+ - "ext_rmii" - external RMII clock - optional,
+ - "ext_jtag" - externalJTAG clock - optional
+
+Example: Clock controller node:
+
+        cru: cru@20000000 {
+                compatible = "rockchip,rk3188-cru";
+                reg = <0x20000000 0x1000>;
+                rockchip,grf = <&grf>;
+
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+        uart0: serial@10124000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x10124000 0x400>;
+                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <1>;
+                clocks = <&cru SCLK_UART0>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
new file mode 100644
index 000000000000..c9fbb76573e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt
@@ -0,0 +1,61 @@
+* Rockchip RK3288 Clock and Reset Unit
+
+The RK3288 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3288-cru"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_edp_24m" - external display port clock - optional,
+ - "ext_vip" - external VIP clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+
+Example: Clock controller node:
+
+        cru: cru@20000000 {
+                compatible = "rockchip,rk3188-cru";
+                reg = <0x20000000 0x1000>;
+                rockchip,grf = <&grf>;
+
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+        };
+
+Example: UART controller node that consumes the clock generated by the clock
+  controller:
+
+        uart0: serial@10124000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x10124000 0x400>;
+                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                reg-shift = <2>;
+                reg-io-width = <1>;
+                clocks = <&cru SCLK_UART0>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/rockchip.txt b/Documentation/devicetree/bindings/clock/rockchip.txt
index a891c823ed44..22f6769e5d4a 100644
--- a/Documentation/devicetree/bindings/clock/rockchip.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip.txt
@@ -6,6 +6,9 @@ This binding uses the common clock binding[1].
 
 == Gate clocks ==
 
+These bindings are deprecated!
+Please use the soc specific CRU bindings instead.
+
 The gate registers form a continuos block which makes the dt node
 structure a matter of taste, as either all gates can be put into
 one gate clock spanning all registers or they can be divided into
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
index ae56315fcec5..6247652044a0 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
@@ -24,26 +24,26 @@ Required properties:
 
 Example:
 
-        clockgenA@fd345000 {
+        clockgen-a@fd345000 {
                 reg = <0xfd345000 0xb50>;
 
-                CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
+                clk_m_a1_div1: clk-m-a1-div1 {
                         #clock-cells = <1>;
                         compatible = "st,clkgena-divmux-c32-odf1",
                                      "st,clkgena-divmux";
 
-                        clocks = <&CLK_M_A1_OSC_PREDIV>,
-                                 <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
-                                 <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
-
-                        clock-output-names = "CLK_M_RX_ICN_TS",
-                                             "CLK_M_RX_ICN_VDP_0",
-                                             "", /* Unused */
-                                             "CLK_M_PRV_T1_BUS",
-                                             "CLK_M_ICN_REG_12",
-                                             "CLK_M_ICN_REG_10",
-                                             "", /* Unused */
-                                             "CLK_M_ICN_ST231";
+                        clocks = <&clk_m_a1_osc_prediv>,
+                                 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
+                                 <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
+
+                        clock-output-names = "clk-m-rx-icn-ts",
+                                             "clk-m-rx-icn-vdp-0",
+                                             "", /* unused */
+                                             "clk-m-prv-t1-bus",
+                                             "clk-m-icn-reg-12",
+                                             "clk-m-icn-reg-10",
+                                             "", /* unused */
+                                             "clk-m-icn-st231";
                 };
         };
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
index 943e0808e212..f1fa91c68768 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -17,7 +17,7 @@ Required properties:
         "st,stih416-clkgenf-vcc-sd",    "st,clkgen-mux"
         "st,stih415-clkgen-a9-mux",     "st,clkgen-mux"
         "st,stih416-clkgen-a9-mux",     "st,clkgen-mux"
-
+        "st,stih407-clkgen-a9-mux",     "st,clkgen-mux"
 
 - #clock-cells : from common clock binding; shall be set to 0.
 
@@ -27,10 +27,10 @@ Required properties:
 
 Example:
 
-        CLK_M_HVA: CLK_M_HVA {
+        clk_m_hva: clk-m-hva@fd690868 {
                 #clock-cells = <0>;
                 compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
                 reg = <0xfd690868 4>;
 
-                clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
+                clocks = <&clockgen_f 1>, <&clk_m_a1_div0 3>;
         };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index 81eb3855ab92..efb51cf0c845 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -19,11 +19,14 @@ Required properties:
         "st,stih415-plls-c32-ddr",      "st,clkgen-plls-c32"
         "st,stih416-plls-c32-a9",       "st,clkgen-plls-c32"
         "st,stih416-plls-c32-ddr",      "st,clkgen-plls-c32"
+        "st,stih407-plls-c32-a0",       "st,clkgen-plls-c32"
+        "st,stih407-plls-c32-a9",       "st,clkgen-plls-c32"
+        "st,stih407-plls-c32-c0_0",     "st,clkgen-plls-c32"
+        "st,stih407-plls-c32-c0_1",     "st,clkgen-plls-c32"
 
         "st,stih415-gpu-pll-c32",       "st,clkgengpu-pll-c32"
         "st,stih416-gpu-pll-c32",       "st,clkgengpu-pll-c32"
 
-
 - #clock-cells : From common clock binding; shall be set to 1.
 
 - clocks : From common clock binding
@@ -32,17 +35,17 @@ Required properties:
 
 Example:
 
-        clockgenA@fee62000 {
+        clockgen-a@fee62000 {
                 reg = <0xfee62000 0xb48>;
 
-                CLK_S_A0_PLL: CLK_S_A0_PLL {
+                clk_s_a0_pll: clk-s-a0-pll {
                         #clock-cells = <1>;
                         compatible = "st,clkgena-plls-c65";
 
-                        clocks = <&CLK_SYSIN>;
+                        clocks = <&clk_sysin>;
 
-                        clock-output-names = "CLK_S_A0_PLL0_HS",
-                                             "CLK_S_A0_PLL0_LS",
-                                             "CLK_S_A0_PLL1";
+                        clock-output-names = "clk-s-a0-pll0-hs",
+                                             "clk-s-a0-pll0-ls",
+                                             "clk-s-a0-pll1";
                 };
         };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
index 566c9d79ed32..604766c2619e 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
@@ -20,17 +20,17 @@ Required properties:
 
 Example:
 
-        clockgenA@fd345000 {
+        clockgen-a@fd345000 {
                 reg = <0xfd345000 0xb50>;
 
-                CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
+                clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
                         #clock-cells = <0>;
                         compatible = "st,clkgena-prediv-c32",
                                      "st,clkgena-prediv";
 
-                        clocks = <&CLK_SYSIN>;
+                        clocks = <&clk_sysin>;
 
-                        clock-output-names = "CLK_M_A2_OSC_PREDIV";
+                        clock-output-names = "clk-m-a2-osc-prediv";
                 };
         };
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
index 4e3ff28b04c3..109b3eddcb17 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
@@ -32,22 +32,30 @@ Required properties:
 
 Example:
 
-        CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
+        clockgen_c_vcc: clockgen-c-vcc@0xfe8308ac {
                 #clock-cells = <1>;
                 compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
                 reg = <0xfe8308ac 12>;
 
-                clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
-                        <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
-
-                clock-output-names  =
-                        "CLK_S_PIX_HDMI",  "CLK_S_PIX_DVO",
-                        "CLK_S_OUT_DVO",   "CLK_S_PIX_HD",
-                        "CLK_S_HDDAC",     "CLK_S_DENC",
-                        "CLK_S_SDDAC",     "CLK_S_PIX_MAIN",
-                        "CLK_S_PIX_AUX",   "CLK_S_STFE_FRC_0",
-                        "CLK_S_REF_MCRU",  "CLK_S_SLAVE_MCRU",
-                        "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
-                        "CLK_S_THSENS";
+                clocks = <&clk_s_vcc_hd>,
+                         <&clockgen_c 1>,
+                         <&clk_s_tmds_fromphy>,
+                         <&clockgen_c 2>;
+
+                clock-output-names  = "clk-s-pix-hdmi",
+                                      "clk-s-pix-dvo",
+                                      "clk-s-out-dvo",
+                                      "clk-s-pix-hd",
+                                      "clk-s-hddac",
+                                      "clk-s-denc",
+                                      "clk-s-sddac",
+                                      "clk-s-pix-main",
+                                      "clk-s-pix-aux",
+                                      "clk-s-stfe-frc-0",
+                                      "clk-s-ref-mcru",
+                                      "clk-s-slave-mcru",
+                                      "clk-s-tmds-hdmi",
+                                      "clk-s-hdmi-reject-pll",
+                                      "clk-s-thsens";
         };
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
index 49ec5ae18b5b..78978f1f5158 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -24,60 +24,77 @@ address is common of all subnode.
                 quadfs_node {
                         ...
                 };
+
+                mux_node {
+                        ...
+                };
+
+                vcc_node {
+                        ...
+                };
+
+                flexgen_node {
+                        ...
+                };
                 ...
         };
 
 This binding uses the common clock binding[1].
-Each subnode should use the binding discribe in [2]..[4]
+Each subnode should use the binding discribe in [2]..[7]
 
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
-[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
+[3] Documentation/devicetree/bindings/clock/st,clkgen-mux.txt
+[4] Documentation/devicetree/bindings/clock/st,clkgen-pll.txt
+[5] Documentation/devicetree/bindings/clock/st,clkgen-prediv.txt
+[6] Documentation/devicetree/bindings/clock/st,vcc.txt
+[7] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[8] Documentation/devicetree/bindings/clock/st,flexgen.txt
+
 
 Required properties:
 - reg : A Base address and length of the register set.
 
 Example:
 
-        clockgenA@fee62000 {
+        clockgen-a@fee62000 {
 
                 reg = <0xfee62000 0xb48>;
 
-                CLK_S_A0_PLL: CLK_S_A0_PLL {
+                clk_s_a0_pll: clk-s-a0-pll {
                         #clock-cells = <1>;
                         compatible = "st,clkgena-plls-c65";
 
-                        clocks = <&CLK_SYSIN>;
+                        clocks = <&clk-sysin>;
 
-                        clock-output-names = "CLK_S_A0_PLL0_HS",
-                                             "CLK_S_A0_PLL0_LS",
-                                             "CLK_S_A0_PLL1";
+                        clock-output-names = "clk-s-a0-pll0-hs",
+                                             "clk-s-a0-pll0-ls",
+                                             "clk-s-a0-pll1";
                 };
 
-                CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+                clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
                         #clock-cells = <0>;
                         compatible = "st,clkgena-prediv-c65",
                                      "st,clkgena-prediv";
 
-                        clocks = <&CLK_SYSIN>;
+                        clocks = <&clk_sysin>;
 
-                        clock-output-names = "CLK_S_A0_OSC_PREDIV";
+                        clock-output-names = "clk-s-a0-osc-prediv";
                 };
 
-                CLK_S_A0_HS: CLK_S_A0_HS {
+                clk_s_a0_hs: clk-s-a0-hs {
                         #clock-cells = <1>;
                         compatible = "st,clkgena-divmux-c65-hs",
                                      "st,clkgena-divmux";
 
-                        clocks = <&CLK_S_A0_OSC_PREDIV>,
-                                 <&CLK_S_A0_PLL 0>, /* PLL0 HS */
-                                 <&CLK_S_A0_PLL 2>; /* PLL1 */
+                        clocks = <&clk-s_a0_osc_prediv>,
+                                 <&clk-s_a0_pll 0>, /* pll0 hs */
+                                 <&clk-s_a0_pll 2>; /* pll1 */
 
-                        clock-output-names = "CLK_S_FDMA_0",
-                                             "CLK_S_FDMA_1",
-                                             ""; /* CLK_S_JIT_SENSE */
-                                             /* Fourth output unused */
+                        clock-output-names = "clk-s-fdma-0",
+                                             "clk-s-fdma-1",
+                                             ""; /* clk-s-jit-sense */
+                                             /* fourth output unused */
                 };
         };
 
diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
new file mode 100644
index 000000000000..1d3ace088172
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt
@@ -0,0 +1,119 @@
+Binding for a type of flexgen structure found on certain
+STMicroelectronics consumer electronics SoC devices
+
+This structure includes:
+- a clock cross bar (represented by a mux element)
+- a pre and final dividers (represented by a divider and gate elements)
+
+Flexgen structure is a part of Clockgen[1].
+
+Please find an example below:
+
+    Clockgen block diagram
+    -------------------------------------------------------------------
+   |                     Flexgen stucture                              |
+   |                  ---------------------------------------------    |
+   |                 |    -------       --------       --------    |   |
+clk_sysin            |   |       |     |        |     |        |   |   |
+---|-----------------|-->|       |     |        |     |        |   |   |
+   | |               |   |       |     |        |     |        |   |   |
+   | |   -------     |   |       |     |Pre     |     |Final   |   |   |
+   | |  |PLL0   |    |   |       |     |Dividers|     |Dividers|   |   |
+   | |->|       |    |   |       |     |  x32   |     |  x32   |   |   |
+   | |  |  odf_0|----|-->|       |     |        |     |        |   |   |
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |   -------     |   |       |     |        |     |        |   |   |
+   | |               |   |       |     |        |     |        |   |   |
+   | |   -------     |   | Clock |     |        |     |        |   |   |
+   | |  |PLL1   |    |   |       |     |        |     |        |   |   |
+   | |->|       |    |   | Cross |     |        |     |        |   |   |
+   | |  |  odf_0|----|-->|       |     |        |     |        | CLK_DIV[31:0]
+   | |  |       |    |   | Bar   |====>|        |====>|        |===|=========>
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |  |       |    |   |       |     |        |     |        |   |   |
+   | |   -------     |   |       |     |        |     |        |   |   |
+   | |               |   |       |     |        |     |        |   |   |
+   | |   -------     |   |       |     |        |     |        |   |   |
+   | |  |QUADFS |    |   |       |     |        |     |        |   |   |
+   | |->|    ch0|----|-->|       |     |        |     |        |   |   |
+   |    |       |    |   |       |     |        |     |        |   |   |
+   |    |    ch1|----|-->|       |     |        |     |        |   |   |
+   |    |       |    |   |       |     |        |     |        |   |   |
+   |    |    ch2|----|-->|       |     | DIV    |     | DIV    |   |   |
+   |    |       |    |   |       |     |  1 to  |     |  1 to  |   |   |
+   |    |    ch3|----|-->|       |     |   1024 |     |     64 |   |   |
+   |     -------     |   |       |     |        |     |        |   |   |
+   |                 |    -------       --------       --------    |   |
+   |                   --------------------------------------------    |
+   |                                                                   |
+    -------------------------------------------------------------------
+
+This binding uses the common clock binding[2].
+
+[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be:
+  "st,flexgen"
+
+- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
+  outputs).
+
+- clocks : must be set to the parent's phandle. it's could be output clocks of
+  a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
+
+- clock-output-names : List of strings used to name the clock outputs.
+
+Example:
+
+        clk_s_c0_flexgen: clk-s-c0-flexgen {
+
+                #clock-cells = <1>;
+                compatible = "st,flexgen";
+
+                clocks = <&clk_s_c0_pll0 0>,
+                         <&clk_s_c0_pll1 0>,
+                         <&clk_s_c0_quadfs 0>,
+                         <&clk_s_c0_quadfs 1>,
+                         <&clk_s_c0_quadfs 2>,
+                         <&clk_s_c0_quadfs 3>,
+                         <&clk_sysin>;
+
+                clock-output-names = "clk-icn-gpu",
+                                     "clk-fdma",
+                                     "clk-nand",
+                                     "clk-hva",
+                                     "clk-proc-stfe",
+                                     "clk-proc-tp",
+                                     "clk-rx-icn-dmu",
+                                     "clk-rx-icn-hva",
+                                     "clk-icn-cpu",
+                                     "clk-tx-icn-dmu",
+                                     "clk-mmc-0",
+                                     "clk-mmc-1",
+                                     "clk-jpegdec",
+                                     "clk-ext2fa9",
+                                     "clk-ic-bdisp-0",
+                                     "clk-ic-bdisp-1",
+                                     "clk-pp-dmu",
+                                     "clk-vid-dmu",
+                                     "clk-dss-lpc",
+                                     "clk-st231-aud-0",
+                                     "clk-st231-gp-1",
+                                     "clk-st231-dmu",
+                                     "clk-icn-lmi",
+                                     "clk-tx-icn-disp-1",
+                                     "clk-icn-sbc",
+                                     "clk-stfe-frc2",
+                                     "clk-eth-phy",
+                                     "clk-eth-ref-phyclk",
+                                     "clk-flash-promip",
+                                     "clk-main-disp",
+                                     "clk-aux-disp",
+                                     "clk-compo-dvp";
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
index ec86d62ca283..cedeb9cc8208 100644
--- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -15,6 +15,9 @@ Required properties:
   "st,stih416-quadfs432",       "st,quadfs"
   "st,stih416-quadfs660-E",     "st,quadfs"
   "st,stih416-quadfs660-F",     "st,quadfs"
+  "st,stih407-quadfs660-C",     "st,quadfs"
+  "st,stih407-quadfs660-D",     "st,quadfs"
+
 
 - #clock-cells : from common clock binding; shall be set to 1.
 
@@ -32,14 +35,14 @@ Required properties:
 
 Example:
 
-        CLOCKGEN_E: CLOCKGEN_E {
+        clockgen_e: clockgen-e@fd3208bc {
                 #clock-cells = <1>;
                 compatible = "st,stih416-quadfs660-E", "st,quadfs";
                 reg = <0xfd3208bc 0xB0>;
 
-                clocks = <&CLK_SYSIN>;
-                clock-output-names = "CLK_M_PIX_MDTP_0",
-                                        "CLK_M_PIX_MDTP_1",
-                                        "CLK_M_PIX_MDTP_2",
-                                        "CLK_M_MPELPC";
+                clocks = <&clk_sysin>;
+                clock-output-names = "clk-m-pix-mdtp-0",
+                                     "clk-m-pix-mdtp-1",
+                                     "clk-m-pix-mdtp-2",
+                                     "clk-m-mpelpc";
         };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index b9ec668bfe62..d3a5c3c6d677 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -9,11 +9,13 @@ Required properties:
         "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
+        "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
+        "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
@@ -23,13 +25,16 @@ Required properties:
         "allwinner,sun6i-a31-ar100-clk" - for the AR100 on A31
         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
+        "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
+        "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
         "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
+        "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
         "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
@@ -37,8 +42,10 @@ Required properties:
         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
+        "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
         "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
+        "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
         "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
         "allwinner,sun7i-a20-out-clk" - for the external output clocks
         "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
diff --git a/Documentation/devicetree/bindings/crypto/amd-ccp.txt b/Documentation/devicetree/bindings/crypto/amd-ccp.txt
new file mode 100644
index 000000000000..8c61183b41e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/amd-ccp.txt
@@ -0,0 +1,19 @@
+* AMD Cryptographic Coprocessor driver (ccp)
+
+Required properties:
+- compatible: Should be "amd,ccp-seattle-v1a"
+- reg: Address and length of the register set for the device
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the CCP interrupt
+
+Optional properties:
+- dma-coherent: Present if dma operations are coherent
+
+Example:
+        ccp@e0100000 {
+                compatible = "amd,ccp-seattle-v1a";
+                reg = <0 0xe0100000 0 0x10000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 3 4>;
+        };
diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.txt b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
new file mode 100644
index 000000000000..fdd53b184ba8
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/qcom-qce.txt
@@ -0,0 +1,25 @@
+Qualcomm crypto engine driver
+
+Required properties:
+
+- compatible  : should be "qcom,crypto-v5.1"
+- reg         : specifies base physical address and size of the registers map
+- clocks      : phandle to clock-controller plus clock-specifier pair
+- clock-names : "iface" clocks register interface
+                "bus" clocks data transfer interface
+                "core" clocks rest of the crypto block
+- dmas        : DMA specifiers for tx and rx dma channels. For more see
+                Documentation/devicetree/bindings/dma/dma.txt
+- dma-names   : DMA request names should be "rx" and "tx"
+
+Example:
+        crypto@fd45a000 {
+                compatible = "qcom,crypto-v5.1";
+                reg = <0xfd45a000 0x6000>;
+                clocks = <&gcc GCC_CE2_AHB_CLK>,
+                         <&gcc GCC_CE2_AXI_CLK>,
+                         <&gcc GCC_CE2_CLK>;
+                clock-names = "iface", "bus", "core";
+                dmas = <&cryptobam 2>, <&cryptobam 3>;
+                dma-names = "rx", "tx";
+        };
diff --git a/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt b/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt
new file mode 100644
index 000000000000..4ecda224955f
--- /dev/null
+++ b/Documentation/devicetree/bindings/extcon/extcon-sm5502.txt
@@ -0,0 +1,23 @@
+
+* SM5502 MUIC (Micro-USB Interface Controller) device
+
+The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device
+which can detect the state of external accessory when external accessory is
+attached or detached and button is pressed or released. It is interfaced to
+the host controller using an I2C interface.
+
+Required properties:
+- compatible: Should be "siliconmitus,sm5502-muic"
+- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from sm5502 are delivered to.
+- interrupts: Interrupt specifiers for detection interrupt sources.
+
+Example:
+
+        sm5502@25 {
+                compatible = "siliconmitus,sm5502-muic";
+                interrupt-parent = <&gpx1>;
+                interrupts = <5 0>;
+                reg = <0x25>;
+        };
diff --git a/Documentation/devicetree/bindings/hwmon/ibmpowernv.txt b/Documentation/devicetree/bindings/hwmon/ibmpowernv.txt
new file mode 100644
index 000000000000..f93242be60a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/ibmpowernv.txt
@@ -0,0 +1,23 @@
+IBM POWERNV platform sensors
+----------------------------
+
+Required node properties:
+- compatible: must be one of
+                "ibm,opal-sensor-cooling-fan"
+                "ibm,opal-sensor-amb-temp"
+                "ibm,opal-sensor-power-supply"
+                "ibm,opal-sensor-power"
+- sensor-id: an opaque id provided by the firmware to the kernel, identifies a
+             given sensor and its attribute data
+
+Example sensors node:
+
+cooling-fan#8-data {
+        sensor-id = <0x7052107>;
+        compatible = "ibm,opal-sensor-cooling-fan";
+};
+
+amb-temp#1-thrs {
+        sensor-id = <0x5096000>;
+        compatible = "ibm,opal-sensor-amb-temp";
+};
diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
index b117b2e9e1a7..2391e5c41999 100644
--- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
+++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
@@ -3,6 +3,7 @@ NTC Thermistor hwmon sensors
 
 Requires node properties:
 - "compatible" value : one of
+        "epcos,b57330v2103"
         "murata,ncp15wb473"
         "murata,ncp18wb473"
         "murata,ncp21wb473"
diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.txt b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt
new file mode 100644
index 000000000000..610757ce4492
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.txt
@@ -0,0 +1,12 @@
+Bindings for a fan connected to the PWM lines
+
+Required properties:
+- compatible    : "pwm-fan"
+- pwms          : the PWM that is used to control the PWM fan
+
+Example:
+        pwm-fan {
+                compatible = "pwm-fan";
+                status = "okay";
+                pwms = <&pwm 0 10000 0>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index bef86e57c388..37803eb5521e 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -50,6 +50,7 @@ epson,rx8581		I2C-BUS INTERFACE REAL TIME CLOCK MODULE
 fsl,mag3110             MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
 fsl,mc13892             MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
 fsl,mma8450             MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
+fsl,mma8452             MMA8452Q: 3-axis 12-bit / 8-bit Digital Accelerometer
 fsl,mpr121              MPR121: Proximity Capacitive Touch Sensor Controller
 fsl,sgtl5000            SGTL5000: Ultra Low-Power Audio Codec
 gmt,g751                G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
@@ -83,5 +84,6 @@ stm,m41t80		M41T80 - SERIAL ACCESS RTC WITH ALARMS
 taos,tsl2550            Ambient Light Sensor with SMBUS/Two Wire Serial Interface
 ti,tsc2003              I2C Touch-Screen Controller
 ti,tmp102               Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
+ti,tmp103               Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
 ti,tmp275               Digital Temperature Sensor
 winbond,wpct301         i2c trusted platform module (TPM)
diff --git a/Documentation/devicetree/bindings/iio/adc/max1027-adc.txt b/Documentation/devicetree/bindings/iio/adc/max1027-adc.txt
new file mode 100644
index 000000000000..a8770cc6bcad
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/max1027-adc.txt
@@ -0,0 +1,22 @@
+* Maxim 1027/1029/1031 Analog to Digital Converter (ADC)
+
+Required properties:
+  - compatible: Should be "maxim,max1027" or "maxim,max1029" or "maxim,max1031"
+  - reg: SPI chip select number for the device
+  - interrupt-parent: phandle to the parent interrupt controller
+  see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+  - interrupts: IRQ line for the ADC
+  see: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+Recommended properties:
+- spi-max-frequency: Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+adc@0 {
+        compatible = "maxim,max1027";
+        reg = <0>;
+        interrupt-parent = <&gpio5>;
+        interrupts = <15 IRQ_TYPE_EDGE_RISING>;
+        spi-max-frequency = <1000000>;
+};
diff --git a/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt b/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt
index 90d5f34db04e..8e191eef014e 100644
--- a/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt
+++ b/Documentation/devicetree/bindings/iio/magnetometer/hmc5843.txt
@@ -3,6 +3,10 @@
 Required properties:
 
   - compatible : should be "honeywell,hmc5843"
+  Other models which are supported with driver are:
+        "honeywell,hmc5883"
+        "honeywell,hmc5883l"
+        "honeywell,hmc5983"
   - reg : the I2C address of the magnetometer - typically 0x1e
 
 Optional properties:
diff --git a/Documentation/devicetree/bindings/iio/st-sensors.txt b/Documentation/devicetree/bindings/iio/st-sensors.txt
new file mode 100644
index 000000000000..a7a0a15913ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/st-sensors.txt
@@ -0,0 +1,54 @@
+STMicroelectronics MEMS sensors
+
+The STMicroelectronics sensor devices are pretty straight-forward I2C or
+SPI devices, all sharing the same device tree descriptions no matter what
+type of sensor it is.
+
+Required properties:
+- compatible: see the list of valid compatible strings below
+- reg: the I2C or SPI address the device will respond to
+
+Optional properties:
+- vdd-supply: an optional regulator that needs to be on to provide VDD
+  power to the sensor.
+- vddio-supply: an optional regulator that needs to be on to provide the
+  VDD IO power to the sensor.
+- st,drdy-int-pin: the pin on the package that will be used to signal
+  "data ready" (valid values: 1 or 2). This property is not configurable
+  on all sensors.
+
+Sensors may also have applicable pin control settings, those use the
+standard bindings from pinctrl/pinctrl-bindings.txt.
+
+Valid compatible strings:
+
+Accelerometers:
+- st,lsm303dlh-accel
+- st,lsm303dlhc-accel
+- st,lis3dh-accel
+- st,lsm330d-accel
+- st,lsm330dl-accel
+- st,lsm330dlc-accel
+- st,lis331dlh-accel
+- st,lsm303dl-accel
+- st,lsm303dlm-accel
+- st,lsm330-accel
+
+Gyroscopes:
+- st,l3g4200d-gyro
+- st,lsm330d-gyro
+- st,lsm330dl-gyro
+- st,lsm330dlc-gyro
+- st,l3gd20-gyro
+- st,l3g4is-gyro
+- st,lsm330-gyro
+
+Magnetometers:
+- st,lsm303dlhc-magn
+- st,lsm303dlm-magn
+- st,lis3mdl-magn
+
+Pressure sensors:
+- st,lps001wp-press
+- st,lps25h-press
+- st,lps331ap-press
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index f284b99402bc..2d0f7cd867ea 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -42,12 +42,6 @@ conditions.
 
 ** System MMU optional properties:
 
-- smmu-parent   : When multiple SMMUs are chained together, this
-                  property can be used to provide a phandle to the
-                  parent SMMU (that is the next SMMU on the path going
-                  from the mmu-masters towards memory) node for this
-                  SMMU.
-
 - calxeda,smmu-secure-config-access : Enable proper handling of buggy
                   implementations that always use secure access to
                   SMMU configuration registers. In this case non-secure
diff --git a/Documentation/devicetree/bindings/iommu/iommu.txt b/Documentation/devicetree/bindings/iommu/iommu.txt
new file mode 100644
index 000000000000..5a8b4624defc
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/iommu.txt
@@ -0,0 +1,182 @@
+This document describes the generic device tree binding for IOMMUs and their
+master(s).
+
+
+IOMMU device node:
+==================
+
+An IOMMU can provide the following services:
+
+* Remap address space to allow devices to access physical memory ranges that
+  they otherwise wouldn't be capable of accessing.
+
+  Example: 32-bit DMA to 64-bit physical addresses
+
+* Implement scatter-gather at page level granularity so that the device does
+  not have to.
+
+* Provide system protection against "rogue" DMA by forcing all accesses to go
+  through the IOMMU and faulting when encountering accesses to unmapped
+  address regions.
+
+* Provide address space isolation between multiple contexts.
+
+  Example: Virtualization
+
+Device nodes compatible with this binding represent hardware with some of the
+above capabilities.
+
+IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
+typically have a fixed association to the master device, whereas multiple-
+master IOMMU devices can translate accesses from more than one master.
+
+The device tree node of the IOMMU device's parent bus must contain a valid
+"dma-ranges" property that describes how the physical address space of the
+IOMMU maps to memory. An empty "dma-ranges" property means that there is a
+1:1 mapping from IOMMU to memory.
+
+Required properties:
+--------------------
+- #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
+  address.
+
+The meaning of the IOMMU specifier is defined by the device tree binding of
+the specific IOMMU. Below are a few examples of typical use-cases:
+
+- #iommu-cells = <0>: Single master IOMMU devices are not configurable and
+  therefore no additional information needs to be encoded in the specifier.
+  This may also apply to multiple master IOMMU devices that do not allow the
+  association of masters to be configured. Note that an IOMMU can by design
+  be multi-master yet only expose a single master in a given configuration.
+  In such cases the number of cells will usually be 1 as in the next case.
+- #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
+  in order to enable translation for a given master. In such cases the single
+  address cell corresponds to the master device's ID. In some cases more than
+  one cell can be required to represent a single master ID.
+- #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
+  be configured. The first cell of the address in this may contain the master
+  device's ID for example, while the second cell could contain the start of
+  the DMA window for the given device. The length of the DMA window is given
+  by the third and fourth cells.
+
+Note that these are merely examples and real-world use-cases may use different
+definitions to represent their individual needs. Always refer to the specific
+IOMMU binding for the exact meaning of the cells that make up the specifier.
+
+
+IOMMU master node:
+==================
+
+Devices that access memory through an IOMMU are called masters. A device can
+have multiple master interfaces (to one or more IOMMU devices).
+
+Required properties:
+--------------------
+- iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
+  master interfaces of the device. One entry in the list describes one master
+  interface of the device.
+
+When an "iommus" property is specified in a device tree node, the IOMMU will
+be used for address translation. If a "dma-ranges" property exists in the
+device's parent node it will be ignored. An exception to this rule is if the
+referenced IOMMU is disabled, in which case the "dma-ranges" property of the
+parent shall take effect. Note that merely disabling a device tree node does
+not guarantee that the IOMMU is really disabled since the hardware may not
+have a means to turn off translation. But it is invalid in such cases to
+disable the IOMMU's device tree node in the first place because it would
+prevent any driver from properly setting up the translations.
+
+
+Notes:
+======
+
+One possible extension to the above is to use an "iommus" property along with
+a "dma-ranges" property in a bus device node (such as PCI host bridges). This
+can be useful to describe how children on the bus relate to the IOMMU if they
+are not explicitly listed in the device tree (e.g. PCI devices). However, the
+requirements of that use-case haven't been fully determined yet. Implementing
+this is therefore not recommended without further discussion and extension of
+this binding.
+
+
+Examples:
+=========
+
+Single-master IOMMU:
+--------------------
+
+        iommu {
+                #iommu-cells = <0>;
+        };
+
+        master {
+                iommus = <&{/iommu}>;
+        };
+
+Multiple-master IOMMU with fixed associations:
+----------------------------------------------
+
+        /* multiple-master IOMMU */
+        iommu {
+                /*
+                 * Masters are statically associated with this IOMMU and share
+                 * the same address translations because the IOMMU does not
+                 * have sufficient information to distinguish between masters.
+                 *
+                 * Consequently address translation is always on or off for
+                 * all masters at any given point in time.
+                 */
+                #iommu-cells = <0>;
+        };
+
+        /* static association with IOMMU */
+        master@1 {
+                reg = <1>;
+                iommus = <&{/iommu}>;
+        };
+
+        /* static association with IOMMU */
+        master@2 {
+                reg = <2>;
+                iommus = <&{/iommu}>;
+        };
+
+Multiple-master IOMMU:
+----------------------
+
+        iommu {
+                /* the specifier represents the ID of the master */
+                #iommu-cells = <1>;
+        };
+
+        master@1 {
+                /* device has master ID 42 in the IOMMU */
+                iommus = <&{/iommu} 42>;
+        };
+
+        master@2 {
+                /* device has master IDs 23 and 24 in the IOMMU */
+                iommus = <&{/iommu} 23>, <&{/iommu} 24>;
+        };
+
+Multiple-master IOMMU with configurable DMA window:
+---------------------------------------------------
+
+        / {
+                iommu {
+                        /*
+                         * One cell for the master ID and one cell for the
+                         * address of the DMA window. The length of the DMA
+                         * window is encoded in two cells.
+                         *
+                         * The DMA window is the range addressable by the
+                         * master (i.e. the I/O virtual address space).
+                         */
+                        #iommu-cells = <4>;
+                };
+
+                master {
+                        /* master ID 42, 4 GiB DMA window starting at 0 */
+                        iommus = <&{/iommu}  42  0  0x1 0x0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
index e5f0f8303461..eda898978d33 100644
--- a/Documentation/devicetree/bindings/mfd/palmas.txt
+++ b/Documentation/devicetree/bindings/mfd/palmas.txt
@@ -6,6 +6,7 @@ twl6037 (palmas)
 tps65913 (palmas)
 tps65914 (palmas)
 tps659038
+tps65917
 
 Required properties:
 - compatible : Should be from the list
@@ -16,6 +17,7 @@ Required properties:
   ti,tps65914
   ti,tps80036
   ti,tps659038
+  ti,tps65917
 and also the generic series names
   ti,palmas
 - interrupt-controller : palmas has its own internal IRQs
diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
new file mode 100644
index 000000000000..88f8c23384c0
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
@@ -0,0 +1,34 @@
+Berlin SATA PHY
+---------------
+
+Required properties:
+- compatible: should be "marvell,berlin2q-sata-phy"
+- address-cells: should be 1
+- size-cells: should be 0
+- phy-cells: from the generic PHY bindings, must be 1
+- reg: address and length of the register
+- clocks: reference to the clock entry
+
+Sub-nodes:
+Each PHY should be represented as a sub-node.
+
+Sub-nodes required properties:
+- reg: the PHY number
+
+Example:
+        sata_phy: phy@f7e900a0 {
+                compatible = "marvell,berlin2q-sata-phy";
+                reg = <0xf7e900a0 0x200>;
+                clocks = <&chip CLKID_SATA>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                #phy-cells = <1>;
+
+                sata-phy@0 {
+                        reg = <0>;
+                };
+
+                sata-phy@1 {
+                        reg = <1>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt b/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt
new file mode 100644
index 000000000000..296168b74d24
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/hix5hd2-phy.txt
@@ -0,0 +1,22 @@
+Hisilicon hix5hd2 SATA PHY
+-----------------------
+
+Required properties:
+- compatible: should be "hisilicon,hix5hd2-sata-phy"
+- reg: offset and length of the PHY registers
+- #phy-cells: must be 0
+Refer to phy/phy-bindings.txt for the generic PHY binding properties
+
+Optional Properties:
+- hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
+- hisilicon,power-reg: offset and bit number within peripheral-syscon,
+        register of controlling sata power supply.
+
+Example:
+        sata_phy: phy@f9900000 {
+                compatible = "hisilicon,hix5hd2-sata-phy";
+                reg = <0xf9900000 0x10000>;
+                #phy-cells = <0>;
+                hisilicon,peripheral-syscon = <&peripheral_ctrl>;
+                hisilicon,power-reg = <0x8 10>;
+        };
diff --git a/Documentation/devicetree/bindings/phy/phy-bindings.txt b/Documentation/devicetree/bindings/phy/phy-bindings.txt
index 8ae844fc0c60..2aa1840200ed 100644
--- a/Documentation/devicetree/bindings/phy/phy-bindings.txt
+++ b/Documentation/devicetree/bindings/phy/phy-bindings.txt
@@ -10,6 +10,10 @@ Required Properties:
                 provider can use the values in cells to find the appropriate
                 PHY.
 
+Optional Properties:
+phy-supply:     Phandle to a regulator that provides power to the PHY. This
+                regulator will be managed during the PHY power on/off sequence.
+
 For example:
 
 phys: phy {
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
new file mode 100644
index 000000000000..42c880886cf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
@@ -0,0 +1,76 @@
+STMicroelectronics STi MIPHY365x PHY binding
+============================================
+
+This binding describes a miphy device that is used to control PHY hardware
+for SATA and PCIe.
+
+Required properties (controller (parent) node):
+- compatible    : Should be "st,miphy365x-phy"
+- st,syscfg     : Should be a phandle of the system configuration register group
+                  which contain the SATA, PCIe mode setting bits
+
+Required nodes  :  A sub-node is required for each channel the controller
+                   provides. Address range information including the usual
+                   'reg' and 'reg-names' properties are used inside these
+                   nodes to describe the controller's topology. These nodes
+                   are translated by the driver's .xlate() function.
+
+Required properties (port (child) node):
+- #phy-cells    : Should be 1 (See second example)
+                  Cell after port phandle is device type from:
+                        - MIPHY_TYPE_SATA
+                        - MIPHY_TYPE_PCI
+- reg           : Address and length of register sets for each device in
+                  "reg-names"
+- reg-names     : The names of the register addresses corresponding to the
+                  registers filled in "reg":
+                        - sata:   For SATA devices
+                        - pcie:   For PCIe devices
+                        - syscfg: To specify the syscfg based config register
+
+Optional properties (port (child) node):
+- st,sata-gen        :  Generation of locally attached SATA IP. Expected values
+                        are {1,2,3). If not supplied generation 1 hardware will
+                        be expected
+- st,pcie-tx-pol-inv :  Bool property to invert the polarity PCIe Tx (Txn/Txp)
+- st,sata-tx-pol-inv :  Bool property to invert the polarity SATA Tx (Txn/Txp)
+
+Example:
+
+        miphy365x_phy: miphy365x@fe382000 {
+                compatible      = "st,miphy365x-phy";
+                st,syscfg       = <&syscfg_rear>;
+                #address-cells  = <1>;
+                #size-cells     = <1>;
+                ranges;
+
+                phy_port0: port@fe382000 {
+                        reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
+                        reg-names = "sata", "pcie", "syscfg";
+                        #phy-cells = <1>;
+                        st,sata-gen = <3>;
+                };
+
+                phy_port1: port@fe38a000 {
+                        reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
+                        reg-names = "sata", "pcie", "syscfg";
+                        #phy-cells = <1>;
+                        st,pcie-tx-pol-inv;
+                };
+        };
+
+Specifying phy control of devices
+=================================
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy port node and a device type.
+
+Example:
+
+#include <dt-bindings/phy/phy-miphy365x.h>
+
+        sata0: sata@fe380000 {
+                ...
+                phys      = <&phy_port0 MIPHY_TYPE_SATA>;
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt
new file mode 100644
index 000000000000..952f6c96bab9
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-apq8064-sata-phy.txt
@@ -0,0 +1,24 @@
+Qualcomm APQ8064 SATA PHY Controller
+------------------------------------
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "qcom,apq8064-sata-phy".
+- reg: offset and length of the SATA PHY register set;
+- #phy-cells: must be zero
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+- clock-names: must be "cfg" for phy config clock.
+
+Example:
+        sata_phy: sata-phy@1b400000 {
+                compatible = "qcom,apq8064-sata-phy";
+                reg = <0x1b400000 0x200>;
+
+                clocks = <&gcc SATA_PHY_CFG_CLK>;
+                clock-names = "cfg";
+
+                #phy-cells = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/phy/qcom-ipq806x-sata-phy.txt b/Documentation/devicetree/bindings/phy/qcom-ipq806x-sata-phy.txt
new file mode 100644
index 000000000000..76bfbd056202
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-ipq806x-sata-phy.txt
@@ -0,0 +1,23 @@
+Qualcomm IPQ806x SATA PHY Controller
+------------------------------------
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains "qcom,ipq806x-sata-phy"
+- reg: offset and length of the SATA PHY register set;
+- #phy-cells: must be zero
+- clocks: must be exactly one entry
+- clock-names: must be "cfg"
+
+Example:
+        sata_phy: sata-phy@1b400000 {
+                compatible = "qcom,ipq806x-sata-phy";
+                reg = <0x1b400000 0x200>;
+
+                clocks = <&gcc SATA_PHY_CFG_CLK>;
+                clock-names = "cfg";
+
+                #phy-cells = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 2049261d8c31..6099a5c94283 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -26,6 +26,7 @@ Samsung S5P/EXYNOS SoC series USB PHY
 
 Required properties:
 - compatible : should be one of the listed compatibles:
+        - "samsung,exynos3250-usb2-phy"
         - "samsung,exynos4210-usb2-phy"
         - "samsung,exynos4x12-usb2-phy"
         - "samsung,exynos5250-usb2-phy"
@@ -46,6 +47,7 @@ and Exynos 4212) it is as follows:
   1 - USB host ("host"),
   2 - HSIC0 ("hsic0"),
   3 - HSIC1 ("hsic1"),
+Exynos3250 has only USB device phy available as phy 0.
 
 Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
 register is supplied.
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 9ce458f32945..305e3df3d9b1 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,15 +9,17 @@ Required properties:
                         e.g. USB2_PHY on OMAP5.
  "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
                         e.g. USB3 PHY and SATA PHY on OMAP5.
+ "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
+                        set PCS delay value.
+                        e.g. PCIE PHY in DRA7x
  "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
                         DRA7 platform.
  "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
                         AM437 platform.
- - reg : Address and length of the register set for the device. It contains
-   the address of "otghs_control" for control-phy-otghs or "power" register
-   for other types.
- - reg-names: should be "otghs_control" control-phy-otghs and "power" for
-   other types.
+ - reg : register ranges as listed in the reg-names property
+ - reg-names: "otghs_control" for control-phy-otghs
+              "power", "pcie_pcs" and "control_sma" for control-phy-pcie
+              "power" for all other types
 
 omap_control_usb: omap-control-usb@4a002300 {
         compatible = "ti,control-phy-otghs";
@@ -56,8 +58,8 @@ usb2phy@4a0ad080 {
 TI PIPE3 PHY
 
 Required properties:
- - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".
-   "ti,omap-usb3" is deprecated.
+ - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
+   "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
  - reg : Address and length of the register set for the device.
  - reg-names: The names of the register addresses corresponding to the registers
    filled in "reg".
@@ -69,10 +71,17 @@ Required properties:
    * "wkupclk" - wakeup clock.
    * "sysclk" - system clock.
    * "refclk" - reference clock.
+   * "dpll_ref" - external dpll ref clk
+   * "dpll_ref_m2" - external dpll ref clk
+   * "phy-div" - divider for apll
+   * "div-clk" - apll clock
 
 Optional properties:
  - ctrl-module : phandle of the control module used by PHY driver to power on
    the PHY.
+ - id: If there are multiple instance of the same type, in order to
+   differentiate between each instance "id" can be used (e.g., multi-lane PCIe
+   PHY). If "id" is not provided, it is set to default value of '1'.
 
 This is usually a subnode of ocp2scp to which it is connected.
 
diff --git a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt
index bef1fbb647ca..865614b34d6f 100644
--- a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt
@@ -1,13 +1,16 @@
-ACT8865 regulator
+ACT88xx regulators
 -------------------
 
 Required properties:
-- compatible: "active-semi,act8865"
+- compatible: "active-semi,act8846" or "active-semi,act8865"
 - reg: I2C slave address
 
 Any standard regulator properties can be used to configure the single regulator.
 
 The valid names for regulators are:
+        - for act8846:
+        REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8, REG9, REG10, REG11, REG12
+        - for act8865:
         DCDC_REG1, DCDC_REG2, DCDC_REG3, LDO_REG1, LDO_REG2, LDO_REG3, LDO_REG4.
 
 Example:
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
index 42e6b6bc48ff..725393c8a7f2 100644
--- a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
+++ b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
@@ -7,6 +7,7 @@ Required properties:
   ti,twl6037-pmic
   ti,tps65913-pmic
   ti,tps65914-pmic
+  ti,tps65917-pmic
 and also the generic series names
   ti,palmas-pmic
 - interrupt-parent : The parent interrupt controller which is palmas.
diff --git a/Documentation/devicetree/bindings/regulator/tps65218.txt b/Documentation/devicetree/bindings/regulator/tps65218.txt
new file mode 100644
index 000000000000..fccc1d24af58
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/tps65218.txt
@@ -0,0 +1,23 @@
+TPS65218 family of regulators
+
+Required properties:
+For tps65218 regulators/LDOs
+- compatible:
+  - "ti,tps65218-dcdc1" for DCDC1
+  - "ti,tps65218-dcdc2" for DCDC2
+  - "ti,tps65218-dcdc3" for DCDC3
+  - "ti,tps65218-dcdc4" for DCDC4
+  - "ti,tps65218-dcdc5" for DCDC5
+  - "ti,tps65218-dcdc6" for DCDC6
+  - "ti,tps65218-ldo1" for LDO1
+
+Optional properties:
+- Any optional property defined in bindings/regulator/regulator.txt
+
+Example:
+
+        xyz: regulator@0 {
+                compatible = "ti,tps65218-dcdc1";
+                regulator-min-microvolt  = <1000000>;
+                regulator-max-microvolt  = <3000000>;
+        };
diff --git a/Documentation/devicetree/bindings/serial/efm32-uart.txt b/Documentation/devicetree/bindings/serial/efm32-uart.txt
index 3ca01336b837..8adbab268ca3 100644
--- a/Documentation/devicetree/bindings/serial/efm32-uart.txt
+++ b/Documentation/devicetree/bindings/serial/efm32-uart.txt
@@ -6,7 +6,7 @@ Required properties:
 - interrupts : Should contain uart interrupt
 
 Optional properties:
-- efm32,location : Decides the location of the USART I/O pins.
+- energymicro,location : Decides the location of the USART I/O pins.
   Allowed range : [0 .. 5]
   Default: 0
 
@@ -16,5 +16,5 @@ uart@0x4000c400 {
         compatible = "energymicro,efm32-uart";
         reg = <0x4000c400 0x400>;
         interrupts = <15>;
-        efm32,location = <0>;
+        energymicro,location = <0>;
 };
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
index a1d1205d8185..c95005efbcb8 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
@@ -1,7 +1,11 @@
 * Freescale low power universal asynchronous receiver/transmitter (lpuart)
 
 Required properties:
-- compatible : Should be "fsl,<soc>-lpuart"
+- compatible :
+  - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
+    on Vybrid vf610 SoC with 8-bit register organization
+  - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
+    on LS1021A SoC with 32-bit big-endian register organization
 - reg : Address and length of the register set for the device
 - interrupts : Should contain uart interrupt
 - clocks : phandle + clock specifier pairs, one for each entry in clock-names
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt b/Documentation/devicetree/bindings/serial/samsung_uart.txt
index 2c8a17cf5cb5..e85f37ec33f0 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.txt
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.txt
@@ -1,14 +1,58 @@
 * Samsung's UART Controller
 
-The Samsung's UART controller is used for interfacing SoC with serial communicaion
-devices.
+The Samsung's UART controller is used for interfacing SoC with serial
+communicaion devices.
 
 Required properties:
-- compatible: should be
-  - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports.
+- compatible: should be one of following:
+  - "samsung,exynos4210-uart" -  Exynos4210 SoC,
+  - "samsung,s3c2410-uart" - compatible with ports present on S3C2410 SoC,
+  - "samsung,s3c2412-uart" - compatible with ports present on S3C2412 SoC,
+  - "samsung,s3c2440-uart" - compatible with ports present on S3C2440 SoC,
+  - "samsung,s3c6400-uart" - compatible with ports present on S3C6400 SoC,
+  - "samsung,s5pv210-uart" - compatible with ports present on S5PV210 SoC.
 
 - reg: base physical address of the controller and length of memory mapped
   region.
 
-- interrupts: interrupt number to the cpu. The interrupt specifier format depends
-  on the interrupt controller parent.
+- interrupts: a single interrupt signal to SoC interrupt controller,
+  according to interrupt bindings documentation [1].
+
+- clock-names: input names of clocks used by the controller:
+  - "uart" - controller bus clock,
+  - "clk_uart_baudN" - Nth baud base clock input (N = 0, 1, ...),
+    according to SoC User's Manual (only N = 0 is allowedfor SoCs without
+    internal baud clock mux).
+- clocks: phandles and specifiers for all clocks specified in "clock-names"
+  property, in the same order, according to clock bindings documentation [2].
+
+[1] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Optional properties:
+- samsung,uart-fifosize: The fifo size supported by the UART channel
+
+Note: Each Samsung UART should have an alias correctly numbered in the
+"aliases" node, according to serialN format, where N is the port number
+(non-negative decimal integer) as specified by User's Manual of respective
+SoC.
+
+Example:
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+        };
+
+Example:
+        uart1: serial@7f005400 {
+                compatible = "samsung,s3c6400-uart";
+                reg = <0x7f005400 0x100>;
+                interrupt-parent = <&vic1>;
+                interrupts = <6>;
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
+                                <&clocks SCLK_UART>;
+                samsung,uart-fifosize = <16>;
+        };
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index f13f1c5be91c..7f76214f728a 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
@@ -4,9 +4,18 @@ Required properties:
 - compatible : "snps,dw-apb-uart"
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
+
+Clock handling:
+The clock rate of the input clock needs to be supplied by one of
 - clock-frequency : the input clock frequency for the UART.
+- clocks : phandle to the input clock
+
+The supplying peripheral clock can also be handled, needing a second property
+- clock-names: tuple listing input clock names.
+        Required elements: "baudclk", "apb_pclk"
 
 Optional properties:
+- resets : phandle to the parent reset controller.
 - reg-shift : quantity to shift the register offsets by.  If this property is
   not present then the register offsets are not shifted.
 - reg-io-width : the size (in bytes) of the IO accesses that should be
@@ -23,3 +32,26 @@ Example:
                 reg-shift = <2>;
                 reg-io-width = <4>;
         };
+
+Example with one clock:
+
+        uart@80230000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x80230000 0x100>;
+                clocks = <&baudclk>;
+                interrupts = <10>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
+
+Example with two clocks:
+
+        uart@80230000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x80230000 0x100>;
+                clocks = <&baudclk>, <&apb_pclk>;
+                clock-names = "baudclk", "apb_pclk";
+                interrupts = <10>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt
index 130cd17e3680..750e29aff9bc 100644
--- a/Documentation/devicetree/bindings/spi/efm32-spi.txt
+++ b/Documentation/devicetree/bindings/spi/efm32-spi.txt
@@ -10,11 +10,12 @@ Required properties:
 - cs-gpios: see spi-bus.txt
 
 Recommended properties :
-- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to
-                  configure the pinmux for the device, see datasheet for values.
-                  If "efm32,location" property is not provided, keeping what is
-                  already configured in the hardware, so its either the reset
-                  default 0 or whatever the bootloader did.
+- energymicro,location: Value to write to the ROUTE register's LOCATION
+                        bitfield to configure the pinmux for the device, see
+                        datasheet for values.
+                        If this property is not provided, keeping what is
+                        already configured in the hardware, so its either the
+                        reset default 0 or whatever the bootloader did.
 
 Example:
 
@@ -26,7 +27,7 @@ spi1: spi@0x4000c400 { /* USART1 */
         interrupts = <15 16>;
         clocks = <&cmu 20>;
         cs-gpios = <&gpio 51 1>; // D3
-        efm32,location = <1>;
+        energymicro,location = <1>;
         status = "ok";
 
         ks8851@0 {
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
index bee6ff204baf..e2c88df2cc15 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz, up to four chip selects, programmable
 data path from 4 bits to 32 bits and numerous protocol variants.
 
 Required properties:
-- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
+- compatible:     Should contain:
+                  "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
+                  "qcom,spi-qup-v2.1.1" for 8974 and later
+                  "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
+
 - reg:            Should contain base register location and length
 - interrupts:     Interrupt number used by this controller
 
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
new file mode 100644
index 000000000000..bd99193e87b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -0,0 +1,28 @@
+Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
+
+Required properties:
+- compatible : "snps,dw-apb-ssi"
+- reg : The register base for the controller.
+- interrupts : One interrupt, used by the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Optional properties:
+- cs-gpios : Specifies the gpio pis to be used for chipselects.
+- num-cs : The number of chipselects. If omitted, this will default to 4.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+        spi@fff00000 {
+                compatible = "snps,dw-apb-ssi";
+                reg = <0xfff00000 0x1000>;
+                interrupts = <0 154 4>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                num-cs = <2>;
+                cs-gpios = <&gpio0 13 0>,
+                           <&gpio0 14 0>;
+        };
+
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt
index 6d0ac8d0ad9b..f80887bca0d6 100644
--- a/Documentation/devicetree/bindings/spi/spi-davinci.txt
+++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -8,7 +8,8 @@ Required properties:
         - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
         - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
 - reg: Offset and length of SPI controller register space
-- num-cs: Number of chip selects
+- num-cs: Number of chip selects. This includes internal as well as
+        GPIO chip selects.
 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
         IP to the interrupt controller within the SoC. Possible values
         are 0 and 1. Manual says one of the two possible interrupt
@@ -17,6 +18,12 @@ Required properties:
 - interrupts: interrupt number mapped to CPU.
 - clocks: spi clk phandle
 
+Optional:
+- cs-gpios: gpio chip selects
+        For example to have 3 internal CS and 2 GPIO CS, user could define
+        cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>;
+        where first three are internal CS and last two are GPIO CS.
+
 Example of a NOR flash slave device (n25q032) connected to DaVinci
 SPI controller device over the SPI bus.
 
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
new file mode 100644
index 000000000000..7bab35575817
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -0,0 +1,37 @@
+* Rockchip SPI Controller
+
+The Rockchip SPI controller is used to interface with various devices such as flash
+and display controllers using the SPI communication interface.
+
+Required Properties:
+
+- compatible: should be one of the following.
+    "rockchip,rk3066-spi" for rk3066.
+    "rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.
+    "rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.
+- reg: physical base address of the controller and length of memory mapped
+       region.
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+              depends on the interrupt controller.
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Shall be "spiclk" for the transfer-clock, and "apb_pclk" for
+                           the peripheral clock.
+- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
+                Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request names should include "tx" and "rx" if present.
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+
+Example:
+
+        spi0: spi@ff110000 {
+                compatible = "rockchip,rk3066-spi";
+                reg = <0xff110000 0x1000>;
+                dmas = <&pdma1 11>, <&pdma1 12>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+                clock-names = "spiclk", "apb_pclk";
+        };
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 86aa061f069f..792efbaedc54 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -18,14 +18,11 @@ Required SoC Specific Properties:
 - interrupts: The interrupt number to the cpu. The interrupt specifier format
   depends on the interrupt controller.
 
-[PRELIMINARY: the dma channel allocation will change once there are
-official DMA bindings]
+- dmas : Two or more DMA channel specifiers following the convention outlined
+  in bindings/dma/dma.txt
 
-- tx-dma-channel: The dma channel specifier for tx operations. The format of
-  the dma specifier depends on the dma controller.
-
-- rx-dma-channel: The dma channel specifier for rx operations. The format of
-  the dma specifier depends on the dma controller.
+- dma-names: Names for the dma channels. There must be at least one channel
+  named "tx" for transmit and named "rx" for receive.
 
 Required Board Specific Properties:
 
@@ -42,15 +39,13 @@ Optional Board Specific Properties:
 - num-cs: Specifies the number of chip select lines supported. If
   not specified, the default number of chip select lines is set to 1.
 
+- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
+
 SPI Controller specific data in SPI slave nodes:
 
 - The spi slave nodes should provide the following information which is required
   by the spi controller.
 
-  - cs-gpio: A gpio specifier that specifies the gpio line used as
-    the slave select line by the spi controller. The format of the gpio
-    specifier depends on the gpio controller.
-
   - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
     miso line (to account for any lag in the miso line). The following are the
     valid values.
@@ -74,8 +69,11 @@ Example:
                 compatible = "samsung,exynos4210-spi";
                 reg = <0x12d20000 0x100>;
                 interrupts = <0 66 0>;
-                tx-dma-channel = <&pdma0 5>;
-                rx-dma-channel = <&pdma0 4>;
+                dmas = <&pdma0 5
+                        &pdma0 4>;
+                dma-names = "tx", "rx";
+                #address-cells = <1>;
+                #size-cells = <0>;
         };
 
 - Board Specific Portion:
@@ -85,6 +83,7 @@ Example:
                 #size-cells = <0>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&spi0_bus>;
+                cs-gpios = <&gpa2 5 0>;
 
                 w25q80bw@0 {
                         #address-cells = <1>;
@@ -94,7 +93,6 @@ Example:
                         spi-max-frequency = <10000>;
 
                         controller-data {
-                                cs-gpio = <&gpa2 5 1 0 3>;
                                 samsung,spi-feedback-delay = <0>;
                         };
 
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
index a6a32cb7f777..1bae71e9ad47 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible: Should be "fsl,imx27-usb"
 - reg: Should contain registers location and length
 - interrupts: Should contain controller interrupt
+- fsl,usbphy: phandle of usb phy that connects to the port
 
 Recommended properies:
 - phy_type: the type of the phy connected to the core. Should be one
@@ -12,7 +13,6 @@ Recommended properies:
 - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
 
 Optional properties:
-- fsl,usbphy: phandler of usb phy that connects to the only one port
 - fsl,usbmisc: phandler of non-core register device, with one argument
   that indicate usb controller index
 - vbus-supply: regulator for vbus
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
index ba797d3e6326..c9205fbf26e2 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -20,6 +20,12 @@ Required properties :
      Present if phy_type == utmi.
    - ulpi-link: The clock Tegra provides to the ULPI PHY (cdev2).
      Present if phy_type == ulpi, and ULPI link mode is in use.
+ - resets : Must contain an entry for each entry in reset-names.
+   See ../reset/reset.txt for details.
+ - reset-names : Must include the following entries:
+   - usb: The PHY's own reset signal.
+   - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control
+     registers. Required even if phy_type == ulpi.
 
 Required properties for phy_type == ulpi:
   - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
@@ -56,6 +62,8 @@ Optional properties:
       host means this is a host controller
       peripheral means it is device controller
       otg means it can operate as either ("on the go")
+  - nvidia,has-utmi-pad-registers : boolean indicates whether this controller
+    contains the UTMI pad control registers common to all USB controllers.
 
 VBUS control (required for dr_mode == otg, optional for dr_mode == host):
   - vbus-supply: regulator for VBUS
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index 5a79377c6a96..86f67f0886bc 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -9,8 +9,9 @@ Required properties:
     register set for the device.
   - interrupts: one XHCI interrupt should be described here.
 
-Optional property:
+Optional properties:
   - clocks: reference to a clock
+  - usb3-lpm-capable: determines if platform is USB3 LPM capable
 
 Example:
         usb@f0931000 {
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 46a311e728a8..97c9c06132c4 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -42,6 +42,7 @@ dmo	Data Modul AG
 ebv     EBV Elektronik
 edt     Emerging Display Technologies
 emmicro EM Microelectronic
+epcos   EPCOS AG
 epfl    Ecole Polytechnique Fédérale de Lausanne
 epson   Seiko Epson Corp.
 est     ESTeem Wireless Modems