104 files changed, 2523 insertions, 155 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
new file mode 100644
index 000000000000..ecdb57d69dbf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-reset.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA Reset Manager
+Required properties:
+- compatible : "altr,rst-mgr"
+- reg : Should contain 1 register ranges(address and length)
+Example:
+         rstmgr@ffd05000 {
+                compatible = "altr,rst-mgr";
+                reg = <0xffd05000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
new file mode 100644
index 000000000000..07c65e3cdcbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-system.txt
@@ -0,0 +1,11 @@
+Altera SOCFPGA System Manager
+Required properties:
+- compatible : "altr,sys-mgr"
+- reg : Should contain 1 register ranges(address and length)
+Example:
+         sysmgr@ffd08000 {
+                compatible = "altr,sys-mgr";
+                reg = <0xffd08000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index fc81a7d6b0f1..db5858e32d3f 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -9,6 +9,10 @@ Required properties (in root node):
 FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
+In the root node the Integrator/CP must have a /cpcon node pointing
+to the CP control registers, and the Integrator/AP must have a
+/syscon node pointing to the Integrator/AP system controller.
 ARM Versatile Application and Platform Baseboards
 -------------------------------------------------
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index d187e9f7cf1c..1196290082d1 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -7,6 +7,12 @@ PIT Timer required properties:
 - interrupts: Should contain interrupt for the PIT which is the IRQ line
  shared across all System Controller members.
+System Timer (ST) required properties:
+- compatible: Should be "atmel,at91rm9200-st"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the ST which is the IRQ line
+  shared across all System Controller members.
 TC/TCLIB Timer required properties:
 - compatible: Should be "atmel,<chip>-tcb".
  <chip> can be "at91rm9200" or "at91sam9x5"
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
new file mode 100644
index 000000000000..fb7b5cd2652f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
@@ -0,0 +1,9 @@
+Broadcom BCM11351 device tree bindings
+-------------------------------------------
+Boards with the bcm281xx SoC family (which includes bcm11130, bcm11140,
+bcm11351, bcm28145, bcm28155 SoCs) shall have the following properties:
+Required root node property:
+compatible = "bcm,bcm11351";
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
index 4755caaccba6..25fcf96795ca 100644
--- a/Documentation/devicetree/bindings/arm/calxeda.txt
+++ b/Documentation/devicetree/bindings/arm/calxeda.txt
@@ -1,8 +1,15 @@
-Calxeda Highbank Platforms Device Tree Bindings
+Calxeda Platforms Device Tree Bindings
 -----------------------------------------------
-Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
-properties.
+following properties.
 Required root node properties:
    - compatible = "calxeda,highbank";
+Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
+properties.
+Required root node properties:
+    - compatible = "calxeda,ecx-2000";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
new file mode 100644
index 000000000000..f32494dbfe19
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -0,0 +1,77 @@
+* ARM CPUs binding description
+The device tree allows to describe the layout of CPUs in a system through
+the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+defining properties for every cpu.
+Bindings for CPU nodes follow the ePAPR standard, available from:
+http://devicetree.org
+For the ARM architecture every CPU node must contain the following properties:
+- device_type:  must be "cpu"
+- reg:          property matching the CPU MPIDR[23:0] register bits
+                reg[31:24] bits must be set to 0
+- compatible:   should be one of:
+                "arm,arm1020"
+                "arm,arm1020e"
+                "arm,arm1022"
+                "arm,arm1026"
+                "arm,arm720"
+                "arm,arm740"
+                "arm,arm7tdmi"
+                "arm,arm920"
+                "arm,arm922"
+                "arm,arm925"
+                "arm,arm926"
+                "arm,arm940"
+                "arm,arm946"
+                "arm,arm9tdmi"
+                "arm,cortex-a5"
+                "arm,cortex-a7"
+                "arm,cortex-a8"
+                "arm,cortex-a9"
+                "arm,cortex-a15"
+                "arm,arm1136"
+                "arm,arm1156"
+                "arm,arm1176"
+                "arm,arm11mpcore"
+                "faraday,fa526"
+                "intel,sa110"
+                "intel,sa1100"
+                "marvell,feroceon"
+                "marvell,mohawk"
+                "marvell,xsc3"
+                "marvell,xscale"
+Example:
+        cpus {
+                #size-cells = <0>;
+                #address-cells = <1>;
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
+                };
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
+                };
+                CPU2: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                };
+                CPU3: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt
new file mode 100644
index 000000000000..cfaeda4274e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/davinci.txt
@@ -0,0 +1,17 @@
+Texas Instruments DaVinci Platforms Device Tree Bindings
+--------------------------------------------------------
+DA850/OMAP-L138/AM18x Evaluation Module (EVM) board
+Required root node properties:
+    - compatible = "ti,da850-evm", "ti,da850";
+EnBW AM1808 based CMC board
+Required root node properties:
+    - compatible = "enbw,cmc", "ti,da850;
+Generic DaVinci Boards
+----------------------
+DA850/OMAP-L138/AM18x generic board
+Required root node properties:
+    - compatible = "ti,da850";
diff --git a/Documentation/devicetree/bindings/arm/davinci/nand.txt b/Documentation/devicetree/bindings/arm/davinci/nand.txt
index e37241f1fdd8..49fc7ada929a 100644
--- a/Documentation/devicetree/bindings/arm/davinci/nand.txt
+++ b/Documentation/devicetree/bindings/arm/davinci/nand.txt
@@ -23,29 +23,16 @@ Recommended properties :
 - ti,davinci-nand-buswidth: buswidth 8 or 16
 - ti,davinci-nand-use-bbt: use flash based bad block table support.
-Example (enbw_cmc board):
+Example(da850 EVM ):
-aemif@60000000 {
+nand_cs3@62000000 {
-        compatible = "ti,davinci-aemif";
+        compatible = "ti,davinci-nand";
-        #address-cells = <2>;
+        reg = <0x62000000 0x807ff
-        #size-cells = <1>;
+                0x68000000 0x8000>;
-        reg = <0x68000000 0x80000>;
+        ti,davinci-chipselect = <1>;
-        ranges = <2 0 0x60000000 0x02000000
+        ti,davinci-mask-ale = <0>;
-                  3 0 0x62000000 0x02000000
+        ti,davinci-mask-cle = <0>;
-                  4 0 0x64000000 0x02000000
+        ti,davinci-mask-chipsel = <0>;
-                  5 0 0x66000000 0x02000000
+        ti,davinci-ecc-mode = "hw";
-                  6 0 0x68000000 0x02000000>;
+        ti,davinci-ecc-bits = <4>;
-        nand@3,0 {
+        ti,davinci-nand-use-bbt;
-                compatible = "ti,davinci-nand";
-                reg = <3 0x0 0x807ff
-                        6 0x0 0x8000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ti,davinci-chipselect = <1>;
-                ti,davinci-mask-ale = <0>;
-                ti,davinci-mask-cle = <0>;
-                ti,davinci-mask-chipsel = <0>;
-                ti,davinci-ecc-mode = "hw";
-                ti,davinci-ecc-bits = <4>;
-                ti,davinci-nand-use-bbt;
-        };
 };
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 6528e215c5fe..5216b419016a 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -4,14 +4,13 @@ Exynos processors include support for multiple power domains which are used
 to gate power to one or more peripherals on the processor.
 Required Properties:
- compatiable: should be one of the following.
+- compatible: should be one of the following.
    * samsung,exynos4210-pd - for exynos4210 type power domain.
 - reg: physical base address of the controller and length of memory mapped
    region.
-Optional Properties:
+Node of a device using power domains must have a samsung,power-domain property
- samsung,exynos4210-pd-off: Specifies that the power domain is in turned-off
+defined with a phandle to respective power domain.
-    state during boot and remains to be turned-off until explicitly turned-on.
 Example:
@@ -19,3 +18,11 @@ Example:
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023C00 0x10>;
        };
+Example of the node using power domain:
+        node {
+                /* ... */
+                samsung,power-domain = <&lcd0>;
+                /* ... */
+        };
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index ac9e7516756e..f79818711e83 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -41,6 +41,10 @@ i.MX6 Quad SABRE Smart Device Board
 Required root node properties:
    - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+i.MX6 Quad SABRE Automotive Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
 Generic i.MX boards
 -------------------
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 76b0ee6ee9a4..cbef09b5c8a7 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -46,7 +46,7 @@ L2: cache-controller {
        reg = <0xfff12000 0x1000>;
        arm,data-latency = <1 1 1>;
        arm,tag-latency = <2 2 2>;
-        arm,filter-latency = <0x80000000 0x8000000>;
+        arm,filter-ranges = <0x80000000 0x8000000>;
        cache-unified;
        cache-level = <2>;
        interrupts = <45>;
diff --git a/Documentation/devicetree/bindings/arm/omap/counter.txt b/Documentation/devicetree/bindings/arm/omap/counter.txt
new file mode 100644
index 000000000000..5bd8aa091315
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/counter.txt
@@ -0,0 +1,15 @@
+OMAP Counter-32K bindings
+Required properties:
+- compatible:   Must be "ti,omap-counter32k" for OMAP controllers
+- reg:          Contains timer register address range (base address and length)
+- ti,hwmods:    Name of the hwmod associated to the counter, which is typically
+                "counter_32k"
+Example:
+counter32k: counter@4a304000 {
+        compatible = "ti,omap-counter32k";
+        reg = <0x4a304000 0x20>;
+        ti,hwmods = "counter_32k";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/timer.txt b/Documentation/devicetree/bindings/arm/omap/timer.txt
new file mode 100644
index 000000000000..8732d4d41f8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/timer.txt
@@ -0,0 +1,31 @@
+OMAP Timer bindings
+Required properties:
+- compatible:           Must be "ti,omap2-timer" for OMAP2+ controllers.
+- reg:                  Contains timer register address range (base address and
+                        length).
+- interrupts:           Contains the interrupt information for the timer. The
+                        format is being dependent on which interrupt controller
+                        the OMAP device uses.
+- ti,hwmods:            Name of the hwmod associated to the timer, "timer<X>",
+                        where <X> is the instance number of the timer from the
+                        HW spec.
+Optional properties:
+- ti,timer-alwon:       Indicates the timer is in an alway-on power domain.
+- ti,timer-dsp:         Indicates the timer can interrupt the on-chip DSP in
+                        addition to the ARM CPU.
+- ti,timer-pwm:         Indicates the timer can generate a PWM output.
+- ti,timer-secure:      Indicates the timer is reserved on a secure OMAP device
+                        and therefore cannot be used by the kernel.
+Example:
+timer12: timer@48304000 {
+        compatible = "ti,omap2-timer";
+        reg = <0x48304000 0x400>;
+        interrupts = <95>;
+        ti,hwmods = "timer12"
+        ti,timer-alwon;
+        ti,timer-secure;
+};
diff --git a/Documentation/devicetree/bindings/arm/spear/shirq.txt b/Documentation/devicetree/bindings/arm/spear/shirq.txt
new file mode 100644
index 000000000000..13fbb8866bd6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/spear/shirq.txt
@@ -0,0 +1,48 @@
+* SPEAr Shared IRQ layer (shirq)
+SPEAr3xx architecture includes shared/multiplexed irqs for certain set
+of devices. The multiplexor provides a single interrupt to parent
+interrupt controller (VIC) on behalf of a group of devices.
+There can be multiple groups available on SPEAr3xx variants but not
+exceeding 4. The number of devices in a group can differ, further they
+may share same set of status/mask registers spanning across different
+bit masks. Also in some cases the group may not have enable or other
+registers. This makes software little complex.
+A single node in the device tree is used to describe the shared
+interrupt multiplexor (one node for all groups). A group in the
+interrupt controller shares config/control registers with other groups.
+For example, a 32-bit interrupt enable/disable config register can
+accommodate upto 4 interrupt groups.
+Required properties:
+  - compatible: should be, either of
+     - "st,spear300-shirq"
+     - "st,spear310-shirq"
+     - "st,spear320-shirq"
+  - interrupt-controller: Identifies the node as an interrupt controller.
+  - #interrupt-cells: should be <1> which basically contains the offset
+    (starting from 0) of interrupts for all the groups.
+  - reg: Base address and size of shirq registers.
+  - interrupts: The list of interrupts generated by the groups which are
+    then connected to a parent interrupt controller. Each group is
+    associated with one of the interrupts, hence number of interrupts (to
+    parent) is equal to number of groups. The format of the interrupt
+    specifier depends in the interrupt parent controller.
+  Optional properties:
+  - interrupt-parent: pHandle of the parent interrupt controller, if not
+    inherited from the parent node.
+Example:
+The following is an example from the SPEAr320 SoC dtsi file.
+shirq: interrupt-controller@0xb3000000 {
+        compatible = "st,spear320-shirq";
+        reg = <0xb3000000 0x1000>;
+        interrupts = <28 29 30 1>;
+        #interrupt-cells = <1>;
+        interrupt-controller;
+};
diff --git a/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
new file mode 100644
index 000000000000..9cf3f25544c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
@@ -0,0 +1,50 @@
+ARM Versatile Express system registers
+--------------------------------------
+This is a system control registers block, providing multiple low level
+platform functions like board detection and identification, software
+interrupt generation, MMC and NOR Flash control etc.
+Required node properties:
+- compatible value : = "arm,vexpress,sysreg";
+- reg : physical base address and the size of the registers window
+- gpio-controller : specifies that the node is a GPIO controller
+- #gpio-cells : size of the GPIO specifier, should be 2:
+  - first cell is the pseudo-GPIO line number:
+    0 - MMC CARDIN
+    1 - MMC WPROT
+    2 - NOR FLASH WPn
+  - second cell can take standard GPIO flags (currently ignored).
+Example:
+        v2m_sysreg: sysreg@10000000 {
+                compatible = "arm,vexpress-sysreg";
+                reg = <0x10000000 0x1000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+This block also can also act a bridge to the platform's configuration
+bus via "system control" interface, addressing devices with site number,
+position in the board stack, config controller, function and device
+numbers - see motherboard's TRM for more details.
+The node describing a config device must refer to the sysreg node via
+"arm,vexpress,config-bridge" phandle (can be also defined in the node's
+parent) and relies on the board topology properties - see main vexpress
+node documentation for more details. It must must also define the
+following property:
+- arm,vexpress-sysreg,func : must contain two cells:
+  - first cell defines function number (eg. 1 for clock generator,
+    2 for voltage regulators etc.)
+  - device number (eg. osc 0, osc 1 etc.)
+Example:
+        mcc {
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+                osc@0 {
+                        compatible = "arm,vexpress-osc";
+                        arm,vexpress-sysreg,func = <1 0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt b/Documentation/devicetree/bindings/arm/vexpress.txt
index ec8b50cbb2e8..ae49161e478a 100644
--- a/Documentation/devicetree/bindings/arm/vexpress.txt
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -11,6 +11,10 @@ the motherboard file using a /include/ directive. As the motherboard
 can be initialized in one of two different configurations ("memory
 maps"), care must be taken to include the correct one.
+Root node
+---------
 Required properties in the root node:
 - compatible value:
        compatible = "arm,vexpress,<model>", "arm,vexpress";
@@ -45,6 +49,10 @@ Optional properties in the root node:
  - Coretile Express A9x4 (V2P-CA9) HBI-0225:
        arm,hbi = <0x225>;
+CPU nodes
+---------
 Top-level standard "cpus" node is required. It must contain a node
 with device_type = "cpu" property for every available core, eg.:
@@ -59,6 +67,52 @@ with device_type = "cpu" property for every available core, eg.:
                };
        };
+Configuration infrastructure
+----------------------------
+The platform has an elaborated configuration system, consisting of
+microcontrollers residing on the mother- and daughterboards known
+as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
+The controllers are responsible for the platform initialization
+(reset generation, flash programming, FPGA bitfiles loading etc.)
+but also control clock generators, voltage regulators, gather
+environmental data like temperature, power consumption etc. Even
+the video output switch (FPGA) is controlled that way.
+Nodes describing devices controlled by this infrastructure should
+point at the bridge device node:
+- bridge phandle:
+        arm,vexpress,config-bridge = <phandle>;
+This property can be also defined in a parent node (eg. for a DCC)
+and is effective for all children.
+Platform topology
+-----------------
+As Versatile Express can be configured in number of physically
+different setups, the device tree should describe platform topology.
+Root node and main motherboard node must define the following
+property, describing physical location of the children nodes:
+- site number:
+        arm,vexpress,site = <number>;
+  where 0 means motherboard, 1 or 2 are daugtherboard sites,
+  0xf means "master" site (site containing main CPU tile)
+- when daughterboards are stacked on one site, their position
+  in the stack be be described with:
+        arm,vexpress,position = <number>;
+- when describing tiles consisting more than one DCC, its number
+  can be described with:
+        arm,vexpress,dcc = <number>;
+Any of the numbers above defaults to zero if not defined in
+the node or any of its parent.
+Motherboard
+-----------
 The motherboard description file provides a single "motherboard" node
 using 2 address cells corresponding to the Static Memory Bus used
 between the motherboard and the tile. The first cell defines the Chip
@@ -87,22 +141,30 @@ can be used to obtain required phandle in the tile's "aliases" node:
 - SP804 timers:
        v2m_timer01 and v2m_timer23
-Current Linux implementation requires a "arm,v2m_timer" alias
+The tile description should define a "smb" node, describing the
-pointing at one of the motherboard's SP804 timers, if it is to be
+Static Memory Bus between the tile and motherboard. It must define
-used as the system timer. This alias should be defined in the
+the following properties:
-motherboard files.
+- "simple-bus" compatible value (to ensure creation of the children)
+        compatible = "simple-bus";
+- mapping of the SMB CS/offset addresses into main address space:
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <...>;
+- interrupts mapping:
+        #interrupt-cells = <1>;
+        interrupt-map-mask = <0 0 63>;
+        interrupt-map = <...>;
-The tile description must define "ranges", "interrupt-map-mask" and
-"interrupt-map" properties to translate the motherboard's address
-and interrupt space into one used by the tile's processor.
-Abbreviated example:
+Example of a VE tile description (simplified)
+---------------------------------------------
 /dts-v1/;
 / {
        model = "V2P-CA5s";
        arm,hbi = <0x225>;
+        arm,vexpress,site = <0xf>;
        compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
        interrupt-parent = <&gic>;
        #address-cells = <1>;
@@ -134,13 +196,29 @@ Abbreviated example:
                      <0x2c000100 0x100>;
        };
-        motherboard {
+        dcc {
+                compatible = "simple-bus";
+                arm,vexpress,config-bridge = <&v2m_sysreg>;
+                osc@0 {
+                        compatible = "arm,vexpress-osc";
+                };
+        };
+        smb {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
                /* CS0 is visible at 0x08000000 */
                ranges = <0 0 0x08000000 0x04000000>;
+                #interrupt-cells = <1>;
                interrupt-map-mask = <0 0 63>;
                /* Active high IRQ 0 is connected to GIC's SPI0 */
                interrupt-map = <0 0 0 &gic 0 0 4>;
+                /include/ "vexpress-v2m-rs1.dtsi"
        };
 };
-/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
new file mode 100644
index 000000000000..37824fac688e
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
@@ -0,0 +1,14 @@
+* Samsung SATA PHY Controller
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
+- reg               : <registers mapping>
+Example:
+        sata@ffe07000 {
+                compatible = "samsung,exynos5-sata-phy";
+                reg = <0xffe07000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
new file mode 100644
index 000000000000..0849f1025e34
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -0,0 +1,17 @@
+* Samsung AHCI SATA Controller
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5-sata"
+- interrupts        : <interrupt mapping for SATA IRQ>
+- reg               : <registers mapping>
+- samsung,sata-freq : <frequency in MHz>
+Example:
+        sata@ffe08000 {
+                compatible = "samsung,exynos5-sata";
+                reg = <0xffe08000 0x1000>;
+                interrupts = <115>;
+        };
diff --git a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
index d2fe064a828b..63dd8051521c 100644
--- a/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
+++ b/Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
@@ -2,9 +2,27 @@
 properties:
 - compatible : Should be "ti,omap-ocp2scp"
+- reg : Address and length of the register set for the device
 - #address-cells, #size-cells : Must be present if the device has sub-nodes
 - ranges : the child address space are mapped 1:1 onto the parent address space
 - ti,hwmods : must be "ocp2scp_usb_phy"
 Sub-nodes:
 All the devices connected to ocp2scp are described using sub-node to ocp2scp
+ocp2scp@4a0ad000 {
+        compatible = "ti,omap-ocp2scp";
+        reg = <0x4a0ad000 0x1f>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        ti,hwmods = "ocp2scp_usb_phy";
+        subnode1 {
+        ...
+        };
+        subnode2 {
+        ...
+        };
+};
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
index a0b867ef8d96..baadbb11fe98 100644
--- a/Documentation/devicetree/bindings/clock/imx23-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -52,7 +52,7 @@ clocks and IDs.
        lcdif           38
        etm             39
        usb             40
-        usb_pwr         41
+        usb_phy         41
 Examples:
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
new file mode 100644
index 000000000000..c2a3525ecb4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -0,0 +1,162 @@
+* Clock bindings for Freescale i.MX25
+Required properties:
+- compatible: Should be "fsl,imx25-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX25
+clocks and IDs.
+        Clock                   ID
+        ---------------------------
+        dummy                   0
+        osc                     1
+        mpll                    2
+        upll                    3
+        mpll_cpu_3_4            4
+        cpu_sel                 5
+        cpu                     6
+        ahb                     7
+        usb_div                 8
+        ipg                     9
+        per0_sel                10
+        per1_sel                11
+        per2_sel                12
+        per3_sel                13
+        per4_sel                14
+        per5_sel                15
+        per6_sel                16
+        per7_sel                17
+        per8_sel                18
+        per9_sel                19
+        per10_sel               20
+        per11_sel               21
+        per12_sel               22
+        per13_sel               23
+        per14_sel               24
+        per15_sel               25
+        per0                    26
+        per1                    27
+        per2                    28
+        per3                    29
+        per4                    30
+        per5                    31
+        per6                    32
+        per7                    33
+        per8                    34
+        per9                    35
+        per10                   36
+        per11                   37
+        per12                   38
+        per13                   39
+        per14                   40
+        per15                   41
+        csi_ipg_per             42
+        epit_ipg_per            43
+        esai_ipg_per            44
+        esdhc1_ipg_per          45
+        esdhc2_ipg_per          46
+        gpt_ipg_per             47
+        i2c_ipg_per             48
+        lcdc_ipg_per            49
+        nfc_ipg_per             50
+        owire_ipg_per           51
+        pwm_ipg_per             52
+        sim1_ipg_per            53
+        sim2_ipg_per            54
+        ssi1_ipg_per            55
+        ssi2_ipg_per            56
+        uart_ipg_per            57
+        ata_ahb                 58
+        reserved                59
+        csi_ahb                 60
+        emi_ahb                 61
+        esai_ahb                62
+        esdhc1_ahb              63
+        esdhc2_ahb              64
+        fec_ahb                 65
+        lcdc_ahb                66
+        rtic_ahb                67
+        sdma_ahb                68
+        slcdc_ahb               69
+        usbotg_ahb              70
+        reserved                71
+        reserved                72
+        reserved                73
+        reserved                74
+        can1_ipg                75
+        can2_ipg                76
+        csi_ipg                 77
+        cspi1_ipg               78
+        cspi2_ipg               79
+        cspi3_ipg               80
+        dryice_ipg              81
+        ect_ipg                 82
+        epit1_ipg               83
+        epit2_ipg               84
+        reserved                85
+        esdhc1_ipg              86
+        esdhc2_ipg              87
+        fec_ipg                 88
+        reserved                89
+        reserved                90
+        reserved                91
+        gpt1_ipg                92
+        gpt2_ipg                93
+        gpt3_ipg                94
+        gpt4_ipg                95
+        reserved                96
+        reserved                97
+        reserved                98
+        iim_ipg                 99
+        reserved                100
+        reserved                101
+        kpp_ipg                 102
+        lcdc_ipg                103
+        reserved                104
+        pwm1_ipg                105
+        pwm2_ipg                106
+        pwm3_ipg                107
+        pwm4_ipg                108
+        rngb_ipg                109
+        reserved                110
+        scc_ipg                 111
+        sdma_ipg                112
+        sim1_ipg                113
+        sim2_ipg                114
+        slcdc_ipg               115
+        spba_ipg                116
+        ssi1_ipg                117
+        ssi2_ipg                118
+        tsc_ipg                 119
+        uart1_ipg               120
+        uart2_ipg               121
+        uart3_ipg               122
+        uart4_ipg               123
+        uart5_ipg               124
+        reserved                125
+        wdt_ipg                 126
+Examples:
+clks: ccm@53f80000 {
+        compatible = "fsl,imx25-ccm";
+        reg = <0x53f80000 0x4000>;
+        interrupts = <31>;
+        clock-output-names = ...
+                        "uart_ipg",
+                        "uart_serial",
+                        ...;
+};
+uart1: serial@43f90000 {
+        compatible = "fsl,imx25-uart", "fsl,imx21-uart";
+        reg = <0x43f90000 0x4000>;
+        interrupts = <45>;
+        clocks = <&clks 79>, <&clks 50>;
+        clock-names = "ipg", "per";
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
index aa2af2866fe8..52a49a4a50b3 100644
--- a/Documentation/devicetree/bindings/clock/imx28-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -73,8 +73,8 @@ clocks and IDs.
        can1            59
        usb0            60
        usb1            61
-        usb0_pwr        62
+        usb0_phy        62
-        usb1_pwr        63
+        usb1_phy        63
        enet_out        64
 Examples:
diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.txt b/Documentation/devicetree/bindings/clock/imx5-clock.txt
new file mode 100644
index 000000000000..04ad47876be0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.txt
@@ -0,0 +1,191 @@
+* Clock bindings for Freescale i.MX5
+Required properties:
+- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX5
+clocks and IDs.
+        Clock                   ID
+        ---------------------------
+        dummy                   0
+        ckil                    1
+        osc                     2
+        ckih1                   3
+        ckih2                   4
+        ahb                     5
+        ipg                     6
+        axi_a                   7
+        axi_b                   8
+        uart_pred               9
+        uart_root               10
+        esdhc_a_pred            11
+        esdhc_b_pred            12
+        esdhc_c_s               13
+        esdhc_d_s               14
+        emi_sel                 15
+        emi_slow_podf           16
+        nfc_podf                17
+        ecspi_pred              18
+        ecspi_podf              19
+        usboh3_pred             20
+        usboh3_podf             21
+        usb_phy_pred            22
+        usb_phy_podf            23
+        cpu_podf                24
+        di_pred                 25
+        tve_di                  26
+        tve_s                   27
+        uart1_ipg_gate          28
+        uart1_per_gate          29
+        uart2_ipg_gate          30
+        uart2_per_gate          31
+        uart3_ipg_gate          32
+        uart3_per_gate          33
+        i2c1_gate               34
+        i2c2_gate               35
+        gpt_ipg_gate            36
+        pwm1_ipg_gate           37
+        pwm1_hf_gate            38
+        pwm2_ipg_gate           39
+        pwm2_hf_gate            40
+        gpt_hf_gate             41
+        fec_gate                42
+        usboh3_per_gate         43
+        esdhc1_ipg_gate         44
+        esdhc2_ipg_gate         45
+        esdhc3_ipg_gate         46
+        esdhc4_ipg_gate         47
+        ssi1_ipg_gate           48
+        ssi2_ipg_gate           49
+        ssi3_ipg_gate           50
+        ecspi1_ipg_gate         51
+        ecspi1_per_gate         52
+        ecspi2_ipg_gate         53
+        ecspi2_per_gate         54
+        cspi_ipg_gate           55
+        sdma_gate               56
+        emi_slow_gate           57
+        ipu_s                   58
+        ipu_gate                59
+        nfc_gate                60
+        ipu_di1_gate            61
+        vpu_s                   62
+        vpu_gate                63
+        vpu_reference_gate      64
+        uart4_ipg_gate          65
+        uart4_per_gate          66
+        uart5_ipg_gate          67
+        uart5_per_gate          68
+        tve_gate                69
+        tve_pred                70
+        esdhc1_per_gate         71
+        esdhc2_per_gate         72
+        esdhc3_per_gate         73
+        esdhc4_per_gate         74
+        usb_phy_gate            75
+        hsi2c_gate              76
+        mipi_hsc1_gate          77
+        mipi_hsc2_gate          78
+        mipi_esc_gate           79
+        mipi_hsp_gate           80
+        ldb_di1_div_3_5         81
+        ldb_di1_div             82
+        ldb_di0_div_3_5         83
+        ldb_di0_div             84
+        ldb_di1_gate            85
+        can2_serial_gate        86
+        can2_ipg_gate           87
+        i2c3_gate               88
+        lp_apm                  89
+        periph_apm              90
+        main_bus                91
+        ahb_max                 92
+        aips_tz1                93
+        aips_tz2                94
+        tmax1                   95
+        tmax2                   96
+        tmax3                   97
+        spba                    98
+        uart_sel                99
+        esdhc_a_sel             100
+        esdhc_b_sel             101
+        esdhc_a_podf            102
+        esdhc_b_podf            103
+        ecspi_sel               104
+        usboh3_sel              105
+        usb_phy_sel             106
+        iim_gate                107
+        usboh3_gate             108
+        emi_fast_gate           109
+        ipu_di0_gate            110
+        gpc_dvfs                111
+        pll1_sw                 112
+        pll2_sw                 113
+        pll3_sw                 114
+        ipu_di0_sel             115
+        ipu_di1_sel             116
+        tve_ext_sel             117
+        mx51_mipi               118
+        pll4_sw                 119
+        ldb_di1_sel             120
+        di_pll4_podf            121
+        ldb_di0_sel             122
+        ldb_di0_gate            123
+        usb_phy1_gate           124
+        usb_phy2_gate           125
+        per_lp_apm              126
+        per_pred1               127
+        per_pred2               128
+        per_podf                129
+        per_root                130
+        ssi_apm                 131
+        ssi1_root_sel           132
+        ssi2_root_sel           133
+        ssi3_root_sel           134
+        ssi_ext1_sel            135
+        ssi_ext2_sel            136
+        ssi_ext1_com_sel        137
+        ssi_ext2_com_sel        138
+        ssi1_root_pred          139
+        ssi1_root_podf          140
+        ssi2_root_pred          141
+        ssi2_root_podf          142
+        ssi_ext1_pred           143
+        ssi_ext1_podf           144
+        ssi_ext2_pred           145
+        ssi_ext2_podf           146
+        ssi1_root_gate          147
+        ssi2_root_gate          148
+        ssi3_root_gate          149
+        ssi_ext1_gate           150
+        ssi_ext2_gate           151
+        epit1_ipg_gate          152
+        epit1_hf_gate           153
+        epit2_ipg_gate          154
+        epit2_hf_gate           155
+        can_sel                 156
+        can1_serial_gate        157
+        can1_ipg_gate           158
+Examples (for mx53):
+clks: ccm@53fd4000{
+        compatible = "fsl,imx53-ccm";
+        reg = <0x53fd4000 0x4000>;
+        interrupts = <0 71 0x04 0 72 0x04>;
+        #clock-cells = <1>;
+};
+can1: can@53fc8000 {
+        compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+        reg = <0x53fc8000 0x4000>;
+        interrupts = <82>;
+        clocks = <&clks 158>, <&clks 157>;
+        clock-names = "ipg", "per";
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 492bd991d52a..d77b4e68dc42 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -187,9 +187,9 @@ clocks and IDs.
        pll3_usb_otg            172
        pll4_audio              173
        pll5_video              174
-        pll6_mlb                175
+        pll8_mlb                175
        pll7_usb_host           176
-        pll8_enet               177
+        pll6_enet               177
        ssi1_ipg                178
        ssi2_ipg                179
        ssi3_ipg                180
@@ -198,6 +198,11 @@ clocks and IDs.
        usbphy2                 183
        ldb_di0_div_3_5         184
        ldb_di1_div_3_5         185
+        sata_ref                186
+        sata_ref_100m           187
+        pcie_ref                188
+        pcie_ref_125m           189
+        enet_ref                190
 Examples:
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
new file mode 100644
index 000000000000..23ae1db1bc13
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -0,0 +1,55 @@
+Device Tree Clock bindings for the Zynq 7000 EPP
+The Zynq EPP has several different clk providers, each with there own bindings.
+The purpose of this document is to document their usage.
+See clock_bindings.txt for more information on the generic clock bindings.
+See Chapter 25 of Zynq TRM for more information about Zynq clocks.
+== PLLs ==
+Used to describe the ARM_PLL, DDR_PLL, and IO_PLL.
+Required properties:
+- #clock-cells : shall be 0 (only one clock is output from this node)
+- compatible : "xlnx,zynq-pll"
+- reg : pair of u32 values, which are the address offsets within the SLCR
+        of the relevant PLL_CTRL register and PLL_CFG register respectively
+- clocks : phandle for parent clock.  should be the phandle for ps_clk
+Optional properties:
+- clock-output-names : name of the output clock
+Example:
+        armpll: armpll {
+                #clock-cells = <0>;
+                compatible = "xlnx,zynq-pll";
+                clocks = <&ps_clk>;
+                reg = <0x100 0x110>;
+                clock-output-names = "armpll";
+        };
+== Peripheral clocks ==
+Describes clock node for the SDIO, SMC, SPI, QSPI, and UART clocks.
+Required properties:
+- #clock-cells : shall be 1
+- compatible : "xlnx,zynq-periph-clock"
+- reg : a single u32 value, describing the offset within the SLCR where
+        the CLK_CTRL register is found for this peripheral
+- clocks : phandle for parent clocks.  should hold phandles for
+           the IO_PLL, ARM_PLL, and DDR_PLL in order
+- clock-output-names : names of the output clock(s).  For peripherals that have
+                       two output clocks (for example, the UART), two clocks
+                       should be listed.
+Example:
+        uart_clk: uart_clk {
+                #clock-cells = <1>;
+                compatible = "xlnx,zynq-periph-clock";
+                clocks = <&iopll &armpll &ddrpll>;
+                reg = <0x154>;
+                clock-output-names = "uart0_ref_clk",
+                                     "uart1_ref_clk";
+        };
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt
new file mode 100644
index 000000000000..f3d44984d91c
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-spear.txt
@@ -0,0 +1,42 @@
+SPEAr cpufreq driver
+-------------------
+SPEAr SoC cpufreq driver for CPU frequency scaling.
+It supports both uniprocessor (UP) and symmetric multiprocessor (SMP) systems
+which share clock across all CPUs.
+Required properties:
+- cpufreq_tbl: Table of frequencies CPU could be transitioned into, in the
+  increasing order.
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock, in
+  unit of nanoseconds.
+Both required and optional properties listed above must be defined under node
+/cpus/cpu@0.
+Examples:
+--------
+cpus {
+        <...>
+        cpu@0 {
+                compatible = "arm,cortex-a9";
+                reg = <0>;
+                <...>
+                cpufreq_tbl = < 166000
+                                200000
+                                250000
+                                300000
+                                400000
+                                500000
+                                600000 >;
+        };
+        <...>
+};
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmi.txt b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
new file mode 100644
index 000000000000..589edee37394
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmi.txt
@@ -0,0 +1,22 @@
+Device-Tree bindings for drm hdmi driver
+Required properties:
+- compatible: value should be "samsung,exynos5-hdmi".
+- reg: physical base address of the hdmi and length of memory mapped
+        region.
+- interrupts: interrupt number to the cpu.
+- hpd-gpio: following information about the hotplug gpio pin.
+        a) phandle of the gpio controller node.
+        b) pin number within the gpio controller.
+        c) pin function mode.
+        d) optional flags and pull up/down.
+        e) drive strength.
+Example:
+        hdmi {
+                compatible = "samsung,exynos5-hdmi";
+                reg = <0x14530000 0x100000>;
+                interrupts = <0 95 0>;
+                hpd-gpio = <&gpx3 7 0xf 1 3>;
+        };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
new file mode 100644
index 000000000000..fa166d945809
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmiddc.txt
@@ -0,0 +1,12 @@
+Device-Tree bindings for hdmiddc driver
+Required properties:
+- compatible: value should be "samsung,exynos5-hdmiddc".
+- reg: I2C address of the hdmiddc device.
+Example:
+        hdmiddc {
+                compatible = "samsung,exynos5-hdmiddc";
+                reg = <0x50>;
+        };
diff --git a/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
new file mode 100644
index 000000000000..858f4f9b902f
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/hdmiphy.txt
@@ -0,0 +1,12 @@
+Device-Tree bindings for hdmiphy driver
+Required properties:
+- compatible: value should be "samsung,exynos5-hdmiphy".
+- reg: I2C address of the hdmiphy device.
+Example:
+        hdmiphy {
+                compatible = "samsung,exynos5-hdmiphy";
+                reg = <0x38>;
+        };
diff --git a/Documentation/devicetree/bindings/drm/exynos/mixer.txt b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
new file mode 100644
index 000000000000..9b2ea0343566
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/exynos/mixer.txt
@@ -0,0 +1,15 @@
+Device-Tree bindings for mixer driver
+Required properties:
+- compatible: value should be "samsung,exynos5-mixer".
+- reg: physical base address of the mixer and length of memory mapped
+        region.
+- interrupts: interrupt number to the cpu.
+Example:
+        mixer {
+                compatible = "samsung,exynos5-mixer";
+                reg = <0x14450000 0x10000>;
+                interrupts = <0 94 0>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
new file mode 100644
index 000000000000..558cdf3c9abc
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-poweroff.txt
@@ -0,0 +1,22 @@
+GPIO line that should be set high/low to power off a device
+Required properties:
+- compatible : should be "gpio-poweroff".
+- gpios : The GPIO to set high/low, see "gpios property" in
+  Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be
+  low to power down the board set it to "Active Low", otherwise set
+  gpio to "Active High".
+Optional properties:
+- input : Initially configure the GPIO line as an input. Only reconfigure
+  it to an output when the pm_power_off function is called. If this optional
+  property is not specified, the GPIO is initialized as an output in its
+  inactive state.
+Examples:
+gpio-poweroff {
+        compatible = "gpio-poweroff";
+        gpios = <&gpio 4 0>; /* GPIO 4 Active Low */
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt b/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt
new file mode 100644
index 000000000000..a0e4cf885213
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-stmpe.txt
@@ -0,0 +1,18 @@
+STMPE gpio
+----------
+Required properties:
+ - compatible: "st,stmpe-gpio"
+Optional properties:
+ - st,norequest-mask: bitmask specifying which GPIOs should _not_ be requestable
+   due to different usage (e.g. touch, keypad)
+Node name must be stmpe_gpio and should be child node of stmpe node to which it
+belongs.
+Example:
+        stmpe_gpio {
+                compatible = "st,stmpe-gpio";
+                st,norequest-mask = <0x20>;     //gpio 5 can't be used
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index 4e16ba4feab0..a33628759d36 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -75,4 +75,40 @@ Example of two SOC GPIO banks defined as gpio-controller nodes:
                gpio-controller;
        };
+2.1) gpio-controller and pinctrl subsystem
+------------------------------------------
+gpio-controller on a SOC might be tightly coupled with the pinctrl
+subsystem, in the sense that the pins can be used by other functions
+together with optional gpio feature.
+While the pin allocation is totally managed by the pin ctrl subsystem,
+gpio (under gpiolib) is still maintained by gpio drivers. It may happen
+that different pin ranges in a SoC is managed by different gpio drivers.
+This makes it logical to let gpio drivers announce their pin ranges to
+the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
+request the corresponding pin before any gpio usage.
+For this, the gpio controller can use a pinctrl phandle and pins to
+announce the pinrange to the pin ctrl subsystem. For example,
+        qe_pio_e: gpio-controller@1460 {
+                #gpio-cells = <2>;
+                compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
+                reg = <0x1460 0x18>;
+                gpio-controller;
+                gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
+    }
+where,
+   &pinctrl1 and &pinctrl2 is the phandle to the pinctrl DT node.
+   Next values specify the base pin and number of pins for the range
+   handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
+   pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
+   by this gpio controller.
+The pinctrl node must have "#gpio-range-cells" property to show number of
+arguments to pass with phandle from gpio controllers node.
diff --git a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
index 66efc804806a..85f8c0d084fa 100644
--- a/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio_atmel.txt
@@ -9,6 +9,10 @@ Required properties:
  unused).
 - gpio-controller: Marks the device node as a GPIO controller.
+optional properties:
+- #gpio-lines: Number of gpio if absent 32.
 Example:
        pioA: gpio@fffff200 {
                compatible = "atmel,at91rm9200-gpio";
@@ -16,5 +20,6 @@ Example:
                interrupts = <2 4>;
                #gpio-cells = <2>;
                gpio-controller;
+                #gpio-lines = <19>;
        };
diff --git a/Documentation/devicetree/bindings/gpio/leds-ns2.txt b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
new file mode 100644
index 000000000000..aef3aca34d2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/leds-ns2.txt
@@ -0,0 +1,26 @@
+Binding for dual-GPIO LED found on Network Space v2 (and parents).
+Required properties:
+- compatible: "lacie,ns2-leds".
+Each LED is represented as a sub-node of the ns2-leds device.
+Required sub-node properties:
+- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification.
+- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification.
+Optional sub-node properties:
+- label: Name for this LED. If omitted, the label is taken from the node name.
+- linux,default-trigger: Trigger assigned to the LED.
+Example:
+ns2-leds {
+        compatible = "lacie,ns2-leds";
+        blue-sata {
+                label = "ns2:blue:sata";
+                slow-gpio = <&gpio0 29 0>;
+                cmd-gpio = <&gpio0 30 0>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/gpio/spear_spics.txt b/Documentation/devicetree/bindings/gpio/spear_spics.txt
new file mode 100644
index 000000000000..96c37eb15075
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/spear_spics.txt
@@ -0,0 +1,50 @@
+=== ST Microelectronics SPEAr SPI CS Driver ===
+SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
+Cell spi controller through its system registers, which otherwise remains under
+PL022 control. If chipselect remain under PL022 control then they would be
+released as soon as transfer is over and TxFIFO becomes empty. This is not
+desired by some of the device protocols above spi which expect (multiple)
+transfers without releasing their chipselects.
+Chipselects can be controlled by software by turning them as GPIOs. SPEAr
+provides another interface through system registers through which software can
+directly control each PL022 chipselect. Hence, it is natural for SPEAr to export
+the control of this interface as gpio.
+Required properties:
+  * compatible: should be defined as "st,spear-spics-gpio"
+  * reg: mentioning address range of spics controller
+  * st-spics,peripcfg-reg: peripheral configuration register offset
+  * st-spics,sw-enable-bit: bit offset to enable sw control
+  * st-spics,cs-value-bit: bit offset to drive chipselect low or high
+  * st-spics,cs-enable-mask: chip select number bit mask
+  * st-spics,cs-enable-shift: chip select number program offset
+  * gpio-controller: Marks the device node as gpio controller
+  * #gpio-cells: should be 1 and will mention chip select number
+All the above bit offsets are within peripcfg register.
+Example:
+-------
+spics: spics@e0700000{
+        compatible = "st,spear-spics-gpio";
+        reg = <0xe0700000 0x1000>;
+        st-spics,peripcfg-reg = <0x3b0>;
+        st-spics,sw-enable-bit = <12>;
+        st-spics,cs-value-bit = <11>;
+        st-spics,cs-enable-mask = <3>;
+        st-spics,cs-enable-shift = <8>;
+        gpio-controller;
+        #gpio-cells = <2>;
+};
+spi0: spi@e0100000 {
+        status = "okay";
+        num-cs = <3>;
+        cs-gpios = <&gpio1 7 0>, <&spics 0>,
+                   <&spics 1>;
+        ...
+}
diff --git a/Documentation/devicetree/bindings/hwmon/vexpress.txt b/Documentation/devicetree/bindings/hwmon/vexpress.txt
new file mode 100644
index 000000000000..9c27ed694bbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/vexpress.txt
@@ -0,0 +1,23 @@
+Versatile Express hwmon sensors
+-------------------------------
+Requires node properties:
+- "compatible" value : one of
+        "arm,vexpress-volt"
+        "arm,vexpress-amp"
+        "arm,vexpress-temp"
+        "arm,vexpress-power"
+        "arm,vexpress-energy"
+- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
+  (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
+  for more details)
+Optional node properties:
+- label : string describing the monitored value
+Example:
+        energy@0 {
+                compatible = "arm,vexpress-energy";
+                arm,vexpress-sysreg,func = <13 0>;
+                label = "A15 Jcore";
+        };
diff --git a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
index b689a0d9441c..b689a0d9441c 100644
--- a/Documentation/devicetree/bindings/i2c/atmel-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-at91.txt
diff --git a/Documentation/devicetree/bindings/i2c/davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
index 2dc935b4113d..2dc935b4113d 100644
--- a/Documentation/devicetree/bindings/i2c/davinci.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
diff --git a/Documentation/devicetree/bindings/i2c/gpio-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
index 4f8ec947c6bd..4f8ec947c6bd 100644
--- a/Documentation/devicetree/bindings/i2c/gpio-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-gpio.txt
diff --git a/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
index f3cf43b66f7e..3614242e7732 100644
--- a/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
@@ -12,13 +12,13 @@ Optional properties:
 Examples:
 i2c@83fc4000 { /* I2C2 on i.MX51 */
-        compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+        compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
        reg = <0x83fc4000 0x4000>;
        interrupts = <63>;
 };
 i2c@70038000 { /* HS-I2C on i.MX51 */
-        compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+        compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
        reg = <0x70038000 0x4000>;
        interrupts = <64>;
        clock-frequency = <400000>;
diff --git a/Documentation/devicetree/bindings/i2c/fsl-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-mpc.txt
index 1eacd6b20ed5..1eacd6b20ed5 100644
--- a/Documentation/devicetree/bindings/i2c/fsl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mpc.txt
diff --git a/Documentation/devicetree/bindings/i2c/mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt
index af84cce5cd7b..af84cce5cd7b 100644
--- a/Documentation/devicetree/bindings/i2c/mux.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux.txt
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
new file mode 100644
index 000000000000..f46d928aa73d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt
@@ -0,0 +1,18 @@
+* Marvell MV64XXX I2C controller
+Required properties :
+ - reg             : Offset and length of the register set for the device
+ - compatible      : Should be "marvell,mv64xxx-i2c"
+ - interrupts      : The interrupt number
+ - clock-frequency : Desired I2C bus clock frequency in Hz.
+Examples:
+        i2c@11000 {
+                compatible = "marvell,mv64xxx-i2c";
+                reg = <0x11000 0x20>;
+                interrupts = <29>;
+                clock-frequency = <100000>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
index 72065b0ff680..72065b0ff680 100644
--- a/Documentation/devicetree/bindings/i2c/nomadik.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt
diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
index dced82ebe31d..dced82ebe31d 100644
--- a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
diff --git a/Documentation/devicetree/bindings/i2c/omap-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
index 56564aa4b444..56564aa4b444 100644
--- a/Documentation/devicetree/bindings/i2c/omap-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-omap.txt
diff --git a/Documentation/devicetree/bindings/i2c/pnx.txt b/Documentation/devicetree/bindings/i2c/i2c-pnx.txt
index fe98ada33ee4..fe98ada33ee4 100644
--- a/Documentation/devicetree/bindings/i2c/pnx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-pnx.txt
diff --git a/Documentation/devicetree/bindings/i2c/ce4100-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
index 569b16248514..569b16248514 100644
--- a/Documentation/devicetree/bindings/i2c/ce4100-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-pxa-pci-ce4100.txt
diff --git a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
index 0f7945019f6f..12b78ac507e9 100644
--- a/Documentation/devicetree/bindings/i2c/mrvl-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
@@ -31,21 +31,3 @@ Examples:
                reg = <0xd4025000 0x1000>;
                interrupts = <58>;
        };
-* Marvell MV64XXX I2C controller
-Required properties :
- - reg             : Offset and length of the register set for the device
- - compatible      : Should be "marvell,mv64xxx-i2c"
- - interrupts      : The interrupt number
- - clock-frequency : Desired I2C bus clock frequency in Hz.
-Examples:
-        i2c@11000 {
-                compatible = "marvell,mv64xxx-i2c";
-                reg = <0x11000 0x20>;
-                interrupts = <29>;
-                clock-frequency = <100000>;
-        };
diff --git a/Documentation/devicetree/bindings/i2c/samsung-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
index b6cb5a12c672..b6cb5a12c672 100644
--- a/Documentation/devicetree/bindings/i2c/samsung-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
diff --git a/Documentation/devicetree/bindings/i2c/sirf-i2c.txt b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
index 7baf9e133fa8..7baf9e133fa8 100644
--- a/Documentation/devicetree/bindings/i2c/sirf-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-sirf.txt
diff --git a/Documentation/devicetree/bindings/i2c/arm-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
index 361d31c51b6f..361d31c51b6f 100644
--- a/Documentation/devicetree/bindings/i2c/arm-versatile.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt
diff --git a/Documentation/devicetree/bindings/i2c/xiic.txt b/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
index ceabbe91ae44..ceabbe91ae44 100644
--- a/Documentation/devicetree/bindings/i2c/xiic.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-xiic.txt
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 2f5322b119eb..446859fcdca4 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -55,5 +55,7 @@ st-micro,24c256		i2c serial eeprom  (24cxx)
 stm,m41t00              Serial Access TIMEKEEPER
 stm,m41t62              Serial real-time clock (RTC) with alarm
 stm,m41t80              M41T80 - SERIAL ACCESS RTC WITH ALARMS
+taos,tsl2550            Ambient Light Sensor with SMBUS/Two Wire Serial Interface
 ti,tsc2003              I2C Touch-Screen Controller
 ti,tmp102               Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
+ti,tmp275               Digital Temperature Sensor
diff --git a/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
new file mode 100644
index 000000000000..ca5a2c86480c
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/bu21013.txt
@@ -0,0 +1,28 @@
+* Rohm BU21013 Touch Screen
+Required properties:
+ - compatible              : "rohm,bu21013_tp"
+ - reg                     :  I2C device address
+Optional properties:
+ - touch-gpio              : GPIO pin registering a touch event
+ - <supply_name>-supply    : Phandle to a regulator supply
+ - rohm,touch-max-x        : Maximum outward permitted limit in the X axis
+ - rohm,touch-max-y        : Maximum outward permitted limit in the Y axis
+ - rohm,flip-x             : Flip touch coordinates on the X axis
+ - rohm,flip-y             : Flip touch coordinates on the Y axis
+Example:
+        i2c@80110000 {
+                bu21013_tp@0x5c {
+                        compatible = "rohm,bu21013_tp";
+                        reg = <0x5c>;
+                        touch-gpio = <&gpio2 20 0x4>;
+                        avdd-supply = <&ab8500_ldo_aux1_reg>;
+                        rohm,touch-max-x = <384>;
+                        rohm,touch-max-y = <704>;
+                        rohm,flip-y;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
new file mode 100644
index 000000000000..7f9fb85f5456
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
@@ -0,0 +1,104 @@
+Allwinner Sunxi Interrupt Controller
+Required properties:
+- compatible : should be "allwinner,sunxi-ic"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+The interrupt sources are as follows:
+0: ENMI
+1: UART0
+2: UART1
+3: UART2
+4: UART3
+5: IR0
+6: IR1
+7: I2C0
+8: I2C1
+9: I2C2
+10: SPI0
+11: SPI1
+12: SPI2
+13: SPDIF
+14: AC97
+15: TS
+16: I2S
+17: UART4
+18: UART5
+19: UART6
+20: UART7
+21: KEYPAD
+22: TIMER0
+23: TIMER1
+24: TIMER2
+25: TIMER3
+26: CAN
+27: DMA
+28: PIO
+29: TOUCH_PANEL
+30: AUDIO_CODEC
+31: LRADC
+32: SDMC0
+33: SDMC1
+34: SDMC2
+35: SDMC3
+36: MEMSTICK
+37: NAND
+38: USB0
+39: USB1
+40: USB2
+41: SCR
+42: CSI0
+43: CSI1
+44: LCDCTRL0
+45: LCDCTRL1
+46: MP
+47: DEFEBE0
+48: DEFEBE1
+49: PMU
+50: SPI3
+51: TZASC
+52: PATA
+53: VE
+54: SS
+55: EMAC
+56: SATA
+57: GPS
+58: HDMI
+59: TVE
+60: ACE
+61: TVD
+62: PS2_0
+63: PS2_1
+64: USB3
+65: USB4
+66: PLE_PFM
+67: TIMER4
+68: TIMER5
+69: GPU_GP
+70: GPU_GPMMU
+71: GPU_PP0
+72: GPU_PPMMU0
+73: GPU_PMU
+74: GPU_RSV0
+75: GPU_RSV1
+76: GPU_RSV2
+77: GPU_RSV3
+78: GPU_RSV4
+79: GPU_RSV5
+80: GPU_RSV6
+82: SYNC_TIMER0
+83: SYNC_TIMER1
+Example:
+intc: interrupt-controller {
+        compatible = "allwinner,sunxi-ic";
+        reg = <0x01c20400 0x400>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt
new file mode 100644
index 000000000000..2d88816dd550
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/common.txt
@@ -0,0 +1,23 @@
+Common leds properties.
+Optional properties for child nodes:
+- label : The label for this LED.  If omitted, the label is
+  taken from the node name (excluding the unit address).
+- linux,default-trigger :  This parameter, if present, is a
+    string defining the trigger assigned to the LED.  Current triggers are:
+     "backlight" - LED will act as a back-light, controlled by the framebuffer
+                   system
+     "default-on" - LED will turn on (but for leds-gpio see "default-state"
+                    property in Documentation/devicetree/bindings/gpio/led.txt)
+     "heartbeat" - LED "double" flashes at a load average based rate
+     "ide-disk" - LED indicates disk activity
+     "timer" - LED flashes at a fixed, configurable rate
+Examples:
+system-status {
+        label = "Status";
+        linux,default-trigger = "heartbeat";
+        ...
+};
diff --git a/Documentation/devicetree/bindings/gpio/led.txt b/Documentation/devicetree/bindings/leds/leds-gpio.txt
index edc83c1c0d54..df1b3080f6b8 100644
--- a/Documentation/devicetree/bindings/gpio/led.txt
+++ b/Documentation/devicetree/bindings/leds/leds-gpio.txt
@@ -10,16 +10,10 @@ LED sub-node properties:
 - gpios :  Should specify the LED's GPIO, see "gpios property" in
  Documentation/devicetree/bindings/gpio/gpio.txt.  Active low LEDs should be
  indicated using flags in the GPIO specifier.
- label :  (optional) The label for this LED.  If omitted, the label is
+- label :  (optional)
-  taken from the node name (excluding the unit address).
+  see Documentation/devicetree/bindings/leds/common.txt
- linux,default-trigger :  (optional) This parameter, if present, is a
+- linux,default-trigger :  (optional)
-  string defining the trigger assigned to the LED.  Current triggers are:
+  see Documentation/devicetree/bindings/leds/common.txt
-    "backlight" - LED will act as a back-light, controlled by the framebuffer
-                  system
-    "default-on" - LED will turn on, but see "default-state" below
-    "heartbeat" - LED "double" flashes at a load average based rate
-    "ide-disk" - LED indicates disk activity
-    "timer" - LED flashes at a fixed, configurable rate
 - default-state:  (optional) The initial state of the LED.  Valid
  values are "on", "off", and "keep".  If the LED is already on or off
  and the default-state property is set the to same value, then no
diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt
new file mode 100644
index 000000000000..67ec3d4ccc7f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -0,0 +1,23 @@
+* Samsung Multi Format Codec (MFC)
+Multi Format Codec (MFC) is the IP present in Samsung SoCs which
+supports high resolution decoding and encoding functionalities.
+The MFC device driver is a v4l2 driver which can encode/decode
+video raw/elementary streams and has support for all popular
+video codecs.
+Required properties:
+  - compatible : value should be either one among the following
+        (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs
+        (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs
+  - reg : Physical base address of the IP registers and length of memory
+          mapped region.
+  - interrupts : MFC interrupt number to the CPU.
+  - samsung,mfc-r : Base address of the first memory bank used by MFC
+                    for DMA contiguous memory allocation and its size.
+  - samsung,mfc-l : Base address of the second memory bank used by MFC
+                    for DMA contiguous memory allocation and its size.
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
index ce83c8d3c00e..13b707b7355c 100644
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -24,7 +24,32 @@ ab8500-bm                :                      :              : Battery Manager
 ab8500-btemp             :                      :              : Battery Temperature
 ab8500-charger           :                      :              : Battery Charger
 ab8500-codec             :                      :              : Audio Codec
-ab8500-fg                :                      :              : Fuel Gauge
+ab8500-fg                :                      : vddadc       : Fuel Gauge
+                         : NCONV_ACCU           :              : Accumulate N Sample Conversion
+                         : BATT_OVV             :              : Battery Over Voltage
+                         : LOW_BAT_F            :              : LOW threshold battery voltage
+                         : CC_INT_CALIB         :              : Coulomb Counter Internal Calibration
+                         : CCEOC                :              : Coulomb Counter End of Conversion
+ab8500-btemp             :                      : vtvout       : Battery Temperature
+                         : BAT_CTRL_INDB        :              : Battery Removal Indicator
+                         : BTEMP_LOW            :              : Btemp < BtempLow, if battery temperature is lower than -10°C
+                         : BTEMP_LOW_MEDIUM     :              : BtempLow < Btemp < BtempMedium,if battery temperature is between -10 and 0°C
+                         : BTEMP_MEDIUM_HIGH    :              : BtempMedium < Btemp < BtempHigh,if battery temperature is between 0°C and“MaxTemp
+                         : BTEMP_HIGH           :              : Btemp > BtempHigh, if battery temperature is higher than “MaxTemp
+ab8500-charger           :                      : vddadc       : Charger interface
+                         : MAIN_CH_UNPLUG_DET   :              : main charger unplug detection management (not in 8505)
+                         : MAIN_CHARGE_PLUG_DET :              : main charger plug detection management (not in 8505)
+                         : MAIN_EXT_CH_NOT_OK   :              : main charger not OK
+                         : MAIN_CH_TH_PROT_R    :              : Die temp is above main charger
+                         : MAIN_CH_TH_PROT_F    :              : Die temp is below main charger
+                         : VBUS_DET_F           :              : VBUS falling detected
+                         : VBUS_DET_R           :              : VBUS rising detected
+                         : USB_LINK_STATUS      :              : USB link status has changed
+                         : USB_CH_TH_PROT_R     :              : Die temp is above usb charger
+                         : USB_CH_TH_PROT_F     :              : Die temp is below usb charger
+                         : USB_CHARGER_NOT_OKR  :              : allowed USB charger not ok detection
+                         : VBUS_OVV             :              : Overvoltage on Vbus ball detected (USB charge is stopped)
+                         : CH_WD_EXP            :              : Charger watchdog detected
 ab8500-gpadc             : HW_CONV_END          : vddadc       : Analogue to Digital Converter
                           SW_CONV_END          :              :
 ab8500-gpio              :                      :              : GPIO Controller
diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
new file mode 100644
index 000000000000..38e51ad2e07e
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -0,0 +1,15 @@
+* Atmel SSC driver.
+Required properties:
+- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
+        - atmel,at91rm9200-ssc: support pdc transfer
+        - atmel,at91sam9g45-ssc: support dma transfer
+- reg: Should contain SSC registers location and length
+- interrupts: Should contain SSC interrupt
+Example:
+ssc0: ssc@fffbc000 {
+        compatible = "atmel,at91rm9200-ssc";
+        reg = <0xfffbc000 0x4000>;
+        interrupts = <14 4 5>;
+};
diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
index 8e2e0ba2f486..a591c6741d75 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -21,6 +21,12 @@ Optional properties:
 - cd-inverted: when present, polarity on the cd gpio line is inverted
 - wp-inverted: when present, polarity on the wp gpio line is inverted
 - max-frequency: maximum operating clock frequency
+- no-1-8-v: when present, denotes that 1.8v card voltage is not supported on
+  this system, even if the controller claims it is.
+Optional SDIO properties:
+- keep-power-in-suspend: Preserves card power during a suspend/resume cycle
+- enable-sdio-wakeup: Enables wake up of host system on SDIO IRQ assertion
 Example:
@@ -33,4 +39,6 @@ sdhci@ab000000 {
        cd-inverted;
        wp-gpios = <&gpio 70 0>;
        max-frequency = <50000000>;
+        keep-power-in-suspend;
+        enable-sdio-wakeup;
 }
diff --git a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
index 630a7d7f4718..97e9e315400d 100644
--- a/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/samsung-sdhci.txt
@@ -12,10 +12,6 @@ is used. The Samsung's SDHCI controller bindings extends this as listed below.
 [A] The property "samsung,cd-pinmux-gpio" can be used as stated in the
    "Optional Board Specific Properties" section below.
-[B] If core card-detect bindings and "samsung,cd-pinmux-gpio" property
-    is not specified, it is assumed that there is no card detection
-    mechanism used.
 Required SoC Specific Properties:
 - compatible: should be one of the following
  - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci
@@ -24,14 +20,18 @@ Required SoC Specific Properties:
    controller.
 Required Board Specific Properties:
- gpios: Should specify the gpios used for clock, command and data lines. The
+- Samsung GPIO variant (will be completely replaced by pinctrl):
-  gpio specifier format depends on the gpio controller.
+  - gpios: Should specify the gpios used for clock, command and data lines. The
+    gpio specifier format depends on the gpio controller.
+- Pinctrl variant (preferred if available):
+  - pinctrl-0: Should specify pin control groups used for this controller.
+  - pinctrl-names: Should contain only one value - "default".
 Optional Board Specific Properties:
 - samsung,cd-pinmux-gpio: Specifies the card detect line that is routed
  through a pinmux to the card-detect pin of the card slot. This property
  should be used only if none of the mmc core card-detect properties are
-  used.
+  used. Only for Samsung GPIO variant.
 Example:
        sdhci@12530000 {
@@ -40,12 +40,18 @@ Example:
                interrupts = <0 75 0>;
                bus-width = <4>;
                cd-gpios = <&gpk2 2 2 3 3>;
+                /* Samsung GPIO variant */
                gpios = <&gpk2 0 2 0 3>,  /* clock line */
                        <&gpk2 1 2 0 3>,  /* command line */
                        <&gpk2 3 2 3 3>,  /* data line 0 */
                        <&gpk2 4 2 3 3>,  /* data line 1 */
                        <&gpk2 5 2 3 3>,  /* data line 2 */
                        <&gpk2 6 2 3 3>;  /* data line 3 */
+                /* Pinctrl variant */
+                pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
+                pinctrl-names = "default";
        };
        Note: This example shows both SoC specific and board specific properties
diff --git a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
index 06cd32d08052..06cd32d08052 100644
--- a/Documentation/devicetree/bindings/mmc/synposis-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/synopsis-dw-mshc.txt
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index be76a23b34c4..ed271fc255b2 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -19,6 +19,7 @@ ti,dual-volt: boolean, supports dual voltage cards
 "supply-name" examples are "vmmc", "vmmc_aux" etc
 ti,non-removable: non-removable slot (like eMMC)
 ti,needs-special-reset: Requires a special softreset sequence
+ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
 Example:
        mmc1: mmc@0x4809c000 {
diff --git a/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt
new file mode 100644
index 000000000000..d7fb6abb3eb8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/vt8500-sdmmc.txt
@@ -0,0 +1,23 @@
+* Wondermedia WM8505/WM8650 SD/MMC Host Controller
+This file documents differences between the core properties described
+by mmc.txt and the properties used by the wmt-sdmmc driver.
+Required properties:
+- compatible: Should be "wm,wm8505-sdhc".
+- interrupts: Two interrupts are required - regular irq and dma irq.
+Optional properties:
+- sdon-inverted: SD_ON bit is inverted on the controller
+Examples:
+sdhc@d800a000 {
+        compatible = "wm,wm8505-sdhc";
+        reg = <0xd800a000 0x1000>;
+        interrupts = <20 21>;
+        clocks = <&sdhc>;
+        bus-width = <4>;
+        sdon-inverted;
+};
diff --git a/Documentation/devicetree/bindings/net/can/grcan.txt b/Documentation/devicetree/bindings/net/can/grcan.txt
new file mode 100644
index 000000000000..34ef3498f887
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/grcan.txt
@@ -0,0 +1,28 @@
+Aeroflex Gaisler GRCAN and GRHCAN CAN controllers.
+The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
+library.
+Note: These properties are built from the AMBA plug&play in a Leon SPARC system
+(the ordinary environment for GRCAN and GRHCAN). There are no dts files for
+sparc.
+Required properties:
+- name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
+- reg : Address and length of the register set for the device
+- freq : Frequency of the external oscillator clock in Hz (the frequency of
+        the amba bus in the ordinary case)
+- interrupts : Interrupt number for this device
+Optional properties:
+- systemid : If not present or if the value of the least significant 16 bits
+        of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
+        a bug workaround is activated.
+For further information look in the documentation for the GLIB IP core library:
+http://www.gaisler.com/products/grlib/grip.pdf
diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt b/Documentation/devicetree/bindings/net/cdns-emac.txt
new file mode 100644
index 000000000000..09055c2495f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/cdns-emac.txt
@@ -0,0 +1,23 @@
+* Cadence EMAC Ethernet controller
+Required properties:
+- compatible: Should be "cdns,[<chip>-]{emac}"
+  Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
+  or the generic form: "cdns,emac".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
+- phy-mode: String, operation mode of the PHY interface.
+  Supported values are: "mii", "rmii".
+Optional properties:
+- local-mac-address: 6 bytes, mac address
+Examples:
+        macb0: ethernet@fffc4000 {
+                compatible = "cdns,at91rm9200-emac";
+                reg = <0xfffc4000 0x4000>;
+                interrupts = <21>;
+                phy-mode = "rmii";
+                local-mac-address = [3a 0e 03 04 05 06];
+        };
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index dcaabe9fe869..6ddd0286a9b7 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -9,21 +9,15 @@ Required properties:
                          number
 - interrupt-parent      : The parent interrupt controller
 - cpdma_channels        : Specifies number of channels in CPDMA
- host_port_no          : Specifies host port shift
- cpdma_reg_ofs         : Specifies CPDMA submodule register offset
- cpdma_sram_ofs        : Specifies CPDMA SRAM offset
- ale_reg_ofs           : Specifies ALE submodule register offset
 - ale_entries           : Specifies No of entries ALE can hold
- host_port_reg_ofs     : Specifies host port register offset
- hw_stats_reg_ofs      : Specifies hardware statistics register offset
- bd_ram_ofs            : Specifies internal desciptor RAM offset
 - bd_ram_size           : Specifies internal descriptor RAM size
 - rx_descs              : Specifies number of Rx descriptors
 - mac_control           : Specifies Default MAC control register content
                          for the specific platform
 - slaves                : Specifies number for slaves
- slave_reg_ofs         : Specifies slave register offset
+- cpts_active_slave     : Specifies the slave to use for time stamping
- sliver_reg_ofs        : Specifies slave sliver register offset
+- cpts_clock_mult       : Numerator to convert input clock ticks into nanoseconds
+- cpts_clock_shift      : Denominator to convert input clock ticks into nanoseconds
 - phy_id                : Specifies slave phy id
 - mac-address           : Specifies slave MAC address
@@ -45,30 +39,22 @@ Examples:
                interrupts = <55 0x4>;
                interrupt-parent = <&intc>;
                cpdma_channels = <8>;
-                host_port_no = <0>;
-                cpdma_reg_ofs = <0x800>;
-                cpdma_sram_ofs = <0xa00>;
-                ale_reg_ofs = <0xd00>;
                ale_entries = <1024>;
-                host_port_reg_ofs = <0x108>;
-                hw_stats_reg_ofs = <0x900>;
-                bd_ram_ofs = <0x2000>;
                bd_ram_size = <0x2000>;
                no_bd_ram = <0>;
                rx_descs = <64>;
                mac_control = <0x20>;
                slaves = <2>;
+                cpts_active_slave = <0>;
+                cpts_clock_mult = <0x80000000>;
+                cpts_clock_shift = <29>;
                cpsw_emac0: slave@0 {
-                        slave_reg_ofs = <0x208>;
+                        phy_id = <&davinci_mdio>, <0>;
-                        sliver_reg_ofs = <0xd80>;
-                        phy_id = "davinci_mdio.16:00";
                        /* Filled in by U-Boot */
                        mac-address = [ 00 00 00 00 00 00 ];
                };
                cpsw_emac1: slave@1 {
-                        slave_reg_ofs = <0x308>;
+                        phy_id = <&davinci_mdio>, <1>;
-                        sliver_reg_ofs = <0xdc0>;
-                        phy_id = "davinci_mdio.16:01";
                        /* Filled in by U-Boot */
                        mac-address = [ 00 00 00 00 00 00 ];
                };
@@ -79,30 +65,22 @@ Examples:
                compatible = "ti,cpsw";
                ti,hwmods = "cpgmac0";
                cpdma_channels = <8>;
-                host_port_no = <0>;
-                cpdma_reg_ofs = <0x800>;
-                cpdma_sram_ofs = <0xa00>;
-                ale_reg_ofs = <0xd00>;
                ale_entries = <1024>;
-                host_port_reg_ofs = <0x108>;
-                hw_stats_reg_ofs = <0x900>;
-                bd_ram_ofs = <0x2000>;
                bd_ram_size = <0x2000>;
                no_bd_ram = <0>;
                rx_descs = <64>;
                mac_control = <0x20>;
                slaves = <2>;
+                cpts_active_slave = <0>;
+                cpts_clock_mult = <0x80000000>;
+                cpts_clock_shift = <29>;
                cpsw_emac0: slave@0 {
-                        slave_reg_ofs = <0x208>;
+                        phy_id = <&davinci_mdio>, <0>;
-                        sliver_reg_ofs = <0xd80>;
-                        phy_id = "davinci_mdio.16:00";
                        /* Filled in by U-Boot */
                        mac-address = [ 00 00 00 00 00 00 ];
                };
                cpsw_emac1: slave@1 {
-                        slave_reg_ofs = <0x308>;
+                        phy_id = <&davinci_mdio>, <1>;
-                        sliver_reg_ofs = <0xdc0>;
-                        phy_id = "davinci_mdio.16:01";
                        /* Filled in by U-Boot */
                        mac-address = [ 00 00 00 00 00 00 ];
                };
diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
new file mode 100644
index 000000000000..3a268127b054
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
@@ -0,0 +1,141 @@
+* Atmel AT91 Pinmux Controller
+The AT91 Pinmux Controler, enables the IC
+to share one PAD to several functional blocks. The sharing is done by
+multiplexing the PAD input/output signals. For each PAD there are up to
+8 muxing options (called periph modes). Since different modules require
+different PAD settings (like pull up, keeper, etc) the contoller controls
+also the PAD settings parameters.
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+Atmel AT91 pin configuration node is a node of a group of pins which can be
+used for a specific device or function. This node represents both mux and config
+of the pins in that group. The 'pins' selects the function mode(also named pin
+mode) this pin can work on and the 'config' configures various pad settings
+such as pull-up, multi drive, etc.
+Required properties for iomux controller:
+- compatible: "atmel,at91rm9200-pinctrl"
+- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
+  configured in this periph mode. All the periph and bank need to be describe.
+How to create such array:
+Each column will represent the possible peripheral of the pinctrl
+Each line will represent a pio bank
+Take an example on the 9260
+Peripheral: 2 ( A and B)
+Bank: 3 (A, B and C)
+=>
+  /*    A         B     */
+  0xffffffff 0xffc00c3b  /* pioA */
+  0xffffffff 0x7fff3ccf  /* pioB */
+  0xffffffff 0x007fffff  /* pioC */
+For each peripheral/bank we will descibe in a u32 if a pin can can be
+configured in it by putting 1 to the pin bit (1 << pin)
+Let's take the pioA on peripheral B
+From the datasheet Table 10-2.
+Peripheral B
+PA0     MCDB0
+PA1     MCCDB
+PA2
+PA3     MCDB3
+PA4     MCDB2
+PA5     MCDB1
+PA6
+PA7
+PA8
+PA9
+PA10    ETX2
+PA11    ETX3
+PA12
+PA13
+PA14
+PA15
+PA16
+PA17
+PA18
+PA19
+PA20
+PA21
+PA22    ETXER
+PA23    ETX2
+PA24    ETX3
+PA25    ERX2
+PA26    ERX3
+PA27    ERXCK
+PA28    ECRS
+PA29    ECOL
+PA30    RXD4
+PA31    TXD4
+=> 0xffc00c3b
+Required properties for pin configuration node:
+- atmel,pins: 4 integers array, represents a group of pins mux and config
+  setting. The format is atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
+  The PERIPH 0 means gpio.
+Bits used for CONFIG:
+PULL_UP         (1 << 0): indicate this pin need a pull up.
+MULTIDRIVE      (1 << 1): indicate this pin need to be configured as multidrive.
+DEGLITCH        (1 << 2): indicate this pin need deglitch.
+PULL_DOWN       (1 << 3): indicate this pin need a pull down.
+DIS_SCHMIT      (1 << 4): indicate this pin need to disable schmit trigger.
+DEBOUNCE        (1 << 16): indicate this pin need debounce.
+DEBOUNCE_VAL    (0x3fff << 17): debounce val.
+NOTE:
+Some requirements for using atmel,at91rm9200-pinctrl binding:
+1. We have pin function node defined under at91 controller node to represent
+   what pinmux functions this SoC supports.
+2. The driver can use the function node's name and pin configuration node's
+   name describe the pin function and group hierarchy.
+   For example, Linux at91 pinctrl driver takes the function node's name
+   as the function name and pin configuration node's name as group name to
+   create the map table.
+3. Each pin configuration node should have a phandle, devices can set pins
+   configurations by referring to the phandle of that pin configuration node.
+4. The gpio controller must be describe in the pinctrl simple-bus.
+Examples:
+pinctrl@fffff400 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
+        reg = <0xfffff400 0x600>;
+        atmel,mux-mask = <
+              /*    A         B     */
+               0xffffffff 0xffc00c3b  /* pioA */
+               0xffffffff 0x7fff3ccf  /* pioB */
+               0xffffffff 0x007fffff  /* pioC */
+              >;
+        /* shared pinctrl settings */
+        dbgu {
+                pinctrl_dbgu: dbgu-0 {
+                        atmel,pins =
+                                <1 14 0x1 0x0   /* PB14 periph A */
+                                 1 15 0x1 0x1>; /* PB15 periph with pullup */
+                };
+        };
+};
+dbgu: serial@fffff200 {
+        compatible = "atmel,at91sam9260-usart";
+        reg = <0xfffff200 0x200>;
+        interrupts = <1 4 7>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_dbgu>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 361bccb7ec89..95daf6335c37 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -7,8 +7,10 @@ Required properties:
 - compatible: "marvell,88f6180-pinctrl",
              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+              "marvell,98dx4122-pinctrl"
 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
@@ -277,3 +279,40 @@ mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
 mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
 mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
 mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
+* Marvell Bobcat 98dx4122
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd)
+mpp5          5        gpo, nand(io7), uart0(txd)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, pex(rsto), spi(cs)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts)
+mpp10         10       gpo, spi(sck), uart0(txd)
+mpp11         11       gpio, spi(miso), uart0(rxd)
+mpp13         13       gpio, uart1(txd)
+mpp14         14       gpio, uart1(rxd)
+mpp15         15       gpio, uart0(rts)
+mpp16         16       gpio, uart0(cts)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp34         34       gpio
+mpp35         35       gpio
+mpp36         36       gpio
+mpp37         37       gpio
+mpp38         38       gpio
+mpp39         39       gpio
+mpp40         40       gpio
+mpp41         41       gpio
+mpp42         42       gpio
+mpp43         43       gpio
+mpp44         44       gpio
+mpp45         45       gpio
+mpp49         49       gpio
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 03dee50532f5..e97a27856b21 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -8,13 +8,20 @@ on-chip controllers onto these pads.
 Required Properties:
 - compatible: should be one of the following.
  - "samsung,pinctrl-exynos4210": for Exynos4210 compatible pin-controller.
+  - "samsung,pinctrl-exynos4x12": for Exynos4x12 compatible pin-controller.
  - "samsung,pinctrl-exynos5250": for Exynos5250 compatible pin-controller.
 - reg: Base address of the pin controller hardware module and length of
  the address space it occupies.
- interrupts: interrupt specifier for the controller. The format and value of
+- Pin banks as child nodes: Pin banks of the controller are represented by child
-  the interrupt specifier depends on the interrupt parent for the controller.
+  nodes of the controller node. Bank name is taken from name of the node. Each
+  bank node must contain following properties:
+  - gpio-controller: identifies the node as a gpio controller and pin bank.
+  - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
+    binding is used, the amount of cells must be specified as 2. See generic
+    GPIO binding documentation for description of particular cells.
 - Pin mux/config groups as child nodes: The pin mux (selecting pin function
  mode) and pin config (pull up/down, driver strength) settings are represented
@@ -72,16 +79,24 @@ used as system wakeup events.
 A. External GPIO Interrupts: For supporting external gpio interrupts, the
   following properties should be specified in the pin-controller device node.
- interrupt-controller: identifies the controller node as interrupt-parent.
+   - interrupt-parent: phandle of the interrupt parent to which the external
- #interrupt-cells: the value of this property should be 2.
+     GPIO interrupts are forwarded to.
-  - First Cell: represents the external gpio interrupt number local to the
+   - interrupts: interrupt specifier for the controller. The format and value of
-    external gpio interrupt space of the controller.
+     the interrupt specifier depends on the interrupt parent for the controller.
-  - Second Cell: flags to identify the type of the interrupt
-    - 1 = rising edge triggered
+   In addition, following properties must be present in node of every bank
-    - 2 = falling edge triggered
+   of pins supporting GPIO interrupts:
-    - 3 = rising and falling edge triggered
-    - 4 = high level triggered
+   - interrupt-controller: identifies the controller node as interrupt-parent.
-    - 8 = low level triggered
+   - #interrupt-cells: the value of this property should be 2.
+     - First Cell: represents the external gpio interrupt number local to the
+       external gpio interrupt space of the controller.
+     - Second Cell: flags to identify the type of the interrupt
+       - 1 = rising edge triggered
+       - 2 = falling edge triggered
+       - 3 = rising and falling edge triggered
+       - 4 = high level triggered
+       - 8 = low level triggered
 B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
   child node representing the external wakeup interrupt controller should be
@@ -94,6 +109,11 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
       found on Samsung Exynos4210 SoC.
   - interrupt-parent: phandle of the interrupt parent to which the external
     wakeup interrupts are forwarded to.
+   - interrupts: interrupt used by multiplexed wakeup interrupts.
+   In addition, following properties must be present in node of every bank
+   of pins supporting wake-up interrupts:
   - interrupt-controller: identifies the node as interrupt-parent.
   - #interrupt-cells: the value of this property should be 2
     - First Cell: represents the external wakeup interrupt number local to
@@ -105,11 +125,63 @@ B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
       - 4 = high level triggered
       - 8 = low level triggered
+   Node of every bank of pins supporting direct wake-up interrupts (without
+   multiplexing) must contain following properties:
+   - interrupt-parent: phandle of the interrupt parent to which the external
+     wakeup interrupts are forwarded to.
+   - interrupts: interrupts of the interrupt parent which are used for external
+     wakeup interrupts from pins of the bank, must contain interrupts for all
+     pins of the bank.
 Aliases:
 All the pin controller nodes should be represented in the aliases node using
 the following format 'pinctrl{n}' where n is a unique number for the alias.
+Example: A pin-controller node with pin banks:
+        pinctrl_0: pinctrl@11400000 {
+                compatible = "samsung,pinctrl-exynos4210";
+                reg = <0x11400000 0x1000>;
+                interrupts = <0 47 0>;
+                /* ... */
+                /* Pin bank without external interrupts */
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+                /* ... */
+                /* Pin bank with external GPIO or muxed wake-up interrupts */
+                gpj0: gpj0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+                /* ... */
+                /* Pin bank with external direct wake-up interrupts */
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                     <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
+                        #interrupt-cells = <2>;
+                };
+                /* ... */
+        };
 Example 1: A pin-controller node with pin groups.
        pinctrl_0: pinctrl@11400000 {
@@ -117,6 +189,8 @@ Example 1: A pin-controller node with pin groups.
                reg = <0x11400000 0x1000>;
                interrupts = <0 47 0>;
+                /* ... */
                uart0_data: uart0-data {
                        samsung,pins = "gpa0-0", "gpa0-1";
                        samsung,pin-function = <2>;
@@ -158,20 +232,14 @@ Example 2: A pin-controller node with external wakeup interrupt controller node.
        pinctrl_1: pinctrl@11000000 {
                compatible = "samsung,pinctrl-exynos4210";
                reg = <0x11000000 0x1000>;
-                interrupts = <0 46 0>;
+                interrupts = <0 46 0>
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                wakup_eint: wakeup-interrupt-controller {
+                /* ... */
+                wakeup-interrupt-controller {
                        compatible = "samsung,exynos4210-wakeup-eint";
                        interrupt-parent = <&gic>;
-                        interrupt-controller;
+                        interrupts = <0 32 0>;
-                        #interrupt-cells = <2>;
-                        interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                        <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                                        <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                                        <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>,
-                                        <0 32 0>;
                };
        };
@@ -190,7 +258,8 @@ Example 4: Set up the default pin state for uart controller.
        static int s3c24xx_serial_probe(struct platform_device *pdev) {
                struct pinctrl *pinctrl;
-                ...
-                ...
+                /* ... */
                pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
        }
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt b/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt
new file mode 100644
index 000000000000..0ba1bcc7f33a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/ab8500/btemp.txt
@@ -0,0 +1,16 @@
+=== AB8500 Battery Temperature Monitor Driver ===
+The properties below describes the node for btemp driver.
+Required Properties:
+- compatible = Shall be: "stericsson,ab8500-btemp"
+- battery = Shall be battery specific information
+        Example:
+        ab8500_btemp {
+                compatible = "stericsson,ab8500-btemp";
+                battery    = <&ab8500_battery>;
+        };
+For information on battery specific node, Ref:
+Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt b/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt
new file mode 100644
index 000000000000..ef5328371122
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/ab8500/chargalg.txt
@@ -0,0 +1,16 @@
+=== AB8500 Charging Algorithm Driver ===
+The properties below describes the node for chargalg driver.
+Required Properties:
+- compatible = Shall be: "stericsson,ab8500-chargalg"
+- battery = Shall be battery specific information
+Example:
+ab8500_chargalg {
+        compatible = "stericsson,ab8500-chargalg";
+        battery    = <&ab8500_battery>;
+};
+For information on battery specific node, Ref:
+Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt b/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt
new file mode 100644
index 000000000000..6bdbb08ea9e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/ab8500/charger.txt
@@ -0,0 +1,25 @@
+=== AB8500 Charger Driver ===
+Required Properties:
+- compatible = Shall be "stericsson,ab8500-charger"
+- battery = Shall be battery specific information
+        Example:
+        ab8500_charger {
+                compatible = "stericsson,ab8500-charger";
+                battery    = <&ab8500_battery>;
+        };
+- vddadc-supply: Supply for USB and Main charger
+        Example:
+        ab8500-charger {
+                vddadc-supply   = <&ab8500_ldo_tvout_reg>;
+        }
+- autopower_cfg:
+        Boolean value depicting the presence of 'automatic poweron after powerloss'
+        Example:
+        ab8500-charger {
+                autopower_cfg;
+        };
+For information on battery specific node, Ref:
+Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
diff --git a/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt b/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
new file mode 100644
index 000000000000..ccafcb9112fb
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/ab8500/fg.txt
@@ -0,0 +1,58 @@
+=== AB8500 Fuel Gauge Driver ===
+AB8500 is a mixed signal multimedia and power management
+device comprising: power and energy-management-module,
+wall-charger, usb-charger, audio codec, general purpose adc,
+tvout, clock management and sim card interface.
+Fuelgauge support is part of energy-management-modules, other
+components of this module are:
+main-charger, usb-combo-charger and battery-temperature-monitoring.
+The properties below describes the node for fuelgauge driver.
+Required Properties:
+- compatible = This shall be: "stericsson,ab8500-fg"
+- battery = Shall be battery specific information
+        Example:
+        ab8500_fg {
+                compatible = "stericsson,ab8500-fg";
+                battery    = <&ab8500_battery>;
+        };
+dependent node:
+        ab8500_battery: ab8500_battery {
+        };
+        This node will provide information on 'thermistor interface' and
+        'battery technology type' used.
+Properties of this node are:
+thermistor-on-batctrl:
+        A boolean value indicating thermistor interface to battery
+        Note:
+        'btemp' and 'batctrl' are the pins interfaced for battery temperature
+        measurement, 'btemp' signal is used when NTC(negative temperature
+        coefficient) resister is interfaced external to battery whereas
+        'batctrl' pin is used when NTC resister is internal to battery.
+        Example:
+        ab8500_battery: ab8500_battery {
+                thermistor-on-batctrl;
+        };
+        indicates: NTC resister is internal to battery, 'batctrl' is used
+                for thermal measurement.
+        The absence of property 'thermal-on-batctrl' indicates
+        NTC resister is external to battery and  'btemp' signal is used
+        for thermal measurement.
+battery-type:
+        This shall be the battery manufacturing technology type,
+        allowed types are:
+                "UNKNOWN" "NiMH" "LION" "LIPO" "LiFe" "NiCd" "LiMn"
+        Example:
+        ab8500_battery: ab8500_battery {
+                stericsson,battery-type = "LIPO";
+        }
diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
new file mode 100644
index 000000000000..63c659800c03
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
@@ -0,0 +1,37 @@
+GPIO controlled regulators
+Required properties:
+- compatible            : Must be "regulator-gpio".
+- states                : Selection of available voltages and GPIO configs.
+                          if there are no states, then use a fixed regulator
+Optional properties:
+- enable-gpio           : GPIO to use to enable/disable the regulator.
+- gpios                 : GPIO group used to control voltage.
+- startup-delay-us      : Startup time in microseconds.
+- enable-active-high    : Polarity of GPIO is active high (default is low).
+Any property defined as part of the core regulator binding defined in
+regulator.txt can also be used.
+Example:
+        mmciv: gpio-regulator {
+                compatible = "regulator-gpio";
+                regulator-name = "mmci-gpio-supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <2600000>;
+                regulator-boot-on;
+                enable-gpio = <&gpio0 23 0x4>;
+                gpios = <&gpio0 24 0x4
+                         &gpio0 25 0x4>;
+                states = <1800000 0x3
+                          2200000 0x2
+                          2600000 0x1
+                          2900000 0x0>;
+                startup-delay-us = <100000>;
+                enable-active-high;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/max8925-regulator.txt b/Documentation/devicetree/bindings/regulator/max8925-regulator.txt
new file mode 100644
index 000000000000..0057695aae8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8925-regulator.txt
@@ -0,0 +1,40 @@
+Max8925 Voltage regulators
+Required nodes:
+-nodes:
+  - SDV1 for SDV SDV1
+  - SDV2 for SDV SDV2
+  - SDV3 for SDV SDV3
+  - LDO1 for LDO LDO1
+  - LDO2 for LDO LDO2
+  - LDO3 for LDO LDO3
+  - LDO4 for LDO LDO4
+  - LDO5 for LDO LDO5
+  - LDO6 for LDO LDO6
+  - LDO7 for LDO LDO7
+  - LDO8 for LDO LDO8
+  - LDO9 for LDO LDO9
+  - LDO10 for LDO LDO10
+  - LDO11 for LDO LDO11
+  - LDO12 for LDO LDO12
+  - LDO13 for LDO LDO13
+  - LDO14 for LDO LDO14
+  - LDO15 for LDO LDO15
+  - LDO16 for LDO LDO16
+  - LDO17 for LDO LDO17
+  - LDO18 for LDO LDO18
+  - LDO19 for LDO LDO19
+  - LDO20 for LDO LDO20
+Optional properties:
+- Any optional property defined in bindings/regulator/regulator.txt
+Example:
+        SDV1 {
+                regulator-min-microvolt = <637500>;
+                regulator-max-microvolt = <1425000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/max8997-regulator.txt b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
new file mode 100644
index 000000000000..9fd69a18b0ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/max8997-regulator.txt
@@ -0,0 +1,146 @@
+* Maxim MAX8997 Voltage and Current Regulator
+The Maxim MAX8997 is a multi-function device which includes volatage and
+current regulators, rtc, charger controller and other sub-blocks. It is
+interfaced to the host controller using a i2c interface. Each sub-block is
+addressed by the host system using different i2c slave address. This document
+describes the bindings for 'pmic' sub-block of max8997.
+Required properties:
+- compatible: Should be "maxim,max8997-pmic".
+- reg: Specifies the i2c slave address of the pmic block. It should be 0x66.
+- max8997,pmic-buck1-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck1 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+- max8997,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck2 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+- max8997,pmic-buck5-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
+  units for buck5 when changing voltage using gpio dvs. Refer to [1] below
+  for additional information.
+[1] If none of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+    property is specified, the 'max8997,pmic-buck[1/2/5]-dvs-voltage'
+    property should specify atleast one voltage level (which would be a
+    safe operating voltage).
+    If either of the 'max8997,pmic-buck[1/2/5]-uses-gpio-dvs' optional
+    property is specified, then all the eigth voltage values for the
+    'max8997,pmic-buck[1/2/5]-dvs-voltage' should be specified.
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from max8997 are delivered to.
+- interrupts: Interrupt specifiers for two interrupt sources.
+  - First interrupt specifier is for 'irq1' interrupt.
+  - Second interrupt specifier is for 'alert' interrupt.
+- max8997,pmic-buck1-uses-gpio-dvs: 'buck1' can be controlled by gpio dvs.
+- max8997,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
+- max8997,pmic-buck5-uses-gpio-dvs: 'buck5' can be controlled by gpio dvs.
+Additional properties required if either of the optional properties are used:
+- max8997,pmic-ignore-gpiodvs-side-effect: When GPIO-DVS mode is used for
+  multiple bucks, changing the voltage value of one of the bucks may affect
+  that of another buck, which is the side effect of the change (set_voltage).
+  Use this property to ignore such side effects and change the voltage.
+- max8997,pmic-buck125-default-dvs-idx: Default voltage setting selected from
+  the possible 8 options selectable by the dvs gpios. The value of this
+  property should be between 0 and 7. If not specified or if out of range, the
+  default value of this property is set to 0.
+- max8997,pmic-buck125-dvs-gpios: GPIO specifiers for three host gpio's used
+  for dvs. The format of the gpio specifier depends in the gpio controller.
+Regulators: The regulators of max8997 that have to be instantiated should be
+included in a sub-node named 'regulators'. Regulator nodes included in this
+sub-node should be of the format as listed below.
+        regulator_name {
+                standard regulator bindings here
+        };
+The following are the names of the regulators that the max8997 pmic block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of max8997.
+        - LDOn
+                  - valid values for n are 1 to 18 and 21
+                  - Example: LDO0, LD01, LDO2, LDO21
+        - BUCKn
+                  - valid values for n are 1 to 7.
+                  - Example: BUCK1, BUCK2, BUCK3, BUCK7
+        - ENVICHG: Battery Charging Current Monitor Output. This is a fixed
+                   voltage type regulator
+        - ESAFEOUT1: (ldo19)
+        - ESAFEOUT2: (ld020)
+        - CHARGER_CV: main battery charger voltage control
+        - CHARGER: main battery charger current control
+        - CHARGER_TOPOFF: end of charge current threshold level
+The bindings inside the regulator nodes use the standard regulator bindings
+which are documented elsewhere.
+Example:
+        max8997_pmic@66 {
+                compatible = "maxim,max8997-pmic";
+                interrupt-parent = <&wakeup_eint>;
+                reg = <0x66>;
+                interrupts = <4 0>, <3 0>;
+                max8997,pmic-buck1-uses-gpio-dvs;
+                max8997,pmic-buck2-uses-gpio-dvs;
+                max8997,pmic-buck5-uses-gpio-dvs;
+                max8997,pmic-ignore-gpiodvs-side-effect;
+                max8997,pmic-buck125-default-dvs-idx = <0>;
+                max8997,pmic-buck125-dvs-gpios = <&gpx0 0 1 0 0>, /* SET1 */
+                                                 <&gpx0 1 1 0 0>, /* SET2 */
+                                                 <&gpx0 2 1 0 0>; /* SET3 */
+                max8997,pmic-buck1-dvs-voltage = <1350000>, <1300000>,
+                                                 <1250000>, <1200000>,
+                                                 <1150000>, <1100000>,
+                                                 <1000000>, <950000>;
+                max8997,pmic-buck2-dvs-voltage = <1100000>, <1100000>,
+                                                 <1100000>, <1100000>,
+                                                 <1000000>, <1000000>,
+                                                 <1000000>, <1000000>;
+                max8997,pmic-buck5-dvs-voltage = <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>,
+                                                 <1200000>, <1200000>;
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VDD_ABB_3.3V";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VDD_ALIVE_1.1V";
+                                regulator-min-microvolt = <1100000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-always-on;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "VDD_ARM_1.2V";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/vexpress.txt b/Documentation/devicetree/bindings/regulator/vexpress.txt
new file mode 100644
index 000000000000..d775f72487aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/vexpress.txt
@@ -0,0 +1,32 @@
+Versatile Express voltage regulators
+------------------------------------
+Requires node properties:
+- "compatible" value: "arm,vexpress-volt"
+- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
+  (see Documentation/devicetree/bindings/arm/vexpress-sysreg.txt
+  for more details)
+Required regulator properties:
+- "regulator-name"
+- "regulator-always-on"
+Optional regulator properties:
+- "regulator-min-microvolt"
+- "regulator-max-microvolt"
+See Documentation/devicetree/bindings/regulator/regulator.txt
+for more details about the regulator properties.
+When no "regulator-[min|max]-microvolt" properties are defined,
+the device is treated as fixed (or rather "read-only") regulator.
+Example:
+        volt@0 {
+                compatible = "arm,vexpress-volt";
+                arm,vexpress-sysreg,func = <2 0>;
+                regulator-name = "Cores";
+                regulator-min-microvolt = <800000>;
+                regulator-max-microvolt = <1050000>;
+                regulator-always-on;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
new file mode 100644
index 000000000000..93f45e9dce7c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nvidia,tegra20-rtc.txt
@@ -0,0 +1,19 @@
+NVIDIA Tegra20 real-time clock
+The Tegra RTC maintains seconds and milliseconds counters, and five alarm
+registers. The alarms and other interrupts may wake the system from low-power
+state.
+Required properties:
+- compatible : should be "nvidia,tegra20-rtc".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A single interrupt specifier.
+Example:
+timer {
+        compatible = "nvidia,tegra20-rtc";
+        reg = <0x7000e000 0x100>;
+        interrupts = <0 2 0x04>;
+};
diff --git a/Documentation/devicetree/bindings/rtc/orion-rtc.txt b/Documentation/devicetree/bindings/rtc/orion-rtc.txt
new file mode 100644
index 000000000000..3bf63ffa5160
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/orion-rtc.txt
@@ -0,0 +1,18 @@
+* Mvebu Real Time Clock
+RTC controller for the Kirkwood, the Dove, the Armada 370 and the
+Armada XP SoCs
+Required properties:
+- compatible : Should be "marvell,orion-rtc"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: IRQ line for the RTC.
+Example:
+rtc@10300 {
+        compatible = "marvell,orion-rtc";
+        reg = <0xd0010300 0x20>;
+        interrupts = <50>;
+};
diff --git a/Documentation/devicetree/bindings/sound/ak4104.txt b/Documentation/devicetree/bindings/sound/ak4104.txt
new file mode 100644
index 000000000000..b902ee39cf89
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ak4104.txt
@@ -0,0 +1,22 @@
+AK4104 S/PDIF transmitter
+This device supports SPI mode only.
+Required properties:
+  - compatible : "asahi-kasei,ak4104"
+  - reg : The chip select number on the SPI bus
+Optional properties:
+  - reset-gpio : a GPIO spec for the reset pin. If specified, it will be
+                 deasserted before communication to the device starts.
+Example:
+spdif: ak4104@0 {
+        compatible = "asahi-kasei,ak4104";
+        reg = <0>;
+        spi-max-frequency = <5000000>;
+};
diff --git a/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt b/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt
new file mode 100644
index 000000000000..9c5a9947b64d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt
@@ -0,0 +1,26 @@
+* Atmel at91sam9g20ek wm8731 audio complex
+Required properties:
+  - compatible: "atmel,at91sam9g20ek-wm8731-audio"
+  - atmel,model: The user-visible name of this sound complex.
+  - atmel,audio-routing: A list of the connections between audio components.
+  - atmel,ssc-controller: The phandle of the SSC controller
+  - atmel,audio-codec: The phandle of the WM8731 audio codec
+Optional properties:
+  - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
+Example:
+sound {
+        compatible = "atmel,at91sam9g20ek-wm8731-audio";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pck0_as_mck>;
+        atmel,model = "wm8731 @ AT91SAMG20EK";
+        atmel,audio-routing =
+                "Ext Spk", "LHPOUT",
+                "Int MIC", "MICIN";
+        atmel,ssc-controller = <&ssc0>;
+        atmel,audio-codec = <&wm8731>;
+};
diff --git a/Documentation/devicetree/bindings/sound/cs4271.txt b/Documentation/devicetree/bindings/sound/cs4271.txt
index c81b5fd5a5bc..a850fb9c88ea 100644
--- a/Documentation/devicetree/bindings/sound/cs4271.txt
+++ b/Documentation/devicetree/bindings/sound/cs4271.txt
@@ -18,6 +18,8 @@ Optional properties:
 - reset-gpio:  a GPIO spec to define which pin is connected to the chip's
                !RESET pin
+ - cirrus,amuteb-eq-bmutec:     When given, the Codec's AMUTEB=BMUTEC flag
+                                is enabled.
 Examples:
diff --git a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
index 65dec876cb2d..fd40c852d7c7 100644
--- a/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
+++ b/Documentation/devicetree/bindings/sound/omap-abe-twl6040.txt
@@ -12,7 +12,7 @@ Required properties:
 Optional properties:
 - ti,dmic: phandle for the OMAP dmic node if the machine have it connected
- ti,jack_detection: Need to be set to <1> if the board capable to detect jack
+- ti,jack_detection: Need to be present if the board capable to detect jack
  insertion, removal.
 Available audio endpoints for the audio-routing table:
@@ -59,7 +59,7 @@ sound {
        compatible = "ti,abe-twl6040";
        ti,model = "SDP4430";
-        ti,jack-detection = <1>;
+        ti,jack-detection;
        ti,mclk-freq = <38400000>;
        ti,mcpdm = <&mcpdm>;
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
new file mode 100644
index 000000000000..8cf24f6f0a99
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt
@@ -0,0 +1,26 @@
+NVIDIA Tegra20 SFLASH controller.
+Required properties:
+- compatible : should be "nvidia,tegra20-sflash".
+- reg: Should contain SFLASH registers location and length.
+- interrupts: Should contain SFLASH interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this SFLASH controller.
+Recommended properties:
+- spi-max-frequency: Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+Example:
+spi@7000d600 {
+        compatible = "nvidia,tegra20-sflash";
+        reg = <0x7000c380 0x80>;
+        interrupts = <0 39 0x04>;
+        nvidia,dma-request-selector = <&apbdma 16>;
+        spi-max-frequency = <25000000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
new file mode 100644
index 000000000000..f5b1ad1a1ec3
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-slink.txt
@@ -0,0 +1,26 @@
+NVIDIA Tegra20/Tegra30 SLINK controller.
+Required properties:
+- compatible : should be "nvidia,tegra20-slink", "nvidia,tegra30-slink".
+- reg: Should contain SLINK registers location and length.
+- interrupts: Should contain SLINK interrupts.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this SLINK controller.
+Recommended properties:
+- spi-max-frequency: Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+Example:
+slink@7000d600 {
+        compatible = "nvidia,tegra20-slink";
+        reg = <0x7000d600 0x200>;
+        interrupts = <0 82 0x04>;
+        nvidia,dma-request-selector = <&apbdma 16>;
+        spi-max-frequency = <25000000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/spi/omap-spi.txt b/Documentation/devicetree/bindings/spi/omap-spi.txt
index 81df374adbb9..938809c6829b 100644
--- a/Documentation/devicetree/bindings/spi/omap-spi.txt
+++ b/Documentation/devicetree/bindings/spi/omap-spi.txt
@@ -6,7 +6,9 @@ Required properties:
  - "ti,omap4-spi" for OMAP4+.
 - ti,spi-num-cs : Number of chipselect supported  by the instance.
 - ti,hwmods: Name of the hwmod associated to the McSPI
+- ti,pindir-d0-out-d1-in: Select the D0 pin as output and D1 as
+                          input. The default is D0 as input and
+                          D1 as output.
 Example:
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt
index d2c33d0f533e..296015e3c632 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -12,6 +12,7 @@ The SPI master node requires the following properties:
 - #size-cells     - should be zero.
 - compatible      - name of SPI bus controller following generic names
                recommended practice.
+- cs-gpios        - (optional) gpios chip select.
 No other properties are required in the SPI bus node.  It is assumed
 that a driver for an SPI bus device will understand that it is an SPI bus.
 However, the binding does not attempt to define the specific method for
@@ -24,6 +25,22 @@ support describing the chip select layout.
 Optional property:
 - num-cs : total number of chipselects
+If cs-gpios is used the number of chip select will automatically increased
+with max(cs-gpios > hw cs)
+So if for example the controller has 2 CS lines, and the cs-gpios
+property looks like this:
+cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
+Then it should be configured so that num_chipselect = 4 with the
+following mapping:
+cs0 : &gpio1 0 0
+cs1 : native
+cs2 : &gpio1 1 0
+cs3 : &gpio1 2 0
 SPI slave nodes must be children of the SPI master node and can
 contain the following properties.
 - reg             - (required) chip select address of device.
@@ -36,6 +53,11 @@ contain the following properties.
                shifted clock phase (CPHA) mode
 - spi-cs-high     - (optional) Empty property indicating device requires
                chip select active high
+- spi-3wire       - (optional) Empty property indicating device requires
+                    3-wire mode.
+If a gpio chipselect is used for the SPI slave the gpio number will be passed
+via the cs_gpio
 SPI example for an MPC5200 SPI bus:
        spi@f00 {
diff --git a/Documentation/devicetree/bindings/thermal/db8500-thermal.txt b/Documentation/devicetree/bindings/thermal/db8500-thermal.txt
new file mode 100644
index 000000000000..2e1c06fad81f
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/db8500-thermal.txt
@@ -0,0 +1,44 @@
+* ST-Ericsson DB8500 Thermal
+** Thermal node properties:
+- compatible : "stericsson,db8500-thermal";
+- reg : address range of the thermal sensor registers;
+- interrupts : interrupts generated from PRCMU;
+- interrupt-names : "IRQ_HOTMON_LOW" and "IRQ_HOTMON_HIGH";
+- num-trips : number of total trip points, this is required, set it 0 if none,
+  if greater than 0, the following properties must be defined;
+- tripN-temp : temperature of trip point N, should be in ascending order;
+- tripN-type : type of trip point N, should be one of "active" "passive" "hot"
+  "critical";
+- tripN-cdev-num : number of the cooling devices which can be bound to trip
+  point N, this is required if trip point N is defined, set it 0 if none,
+  otherwise the following cooling device names must be defined;
+- tripN-cdev-nameM : name of the No. M cooling device of trip point N;
+Usually the num-trips and tripN-*** are separated in board related dts files.
+Example:
+thermal@801573c0 {
+        compatible = "stericsson,db8500-thermal";
+        reg = <0x801573c0 0x40>;
+        interrupts = <21 0x4>, <22 0x4>;
+        interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
+        num-trips = <3>;
+        trip0-temp = <75000>;
+        trip0-type = "active";
+        trip0-cdev-num = <1>;
+        trip0-cdev-name0 = "thermal-cpufreq-0";
+        trip1-temp = <80000>;
+        trip1-type = "active";
+        trip1-cdev-num = <2>;
+        trip1-cdev-name0 = "thermal-cpufreq-0";
+        trip1-cdev-name1 = "thermal-fan";
+        trip2-temp = <85000>;
+        trip2-type = "critical";
+        trip2-cdev-num = <0>;
+}
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
new file mode 100644
index 000000000000..0c7b64e95a61
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
@@ -0,0 +1,17 @@
+Allwinner A1X SoCs Timer Controller
+Required properties:
+- compatible : should be "allwinner,sunxi-timer"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : The interrupt of the first timer
+- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
+Example:
+timer {
+        compatible = "allwinner,sunxi-timer";
+        reg = <0x01c20c00 0x400>;
+        interrupts = <22>;
+        clocks = <&osc>;
+};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
new file mode 100644
index 000000000000..e019fdc38773
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra20-timer.txt
@@ -0,0 +1,21 @@
+NVIDIA Tegra20 timer
+The Tegra20 timer provides four 29-bit timer channels and a single 32-bit free
+running counter. The first two channels may also trigger a watchdog reset.
+Required properties:
+- compatible : should be "nvidia,tegra20-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 4 interrupts; one per timer channel.
+Example:
+timer {
+        compatible = "nvidia,tegra20-timer";
+        reg = <0x60005000 0x60>;
+        interrupts = <0 0 0x04
+                        0 1 0x04
+                        0 41 0x04
+                        0 42 0x04>;
+};
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
new file mode 100644
index 000000000000..906109d4c593
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra30-timer.txt
@@ -0,0 +1,23 @@
+NVIDIA Tegra30 timer
+The Tegra30 timer provides ten 29-bit timer channels, a single 32-bit free
+running counter, and 5 watchdog modules. The first two channels may also
+trigger a legacy watchdog reset.
+Required properties:
+- compatible : should be "nvidia,tegra30-timer", "nvidia,tegra20-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 6 interrupts; one per each of timer channels 1
+    through 5, and one for the shared interrupt for the remaining channels.
+timer {
+        compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
+        reg = <0x60005000 0x400>;
+        interrupts = <0 0 0x04
+                      0 1 0x04
+                      0 41 0x04
+                      0 42 0x04
+                      0 121 0x04
+                      0 122 0x04>;
+};
diff --git a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
index 2ee903fad25c..273a8d5b3300 100644
--- a/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
+++ b/Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
@@ -6,11 +6,19 @@ Required properties:
 - reg : Address and length of the register set for the device
 - interrupts : Should contain the auart interrupt numbers
+Optional properties:
+- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other
+                is for TX. If you add this property, it also means that you
+                will enable the DMA support for the auart.
+                Note: due to the hardware bug in imx23(see errata : 2836),
+                only the imx28 can enable the DMA support for the auart.
 Example:
 auart0: serial@8006a000 {
        compatible = "fsl,imx28-auart", "fsl,imx23-auart";
        reg = <0x8006a000 0x2000>;
        interrupts = <112 70 71>;
+        fsl,auart-dma-channel = <8 9>;
 };
 Note: Each auart port should have an alias correctly numbered in "aliases"
diff --git a/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
index ba385f2e0ddc..1e1145ca4f3c 100644
--- a/Documentation/devicetree/bindings/tty/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/tty/serial/of-serial.txt
@@ -14,7 +14,10 @@ Required properties:
        - "serial" if the port type is unknown.
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
- clock-frequency : the input clock frequency for the UART.
+- clock-frequency : the input clock frequency for the UART
+         or
+  clocks phandle to refer to the clk used as per Documentation/devicetree
+  /bindings/clock/clock-bindings.txt
 Optional properties:
 - current-speed : the current active speed of the UART.
diff --git a/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
index ca8fa56e9f03..ea840f7f9258 100644
--- a/Documentation/devicetree/bindings/usb/am33xx-usb.txt
+++ b/Documentation/devicetree/bindings/usb/am33xx-usb.txt
@@ -1,14 +1,35 @@
 AM33XX MUSB GLUE
 - compatible : Should be "ti,musb-am33xx"
+ - reg : offset and length of register sets, first usbss, then for musb instances
+ - interrupts : usbss, musb instance interrupts in order
 - ti,hwmods : must be "usb_otg_hs"
 - multipoint : Should be "1" indicating the musb controller supports
   multipoint. This is a MUSB configuration-specific setting.
- - num_eps : Specifies the number of endpoints. This is also a
+ - num-eps : Specifies the number of endpoints. This is also a
   MUSB configuration-specific setting. Should be set to "16"
- - ram_bits : Specifies the ram address size. Should be set to "12"
+ - ram-bits : Specifies the ram address size. Should be set to "12"
- - port0_mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
+ - port0-mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
   represents PERIPHERAL.
- - port1_mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
+ - port1-mode : Should be "1" to represent HOST. "3" signifies OTG and "2"
   represents PERIPHERAL.
 - power : Should be "250". This signifies the controller can supply upto
   500mA when operating in host mode.
+Example:
+usb@47400000  {
+        compatible = "ti,musb-am33xx";
+        reg = <0x47400000 0x1000        /* usbss */
+               0x47401000 0x800         /* musb instance 0 */
+               0x47401800 0x800>;       /* musb instance 1 */
+        interrupts = <17                /* usbss */
+                      18                /* musb instance 0 */
+                      19>;              /* musb instance 1 */
+        multipoint = <1>;
+        num-eps = <16>;
+        ram-bits = <12>;
+        port0-mode = <3>;
+        port1-mode = <3>;
+        power = <250>;
+        ti,hwmods = "usb_otg_hs";
+};
diff --git a/Documentation/devicetree/bindings/usb/ehci-orion.txt b/Documentation/devicetree/bindings/usb/ehci-orion.txt
new file mode 100644
index 000000000000..6bc09ec14c4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ehci-orion.txt
@@ -0,0 +1,15 @@
+* EHCI controller, Orion Marvell variants
+Required properties:
+- compatible: must be "marvell,orion-ehci"
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: The EHCI interrupt
+Example:
+        ehci@50000 {
+                compatible = "marvell,orion-ehci";
+                reg = <0x50000 0x1000>;
+                interrupts = <19>;
+        };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 9de2b9ff9d6e..902b1b1f568e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -5,6 +5,7 @@ using them to avoid name-space collisions.
 ad      Avionic Design GmbH
 adi     Analog Devices, Inc.
+ak      Asahi Kasei Corp.
 amcc    Applied Micro Circuits Corporation (APM, formally AMCC)
 apm     Applied Micro Circuits Corporation (APM)
 arm     ARM Ltd.
@@ -25,6 +26,7 @@ gef	GE Fanuc Intelligent Platforms Embedded Systems, Inc.
 hp      Hewlett Packard
 ibm     International Business Machines (IBM)
 idt     Integrated Device Technologies, Inc.
+img     Imagination Technologies Ltd.
 intercontrol    Inter Control Group
 linux   Linux-specific binding
 marvell Marvell Technology Group Ltd.
@@ -34,8 +36,9 @@ national	National Semiconductor
 nintendo        Nintendo
 nvidia  NVIDIA
 nxp     NXP Semiconductors
+onnn    ON Semiconductor Corp.
 picochip        Picochip Ltd
-powervr Imagination Technologies
+powervr PowerVR (deprecated, use img)
 qcom    Qualcomm, Inc.
 ramtron Ramtron International
 realtek Realtek Semiconductor Corp.
@@ -45,10 +48,12 @@ schindler	Schindler
 sil     Silicon Image
 simtek
 sirf    SiRF Technology, Inc.
+snps    Synopsys, Inc.
 st      STMicroelectronics
 stericsson      ST-Ericsson
 ti      Texas Instruments
 via     VIA Technologies, Inc.
 wlf     Wolfson Microelectronics
 wm      Wondermedia Technologies, Inc.
+winbond Winbond Electronics corp.
 xlnx    Xilinx
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
new file mode 100644
index 000000000000..2957ebb5aa71
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -0,0 +1,15 @@
+* Atmel Watchdog Timers
+** at91sam9-wdt
+Required properties:
+- compatible: must be "atmel,at91sam9260-wdt".
+- reg: physical base address of the controller and length of memory mapped
+  region.
+Example:
+        watchdog@fffffd40 {
+                compatible = "atmel,at91sam9260-wdt";
+                reg = <0xfffffd40 0x10>;
+        };
diff --git a/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
new file mode 100644
index 000000000000..d209366b4a69
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/brcm,bcm2835-pm-wdog.txt
@@ -0,0 +1,13 @@
+BCM2835 Watchdog timer
+Required properties:
+- compatible : should be "brcm,bcm2835-pm-wdt"
+- reg : Specifies base physical address and size of the registers.
+Example:
+watchdog {
+        compatible = "brcm,bcm2835-pm-wdt";
+        reg = <0x7e100000 0x28>;
+};
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
new file mode 100644
index 000000000000..0b2717775600
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -0,0 +1,13 @@
+Allwinner sunXi Watchdog timer
+Required properties:
+- compatible : should be "allwinner,sunxi-wdt"
+- reg : Specifies base physical address and size of the registers.
+Example:
+wdt: watchdog@01c20c90 {
+        compatible = "allwinner,sunxi-wdt";
+        reg = <0x01c20c90 0x10>;
+};