diff options
Diffstat (limited to 'Documentation/devicetree/bindings')
12 files changed, 542 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt new file mode 100644 index 000000000000..93986a5a8018 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | * Compact Flash | ||
2 | |||
3 | The Cavium Compact Flash device is connected to the Octeon Boot Bus, | ||
4 | and is thus a child of the Boot Bus device. It can read and write | ||
5 | industry standard compact flash devices. | ||
6 | |||
7 | Properties: | ||
8 | - compatible: "cavium,ebt3000-compact-flash"; | ||
9 | |||
10 | Compatibility with many Cavium evaluation boards. | ||
11 | |||
12 | - reg: The base address of the the CF chip select banks. Depending on | ||
13 | the device configuration, there may be one or two banks. | ||
14 | |||
15 | - cavium,bus-width: The width of the connection to the CF devices. Valid | ||
16 | values are 8 and 16. | ||
17 | |||
18 | - cavium,true-ide: Optional, if present the CF connection is in True IDE mode. | ||
19 | |||
20 | - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected | ||
21 | to this device. | ||
22 | |||
23 | Example: | ||
24 | compact-flash@5,0 { | ||
25 | compatible = "cavium,ebt3000-compact-flash"; | ||
26 | reg = <5 0 0x10000>, <6 0 0x10000>; | ||
27 | cavium,bus-width = <16>; | ||
28 | cavium,true-ide; | ||
29 | cavium,dma-engine-handle = <&dma0>; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt new file mode 100644 index 000000000000..9d6dcd3fe7f9 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt | |||
@@ -0,0 +1,49 @@ | |||
1 | * General Purpose Input Output (GPIO) bus. | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-gpio" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
7 | |||
8 | - reg: The base address of the GPIO unit's register bank. | ||
9 | |||
10 | - gpio-controller: This is a GPIO controller. | ||
11 | |||
12 | - #gpio-cells: Must be <2>. The first cell is the GPIO pin. | ||
13 | |||
14 | - interrupt-controller: The GPIO controller is also an interrupt | ||
15 | controller, many of its pins may be configured as an interrupt | ||
16 | source. | ||
17 | |||
18 | - #interrupt-cells: Must be <2>. The first cell is the GPIO pin | ||
19 | connected to the interrupt source. The second cell is the interrupt | ||
20 | triggering protocol and may have one of four values: | ||
21 | 1 - edge triggered on the rising edge. | ||
22 | 2 - edge triggered on the falling edge | ||
23 | 4 - level triggered active high. | ||
24 | 8 - level triggered active low. | ||
25 | |||
26 | - interrupts: Interrupt routing for each pin. | ||
27 | |||
28 | Example: | ||
29 | |||
30 | gpio-controller@1070000000800 { | ||
31 | #gpio-cells = <2>; | ||
32 | compatible = "cavium,octeon-3860-gpio"; | ||
33 | reg = <0x10700 0x00000800 0x0 0x100>; | ||
34 | gpio-controller; | ||
35 | /* Interrupts are specified by two parts: | ||
36 | * 1) GPIO pin number (0..15) | ||
37 | * 2) Triggering (1 - edge rising | ||
38 | * 2 - edge falling | ||
39 | * 4 - level active high | ||
40 | * 8 - level active low) | ||
41 | */ | ||
42 | interrupt-controller; | ||
43 | #interrupt-cells = <2>; | ||
44 | /* The GPIO pin connect to 16 consecutive CUI bits */ | ||
45 | interrupts = <0 16>, <0 17>, <0 18>, <0 19>, | ||
46 | <0 20>, <0 21>, <0 22>, <0 23>, | ||
47 | <0 24>, <0 25>, <0 26>, <0 27>, | ||
48 | <0 28>, <0 29>, <0 30>, <0 31>; | ||
49 | }; | ||
diff --git a/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt new file mode 100644 index 000000000000..dced82ebe31d --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/cavium-i2c.txt | |||
@@ -0,0 +1,34 @@ | |||
1 | * Two Wire Serial Interface (TWSI) / I2C | ||
2 | |||
3 | - compatible: "cavium,octeon-3860-twsi" | ||
4 | |||
5 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
6 | |||
7 | - reg: The base address of the TWSI/I2C bus controller register bank. | ||
8 | |||
9 | - #address-cells: Must be <1>. | ||
10 | |||
11 | - #size-cells: Must be <0>. I2C addresses have no size component. | ||
12 | |||
13 | - interrupts: A single interrupt specifier. | ||
14 | |||
15 | - clock-frequency: The I2C bus clock rate in Hz. | ||
16 | |||
17 | Example: | ||
18 | twsi0: i2c@1180000001000 { | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | compatible = "cavium,octeon-3860-twsi"; | ||
22 | reg = <0x11800 0x00001000 0x0 0x200>; | ||
23 | interrupts = <0 45>; | ||
24 | clock-frequency = <100000>; | ||
25 | |||
26 | rtc@68 { | ||
27 | compatible = "dallas,ds1337"; | ||
28 | reg = <0x68>; | ||
29 | }; | ||
30 | tmp@4c { | ||
31 | compatible = "ti,tmp421"; | ||
32 | reg = <0x4c>; | ||
33 | }; | ||
34 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt new file mode 100644 index 000000000000..6581478225a2 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt | |||
@@ -0,0 +1,126 @@ | |||
1 | * Boot Bus | ||
2 | |||
3 | The Octeon Boot Bus is a configurable parallel bus with 8 chip | ||
4 | selects. Each chip select is independently configurable. | ||
5 | |||
6 | Properties: | ||
7 | - compatible: "cavium,octeon-3860-bootbus" | ||
8 | |||
9 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
10 | |||
11 | - reg: The base address of the Boot Bus' register bank. | ||
12 | |||
13 | - #address-cells: Must be <2>. The first cell is the chip select | ||
14 | within the bootbus. The second cell is the offset from the chip select. | ||
15 | |||
16 | - #size-cells: Must be <1>. | ||
17 | |||
18 | - ranges: There must be one one triplet of (child-bus-address, | ||
19 | parent-bus-address, length) for each active chip select. If the | ||
20 | length element for any triplet is zero, the chip select is disabled, | ||
21 | making it inactive. | ||
22 | |||
23 | The configuration parameters for each chip select are stored in child | ||
24 | nodes. | ||
25 | |||
26 | Configuration Properties: | ||
27 | - compatible: "cavium,octeon-3860-bootbus-config" | ||
28 | |||
29 | - cavium,cs-index: A single cell indicating the chip select that | ||
30 | corresponds to this configuration. | ||
31 | |||
32 | - cavium,t-adr: A cell specifying the ADR timing (in nS). | ||
33 | |||
34 | - cavium,t-ce: A cell specifying the CE timing (in nS). | ||
35 | |||
36 | - cavium,t-oe: A cell specifying the OE timing (in nS). | ||
37 | |||
38 | - cavium,t-we: A cell specifying the WE timing (in nS). | ||
39 | |||
40 | - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). | ||
41 | |||
42 | - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). | ||
43 | |||
44 | - cavium,t-pause: A cell specifying the PAUSE timing (in nS). | ||
45 | |||
46 | - cavium,t-wait: A cell specifying the WAIT timing (in nS). | ||
47 | |||
48 | - cavium,t-page: A cell specifying the PAGE timing (in nS). | ||
49 | |||
50 | - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). | ||
51 | |||
52 | - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 | ||
53 | = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). | ||
54 | |||
55 | - cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. | ||
56 | |||
57 | - cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. | ||
58 | |||
59 | - cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of | ||
60 | the bus for this chip select. | ||
61 | |||
62 | - cavium,ale-mode: Optional. If present, ALE mode is selected. | ||
63 | |||
64 | - cavium,sam-mode: Optional. If present, SAM mode is selected. | ||
65 | |||
66 | - cavium,or-mode: Optional. If present, OR mode is selected. | ||
67 | |||
68 | Example: | ||
69 | bootbus: bootbus@1180000000000 { | ||
70 | compatible = "cavium,octeon-3860-bootbus"; | ||
71 | reg = <0x11800 0x00000000 0x0 0x200>; | ||
72 | /* The chip select number and offset */ | ||
73 | #address-cells = <2>; | ||
74 | /* The size of the chip select region */ | ||
75 | #size-cells = <1>; | ||
76 | ranges = <0 0 0x0 0x1f400000 0xc00000>, | ||
77 | <1 0 0x10000 0x30000000 0>, | ||
78 | <2 0 0x10000 0x40000000 0>, | ||
79 | <3 0 0x10000 0x50000000 0>, | ||
80 | <4 0 0x0 0x1d020000 0x10000>, | ||
81 | <5 0 0x0 0x1d040000 0x10000>, | ||
82 | <6 0 0x0 0x1d050000 0x10000>, | ||
83 | <7 0 0x10000 0x90000000 0>; | ||
84 | |||
85 | cavium,cs-config@0 { | ||
86 | compatible = "cavium,octeon-3860-bootbus-config"; | ||
87 | cavium,cs-index = <0>; | ||
88 | cavium,t-adr = <20>; | ||
89 | cavium,t-ce = <60>; | ||
90 | cavium,t-oe = <60>; | ||
91 | cavium,t-we = <45>; | ||
92 | cavium,t-rd-hld = <35>; | ||
93 | cavium,t-wr-hld = <45>; | ||
94 | cavium,t-pause = <0>; | ||
95 | cavium,t-wait = <0>; | ||
96 | cavium,t-page = <35>; | ||
97 | cavium,t-rd-dly = <0>; | ||
98 | |||
99 | cavium,pages = <0>; | ||
100 | cavium,bus-width = <8>; | ||
101 | }; | ||
102 | . | ||
103 | . | ||
104 | . | ||
105 | cavium,cs-config@6 { | ||
106 | compatible = "cavium,octeon-3860-bootbus-config"; | ||
107 | cavium,cs-index = <6>; | ||
108 | cavium,t-adr = <5>; | ||
109 | cavium,t-ce = <300>; | ||
110 | cavium,t-oe = <270>; | ||
111 | cavium,t-we = <150>; | ||
112 | cavium,t-rd-hld = <100>; | ||
113 | cavium,t-wr-hld = <70>; | ||
114 | cavium,t-pause = <0>; | ||
115 | cavium,t-wait = <0>; | ||
116 | cavium,t-page = <320>; | ||
117 | cavium,t-rd-dly = <0>; | ||
118 | |||
119 | cavium,pages = <0>; | ||
120 | cavium,wait-mode; | ||
121 | cavium,bus-width = <16>; | ||
122 | }; | ||
123 | . | ||
124 | . | ||
125 | . | ||
126 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt new file mode 100644 index 000000000000..2c2d0746b43d --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt | |||
@@ -0,0 +1,26 @@ | |||
1 | * Central Interrupt Unit | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-ciu" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. | ||
7 | |||
8 | - interrupt-controller: This is an interrupt controller. | ||
9 | |||
10 | - reg: The base address of the CIU's register bank. | ||
11 | |||
12 | - #interrupt-cells: Must be <2>. The first cell is the bank within | ||
13 | the CIU and may have a value of 0 or 1. The second cell is the bit | ||
14 | within the bank and may have a value between 0 and 63. | ||
15 | |||
16 | Example: | ||
17 | interrupt-controller@1070000000000 { | ||
18 | compatible = "cavium,octeon-3860-ciu"; | ||
19 | interrupt-controller; | ||
20 | /* Interrupts are specified by two parts: | ||
21 | * 1) Controller register (0 or 1) | ||
22 | * 2) Bit within the register (0..63) | ||
23 | */ | ||
24 | #interrupt-cells = <2>; | ||
25 | reg = <0x10700 0x00000000 0x0 0x7000>; | ||
26 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt new file mode 100644 index 000000000000..0ec7ba8bbbcb --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/ciu2.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | * Central Interrupt Unit | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-6880-ciu2" | ||
5 | |||
6 | Compatibility with 68XX SOCs. | ||
7 | |||
8 | - interrupt-controller: This is an interrupt controller. | ||
9 | |||
10 | - reg: The base address of the CIU's register bank. | ||
11 | |||
12 | - #interrupt-cells: Must be <2>. The first cell is the bank within | ||
13 | the CIU and may have a value between 0 and 63. The second cell is | ||
14 | the bit within the bank and may also have a value between 0 and 63. | ||
15 | |||
16 | Example: | ||
17 | interrupt-controller@1070100000000 { | ||
18 | compatible = "cavium,octeon-6880-ciu2"; | ||
19 | interrupt-controller; | ||
20 | /* Interrupts are specified by two parts: | ||
21 | * 1) Controller register (0..63) | ||
22 | * 2) Bit within the register (0..63) | ||
23 | */ | ||
24 | #address-cells = <0>; | ||
25 | #interrupt-cells = <2>; | ||
26 | reg = <0x10701 0x00000000 0x0 0x4000000>; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt new file mode 100644 index 000000000000..cb4291e3b1d1 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt | |||
@@ -0,0 +1,21 @@ | |||
1 | * DMA Engine. | ||
2 | |||
3 | The Octeon DMA Engine transfers between the Boot Bus and main memory. | ||
4 | The DMA Engine will be refered to by phandle by any device that is | ||
5 | connected to it. | ||
6 | |||
7 | Properties: | ||
8 | - compatible: "cavium,octeon-5750-bootbus-dma" | ||
9 | |||
10 | Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. | ||
11 | |||
12 | - reg: The base address of the DMA Engine's register bank. | ||
13 | |||
14 | - interrupts: A single interrupt specifier. | ||
15 | |||
16 | Example: | ||
17 | dma0: dma-engine@1180000000100 { | ||
18 | compatible = "cavium,octeon-5750-bootbus-dma"; | ||
19 | reg = <0x11800 0x00000100 0x0 0x8>; | ||
20 | interrupts = <0 63>; | ||
21 | }; | ||
diff --git a/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/Documentation/devicetree/bindings/mips/cavium/uctl.txt new file mode 100644 index 000000000000..aa66b9b8d801 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/cavium/uctl.txt | |||
@@ -0,0 +1,46 @@ | |||
1 | * UCTL USB controller glue | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-6335-uctl" | ||
5 | |||
6 | Compatibility with all cn6XXX SOCs. | ||
7 | |||
8 | - reg: The base address of the UCTL register bank. | ||
9 | |||
10 | - #address-cells: Must be <2>. | ||
11 | |||
12 | - #size-cells: Must be <2>. | ||
13 | |||
14 | - ranges: Empty to signify direct mapping of the children. | ||
15 | |||
16 | - refclk-frequency: A single cell containing the reference clock | ||
17 | frequency in Hz. | ||
18 | |||
19 | - refclk-type: A string describing the reference clock connection | ||
20 | either "crystal" or "external". | ||
21 | |||
22 | Example: | ||
23 | uctl@118006f000000 { | ||
24 | compatible = "cavium,octeon-6335-uctl"; | ||
25 | reg = <0x11800 0x6f000000 0x0 0x100>; | ||
26 | ranges; /* Direct mapping */ | ||
27 | #address-cells = <2>; | ||
28 | #size-cells = <2>; | ||
29 | /* 12MHz, 24MHz and 48MHz allowed */ | ||
30 | refclk-frequency = <24000000>; | ||
31 | /* Either "crystal" or "external" */ | ||
32 | refclk-type = "crystal"; | ||
33 | |||
34 | ehci@16f0000000000 { | ||
35 | compatible = "cavium,octeon-6335-ehci","usb-ehci"; | ||
36 | reg = <0x16f00 0x00000000 0x0 0x100>; | ||
37 | interrupts = <0 56>; | ||
38 | big-endian-regs; | ||
39 | }; | ||
40 | ohci@16f0000000400 { | ||
41 | compatible = "cavium,octeon-6335-ohci","usb-ohci"; | ||
42 | reg = <0x16f00 0x00000400 0x0 0x100>; | ||
43 | interrupts = <0 56>; | ||
44 | big-endian-regs; | ||
45 | }; | ||
46 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cavium-mdio.txt b/Documentation/devicetree/bindings/net/cavium-mdio.txt new file mode 100644 index 000000000000..04cb7491d232 --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mdio.txt | |||
@@ -0,0 +1,27 @@ | |||
1 | * System Management Interface (SMI) / MDIO | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-3860-mdio" | ||
5 | |||
6 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
7 | |||
8 | - reg: The base address of the MDIO bus controller register bank. | ||
9 | |||
10 | - #address-cells: Must be <1>. | ||
11 | |||
12 | - #size-cells: Must be <0>. MDIO addresses have no size component. | ||
13 | |||
14 | Typically an MDIO bus might have several children. | ||
15 | |||
16 | Example: | ||
17 | mdio@1180000001800 { | ||
18 | compatible = "cavium,octeon-3860-mdio"; | ||
19 | #address-cells = <1>; | ||
20 | #size-cells = <0>; | ||
21 | reg = <0x11800 0x00001800 0x0 0x40>; | ||
22 | |||
23 | ethernet-phy@0 { | ||
24 | ... | ||
25 | reg = <0>; | ||
26 | }; | ||
27 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt new file mode 100644 index 000000000000..5da628db68bf --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-mix.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | * MIX Ethernet controller. | ||
2 | |||
3 | Properties: | ||
4 | - compatible: "cavium,octeon-5750-mix" | ||
5 | |||
6 | Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX | ||
7 | devices. | ||
8 | |||
9 | - reg: The base addresses of four separate register banks. The first | ||
10 | bank contains the MIX registers. The second bank the corresponding | ||
11 | AGL registers. The third bank are the AGL registers shared by all | ||
12 | MIX devices present. The fourth bank is the AGL_PRT_CTL shared by | ||
13 | all MIX devices present. | ||
14 | |||
15 | - cell-index: A single cell specifying which portion of the shared | ||
16 | register banks corresponds to this MIX device. | ||
17 | |||
18 | - interrupts: Two interrupt specifiers. The first is the MIX | ||
19 | interrupt routing and the second the routing for the AGL interrupts. | ||
20 | |||
21 | - mac-address: Optional, the MAC address to assign to the device. | ||
22 | |||
23 | - local-mac-address: Optional, the MAC address to assign to the device | ||
24 | if mac-address is not specified. | ||
25 | |||
26 | - phy-handle: Optional, a phandle for the PHY device connected to this device. | ||
27 | |||
28 | Example: | ||
29 | ethernet@1070000100800 { | ||
30 | compatible = "cavium,octeon-5750-mix"; | ||
31 | reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ | ||
32 | <0x11800 0xE0000800 0x0 0x300>, /* AGL */ | ||
33 | <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ | ||
34 | <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ | ||
35 | cell-index = <1>; | ||
36 | interrupts = <1 18>, < 1 46>; | ||
37 | local-mac-address = [ 00 0f b7 10 63 54 ]; | ||
38 | phy-handle = <&phy1>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt new file mode 100644 index 000000000000..d4c53ba04b3b --- /dev/null +++ b/Documentation/devicetree/bindings/net/cavium-pip.txt | |||
@@ -0,0 +1,98 @@ | |||
1 | * PIP Ethernet nexus. | ||
2 | |||
3 | The PIP Ethernet nexus can control several data packet input/output | ||
4 | devices. The devices have a two level grouping scheme. There may be | ||
5 | several interfaces, and each interface may have several ports. These | ||
6 | ports might be an individual Ethernet PHY. | ||
7 | |||
8 | |||
9 | Properties for the PIP nexus: | ||
10 | - compatible: "cavium,octeon-3860-pip" | ||
11 | |||
12 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
13 | |||
14 | - reg: The base address of the PIP's register bank. | ||
15 | |||
16 | - #address-cells: Must be <1>. | ||
17 | |||
18 | - #size-cells: Must be <0>. | ||
19 | |||
20 | Properties for PIP interfaces which is a child the PIP nexus: | ||
21 | - compatible: "cavium,octeon-3860-pip-interface" | ||
22 | |||
23 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
24 | |||
25 | - reg: The interface number. | ||
26 | |||
27 | - #address-cells: Must be <1>. | ||
28 | |||
29 | - #size-cells: Must be <0>. | ||
30 | |||
31 | Properties for PIP port which is a child the PIP interface: | ||
32 | - compatible: "cavium,octeon-3860-pip-port" | ||
33 | |||
34 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
35 | |||
36 | - reg: The port number within the interface group. | ||
37 | |||
38 | - mac-address: Optional, the MAC address to assign to the device. | ||
39 | |||
40 | - local-mac-address: Optional, the MAC address to assign to the device | ||
41 | if mac-address is not specified. | ||
42 | |||
43 | - phy-handle: Optional, a phandle for the PHY device connected to this device. | ||
44 | |||
45 | Example: | ||
46 | |||
47 | pip@11800a0000000 { | ||
48 | compatible = "cavium,octeon-3860-pip"; | ||
49 | #address-cells = <1>; | ||
50 | #size-cells = <0>; | ||
51 | reg = <0x11800 0xa0000000 0x0 0x2000>; | ||
52 | |||
53 | interface@0 { | ||
54 | compatible = "cavium,octeon-3860-pip-interface"; | ||
55 | #address-cells = <1>; | ||
56 | #size-cells = <0>; | ||
57 | reg = <0>; /* interface */ | ||
58 | |||
59 | ethernet@0 { | ||
60 | compatible = "cavium,octeon-3860-pip-port"; | ||
61 | reg = <0x0>; /* Port */ | ||
62 | local-mac-address = [ 00 0f b7 10 63 60 ]; | ||
63 | phy-handle = <&phy2>; | ||
64 | }; | ||
65 | ethernet@1 { | ||
66 | compatible = "cavium,octeon-3860-pip-port"; | ||
67 | reg = <0x1>; /* Port */ | ||
68 | local-mac-address = [ 00 0f b7 10 63 61 ]; | ||
69 | phy-handle = <&phy3>; | ||
70 | }; | ||
71 | ethernet@2 { | ||
72 | compatible = "cavium,octeon-3860-pip-port"; | ||
73 | reg = <0x2>; /* Port */ | ||
74 | local-mac-address = [ 00 0f b7 10 63 62 ]; | ||
75 | phy-handle = <&phy4>; | ||
76 | }; | ||
77 | ethernet@3 { | ||
78 | compatible = "cavium,octeon-3860-pip-port"; | ||
79 | reg = <0x3>; /* Port */ | ||
80 | local-mac-address = [ 00 0f b7 10 63 63 ]; | ||
81 | phy-handle = <&phy5>; | ||
82 | }; | ||
83 | }; | ||
84 | |||
85 | interface@1 { | ||
86 | compatible = "cavium,octeon-3860-pip-interface"; | ||
87 | #address-cells = <1>; | ||
88 | #size-cells = <0>; | ||
89 | reg = <1>; /* interface */ | ||
90 | |||
91 | ethernet@0 { | ||
92 | compatible = "cavium,octeon-3860-pip-port"; | ||
93 | reg = <0x0>; /* Port */ | ||
94 | local-mac-address = [ 00 0f b7 10 63 64 ]; | ||
95 | phy-handle = <&phy6>; | ||
96 | }; | ||
97 | }; | ||
98 | }; | ||
diff --git a/Documentation/devicetree/bindings/serial/cavium-uart.txt b/Documentation/devicetree/bindings/serial/cavium-uart.txt new file mode 100644 index 000000000000..87a6c375cd44 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/cavium-uart.txt | |||
@@ -0,0 +1,19 @@ | |||
1 | * Universal Asynchronous Receiver/Transmitter (UART) | ||
2 | |||
3 | - compatible: "cavium,octeon-3860-uart" | ||
4 | |||
5 | Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. | ||
6 | |||
7 | - reg: The base address of the UART register bank. | ||
8 | |||
9 | - interrupts: A single interrupt specifier. | ||
10 | |||
11 | - current-speed: Optional, the current bit rate in bits per second. | ||
12 | |||
13 | Example: | ||
14 | uart1: serial@1180000000c00 { | ||
15 | compatible = "cavium,octeon-3860-uart","ns16550"; | ||
16 | reg = <0x11800 0x00000c00 0x0 0x400>; | ||
17 | current-speed = <115200>; | ||
18 | interrupts = <0 35>; | ||
19 | }; | ||