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-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt41
-rw-r--r--Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt127
-rw-r--r--Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt227
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt49
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt48
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt3
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt153
-rw-r--r--Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt97
-rw-r--r--Documentation/devicetree/bindings/pinctrl/ste,abx500.txt352
9 files changed, 1080 insertions, 17 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
new file mode 100644
index 000000000000..ddcdeb697c29
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
@@ -0,0 +1,41 @@
1Freescale Vybrid VF610 IOMUX Controller
2
3Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
4and usage.
5
6Required properties:
7- compatible: "fsl,vf610-iomuxc"
8- fsl,pins: two integers array, represents a group of pins mux and config
9 setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
10 a pin working on a specific function, CONFIG is the pad setting value
11 such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
12 datasheet for the valid pad config settings.
13
14CONFIG bits definition:
15PAD_CTL_SPEED_LOW (1 << 12)
16PAD_CTL_SPEED_MED (2 << 12)
17PAD_CTL_SPEED_HIGH (3 << 12)
18PAD_CTL_SRE_FAST (1 << 11)
19PAD_CTL_SRE_SLOW (0 << 11)
20PAD_CTL_ODE (1 << 10)
21PAD_CTL_HYS (1 << 9)
22PAD_CTL_DSE_DISABLE (0 << 6)
23PAD_CTL_DSE_150ohm (1 << 6)
24PAD_CTL_DSE_75ohm (2 << 6)
25PAD_CTL_DSE_50ohm (3 << 6)
26PAD_CTL_DSE_37ohm (4 << 6)
27PAD_CTL_DSE_30ohm (5 << 6)
28PAD_CTL_DSE_25ohm (6 << 6)
29PAD_CTL_DSE_20ohm (7 << 6)
30PAD_CTL_PUS_100K_DOWN (0 << 4)
31PAD_CTL_PUS_47K_UP (1 << 4)
32PAD_CTL_PUS_100K_UP (2 << 4)
33PAD_CTL_PUS_22K_UP (3 << 4)
34PAD_CTL_PKE (1 << 3)
35PAD_CTL_PUE (1 << 2)
36PAD_CTL_OBE_ENABLE (1 << 1)
37PAD_CTL_IBE_ENABLE (1 << 0)
38PAD_CTL_OBE_IBE_ENABLE (3 << 0)
39
40Please refer to vf610-pinfunc.h in device tree source folder
41for all available PIN_FUNC_ID for Vybrid VF610.
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
new file mode 100644
index 000000000000..a186181c402b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt
@@ -0,0 +1,127 @@
1ImgTec TZ1090 PDC pin controller
2
3Required properties:
4- compatible: "img,tz1090-pdc-pinctrl"
5- reg: Should contain the register physical address and length of the
6 SOC_GPIO_CONTROL registers in the PDC register region.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12TZ1090-PDC's pin configuration nodes act as a container for an abitrary number
13of subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function. For this reason, even seemingly boolean
26values are actually tristates in this binding: unspecified, off, or on.
27Unspecified is represented as an absent property, and off/on are represented as
28integer values 0 and 1.
29
30Required subnode-properties:
31- tz1090,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- tz1090,function: A string containing the name of the function to mux to the
36 pin or group. Valid values for function names are listed below, including
37 which pingroups can be muxed to them.
38- supported generic pinconfig properties (for further details see
39 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
40 - bias-disable
41 - bias-high-impedance
42 - bias-bus-hold
43 - bias-pull-up
44 - bias-pull-down
45 - input-schmitt-enable
46 - input-schmitt-disable
47 - drive-strength: Integer, control drive strength of pins in mA.
48 2: 2mA
49 4: 4mA
50 8: 8mA
51 12: 12mA
52 - low-power-enable: Flag, power-on-start weak pull-down for invalid power.
53 - low-power-disable: Flag, power-on-start weak pull-down disabled.
54
55Note that many of these properties are only valid for certain specific pins
56or groups. See the TZ1090 TRM for complete details regarding which groups
57support which functionality. The Linux pinctrl driver may also be a useful
58reference.
59
60Valid values for pin and group names are:
61
62 pins:
63
64 These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
65 bias-bus-hold (which can also be provided to any of the groups below to set
66 it for all gpio pins in that group).
67
68 gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power.
69
70 mux groups:
71
72 These all support function.
73
74 gpio0
75 pins: gpio0.
76 function: ir_mod_stable_out.
77 gpio1
78 pins: gpio1.
79 function: ir_mod_power_out.
80
81 drive groups:
82
83 These support input-schmitt-enable, input-schmitt-disable,
84 drive-strength, low-power-enable, and low-power-disable.
85
86 pdc
87 pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data,
88 ext_power.
89
90Example:
91
92 pinctrl_pdc: pinctrl@02006500 {
93 #gpio-range-cells = <3>;
94 compatible = "img,tz1090-pdc-pinctrl";
95 reg = <0x02006500 0x100>;
96 };
97
98Example board file extracts:
99
100 &pinctrl_pdc {
101 pinctrl-names = "default";
102 pinctrl-0 = <&syswake_default>;
103
104 syswake_default: syswakes {
105 syswake_cfg {
106 tz1090,pins = "sys_wake0",
107 "sys_wake1",
108 "sys_wake2";
109 pull-up;
110 };
111 };
112 irmod_default: irmod {
113 gpio0_cfg {
114 tz1090,pins = "gpio0";
115 tz1090,function = "ir_mod_stable_out";
116 };
117 gpio1_cfg {
118 tz1090,pins = "gpio1";
119 tz1090,function = "ir_mod_power_out";
120 };
121 };
122 };
123
124 ir: ir@02006200 {
125 pinctrl-names = "default";
126 pinctrl-0 = <&irmod_default>;
127 };
diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
new file mode 100644
index 000000000000..4b27c99f7f9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt
@@ -0,0 +1,227 @@
1ImgTec TZ1090 pin controller
2
3Required properties:
4- compatible: "img,tz1090-pinctrl"
5- reg: Should contain the register physical address and length of the pad
6 configuration registers (CR_PADS_* and CR_IF_CTL0).
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12TZ1090's pin configuration nodes act as a container for an abitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function. For this reason, even seemingly boolean
26values are actually tristates in this binding: unspecified, off, or on.
27Unspecified is represented as an absent property, and off/on are represented as
28integer values 0 and 1.
29
30Required subnode-properties:
31- tz1090,pins : An array of strings. Each string contains the name of a pin or
32 group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- tz1090,function: A string containing the name of the function to mux to the
36 pin or group. Valid values for function names are listed below, including
37 which pingroups can be muxed to them.
38- supported generic pinconfig properties (for further details see
39 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt):
40 - bias-disable
41 - bias-high-impedance
42 - bias-bus-hold
43 - bias-pull-up
44 - bias-pull-down
45 - input-schmitt-enable
46 - input-schmitt-disable
47 - drive-strength: Integer, control drive strength of pins in mA.
48 2: 2mA
49 4: 4mA
50 8: 8mA
51 12: 12mA
52
53
54Note that many of these properties are only valid for certain specific pins
55or groups. See the TZ1090 TRM for complete details regarding which groups
56support which functionality. The Linux pinctrl driver may also be a useful
57reference.
58
59Valid values for pin and group names are:
60
61 gpio pins:
62
63 These all support bias-high-impediance, bias-pull-up, bias-pull-down, and
64 bias-bus-hold (which can also be provided to any of the groups below to set
65 it for all pins in that group).
66
67 They also all support the some form of muxing. Any pins which are contained
68 in one of the mux groups (see below) can be muxed only to the functions
69 supported by the mux group. All other pins can be muxed to the "perip"
70 function which which enables them with their intended peripheral.
71
72 Different pins in the same mux group cannot be muxed to different functions,
73 however it is possible to mux only a subset of the pins in a mux group to a
74 particular function and leave the remaining pins unmuxed. This is useful if
75 the board connects certain pins in a group to other devices to be controlled
76 by GPIO, and you don't want the usual peripheral to have any control of the
77 pin.
78
79 ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7,
80 i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out,
81 i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on,
82 scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd,
83 sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
84 spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0,
85 spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0,
86 tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7,
87 tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5,
88 tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0,
89 tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7,
90 tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts,
91 uart0_rxd, uart0_txd, uart1_rxd, uart1_txd.
92
93 bias-high-impediance: supported.
94 bias-pull-up: supported.
95 bias-pull-down: supported.
96 bias-bus-hold: supported.
97 function: perip or those supported by pin's mux group.
98
99 other pins:
100
101 These other pins are part of various pin groups below, but can't be
102 controlled as GPIOs. They do however support bias-high-impediance,
103 bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided
104 to any of the groups below to set it for all pins in that group).
105
106 clk_out0, clk_out1, tck, tdi, tdo, tms, trst.
107
108 bias-high-impediance: supported.
109 bias-pull-up: supported.
110 bias-pull-down: supported.
111 bias-bus-hold: supported.
112
113 mux groups:
114
115 These all support function, and some support drive configs.
116
117 afe
118 pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0,
119 ant_sel1, gain0, gain1, gain2, gain3, gain4,
120 gain5, gain6, gain7.
121 function: afe, ts_out_0.
122 input-schmitt-enable: supported.
123 input-schmitt-disable: supported.
124 drive-strength: supported.
125 pdm_d
126 pins: pdm_d.
127 function: pdm_dac, usb_vbus.
128 sdh
129 pins: sdh_cd, sdh_wp, sdh_clk_in.
130 function: sdh, sdio.
131 sdio
132 pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2,
133 sdio_d3.
134 function: sdio, sdh.
135 spi1_cs2
136 pins: spi1_cs2.
137 function: spi1_cs2, usb_vbus.
138 tft
139 pins: tft_red0, tft_red1, tft_red2, tft_red3,
140 tft_red4, tft_red5, tft_red6, tft_red7,
141 tft_green0, tft_green1, tft_green2, tft_green3,
142 tft_green4, tft_green5, tft_green6, tft_green7,
143 tft_blue0, tft_blue1, tft_blue2, tft_blue3,
144 tft_blue4, tft_blue5, tft_blue6, tft_blue7,
145 tft_vdden_gd, tft_panelclk, tft_blank_ls,
146 tft_vsync_ns, tft_hsync_nr, tft_vd12acb,
147 tft_pwrsave.
148 function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1,
149 lcd_trace, phy_ringosc.
150 input-schmitt-enable: supported.
151 input-schmitt-disable: supported.
152 drive-strength: supported.
153
154 drive groups:
155
156 These all support input-schmitt-enable, input-schmitt-disable,
157 and drive-strength.
158
159 jtag
160 pins: tck, trst, tdi, tdo, tms.
161 scb1
162 pins: scb1_sdat, scb1_sclk.
163 scb2
164 pins: scb2_sdat, scb2_sclk.
165 spi0
166 pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din.
167 spi1
168 pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din.
169 uart
170 pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts,
171 uart1_txd, uart1_rxd.
172 drive_i2s
173 pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
174 i2s_lrclk_out, i2s_bclk_out, i2s_mclk.
175 drive_pdm
176 pins: clk_out0, pdm_b, pdm_a.
177 drive_scb0
178 pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c.
179 drive_sdio
180 pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3,
181 sdh_wp, sdh_cd, sdh_clk_in.
182
183 convenience groups:
184
185 These are just convenient groupings of pins and don't support any drive
186 configs.
187
188 uart0
189 pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd.
190 uart1
191 pins: uart1_rxd, uart1_txd.
192 scb0
193 pins: scb0_sclk, scb0_sdat.
194 i2s
195 pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2,
196 i2s_lrclk_out, i2s_mclk.
197
198Example:
199
200 pinctrl: pinctrl@02005800 {
201 #gpio-range-cells = <3>;
202 compatible = "img,tz1090-pinctrl";
203 reg = <0x02005800 0xe4>;
204 };
205
206Example board file extract:
207
208 &pinctrl {
209 uart0_default: uart0 {
210 uart0_cfg {
211 tz1090,pins = "uart0_rxd",
212 "uart0_txd";
213 tz1090,function = "perip";
214 };
215 };
216 tft_default: tft {
217 tft_cfg {
218 tz1090,pins = "tft";
219 tz1090,function = "tft";
220 };
221 };
222 };
223
224 uart@02004b00 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&uart0_default>;
227 };
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index a648aaad6110..50ec3512a292 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -10,29 +10,31 @@ Required properties:
10Available mpp pins/groups and functions: 10Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given 11Note: brackets (x) are not part of the mpp name for marvell,function and given
12only for more detailed description in this document. 12only for more detailed description in this document.
13Note: pmu* also allows for Power Management functions listed below
13 14
14name pins functions 15name pins functions
15================================================================================ 16================================================================================
16mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm) 17mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
17mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm) 18mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
18mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), 19mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
19 uart1(rts) 20 uart1(rts), pmu*
20mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), 21mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
21 uart1(cts), lcd-spi(cs1) 22 uart1(cts), lcd-spi(cs1), pmu*
22mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso) 23mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
23mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs) 24mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
24mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi) 25mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
25mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck) 26mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
26mpp8 8 gpio, pmu, watchdog(rstout) 27mpp8 8 gpio, pmu, watchdog(rstout), pmu*
27mpp9 9 gpio, pmu, pex1(clkreq) 28mpp9 9 gpio, pmu, pex1(clkreq), pmu*
28mpp10 10 gpio, pmu, ssp(sclk) 29mpp10 10 gpio, pmu, ssp(sclk), pmu*
29mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), 30mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
30 sdio1(ledctrl), pex0(clkreq) 31 sdio1(ledctrl), pex0(clkreq), pmu*
31mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act) 32mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
33 sata(act), pmu*
32mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), 34mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
33 ssp(extclk) 35 ssp(extclk), pmu*
34mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd) 36mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
35mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm) 37mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
36mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) 38mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
37mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), 39mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
38 ac97-1(sysclko) 40 ac97-1(sysclko)
@@ -57,6 +59,21 @@ mpp_nand 64-71 gpo, nand
57audio0 - i2s, ac97 59audio0 - i2s, ac97
58twsi - none, opt1, opt2, opt3 60twsi - none, opt1, opt2, opt3
59 61
62Power Management functions (pmu*):
63pmu-nc Pin not driven by any PM function
64pmu-low Pin driven low (0)
65pmu-high Pin driven high (1)
66pmic(sdi) Pin is used for PMIC SDI
67cpu-pwr-down Pin is used for CPU_PWRDWN
68standby-pwr-down Pin is used for STBY_PWRDWN
69core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
70cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
71bat-fault Pin is used for BATTERY_FAULT
72ext0-wakeup Pin is used for EXT0_WU
73ext1-wakeup Pin is used for EXT0_WU
74ext2-wakeup Pin is used for EXT0_WU
75pmu-blink Pin is used for blink function
76
60Notes: 77Notes:
61* group "mpp_audio1" allows the following functions and gpio pins: 78* group "mpp_audio1" allows the following functions and gpio pins:
62 - gpio : gpio on pins 52-57 79 - gpio : gpio on pins 52-57
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index c95ea8278f87..aeb3c995cc04 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -126,3 +126,51 @@ device; they may be grandchildren, for example. Whether this is legal, and
126whether there is any interaction between the child and intermediate parent 126whether there is any interaction between the child and intermediate parent
127nodes, is again defined entirely by the binding for the individual pin 127nodes, is again defined entirely by the binding for the individual pin
128controller device. 128controller device.
129
130== Using generic pinconfig options ==
131
132Generic pinconfig parameters can be used by defining a separate node containing
133the applicable parameters (and optional values), like:
134
135pcfg_pull_up: pcfg_pull_up {
136 bias-pull-up;
137 drive-strength = <20>;
138};
139
140This node should then be referenced in the appropriate pinctrl node as a phandle
141and parsed in the driver using the pinconf_generic_parse_dt_config function.
142
143Supported configuration parameters are:
144
145bias-disable - disable any pin bias
146bias-high-impedance - high impedance mode ("third-state", "floating")
147bias-bus-hold - latch weakly
148bias-pull-up - pull up the pin
149bias-pull-down - pull down the pin
150bias-pull-pin-default - use pin-default pull state
151drive-push-pull - drive actively high and low
152drive-open-drain - drive with open drain
153drive-open-source - drive with open source
154drive-strength - sink or source at most X mA
155input-schmitt-enable - enable schmitt-trigger mode
156input-schmitt-disable - disable schmitt-trigger mode
157input-debounce - debounce mode with debound time X
158low-power-enable - enable low power mode
159low-power-disable - disable low power mode
160output-low - set the pin to output mode with low level
161output-high - set the pin to output mode with high level
162
163Arguments for parameters:
164
165- bias-pull-up, -down and -pin-default take as optional argument on hardware
166 supporting it the pull strength in Ohm. bias-disable will disable the pull.
167
168- drive-strength takes as argument the target strength in mA.
169
170- input-debounce takes the debounce time in usec as argument
171 or 0 to disable debouncing
172
173All parameters not listed here, do not take an argument.
174
175More in-depth documentation on these parameters can be found in
176<include/linux/pinctrl/pinconfig-generic.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 08f0c3d01575..5a02e30dd262 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -18,7 +18,8 @@ Optional properties:
18 pin functions is ignored 18 pin functions is ignored
19 19
20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls 20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
21 more than one pin 21 more than one pin, for which "pinctrl-single,function-mask" property specifies
22 position mask of pin.
22 23
23- pinctrl-single,drive-strength : array of value that are used to configure 24- pinctrl-single,drive-strength : array of value that are used to configure
24 drive strength in the pinmux register. They're value of drive strength 25 drive strength in the pinmux register. They're value of drive strength
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
new file mode 100644
index 000000000000..d5dac7b843a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -0,0 +1,153 @@
1* Renesas Pin Function Controller (GPIO and Pin Mux/Config)
2
3The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH7372,
4SH73A0, R8A73A4 and R8A7740 it also acts as a GPIO controller.
5
6
7Pin Control
8-----------
9
10Required Properties:
11
12 - compatible: should be one of the following.
13 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
14 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
15 - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
16 - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller.
17 - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller.
18 - "renesas,pfc-sh7372": for SH7372 (SH-Mobile AP4) compatible pin-controller.
19 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
20
21 - reg: Base address and length of each memory resource used by the pin
22 controller hardware module.
23
24Optional properties:
25
26 - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden
27 otherwise. Should be 3.
28
29The PFC node also acts as a container for pin configuration nodes. Please refer
30to pinctrl-bindings.txt in this directory for the definition of the term "pin
31configuration node" and for the common pinctrl bindings used by client devices.
32
33Each pin configuration node represents a desired configuration for a pin, a
34pin group, or a list of pins or pin groups. The configuration can include the
35function to select on those pin(s) and pin configuration parameters (such as
36pull-up and pull-down).
37
38Pin configuration nodes contain pin configuration properties, either directly
39or grouped in child subnodes. Both pin muxing and configuration parameters can
40be grouped in that way and referenced as a single pin configuration node by
41client devices.
42
43A configuration node or subnode must reference at least one pin (through the
44pins or pin groups properties) and contain at least a function or one
45configuration parameter. When the function is present only pin groups can be
46used to reference pins.
47
48All pin configuration nodes and subnodes names are ignored. All of those nodes
49are parsed through phandles and processed purely based on their content.
50
51Pin Configuration Node Properties:
52
53- renesas,pins : An array of strings, each string containing the name of a pin.
54- renesas,groups : An array of strings, each string containing the name of a pin
55 group.
56
57- renesas,function: A string containing the name of the function to mux to the
58 pin group(s) specified by the renesas,groups property
59
60 Valid values for pin, group and function names can be found in the group and
61 function arrays of the PFC data file corresponding to the SoC
62 (drivers/pinctrl/sh-pfc/pfc-*.c)
63
64The pin configuration parameters use the generic pinconf bindings defined in
65pinctrl-bindings.txt in this directory. The supported parameters are
66bias-disable, bias-pull-up and bias-pull-down.
67
68
69GPIO
70----
71
72On SH7372, SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller
73node.
74
75Required Properties:
76
77 - gpio-controller: Marks the device node as a gpio controller.
78
79 - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
80 cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
81 GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
82
83The syntax of the gpio specifier used by client nodes should be the following
84with values derived from the SoC user manual.
85
86 <[phandle of the gpio controller node]
87 [pin number within the gpio controller]
88 [flags]>
89
90On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver.
91Please refer to Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
92for documentation of the GPIO device tree bindings on those platforms.
93
94
95Examples
96--------
97
98Example 1: SH73A0 (SH-Mobile AG5) pin controller node
99
100 pfc: pfc@e6050000 {
101 compatible = "renesas,pfc-sh73a0";
102 reg = <0xe6050000 0x8000>,
103 <0xe605801c 0x1c>;
104 gpio-controller;
105 #gpio-cells = <2>;
106 };
107
108Example 2: A GPIO LED node that references a GPIO
109
110 #include <dt-bindings/gpio/gpio.h>
111
112 leds {
113 compatible = "gpio-leds";
114 led1 {
115 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
116 };
117 };
118
119Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
120 for the MMCIF and SCIFA4 devices
121
122 &pfc {
123 pinctrl-0 = <&scifa4_pins>;
124 pinctrl-names = "default";
125
126 mmcif_pins: mmcif {
127 mux {
128 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
129 renesas,function = "mmc0";
130 };
131 cfg {
132 renesas,groups = "mmc0_data8_0";
133 renesas,pins = "PORT279";
134 bias-pull-up;
135 };
136 };
137
138 scifa4_pins: scifa4 {
139 renesas,groups = "scifa4_data", "scifa4_ctrl";
140 renesas,function = "scifa4";
141 };
142 };
143
144Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device
145
146 &mmcif {
147 pinctrl-0 = <&mmcif_pins>;
148 pinctrl-names = "default";
149
150 bus-width = <8>;
151 vmmc-supply = <&reg_1p8v>;
152 status = "okay";
153 };
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
new file mode 100644
index 000000000000..b0fb1018d7ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -0,0 +1,97 @@
1* Rockchip Pinmux Controller
2
3The Rockchip Pinmux Controller, enables the IC
4to share one PAD to several functional blocks. The sharing is done by
5multiplexing the PAD input/output signals. For each PAD there are up to
64 muxing options with option 0 being the use as a GPIO.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12The Rockchip pin configuration node is a node of a group of pins which can be
13used for a specific device or function. This node represents both mux and
14config of the pins in that group. The 'pins' selects the function mode(also
15named pin mode) this pin can work on and the 'config' configures various pad
16settings such as pull-up, etc.
17
18The pins are grouped into up to 5 individual pin banks which need to be
19defined as gpio sub-nodes of the pinmux controller.
20
21Required properties for iomux controller:
22 - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
23 "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
24
25Required properties for gpio sub nodes:
26 - compatible: "rockchip,gpio-bank"
27 - reg: register of the gpio bank (different than the iomux registerset)
28 - interrupts: base interrupt of the gpio bank in the interrupt controller
29 - clocks: clock that drives this bank
30 - gpio-controller: identifies the node as a gpio controller and pin bank.
31 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
32 binding is used, the amount of cells must be specified as 2. See generic
33 GPIO binding documentation for description of particular cells.
34 - interrupt-controller: identifies the controller node as interrupt-parent.
35 - #interrupt-cells: the value of this property should be 2 and the interrupt
36 cells should use the standard two-cell scheme described in
37 bindings/interrupt-controller/interrupts.txt
38
39Required properties for pin configuration node:
40 - rockchip,pins: 3 integers array, represents a group of pins mux and config
41 setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
42 The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
43 The phandle of a node containing the generic pinconfig options
44 to use, as described in pinctrl-bindings.txt in this directory.
45
46Examples:
47
48#include <dt-bindings/pinctrl/rockchip.h>
49
50...
51
52pinctrl@20008000 {
53 compatible = "rockchip,rk3066a-pinctrl";
54 reg = <0x20008000 0x150>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57 ranges;
58
59 gpio0: gpio0@20034000 {
60 compatible = "rockchip,gpio-bank";
61 reg = <0x20034000 0x100>;
62 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&clk_gates8 9>;
64
65 gpio-controller;
66 #gpio-cells = <2>;
67
68 interrupt-controller;
69 #interrupt-cells = <2>;
70 };
71
72 ...
73
74 pcfg_pull_default: pcfg_pull_default {
75 bias-pull-pin-default
76 };
77
78 uart2 {
79 uart2_xfer: uart2-xfer {
80 rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
81 <RK_GPIO1 9 1 &pcfg_pull_default>;
82 };
83 };
84};
85
86uart2: serial@20064000 {
87 compatible = "snps,dw-apb-uart";
88 reg = <0x20064000 0x400>;
89 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
90 reg-shift = <2>;
91 reg-io-width = <1>;
92 clocks = <&mux_uart2>;
93 status = "okay";
94
95 pinctrl-names = "default";
96 pinctrl-0 = <&uart2_xfer>;
97};
diff --git a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt
new file mode 100644
index 000000000000..e3865e136067
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt
@@ -0,0 +1,352 @@
1ST Ericsson abx500 pinmux controller
2
3Required properties:
4- compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio",
5 "stericsson,ab8505-gpio", "stericsson,ab9540-gpio",
6
7Please refer to pinctrl-bindings.txt in this directory for details of the
8common pinctrl bindings used by client devices, including the meaning of the
9phrase "pin configuration node".
10
11ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
12subnodes. Each of these subnodes represents some desired configuration for a
13pin, a group, or a list of pins or groups. This configuration can include the
14mux function to select on those pin(s)/group(s), and various pin configuration
15parameters, such as input, output, pull up, pull down...
16
17The name of each subnode is not important; all subnodes should be enumerated
18and processed purely based on their content.
19
20Required subnode-properties:
21- ste,pins : An array of strings. Each string contains the name of a pin or
22 group.
23
24Optional subnode-properties:
25- ste,function: A string containing the name of the function to mux to the
26 pin or group.
27
28- generic pin configuration option to use. Example :
29
30 default_cfg {
31 ste,pins = "GPIO1";
32 bias-disable;
33 };
34
35- ste,config: Handle of pin configuration node containing the generic
36 pinconfig options to use, as described in pinctrl-bindings.txt in
37 this directory. Example :
38
39 pcfg_bias_disable: pcfg_bias_disable {
40 bias-disable;
41 };
42
43 default_cfg {
44 ste,pins = "GPIO1";
45 ste.config = <&pcfg_bias_disable>;
46 };
47
48Example board file extract:
49
50&pinctrl_abx500 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>;
53
54 sysclkreq2 {
55 sysclkreq2_default_mode: sysclkreq2_default {
56 default_mux {
57 ste,function = "sysclkreq";
58 ste,pins = "sysclkreq2_d_1";
59 };
60 default_cfg {
61 ste,pins = "GPIO1";
62 bias-disable;
63 };
64 };
65 };
66 sysclkreq3 {
67 sysclkreq3_default_mode: sysclkreq3_default {
68 default_mux {
69 ste,function = "sysclkreq";
70 ste,pins = "sysclkreq3_d_1";
71 };
72 default_cfg {
73 ste,pins = "GPIO2";
74 output-low;
75 };
76 };
77 };
78 gpio3 {
79 gpio3_default_mode: gpio3_default {
80 default_mux {
81 ste,function = "gpio";
82 ste,pins = "gpio3_a_1";
83 };
84 default_cfg {
85 ste,pins = "GPIO3";
86 output-low;
87 };
88 };
89 };
90 sysclkreq6 {
91 sysclkreq6_default_mode: sysclkreq6_default {
92 default_mux {
93 ste,function = "sysclkreq";
94 ste,pins = "sysclkreq6_d_1";
95 };
96 default_cfg {
97 ste,pins = "GPIO4";
98 bias-disable;
99 };
100 };
101 };
102 pwmout1 {
103 pwmout1_default_mode: pwmout1_default {
104 default_mux {
105 ste,function = "pwmout";
106 ste,pins = "pwmout1_d_1";
107 };
108 default_cfg {
109 ste,pins = "GPIO14";
110 output-low;
111 };
112 };
113 };
114 pwmout2 {
115 pwmout2_default_mode: pwmout2_default {
116 pwmout2_default_mux {
117 ste,function = "pwmout";
118 ste,pins = "pwmout2_d_1";
119 };
120 pwmout2_default_cfg {
121 ste,pins = "GPIO15";
122 output-low;
123 };
124 };
125 };
126 pwmout3 {
127 pwmout3_default_mode: pwmout3_default {
128 pwmout3_default_mux {
129 ste,function = "pwmout";
130 ste,pins = "pwmout3_d_1";
131 };
132 pwmout3_default_cfg {
133 ste,pins = "GPIO16";
134 output-low;
135 };
136 };
137 };
138 adi1 {
139
140 adi1_default_mode: adi1_default {
141 adi1_default_mux {
142 ste,function = "adi1";
143 ste,pins = "adi1_d_1";
144 };
145 adi1_default_cfg1 {
146 ste,pins = "GPIO17","GPIO19","GPIO20";
147 bias-disable;
148 };
149 adi1_default_cfg2 {
150 ste,pins = "GPIO18";
151 output-low;
152 };
153 };
154 };
155 dmic12 {
156 dmic12_default_mode: dmic12_default {
157 dmic12_default_mux {
158 ste,function = "dmic";
159 ste,pins = "dmic12_d_1";
160 };
161 dmic12_default_cfg1 {
162 ste,pins = "GPIO27";
163 output-low;
164 };
165 dmic12_default_cfg2 {
166 ste,pins = "GPIO28";
167 bias-disable;
168 };
169 };
170 };
171 dmic34 {
172 dmic34_default_mode: dmic34_default {
173 dmic34_default_mux {
174 ste,function = "dmic";
175 ste,pins = "dmic34_d_1";
176 };
177 dmic34_default_cfg1 {
178 ste,pins = "GPIO29";
179 output-low;
180 };
181 dmic34_default_cfg2 {
182 ste,pins = "GPIO30";
183 bias-disable;{
184
185 };
186 };
187 };
188 dmic56 {
189 dmic56_default_mode: dmic56_default {
190 dmic56_default_mux {
191 ste,function = "dmic";
192 ste,pins = "dmic56_d_1";
193 };
194 dmic56_default_cfg1 {
195 ste,pins = "GPIO31";
196 output-low;
197 };
198 dmic56_default_cfg2 {
199 ste,pins = "GPIO32";
200 bias-disable;
201 };
202 };
203 };
204 sysclkreq5 {
205 sysclkreq5_default_mode: sysclkreq5_default {
206 sysclkreq5_default_mux {
207 ste,function = "sysclkreq";
208 ste,pins = "sysclkreq5_d_1";
209 };
210 sysclkreq5_default_cfg {
211 ste,pins = "GPIO42";
212 output-low;
213 };
214 };
215 };
216 batremn {
217 batremn_default_mode: batremn_default {
218 batremn_default_mux {
219 ste,function = "batremn";
220 ste,pins = "batremn_d_1";
221 };
222 batremn_default_cfg {
223 ste,pins = "GPIO43";
224 bias-disable;
225 };
226 };
227 };
228 service {
229 service_default_mode: service_default {
230 service_default_mux {
231 ste,function = "service";
232 ste,pins = "service_d_1";
233 };
234 service_default_cfg {
235 ste,pins = "GPIO44";
236 bias-disable;
237 };
238 };
239 };
240 pwrctrl0 {
241 pwrctrl0_default_mux: pwrctrl0_mux {
242 pwrctrl0_default_mux {
243 ste,function = "pwrctrl";
244 ste,pins = "pwrctrl0_d_1";
245 };
246 };
247 pwrctrl0_default_mode: pwrctrl0_default {
248 pwrctrl0_default_cfg {
249 ste,pins = "GPIO45";
250 bias-disable;
251 };
252 };
253 };
254 pwrctrl1 {
255 pwrctrl1_default_mux: pwrctrl1_mux {
256 pwrctrl1_default_mux {
257 ste,function = "pwrctrl";
258 ste,pins = "pwrctrl1_d_1";
259 };
260 };
261 pwrctrl1_default_mode: pwrctrl1_default {
262 pwrctrl1_default_cfg {
263 ste,pins = "GPIO46";
264 bias-disable;
265 };
266 };
267 };
268 pwmextvibra1 {
269 pwmextvibra1_default_mode: pwmextvibra1_default {
270 pwmextvibra1_default_mux {
271 ste,function = "pwmextvibra";
272 ste,pins = "pwmextvibra1_d_1";
273 };
274 pwmextvibra1_default_cfg {
275 ste,pins = "GPIO47";
276 bias-disable;
277 };
278 };
279 };
280 pwmextvibra2 {
281 pwmextvibra2_default_mode: pwmextvibra2_default {
282 pwmextvibra2_default_mux {
283 ste,function = "pwmextvibra";
284 ste,pins = "pwmextvibra2_d_1";
285 };
286 pwmextvibra1_default_cfg {
287 ste,pins = "GPIO48";
288 bias-disable;
289 };
290 };
291 };
292 gpio51 {
293 gpio51_default_mode: gpio51_default {
294 gpio51_default_mux {
295 ste,function = "gpio";
296 ste,pins = "gpio51_a_1";
297 };
298 gpio51_default_cfg {
299 ste,pins = "GPIO51";
300 output-low;
301 };
302 };
303 };
304 gpio52 {
305 gpio52_default_mode: gpio52_default {
306 gpio52_default_mux {
307 ste,function = "gpio";
308 ste,pins = "gpio52_a_1";
309 };
310 gpio52_default_cfg {
311 ste,pins = "GPIO52";
312 bias-pull-down;
313 };
314 };
315 };
316 gpio53 {
317 gpio53_default_mode: gpio53_default {
318 gpio53_default_mux {
319 ste,function = "gpio";
320 ste,pins = "gpio53_a_1";
321 };
322 gpio53_default_cfg {
323 ste,pins = "GPIO53";
324 bias-pull-down;
325 };
326 };
327 };
328 gpio54 {
329 gpio54_default_mode: gpio54_default {
330 gpio54_default_mux {
331 ste,function = "gpio";
332 ste,pins = "gpio54_a_1";
333 };
334 gpio54_default_cfg {
335 ste,pins = "GPIO54";
336 output-low;
337 };
338 };
339 };
340 pdmclkdat {
341 pdmclkdat_default_mode: pdmclkdat_default {
342 pdmclkdat_default_mux {
343 ste,function = "pdm";
344 ste,pins = "pdmclkdat_d_1";
345 };
346 pdmclkdat_default_cfg {
347 ste,pins = "GPIO55", "GPIO56";
348 bias-disable;
349 };
350 };
351 };
352};
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-11 21:53:02 -0400