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-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt14
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5420-clock.txt12
-rw-r--r--Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt77
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt12
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt75
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt83
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt98
-rw-r--r--Documentation/devicetree/bindings/gpu/samsung-g2d.txt7
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm-samsung.txt12
10 files changed, 388 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index 14d5c2af26f4..c6bf8a6c8f52 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -236,6 +236,7 @@ Exynos4 SoC and this is specified where applicable.
236 spi0_isp_sclk 380 Exynos4x12 236 spi0_isp_sclk 380 Exynos4x12
237 spi1_isp_sclk 381 Exynos4x12 237 spi1_isp_sclk 381 Exynos4x12
238 uart_isp_sclk 382 Exynos4x12 238 uart_isp_sclk 382 Exynos4x12
239 tmu_apbif 383
239 240
240 [Mux Clocks] 241 [Mux Clocks]
241 242
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 781a6276adf7..24765c146e31 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -59,6 +59,9 @@ clock which they consume.
59 sclk_spi0 154 59 sclk_spi0 154
60 sclk_spi1 155 60 sclk_spi1 155
61 sclk_spi2 156 61 sclk_spi2 156
62 div_i2s1 157
63 div_i2s2 158
64 sclk_hdmiphy 159
62 65
63 66
64 [Peripheral Clock Gates] 67 [Peripheral Clock Gates]
@@ -154,7 +157,16 @@ clock which they consume.
154 dsim0 341 157 dsim0 341
155 dp 342 158 dp 342
156 mixer 343 159 mixer 343
157 hdmi 345 160 hdmi 344
161 g2d 345
162
163
164 [Clock Muxes]
165
166 Clock ID
167 ----------------------------
168 mout_hdmi 1024
169
158 170
159Example 1: An example of a clock controller node is listed below. 171Example 1: An example of a clock controller node is listed below.
160 172
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 9bcc4b1bff51..32aa34ecad36 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -59,6 +59,7 @@ clock which they consume.
59 sclk_pwm 155 59 sclk_pwm 155
60 sclk_gscl_wa 156 60 sclk_gscl_wa 156
61 sclk_gscl_wb 157 61 sclk_gscl_wb 157
62 sclk_hdmiphy 158
62 63
63 [Peripheral Clock Gates] 64 [Peripheral Clock Gates]
64 65
@@ -179,6 +180,17 @@ clock which they consume.
179 fimc_lite3 495 180 fimc_lite3 495
180 aclk_g3d 500 181 aclk_g3d 500
181 g3d 501 182 g3d 501
183 smmu_mixer 502
184
185 Mux ID
186 ----------------------------
187
188 mout_hdmi 640
189
190 Divider ID
191 ----------------------------
192
193 dout_pixel 768
182 194
183Example 1: An example of a clock controller node is listed below. 195Example 1: An example of a clock controller node is listed below.
184 196
diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
new file mode 100644
index 000000000000..fa171dc4bd3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,s3c64xx-clock.txt
@@ -0,0 +1,77 @@
1* Samsung S3C64xx Clock Controller
2
3The S3C64xx clock controller generates and supplies clock to various controllers
4within the SoC. The clock binding described here is applicable to all SoCs in
5the S3C64xx family.
6
7Required Properties:
8
9- compatible: should be one of the following.
10 - "samsung,s3c6400-clock" - controller compatible with S3C6400 SoC.
11 - "samsung,s3c6410-clock" - controller compatible with S3C6410 SoC.
12
13- reg: physical base address of the controller and length of memory mapped
14 region.
15
16- #clock-cells: should be 1.
17
18Each clock is assigned an identifier and client nodes can use this identifier
19to specify the clock which they consume. Some of the clocks are available only
20on a particular S3C64xx SoC and this is specified where applicable.
21
22All available clocks are defined as preprocessor macros in
23dt-bindings/clock/samsung,s3c64xx-clock.h header and can be used in device
24tree sources.
25
26External clocks:
27
28There are several clocks that are generated outside the SoC. It is expected
29that they are defined using standard clock bindings with following
30clock-output-names:
31 - "fin_pll" - PLL input clock (xtal/extclk) - required,
32 - "xusbxti" - USB xtal - required,
33 - "iiscdclk0" - I2S0 codec clock - optional,
34 - "iiscdclk1" - I2S1 codec clock - optional,
35 - "iiscdclk2" - I2S2 codec clock - optional,
36 - "pcmcdclk0" - PCM0 codec clock - optional,
37 - "pcmcdclk1" - PCM1 codec clock - optional, only S3C6410.
38
39Example: Clock controller node:
40
41 clock: clock-controller@7e00f000 {
42 compatible = "samsung,s3c6410-clock";
43 reg = <0x7e00f000 0x1000>;
44 #clock-cells = <1>;
45 };
46
47Example: Required external clocks:
48
49 fin_pll: clock-fin-pll {
50 compatible = "fixed-clock";
51 clock-output-names = "fin_pll";
52 clock-frequency = <12000000>;
53 #clock-cells = <0>;
54 };
55
56 xusbxti: clock-xusbxti {
57 compatible = "fixed-clock";
58 clock-output-names = "xusbxti";
59 clock-frequency = <48000000>;
60 #clock-cells = <0>;
61 };
62
63Example: UART controller node that consumes the clock generated by the clock
64 controller (refer to the standard clock bindings for information about
65 "clocks" and "clock-names" properties):
66
67 uart0: serial@7f005000 {
68 compatible = "samsung,s3c6400-uart";
69 reg = <0x7f005000 0x100>;
70 interrupt-parent = <&vic1>;
71 interrupts = <5>;
72 clock-names = "uart", "clk_uart_baud2",
73 "clk_uart_baud3";
74 clocks = <&clock PCLK_UART0>, <&clocks PCLK_UART0>,
75 <&clock SCLK_UART>;
76 status = "disabled";
77 };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index d495521a79d2..00a5c26454eb 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -8,19 +8,31 @@ Required properties:
8- compatible : shall be one of the following: 8- compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator 9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock 10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
11 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock 12 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
12 "allwinner,sun4i-axi-clk" - for the AXI clock 13 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sun4i-axi-gates-clk" - for the AXI gates 14 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
14 "allwinner,sun4i-ahb-clk" - for the AHB clock 15 "allwinner,sun4i-ahb-clk" - for the AHB clock
15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10 16 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
16 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 17 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
18 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
19 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
20 "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
21 "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
17 "allwinner,sun4i-apb0-clk" - for the APB0 clock 22 "allwinner,sun4i-apb0-clk" - for the APB0 clock
18 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10 23 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
19 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13 24 "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
25 "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
26 "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
20 "allwinner,sun4i-apb1-clk" - for the APB1 clock 27 "allwinner,sun4i-apb1-clk" - for the APB1 clock
21 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing 28 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
22 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10 29 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
23 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13 30 "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
31 "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
32 "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
33 "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
34 "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
35 "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
24 36
25Required properties for all clocks: 37Required properties for all clocks:
26- reg : shall be the control register address for the clock. 38- reg : shall be the control register address for the clock.
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
new file mode 100644
index 000000000000..d24279fe1429
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun5i-a10s-gates.txt
@@ -0,0 +1,75 @@
1Gate clock outputs
2------------------
3
4 * AXI gates ("allwinner,sun4i-axi-gates-clk")
5
6 DRAM 0
7
8 * AHB gates ("allwinner,sun5i-a10s-ahb-gates-clk")
9
10 USB0 0
11 EHCI0 1
12 OHCI0 2
13
14 SS 5
15 DMA 6
16 BIST 7
17 MMC0 8
18 MMC1 9
19 MMC2 10
20
21 NAND 13
22 SDRAM 14
23
24 EMAC 17
25 TS 18
26
27 SPI0 20
28 SPI1 21
29 SPI2 22
30
31 GPS 26
32
33 HSTIMER 28
34
35 VE 32
36
37 TVE 34
38
39 LCD 36
40
41 CSI 40
42
43 HDMI 43
44 DE_BE 44
45
46 DE_FE 46
47
48 IEP 51
49 MALI400 52
50
51 * APB0 gates ("allwinner,sun5i-a10s-apb0-gates-clk")
52
53 CODEC 0
54
55 IIS 3
56
57 PIO 5
58 IR 6
59
60 KEYPAD 10
61
62 * APB1 gates ("allwinner,sun5i-a10s-apb1-gates-clk")
63
64 I2C0 0
65 I2C1 1
66 I2C2 2
67
68 UART0 16
69 UART1 17
70 UART2 18
71 UART3 19
72
73Notation:
74 [*]: The datasheet didn't mention these, but they are present on AW code
75 [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
new file mode 100644
index 000000000000..fe44932b5c6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun6i-a31-gates.txt
@@ -0,0 +1,83 @@
1Gate clock outputs
2------------------
3
4 * AHB1 gates ("allwinner,sun6i-a31-ahb1-gates-clk")
5
6 MIPI DSI 1
7
8 SS 5
9 DMA 6
10
11 MMC0 8
12 MMC1 9
13 MMC2 10
14 MMC3 11
15
16 NAND1 12
17 NAND0 13
18 SDRAM 14
19
20 GMAC 17
21 TS 18
22 HSTIMER 19
23 SPI0 20
24 SPI1 21
25 SPI2 22
26 SPI3 23
27 USB_OTG 24
28
29 EHCI0 26
30 EHCI1 27
31
32 OHCI0 29
33 OHCI1 30
34 OHCI2 31
35 VE 32
36
37 LCD0 36
38 LCD1 37
39
40 CSI 40
41
42 HDMI 43
43 DE_BE0 44
44 DE_BE1 45
45 DE_FE1 46
46 DE_FE1 47
47
48 MP 50
49
50 GPU 52
51
52 DEU0 55
53 DEU1 56
54 DRC0 57
55 DRC1 58
56
57 * APB1 gates ("allwinner,sun6i-a31-apb1-gates-clk")
58
59 CODEC 0
60
61 DIGITAL MIC 4
62 PIO 5
63
64 DAUDIO0 12
65 DAUDIO1 13
66
67 * APB2 gates ("allwinner,sun6i-a31-apb2-gates-clk")
68
69 I2C0 0
70 I2C1 1
71 I2C2 2
72 I2C3 3
73
74 UART0 16
75 UART1 17
76 UART2 18
77 UART3 19
78 UART4 20
79 UART5 21
80
81Notation:
82 [*]: The datasheet didn't mention these, but they are present on AW code
83 [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
new file mode 100644
index 000000000000..357f4fdc02ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi/sun7i-a20-gates.txt
@@ -0,0 +1,98 @@
1Gate clock outputs
2------------------
3
4 * AXI gates ("allwinner,sun4i-axi-gates-clk")
5
6 DRAM 0
7
8 * AHB gates ("allwinner,sun7i-a20-ahb-gates-clk")
9
10 USB0 0
11 EHCI0 1
12 OHCI0 2
13 EHCI1 3
14 OHCI1 4
15 SS 5
16 DMA 6
17 BIST 7
18 MMC0 8
19 MMC1 9
20 MMC2 10
21 MMC3 11
22 MS 12
23 NAND 13
24 SDRAM 14
25
26 ACE 16
27 EMAC 17
28 TS 18
29
30 SPI0 20
31 SPI1 21
32 SPI2 22
33 SPI3 23
34
35 SATA 25
36
37 HSTIMER 28
38
39 VE 32
40 TVD 33
41 TVE0 34
42 TVE1 35
43 LCD0 36
44 LCD1 37
45
46 CSI0 40
47 CSI1 41
48
49 HDMI1 42
50 HDMI0 43
51 DE_BE0 44
52 DE_BE1 45
53 DE_FE1 46
54 DE_FE1 47
55
56 GMAC 49
57 MP 50
58
59 MALI400 52
60
61 * APB0 gates ("allwinner,sun7i-a20-apb0-gates-clk")
62
63 CODEC 0
64 SPDIF 1
65 AC97 2
66 IIS0 3
67 IIS1 4
68 PIO 5
69 IR0 6
70 IR1 7
71 IIS2 8
72
73 KEYPAD 10
74
75 * APB1 gates ("allwinner,sun7i-a20-apb1-gates-clk")
76
77 I2C0 0
78 I2C1 1
79 I2C2 2
80 I2C3 3
81 CAN 4
82 SCR 5
83 PS20 6
84 PS21 7
85
86 I2C4 15
87 UART0 16
88 UART1 17
89 UART2 18
90 UART3 19
91 UART4 20
92 UART5 21
93 UART6 22
94 UART7 23
95
96Notation:
97 [*]: The datasheet didn't mention these, but they are present on AW code
98 [**]: The datasheet had this marked as "NC" but they are used on AW code
diff --git a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
index 3f454ffc654a..c4f358dafdaa 100644
--- a/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
+++ b/Documentation/devicetree/bindings/gpu/samsung-g2d.txt
@@ -11,8 +11,11 @@ Required properties:
11 11
12 - interrupts : G2D interrupt number to the CPU. 12 - interrupts : G2D interrupt number to the CPU.
13 - clocks : from common clock binding: handle to G2D clocks. 13 - clocks : from common clock binding: handle to G2D clocks.
14 - clock-names : from common clock binding: must contain "sclk_fimg2d" and 14 - clock-names : names of clocks listed in clocks property, in the same
15 "fimg2d", corresponding to entries in the clocks property. 15 order, depending on SoC type:
16 - for S5PV210 and Exynos4 based SoCs: "fimg2d" and
17 "sclk_fimg2d"
18 - for Exynos5250 SoC: "fimg2d".
16 19
17Example: 20Example:
18 g2d@12800000 { 21 g2d@12800000 {
diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
index 4caa1a78863e..d61fccd40bad 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.txt
@@ -19,6 +19,16 @@ Required properties:
19- reg: base address and size of register area 19- reg: base address and size of register area
20- interrupts: list of timer interrupts (one interrupt per timer, starting at 20- interrupts: list of timer interrupts (one interrupt per timer, starting at
21 timer 0) 21 timer 0)
22- clock-names: should contain all following required clock names:
23 - "timers" - PWM base clock used to generate PWM signals,
24 and any subset of following optional clock names:
25 - "pwm-tclk0" - first external PWM clock source,
26 - "pwm-tclk1" - second external PWM clock source.
27 Note that not all IP variants allow using all external clock sources.
28 Refer to SoC documentation to learn which clock source configurations
29 are available.
30- clocks: should contain clock specifiers of all clocks, which input names
31 have been specified in clock-names property, in same order.
22- #pwm-cells: should be 3. See pwm.txt in this directory for a description of 32- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
23 the cells format. The only third cell flag supported by this binding is 33 the cells format. The only third cell flag supported by this binding is
24 PWM_POLARITY_INVERTED. 34 PWM_POLARITY_INVERTED.
@@ -34,6 +44,8 @@ Example:
34 reg = <0x7f006000 0x1000>; 44 reg = <0x7f006000 0x1000>;
35 interrupt-parent = <&vic0>; 45 interrupt-parent = <&vic0>;
36 interrupts = <23>, <24>, <25>, <27>, <28>; 46 interrupts = <23>, <24>, <25>, <27>, <28>;
47 clocks = <&clock 67>;
48 clock-names = "timers";
37 samsung,pwm-outputs = <0>, <1>; 49 samsung,pwm-outputs = <0>, <1>;
38 #pwm-cells = <3>; 50 #pwm-cells = <3>;
39 } 51 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 16:26:23 -0500