246 files changed, 6917 insertions, 1038 deletions
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
index d74091a8a3bf..5fc03134a999 100644
--- a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
+++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt
@@ -1,4 +1,4 @@
-Marvell Armada 370 and Armada XP Interrupt Controller
+Marvell Armada 370, 375, 38x, XP Interrupt Controller
 -----------------------------------------------------
 Required properties:
@@ -16,7 +16,13 @@ Required properties:
  automatically map to the interrupt controller registers of the
  current CPU)
+Optional properties:
+- interrupts: If defined, then it indicates that this MPIC is
+  connected as a slave to another interrupt controller. This is
+  typically the case on Armada 375 and Armada 38x, where the MPIC is
+  connected as a slave to the Cortex-A9 GIC. The provided interrupt
+  indicate to which GIC interrupt the MPIC output is connected.
 Example:
diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt b/Documentation/devicetree/bindings/arm/armada-375.txt
new file mode 100644
index 000000000000..867d0b80cb8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-375.txt
@@ -0,0 +1,9 @@
+Marvell Armada 375 Platforms Device Tree Bindings
+-------------------------------------------------
+Boards with a SoC of the Marvell Armada 375 family shall have the
+following property:
+Required root node property:
+compatible: must contain "marvell,armada375"
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
new file mode 100644
index 000000000000..11f2330a6554
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
@@ -0,0 +1,10 @@
+Marvell Armada 38x Platforms Device Tree Bindings
+-------------------------------------------------
+Boards with a SoC of the Marvell Armada 38x family shall have the
+following property:
+Required root node property:
+ - compatible: must contain either "marvell,armada380" or
+   "marvell,armada385" depending on the variant of the SoC being used.
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm21664.txt b/Documentation/devicetree/bindings/arm/bcm/bcm21664.txt
new file mode 100644
index 000000000000..e0774255e1a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm21664.txt
@@ -0,0 +1,15 @@
+Broadcom BCM21664 device tree bindings
+--------------------------------------
+This document describes the device tree bindings for boards with the BCM21664
+SoC.
+Required root node property:
+  - compatible: brcm,bcm21664
+Example:
+        / {
+                model = "BCM21664 SoC";
+                compatible = "brcm,bcm21664";
+                [...]
+        }
diff --git a/Documentation/devicetree/bindings/arm/bcm/kona-resetmgr.txt b/Documentation/devicetree/bindings/arm/bcm/kona-resetmgr.txt
new file mode 100644
index 000000000000..93f31ca1ef4b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/kona-resetmgr.txt
@@ -0,0 +1,14 @@
+Broadcom Kona Family Reset Manager
+----------------------------------
+The reset manager is used on the Broadcom BCM21664 SoC.
+Required properties:
+  - compatible: brcm,bcm21664-resetmgr
+  - reg: memory address & range
+Example:
+        brcm,resetmgr@35001f00 {
+                compatible = "brcm,bcm21664-resetmgr";
+                reg = <0x35001f00 0x24>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/bcm4708.txt b/Documentation/devicetree/bindings/arm/bcm4708.txt
new file mode 100644
index 000000000000..6b0f49f6f499
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm4708.txt
@@ -0,0 +1,8 @@
+Broadcom BCM4708 device tree bindings
+-------------------------------------------
+Boards with the BCM4708 SoC shall have the following properties:
+Required root node property:
+compatible = "brcm,bcm4708";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91304353eea4..333f4aea3029 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
                          be one of:
                             "spin-table"
                             "psci"
-                        # On ARM 32-bit systems this property is optional.
+                        # On ARM 32-bit systems this property is optional and
+                          can be one of:
+                            "qcom,gcc-msm8660"
+                            "qcom,kpss-acc-v1"
+                            "qcom,kpss-acc-v2"
        - cpu-release-addr
                Usage: required for systems that have an "enable-method"
@@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
                          property identifying a 64-bit zero-initialised
                          memory location.
+        - qcom,saw
+                Usage: required for systems that have an "enable-method"
+                       property value of "qcom,kpss-acc-v1" or
+                       "qcom,kpss-acc-v2"
+                Value type: <phandle>
+                Definition: Specifies the SAW[1] node associated with this CPU.
+        - qcom,acc
+                Usage: required for systems that have an "enable-method"
+                       property value of "qcom,kpss-acc-v1" or
+                       "qcom,kpss-acc-v2"
+                Value type: <phandle>
+                Definition: Specifies the ACC[2] node associated with this CPU.
 Example 1 (dual-cluster big.LITTLE system 32-bit):
        cpus {
@@ -382,3 +401,7 @@ cpus {
                cpu-release-addr = <0 0x20000000>;
        };
 };
+--
+[1] arm/msm/qcom,saw2.txt
+[2] arm/msm/qcom,kpss-acc.txt
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index bae0d87a38b2..5573c08d3180 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -50,6 +50,11 @@ Optional
  regions, used when the GIC doesn't have banked registers. The offset is
  cpu-offset * cpu-nr.
+- arm,routable-irqs : Total number of gic irq inputs which are not directly
+                  connected from the peripherals, but are routed dynamically
+                  by a crossbar/multiplexer preceding the GIC. The GIC irq
+                  input line is assigned dynamically when the corresponding
+                  peripheral's crossbar line is mapped.
 Example:
        intc: interrupt-controller@fff11000 {
@@ -57,6 +62,7 @@ Example:
                #interrupt-cells = <3>;
                #address-cells = <1>;
                interrupt-controller;
+                arm,routable-irqs = <160>;
                reg = <0xfff11000 0x1000>,
                      <0xfff10100 0x100>;
        };
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 8c7a4653508d..df0a452b8526 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -30,3 +30,17 @@ Example:
                resume-offset = <0x308>;
                reboot-offset = <0x4>;
        };
+PCTRL: Peripheral misc control register
+Required Properties:
+- compatible: "hisilicon,pctrl"
+- reg: Address and size of pctrl.
+Example:
+        /* for Hi3620 */
+        pctrl: pctrl@fca09000 {
+                compatible = "hisilicon,pctrl";
+                reg = <0xfca09000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
index 63c0e6ae5cf7..59d7a46f85eb 100644
--- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt
+++ b/Documentation/devicetree/bindings/arm/keystone/keystone.txt
@@ -8,3 +8,13 @@ Required properties:
 - compatible: All TI specific devices present in Keystone SOC should be in
   the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550
   type UART should use the specified compatible for those devices.
+Boards:
+-  Keystone 2 Hawking/Kepler EVM
+   compatible = "ti,k2hk-evm","ti,keystone"
+-  Keystone 2 Lamarr EVM
+   compatible = "ti,k2l-evm","ti,keystone"
+-  Keystone 2 Edison EVM
+   compatible = "ti,k2e-evm","ti,keystone"
diff --git a/Documentation/devicetree/bindings/arm/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell,dove.txt
new file mode 100644
index 000000000000..aaaf64c56e44
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,dove.txt
@@ -0,0 +1,22 @@
+Marvell Dove Platforms Device Tree Bindings
+-----------------------------------------------
+Boards with a Marvell Dove SoC shall have the following properties:
+Required root node property:
+- compatible: must contain "marvell,dove";
+* Global Configuration registers
+Global Configuration registers of Dove SoC are shared by a syscon node.
+Required properties:
+- compatible: must contain "marvell,dove-global-config" and "syscon".
+- reg: base address and size of the Global Configuration registers.
+Example:
+gconf: global-config@e802c {
+        compatible = "marvell,dove-global-config", "syscon";
+        reg = <0xe802c 0x14>;
+};
diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
new file mode 100644
index 000000000000..0d244b999d10
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
@@ -0,0 +1,16 @@
+* Marvell Feroceon Cache
+Required properties:
+- compatible : Should be either "marvell,feroceon-cache" or
+               "marvell,kirkwood-cache".
+Optional properties:
+- reg        : Address of the L2 cache control register. Mandatory for
+               "marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
+Example:
+                l2: l2-cache@20128 {
+                        compatible = "marvell,kirkwood-cache";
+                        reg = <0x20128 0x4>;
+                };
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
new file mode 100644
index 000000000000..1333db9acfee
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -0,0 +1,30 @@
+Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
+The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+There is one ACC register region per CPU within the KPSS remapped region as
+well as an alias register region that remaps accesses to the ACC associated
+with the CPU accessing the region.
+PROPERTIES
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: should be one of:
+                        "qcom,kpss-acc-v1"
+                        "qcom,kpss-acc-v2"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the first element specifies the base address and size of
+                    the register region. An optional second element specifies
+                    the base address and size of the alias register region.
+Example:
+        clock-controller@2088000 {
+                compatible = "qcom,kpss-acc-v2";
+                reg = <0x02088000 0x1000>,
+                      <0x02008000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
new file mode 100644
index 000000000000..1505fb8e131a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -0,0 +1,35 @@
+SPM AVS Wrapper 2 (SAW2)
+The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+micro-controller that transitions a piece of hardware (like a processor or
+subsystem) into and out of low power modes via a direct connection to
+the PMIC. It can also be wired up to interact with other processors in the
+system, notifying them when a low power state is entered or exited.
+PROPERTIES
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: shall contain "qcom,saw2". A more specific value should be
+                    one of:
+                         "qcom,saw2-v1"
+                         "qcom,saw2-v1.1"
+                         "qcom,saw2-v2"
+                         "qcom,saw2-v2.1"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the first element specifies the base address and size of
+                    the register region. An optional second element specifies
+                    the base address and size of the alias register region.
+Example:
+        regulator@2099000 {
+                compatible = "qcom,saw2";
+                reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
index 081c6a786c8a..d24ab2ebf8a7 100644
--- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -1,12 +1,13 @@
 MVEBU System Controller
 -----------------------
-MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
 Required properties:
 - compatible: one of:
        - "marvell,orion-system-controller"
        - "marvell,armada-370-xp-system-controller"
+        - "marvell,armada-375-system-controller"
 - reg: Should contain system controller registers location and length.
 Example:
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
new file mode 100644
index 000000000000..fb88585cfb93
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -0,0 +1,27 @@
+Some socs have a large number of interrupts requests to service
+the needs of its many peripherals and subsystems. All of the
+interrupt lines from the subsystems are not needed at the same
+time, so they have to be muxed to the irq-controller appropriately.
+In such places a interrupt controllers are preceded by an CROSSBAR
+that provides flexibility in muxing the device requests to the controller
+inputs.
+Required properties:
+- compatible : Should be "ti,irq-crossbar"
+- reg: Base address and the size of the crossbar registers.
+- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- ti,reg-size: Size of a individual register in bytes. Every individual
+            register is assumed to be of same size. Valid sizes are 1, 2, 4.
+- ti,irqs-reserved: List of the reserved irq lines that are not muxed using
+                 crossbar. These interrupt lines are reserved in the soc,
+                 so crossbar bar driver should not consider them as free
+                 lines.
+Examples:
+                crossbar_mpu: @4a020000 {
+                        compatible = "ti,irq-crossbar";
+                        reg = <0x4a002a48 0x130>;
+                        ti,max-irqs = <160>;
+                        ti,reg-size = <2>;
+                        ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+                };
diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt
new file mode 100644
index 000000000000..8bd6d0a238a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/dmm.txt
@@ -0,0 +1,22 @@
+OMAP Dynamic Memory Manager (DMM) bindings
+The dynamic memory manager (DMM) is a module located immediately in front of the
+SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
+accesses such as priority generation amongst initiators, configuration of SDRAM
+interleaving, optimizing transfer of 2D block objects, and provide MMU-like page
+translation for initiators which need contiguous dma bus addresses.
+Required properties:
+- compatible:   Should contain "ti,omap4-dmm" for OMAP4 family
+                Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family
+- reg:          Contains DMM register address range (base address and length)
+- interrupts:   Should contain an interrupt-specifier for DMM_IRQ.
+- ti,hwmods:    Name of the hwmod associated to DMM, which is typically "dmm"
+Example:
+dmm@4e000000 {
+        compatible = "ti,omap4-dmm";
+        reg = <0x4e000000 0x800>;
+        ti,hwmods = "dmm";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 34dc40cffdfd..36ede19a1630 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -91,7 +91,7 @@ Boards:
  compatible = "ti,omap3-beagle", "ti,omap3"
 - OMAP3 Tobi with Overo : Commercial expansion board with daughter board
-  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
+  compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3"
 - OMAP4 SDP : Software Development Board
  compatible = "ti,omap4-sdp", "ti,omap4430"
@@ -99,6 +99,9 @@ Boards:
 - OMAP4 PandaBoard : Low cost community board
  compatible = "ti,omap4-panda", "ti,omap4430"
+- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
+  compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
 - OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
  compatible = "ti,omap3-evm", "ti,omap3"
@@ -114,5 +117,8 @@ Boards:
 - AM43x EPOS EVM
  compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
+- AM437x GP EVM
+  compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
 - DRA7 EVM:  Software Developement Board for DRA7XX
  compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 3e1e498fea96..fe5cef8976cb 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -9,6 +9,7 @@ Required properties:
 - compatible : should be one of
        "arm,armv8-pmuv3"
        "arm,cortex-a15-pmu"
+        "arm,cortex-a12-pmu"
        "arm,cortex-a9-pmu"
        "arm,cortex-a8-pmu"
        "arm,cortex-a7-pmu"
@@ -16,7 +17,14 @@ Required properties:
        "arm,arm11mpcore-pmu"
        "arm,arm1176-pmu"
        "arm,arm1136-pmu"
- interrupts : 1 combined interrupt or 1 per core.
+        "qcom,krait-pmu"
+- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
+               interrupt (PPI) then 1 interrupt should be specified.
+Optional properties:
+- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
+                     events.
 Example:
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt
new file mode 100644
index 000000000000..3ee9b428b2f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt
@@ -0,0 +1,16 @@
+Rockchip power-management-unit:
+-------------------------------
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+Required node properties:
+- compatible value : = "rockchip,rk3066-pmu";
+- reg : physical base address and the size of the registers window
+Example:
+        pmu@20004000 {
+                compatible = "rockchip,rk3066-pmu";
+                reg = <0x20004000 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
new file mode 100644
index 000000000000..d9416fb8db6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
@@ -0,0 +1,30 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+Rockchip's smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+Required sub-node properties:
+- compatible : should be "rockchip,rk3066-smp-sram"
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+Example:
+        sram: sram@10080000 {
+                compatible = "mmio-sram";
+                reg = <0x10080000 0x10000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                smp-sram@10080000 {
+                        compatible = "rockchip,rk3066-smp-sram";
+                        reg = <0x10080000 0x50>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
new file mode 100644
index 000000000000..f1f155255f28
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -0,0 +1,15 @@
+SAMSUNG Exynos SoC series PMU Registers
+Properties:
+ - compatible : should contain two values. First value must be one from following list:
+                   - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
+                   - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
+                second value must be always "syscon".
+ - reg : offset and length of the register set.
+Example :
+pmu_system_controller: system-controller@10040000 {
+        compatible = "samsung,exynos5250-pmu", "syscon";
+        reg = <0x10040000 0x5000>;
+};
diff --git a/Documentation/devicetree/bindings/arm/topology.txt b/Documentation/devicetree/bindings/arm/topology.txt
index 4aa20e7a424e..1061faf5f602 100644
--- a/Documentation/devicetree/bindings/arm/topology.txt
+++ b/Documentation/devicetree/bindings/arm/topology.txt
@@ -75,9 +75,10 @@ The cpu-map node can only contain three types of child nodes:
 whose bindings are described in paragraph 3.
-The nodes describing the CPU topology (cluster/core/thread) can only be
+The nodes describing the CPU topology (cluster/core/thread) can only
-defined within the cpu-map node.
+be defined within the cpu-map node and every core/thread in the system
-Any other configuration is consider invalid and therefore must be ignored.
+must be defined within the topology.  Any other configuration is
+invalid and therefore must be ignored.
 ===========================================
 2.1 - cpu-map child nodes naming convention
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 89de1564950c..48b285ffa3a6 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -4,17 +4,33 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 Required properties:
- compatible        : compatible list, contains "snps,spear-ahci"
+- compatible        : compatible list, one of "snps,spear-ahci",
+                      "snps,exynos5440-ahci", "ibm,476gtr-ahci",
+                      "allwinner,sun4i-a10-ahci", "fsl,imx53-ahci"
+                      "fsl,imx6q-ahci" or "snps,dwc-ahci"
 - interrupts        : <interrupt mapping for SATA IRQ>
 - reg               : <registers mapping>
 Optional properties:
 - dma-coherent      : Present if dma operations are coherent
+- clocks            : a list of phandle + clock specifier pairs
+- target-supply     : regulator for SATA target power
-Example:
+"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
+- clocks            : must contain the sata, sata_ref and ahb clocks
+- clock-names       : must contain "ahb" for the ahb clock
+Examples:
        sata@ffe08000 {
                compatible = "snps,spear-ahci";
                reg = <0xffe08000 0x1000>;
                interrupts = <115>;
        };
+        ahci: sata@01c18000 {
+                compatible = "allwinner,sun4i-a10-ahci";
+                reg = <0x01c18000 0x1000>;
+                interrupts = <56>;
+                clocks = <&pll6 0>, <&ahb_gates 25>;
+                target-supply = <&reg_ahci_5v>;
+        };
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
new file mode 100644
index 000000000000..7bcfbf59810e
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -0,0 +1,76 @@
+* APM X-Gene 6.0 Gb/s SATA host controller nodes
+SATA host controller nodes are defined to describe on-chip Serial ATA
+controllers. Each SATA controller (pair of ports) have its own node.
+Required properties:
+- compatible            : Shall contain:
+  * "apm,xgene-ahci"
+- reg                   : First memory resource shall be the AHCI memory
+                          resource.
+                          Second memory resource shall be the host controller
+                          core memory resource.
+                          Third memory resource shall be the host controller
+                          diagnostic memory resource.
+                          4th memory resource shall be the host controller
+                          AXI memory resource.
+                          5th optional memory resource shall be the host
+                          controller MUX memory resource if required.
+- interrupts            : Interrupt-specifier for SATA host controller IRQ.
+- clocks                : Reference to the clock entry.
+- phys                  : A list of phandles + phy-specifiers, one for each
+                          entry in phy-names.
+- phy-names             : Should contain:
+  * "sata-phy" for the SATA 6.0Gbps PHY
+Optional properties:
+- status                : Shall be "ok" if enabled or "disabled" if disabled.
+                          Default is "ok".
+Example:
+                sataclk: sataclk {
+                        compatible = "fixed-clock";
+                        #clock-cells = <1>;
+                        clock-frequency = <100000000>;
+                        clock-output-names = "sataclk";
+                };
+                phy2: phy@1f22a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f22a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                };
+                phy3: phy@1f23a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f23a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                };
+                sata2: sata@1a400000 {
+                        compatible = "apm,xgene-ahci";
+                        reg = <0x0 0x1a400000 0x0 0x1000>,
+                              <0x0 0x1f220000 0x0 0x1000>,
+                              <0x0 0x1f22d000 0x0 0x1000>,
+                              <0x0 0x1f22e000 0x0 0x1000>,
+                              <0x0 0x1f227000 0x0 0x1000>;
+                        interrupts = <0x0 0x87 0x4>;
+                        status = "ok";
+                        clocks = <&sataclk 0>;
+                        phys = <&phy2 0>;
+                        phy-names = "sata-phy";
+                };
+                sata3: sata@1a800000 {
+                        compatible = "apm,xgene-ahci-pcie";
+                        reg = <0x0 0x1a800000 0x0 0x1000>,
+                              <0x0 0x1f230000 0x0 0x1000>,
+                              <0x0 0x1f23d000 0x0 0x1000>,
+                              <0x0 0x1f23e000 0x0 0x1000>,
+                              <0x0 0x1f237000 0x0 0x1000>;
+                        interrupts = <0x0 0x88 0x4>;
+                        status = "ok";
+                        clocks = <&sataclk 0>;
+                        phys = <&phy3 0>;
+                        phy-names = "sata-phy";
+                };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fac688e..000000000000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-Required properties:
- compatible        : compatible list, contains "samsung,exynos5-sata-phy"
- reg               : <registers mapping>
-Example:
-        sata@ffe07000 {
-                compatible = "samsung,exynos5-sata-phy";
-                reg = <0xffe07000 0x1000>;
-        };
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f1025e34..cb48448247ea 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,27 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
 Each SATA controller should have its own node.
 Required properties:
- compatible        : compatible list, contains "samsung,exynos5-sata"
+- compatible            : compatible list, contains "samsung,exynos5-sata"
- interrupts        : <interrupt mapping for SATA IRQ>
+- interrupts            : <interrupt mapping for SATA IRQ>
- reg               : <registers mapping>
+- reg                   : <registers mapping>
- samsung,sata-freq : <frequency in MHz>
+- samsung,sata-freq     : <frequency in MHz>
+- phys                  : Must contain exactly one entry as specified
+                          in phy-bindings.txt
+- phy-names             : Must be "sata-phy"
+Optional properties:
+- clocks                : Must contain an entry for each entry in clock-names.
+- clock-names           : Shall be "sata" for the external SATA bus clock,
+                          and "sclk_sata" for the internal controller clock.
 Example:
-        sata@ffe08000 {
+        sata@122f0000 {
-                compatible = "samsung,exynos5-sata";
+                compatible = "snps,dwc-ahci";
-                reg = <0xffe08000 0x1000>;
+                samsung,sata-freq = <66>;
-                interrupts = <115>;
+                reg = <0x122f0000 0x1ff>;
-        };
+                interrupts = <0 115 0>;
+                clocks = <&clock 277>, <&clock 143>;
+                clock-names = "sata", "sclk_sata";
+                phys = <&sata_phy>;
+                phy-names = "sata-phy";
+        };
diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt
index 0fd76c405208..6630d842c7a3 100644
--- a/Documentation/devicetree/bindings/bus/imx-weim.txt
+++ b/Documentation/devicetree/bindings/bus/imx-weim.txt
@@ -8,7 +8,12 @@ The actual devices are instantiated from the child nodes of a WEIM node.
 Required properties:
- - compatible:          Should be set to "fsl,<soc>-weim"
+ - compatible:          Should contain one of the following:
+                          "fsl,imx1-weim"
+                          "fsl,imx27-weim"
+                          "fsl,imx51-weim"
+                          "fsl,imx50-weim"
+                          "fsl,imx6q-weim"
 - reg:                 A resource specifier for the register space
                        (see the example below)
 - clocks:              the clock, see the example below.
@@ -19,6 +24,26 @@ Required properties:
                           <cs-number> 0 <physical address of mapping> <size>
+Optional properties:
+ - fsl,weim-cs-gpr:     For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
+                        devices, it should be the phandle to the system General
+                        Purpose Register controller that contains WEIM CS GPR
+                        register, e.g. IOMUXC_GPR1 on i.MX6Q.  IOMUXC_GPR1[11:0]
+                        should be set up as one of the following 4 possible
+                        values depending on the CS space configuration.
+                        IOMUXC_GPR1[11:0]    CS0    CS1    CS2    CS3
+                        ---------------------------------------------
+                                05          128M     0M     0M     0M
+                                033          64M    64M     0M     0M
+                                0113         64M    32M    32M     0M
+                                01111        32M    32M    32M    32M
+                        In case that the property is absent, the reset value or
+                        what bootloader sets up in IOMUXC_GPR1[11:0] will be
+                        used.
 Timing property for child nodes. It is mandatory, not optional.
 - fsl,weim-cs-timing:  The timing array, contains timing values for the
@@ -43,6 +68,7 @@ Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
                #address-cells = <2>;
                #size-cells = <1>;
                ranges = <0 0 0x08000000 0x08000000>;
+                fsl,weim-cs-gpr = <&gpr>;
                nor@0,0 {
                        compatible = "cfi-flash";
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
index 0045433eae1f..5dfd145d3ccf 100644
--- a/Documentation/devicetree/bindings/clock/altr_socfpga.txt
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -23,3 +23,8 @@ Optional properties:
        and the bit index.
 - div-reg : For "socfpga-gate-clk", div-reg contains the divider register, bit shift,
        and width.
+- clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
+        the SDMMC CIU clock. The first value is the clk_sample(smpsel), and the second
+        value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
+        hold/delay times that is needed for the SD/MMC CIU clock. The values of both
+        can be 0-315 degrees, in 45 degree increments.
diff --git a/Documentation/devicetree/bindings/clock/arm-integrator.txt b/Documentation/devicetree/bindings/clock/arm-integrator.txt
new file mode 100644
index 000000000000..652914b17b95
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/arm-integrator.txt
@@ -0,0 +1,34 @@
+Clock bindings for ARM Integrator Core Module clocks
+Auxilary Oscillator Clock
+This is a configurable clock fed from a 24 MHz chrystal,
+used for generating e.g. video clocks. It is located on the
+core module and there is only one of these.
+This clock node *must* be a subnode of the core module, since
+it obtains the base address for it's address range from its
+parent node.
+Required properties:
+- compatible: must be "arm,integrator-cm-auxosc"
+- #clock-cells: must be <0>
+Optional properties:
+- clocks: parent clock(s)
+Example:
+core-module@10000000 {
+        xtal24mhz: xtal24mhz@24M {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+        auxosc: cm_aux_osc@25M {
+                #clock-cells = <0>;
+                compatible = "arm,integrator-cm-auxosc";
+                clocks = <&xtal24mhz>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
index 028b493e97ff..20e1704e7df2 100644
--- a/Documentation/devicetree/bindings/clock/axi-clkgen.txt
+++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
@@ -5,7 +5,7 @@ This binding uses the common clock binding[1].
 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
 Required properties:
- compatible : shall be "adi,axi-clkgen".
+- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
 - #clock-cells : from common clock binding; Should always be set to 0.
 - reg : Address and length of the axi-clkgen register set.
 - clocks : Phandle and clock specifier for the parent clock.
diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
index 7c52c29d99fa..700e7aac3717 100644
--- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
+++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -44,6 +44,23 @@ For example:
  clocks by index. The names should reflect the clock output signal
  names for the device.
+clock-indices:     If the identifyng number for the clocks in the node
+                   is not linear from zero, then the this mapping allows
+                   the mapping of identifiers into the clock-output-names
+                   array.
+For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
+        oscillator {
+                compatible = "myclocktype";
+                #clock-cells = <1>;
+                clock-indices = <1>, <3>;
+                clock-output-names = "clka", "clkb";
+        }
+        This ensures we do not have any empty nodes in clock-output-names
 ==Clock consumers==
 Required properties:
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index a2ac2d9ac71a..f5a5b19ed3b2 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -15,259 +15,12 @@ Required Properties:
 - #clock-cells: should be 1.
-The following is the list of clocks generated by the controller. Each clock is
+Each clock is assigned an identifier and client nodes can use this identifier
-assigned an identifier and client nodes use this identifier to specify the
+to specify the clock which they consume.
-clock which they consume. Some of the clocks are available only on a particular
-Exynos4 SoC and this is specified where applicable.
-                 [Core Clocks]
-  Clock               ID      SoC (if specific)
-  -----------------------------------------------
-  xxti                1
-  xusbxti             2
-  fin_pll             3
-  fout_apll           4
-  fout_mpll           5
-  fout_epll           6
-  fout_vpll           7
-  sclk_apll           8
-  sclk_mpll           9
-  sclk_epll           10
-  sclk_vpll           11
-  arm_clk             12
-  aclk200             13
-  aclk100             14
-  aclk160             15
-  aclk133             16
-  mout_mpll_user_t    17      Exynos4x12
-  mout_mpll_user_c    18      Exynos4x12
-  mout_core           19
-  mout_apll           20
-            [Clock Gate for Special Clocks]
-  Clock               ID      SoC (if specific)
-  -----------------------------------------------
-  sclk_fimc0          128
-  sclk_fimc1          129
-  sclk_fimc2          130
-  sclk_fimc3          131
-  sclk_cam0           132
-  sclk_cam1           133
-  sclk_csis0          134
-  sclk_csis1          135
-  sclk_hdmi           136
-  sclk_mixer          137
-  sclk_dac            138
-  sclk_pixel          139
-  sclk_fimd0          140
-  sclk_mdnie0         141     Exynos4412
-  sclk_mdnie_pwm0 12  142     Exynos4412
-  sclk_mipi0          143
-  sclk_audio0         144
-  sclk_mmc0           145
-  sclk_mmc1           146
-  sclk_mmc2           147
-  sclk_mmc3           148
-  sclk_mmc4           149
-  sclk_sata           150     Exynos4210
-  sclk_uart0          151
-  sclk_uart1          152
-  sclk_uart2          153
-  sclk_uart3          154
-  sclk_uart4          155
-  sclk_audio1         156
-  sclk_audio2         157
-  sclk_spdif          158
-  sclk_spi0           159
-  sclk_spi1           160
-  sclk_spi2           161
-  sclk_slimbus        162
-  sclk_fimd1          163     Exynos4210
-  sclk_mipi1          164     Exynos4210
-  sclk_pcm1           165
-  sclk_pcm2           166
-  sclk_i2s1           167
-  sclk_i2s2           168
-  sclk_mipihsi        169     Exynos4412
-  sclk_mfc            170
-  sclk_pcm0           171
-  sclk_g3d            172
-  sclk_pwm_isp        173     Exynos4x12
-  sclk_spi0_isp       174     Exynos4x12
-  sclk_spi1_isp       175     Exynos4x12
-  sclk_uart_isp       176     Exynos4x12
-  sclk_fimg2d         177
-              [Peripheral Clock Gates]
-  Clock               ID      SoC (if specific)
-  -----------------------------------------------
-  fimc0               256
-  fimc1               257
-  fimc2               258
-  fimc3               259
-  csis0               260
-  csis1               261
-  jpeg                262
-  smmu_fimc0          263
-  smmu_fimc1          264
-  smmu_fimc2          265
-  smmu_fimc3          266
-  smmu_jpeg           267
-  vp                  268
-  mixer               269
-  tvenc               270     Exynos4210
-  hdmi                271
-  smmu_tv             272
-  mfc                 273
-  smmu_mfcl           274
-  smmu_mfcr           275
-  g3d                 276
-  g2d                 277
-  rotator             278     Exynos4210
-  mdma                279     Exynos4210
-  smmu_g2d            280     Exynos4210
-  smmu_rotator        281     Exynos4210
-  smmu_mdma           282     Exynos4210
-  fimd0               283
-  mie0                284
-  mdnie0              285     Exynos4412
-  dsim0               286
-  smmu_fimd0          287
-  fimd1               288     Exynos4210
-  mie1                289     Exynos4210
-  dsim1               290     Exynos4210
-  smmu_fimd1          291     Exynos4210
-  pdma0               292
-  pdma1               293
-  pcie_phy            294
-  sata_phy            295     Exynos4210
-  tsi                 296
-  sdmmc0              297
-  sdmmc1              298
-  sdmmc2              299
-  sdmmc3              300
-  sdmmc4              301
-  sata                302     Exynos4210
-  sromc               303
-  usb_host            304
-  usb_device          305
-  pcie                306
-  onenand             307
-  nfcon               308
-  smmu_pcie           309
-  gps                 310
-  smmu_gps            311
-  uart0               312
-  uart1               313
-  uart2               314
-  uart3               315
-  uart4               316
-  i2c0                317
-  i2c1                318
-  i2c2                319
-  i2c3                320
-  i2c4                321
-  i2c5                322
-  i2c6                323
-  i2c7                324
-  i2c_hdmi            325
-  tsadc               326
-  spi0                327
-  spi1                328
-  spi2                329
-  i2s1                330
-  i2s2                331
-  pcm0                332
-  i2s0                333
-  pcm1                334
-  pcm2                335
-  pwm                 336
-  slimbus             337
-  spdif               338
-  ac97                339
-  modemif             340
-  chipid              341
-  sysreg              342
-  hdmi_cec            343
-  mct                 344
-  wdt                 345
-  rtc                 346
-  keyif               347
-  audss               348
-  mipi_hsi            349     Exynos4210
-  mdma2               350     Exynos4210
-  pixelasyncm0        351
-  pixelasyncm1        352
-  fimc_lite0          353     Exynos4x12
-  fimc_lite1          354     Exynos4x12
-  ppmuispx            355     Exynos4x12
-  ppmuispmx           356     Exynos4x12
-  fimc_isp            357     Exynos4x12
-  fimc_drc            358     Exynos4x12
-  fimc_fd             359     Exynos4x12
-  mcuisp              360     Exynos4x12
-  gicisp              361     Exynos4x12
-  smmu_isp            362     Exynos4x12
-  smmu_drc            363     Exynos4x12
-  smmu_fd             364     Exynos4x12
-  smmu_lite0          365     Exynos4x12
-  smmu_lite1          366     Exynos4x12
-  mcuctl_isp          367     Exynos4x12
-  mpwm_isp            368     Exynos4x12
-  i2c0_isp            369     Exynos4x12
-  i2c1_isp            370     Exynos4x12
-  mtcadc_isp          371     Exynos4x12
-  pwm_isp             372     Exynos4x12
-  wdt_isp             373     Exynos4x12
-  uart_isp            374     Exynos4x12
-  asyncaxim           375     Exynos4x12
-  smmu_ispcx          376     Exynos4x12
-  spi0_isp            377     Exynos4x12
-  spi1_isp            378     Exynos4x12
-  pwm_isp_sclk        379     Exynos4x12
-  spi0_isp_sclk       380     Exynos4x12
-  spi1_isp_sclk       381     Exynos4x12
-  uart_isp_sclk       382     Exynos4x12
-  tmu_apbif           383
-                [Mux Clocks]
-  Clock                 ID      SoC (if specific)
-  -----------------------------------------------
-  mout_fimc0            384
-  mout_fimc1            385
-  mout_fimc2            386
-  mout_fimc3            387
-  mout_cam0             388
-  mout_cam1             389
-  mout_csis0            390
-  mout_csis1            391
-  mout_g3d0             392
-  mout_g3d1             393
-  mout_g3d              394
-  aclk400_mcuisp        395     Exynos4x12
-                [Div Clocks]
-  Clock                 ID      SoC (if specific)
-  -----------------------------------------------
-  div_isp0              450     Exynos4x12
-  div_isp1              451     Exynos4x12
-  div_mcuisp0           452     Exynos4x12
-  div_mcuisp1           453     Exynos4x12
-  div_aclk200           454     Exynos4x12
-  div_aclk400_mcuisp    455     Exynos4x12
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4.h header and can be used in device
+tree sources.
 Example 1: An example of a clock controller node is listed below.
@@ -285,6 +38,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
                compatible = "samsung,exynos4210-uart";
                reg = <0x13820000 0x100>;
                interrupts = <0 54 0>;
-                clocks = <&clock 314>, <&clock 153>;
+                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 72ce617dea82..536eacd1063f 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -13,163 +13,12 @@ Required Properties:
 - #clock-cells: should be 1.
-The following is the list of clocks generated by the controller. Each clock is
+Each clock is assigned an identifier and client nodes can use this identifier
-assigned an identifier and client nodes use this identifier to specify the
+to specify the clock which they consume.
-clock which they consume.
-       [Core Clocks]
-  Clock                 ID
-  ----------------------------
-  fin_pll               1
-  [Clock Gate for Special Clocks]
-  Clock                 ID
-  ----------------------------
-  sclk_cam_bayer        128
-  sclk_cam0             129
-  sclk_cam1             130
-  sclk_gscl_wa          131
-  sclk_gscl_wb          132
-  sclk_fimd1            133
-  sclk_mipi1            134
-  sclk_dp               135
-  sclk_hdmi             136
-  sclk_pixel            137
-  sclk_audio0           138
-  sclk_mmc0             139
-  sclk_mmc1             140
-  sclk_mmc2             141
-  sclk_mmc3             142
-  sclk_sata             143
-  sclk_usb3             144
-  sclk_jpeg             145
-  sclk_uart0            146
-  sclk_uart1            147
-  sclk_uart2            148
-  sclk_uart3            149
-  sclk_pwm              150
-  sclk_audio1           151
-  sclk_audio2           152
-  sclk_spdif            153
-  sclk_spi0             154
-  sclk_spi1             155
-  sclk_spi2             156
-  div_i2s1              157
-  div_i2s2              158
-  sclk_hdmiphy          159
-  div_pcm0              160
-   [Peripheral Clock Gates]
-  Clock                 ID
-  ----------------------------
-  gscl0                 256
-  gscl1                 257
-  gscl2                 258
-  gscl3                 259
-  gscl_wa               260
-  gscl_wb               261
-  smmu_gscl0            262
-  smmu_gscl1            263
-  smmu_gscl2            264
-  smmu_gscl3            265
-  mfc                   266
-  smmu_mfcl             267
-  smmu_mfcr             268
-  rotator               269
-  jpeg                  270
-  mdma1                 271
-  smmu_rotator          272
-  smmu_jpeg             273
-  smmu_mdma1            274
-  pdma0                 275
-  pdma1                 276
-  sata                  277
-  usbotg                278
-  mipi_hsi              279
-  sdmmc0                280
-  sdmmc1                281
-  sdmmc2                282
-  sdmmc3                283
-  sromc                 284
-  usb2                  285
-  usb3                  286
-  sata_phyctrl          287
-  sata_phyi2c           288
-  uart0                 289
-  uart1                 290
-  uart2                 291
-  uart3                 292
-  uart4                 293
-  i2c0                  294
-  i2c1                  295
-  i2c2                  296
-  i2c3                  297
-  i2c4                  298
-  i2c5                  299
-  i2c6                  300
-  i2c7                  301
-  i2c_hdmi              302
-  adc                   303
-  spi0                  304
-  spi1                  305
-  spi2                  306
-  i2s1                  307
-  i2s2                  308
-  pcm1                  309
-  pcm2                  310
-  pwm                   311
-  spdif                 312
-  ac97                  313
-  hsi2c0                314
-  hsi2c1                315
-  hs12c2                316
-  hs12c3                317
-  chipid                318
-  sysreg                319
-  pmu                   320
-  cmu_top               321
-  cmu_core              322
-  cmu_mem               323
-  tzpc0                 324
-  tzpc1                 325
-  tzpc2                 326
-  tzpc3                 327
-  tzpc4                 328
-  tzpc5                 329
-  tzpc6                 330
-  tzpc7                 331
-  tzpc8                 332
-  tzpc9                 333
-  hdmi_cec              334
-  mct                   335
-  wdt                   336
-  rtc                   337
-  tmu                   338
-  fimd1                 339
-  mie1                  340
-  dsim0                 341
-  dp                    342
-  mixer                 343
-  hdmi                  344
-  g2d                   345
-  mdma0                 346
-  smmu_mdma0            347
-   [Clock Muxes]
-  Clock                 ID
-  ----------------------------
-  mout_hdmi             1024
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5250.h header and can be used in device
+tree sources.
 Example 1: An example of a clock controller node is listed below.
@@ -187,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
                compatible = "samsung,exynos4210-uart";
                reg = <0x13820000 0x100>;
                interrupts = <0 54 0>;
-                clocks = <&clock 314>, <&clock 153>;
+                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 458f34789e5d..ca88c97a8562 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -13,184 +13,12 @@ Required Properties:
 - #clock-cells: should be 1.
-The following is the list of clocks generated by the controller. Each clock is
+Each clock is assigned an identifier and client nodes can use this identifier
-assigned an identifier and client nodes use this identifier to specify the
+to specify the clock which they consume.
-clock which they consume.
+All available clocks are defined as preprocessor macros in
-       [Core Clocks]
+dt-bindings/clock/exynos5420.h header and can be used in device
+tree sources.
-  Clock                 ID
-  ----------------------------
-  fin_pll               1
-  [Clock Gate for Special Clocks]
-  Clock                 ID
-  ----------------------------
-  sclk_uart0            128
-  sclk_uart1            129
-  sclk_uart2            130
-  sclk_uart3            131
-  sclk_mmc0             132
-  sclk_mmc1             133
-  sclk_mmc2             134
-  sclk_spi0             135
-  sclk_spi1             136
-  sclk_spi2             137
-  sclk_i2s1             138
-  sclk_i2s2             139
-  sclk_pcm1             140
-  sclk_pcm2             141
-  sclk_spdif            142
-  sclk_hdmi             143
-  sclk_pixel            144
-  sclk_dp1              145
-  sclk_mipi1            146
-  sclk_fimd1            147
-  sclk_maudio0          148
-  sclk_maupcm0          149
-  sclk_usbd300          150
-  sclk_usbd301          151
-  sclk_usbphy300        152
-  sclk_usbphy301        153
-  sclk_unipro           154
-  sclk_pwm              155
-  sclk_gscl_wa          156
-  sclk_gscl_wb          157
-  sclk_hdmiphy          158
-   [Peripheral Clock Gates]
-  Clock                 ID
-  ----------------------------
-  aclk66_peric          256
-  uart0                 257
-  uart1                 258
-  uart2                 259
-  uart3                 260
-  i2c0                  261
-  i2c1                  262
-  i2c2                  263
-  i2c3                  264
-  i2c4                  265
-  i2c5                  266
-  i2c6                  267
-  i2c7                  268
-  i2c_hdmi              269
-  tsadc                 270
-  spi0                  271
-  spi1                  272
-  spi2                  273
-  keyif                 274
-  i2s1                  275
-  i2s2                  276
-  pcm1                  277
-  pcm2                  278
-  pwm                   279
-  spdif                 280
-  i2c8                  281
-  i2c9                  282
-  i2c10                 283
-  aclk66_psgen          300
-  chipid                301
-  sysreg                302
-  tzpc0                 303
-  tzpc1                 304
-  tzpc2                 305
-  tzpc3                 306
-  tzpc4                 307
-  tzpc5                 308
-  tzpc6                 309
-  tzpc7                 310
-  tzpc8                 311
-  tzpc9                 312
-  hdmi_cec              313
-  seckey                314
-  mct                   315
-  wdt                   316
-  rtc                   317
-  tmu                   318
-  tmu_gpu               319
-  pclk66_gpio           330
-  aclk200_fsys2         350
-  mmc0                  351
-  mmc1                  352
-  mmc2                  353
-  sromc                 354
-  ufs                   355
-  aclk200_fsys          360
-  tsi                   361
-  pdma0                 362
-  pdma1                 363
-  rtic                  364
-  usbh20                365
-  usbd300               366
-  usbd301               377
-  aclk400_mscl          380
-  mscl0                 381
-  mscl1                 382
-  mscl2                 383
-  smmu_mscl0            384
-  smmu_mscl1            385
-  smmu_mscl2            386
-  aclk333               400
-  mfc                   401
-  smmu_mfcl             402
-  smmu_mfcr             403
-  aclk200_disp1         410
-  dsim1                 411
-  dp1                   412
-  hdmi                  413
-  aclk300_disp1         420
-  fimd1                 421
-  smmu_fimd1            422
-  aclk166               430
-  mixer                 431
-  aclk266               440
-  rotator               441
-  mdma1                 442
-  smmu_rotator          443
-  smmu_mdma1            444
-  aclk300_jpeg          450
-  jpeg                  451
-  jpeg2                 452
-  smmu_jpeg             453
-  aclk300_gscl          460
-  smmu_gscl0            461
-  smmu_gscl1            462
-  gscl_wa               463
-  gscl_wb               464
-  gscl0                 465
-  gscl1                 466
-  clk_3aa               467
-  aclk266_g2d           470
-  sss                   471
-  slim_sss              472
-  mdma0                 473
-  aclk333_g2d           480
-  g2d                   481
-  aclk333_432_gscl      490
-  smmu_3aa              491
-  smmu_fimcl0           492
-  smmu_fimcl1           493
-  smmu_fimcl3           494
-  fimc_lite3            495
-  aclk_g3d              500
-  g3d                   501
-  smmu_mixer            502
-  Mux                   ID
-  ----------------------------
-  mout_hdmi             640
-  Divider               ID
-  ----------------------------
-  dout_pixel            768
 Example 1: An example of a clock controller node is listed below.
@@ -208,6 +36,6 @@ Example 2: UART controller node that consumes the clock generated by the clock
                compatible = "samsung,exynos4210-uart";
                reg = <0x13820000 0x100>;
                interrupts = <0 54 0>;
-                clocks = <&clock 259>, <&clock 130>;
+                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
        };
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
index 9955dc9c7d96..5f7005f73058 100644
--- a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -12,45 +12,12 @@ Required Properties:
 - #clock-cells: should be 1.
-The following is the list of clocks generated by the controller. Each clock is
+Each clock is assigned an identifier and client nodes can use this identifier
-assigned an identifier and client nodes use this identifier to specify the
+to specify the clock which they consume.
-clock which they consume.
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5440.h header and can be used in device
-       [Core Clocks]
+tree sources.
-  Clock                 ID
-  ----------------------------
-  xtal                  1
-  arm_clk               2
-   [Peripheral Clock Gates]
-  Clock                 ID
-  ----------------------------
-  spi_baud              16
-  pb0_250               17
-  pr0_250               18
-  pr1_250               19
-  b_250                 20
-  b_125                 21
-  b_200                 22
-  sata                  23
-  usb                   24
-  gmac0                 25
-  cs250                 26
-  pb0_250_o             27
-  pr0_250_o             28
-  pr1_250_o             29
-  b_250_o               30
-  b_125_o               31
-  b_200_o               32
-  sata_o                33
-  usb_o                 34
-  gmac0_o               35
-  cs250_o               36
 Example: An example of a clock controller node is listed below.
diff --git a/Documentation/devicetree/bindings/clock/hi3620-clock.txt b/Documentation/devicetree/bindings/clock/hi3620-clock.txt
index 4b71ab41be53..dad6269f52c5 100644
--- a/Documentation/devicetree/bindings/clock/hi3620-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi3620-clock.txt
@@ -7,6 +7,7 @@ Required Properties:
 - compatible: should be one of the following.
  - "hisilicon,hi3620-clock" - controller compatible with Hi3620 SoC.
+  - "hisilicon,hi3620-mmc-clock" - controller specific for Hi3620 mmc.
 - reg: physical base address of the controller and length of memory mapped
  region.
diff --git a/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt
new file mode 100644
index 000000000000..fedea84314a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/moxa,moxart-clock.txt
@@ -0,0 +1,48 @@
+Device Tree Clock bindings for arch-moxart
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+MOXA ART SoCs allow to determine PLL output and APB frequencies
+by reading registers holding multiplier and divisor information.
+PLL:
+Required properties:
+- compatible : Must be "moxa,moxart-pll-clock"
+- #clock-cells : Should be 0
+- reg : Should contain registers location and length
+- clocks : Should contain phandle + clock-specifier for the parent clock
+Optional properties:
+- clock-output-names : Should contain clock name
+APB:
+Required properties:
+- compatible : Must be "moxa,moxart-apb-clock"
+- #clock-cells : Should be 0
+- reg : Should contain registers location and length
+- clocks : Should contain phandle + clock-specifier for the parent clock
+Optional properties:
+- clock-output-names : Should contain clock name
+For example:
+        clk_pll: clk_pll@98100000 {
+                compatible = "moxa,moxart-pll-clock";
+                #clock-cells = <0>;
+                reg = <0x98100000 0x34>;
+        };
+        clk_apb: clk_apb@98100000 {
+                compatible = "moxa,moxart-apb-clock";
+                #clock-cells = <0>;
+                reg = <0x98100000 0x34>;
+                clocks = <&clk_pll>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index 1e662948661e..307a503c5db8 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -11,6 +11,18 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
 3 = hclk    (DRAM control clock)
 4 = dramclk (DDR clock)
+The following is a list of provided IDs and clock names on Armada 375:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = l2clk   (L2 Cache clock)
+ 3 = ddrclk  (DDR clock)
+The following is a list of provided IDs and clock names on Armada 380/385:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = l2clk   (L2 Cache clock)
+ 3 = ddrclk  (DDR clock)
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
 0 = tclk   (Internal Bus clock)
 1 = cpuclk (CPU0 clock)
@@ -20,6 +32,8 @@ The following is a list of provided IDs and clock names on Kirkwood and Dove:
 Required properties:
 - compatible : shall be one of the following:
        "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
+        "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
+        "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
        "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
        "marvell,dove-core-clock" - for Dove SoC core clocks
        "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index c62391fc0e39..520562a7dc2a 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
 0 = nand (NAND clock)
 Required properties:
- compatible : must be "marvell,armada-370-corediv-clock"
+- compatible : must be "marvell,armada-370-corediv-clock",
+                       "marvell,armada-375-corediv-clock",
+                       "marvell,armada-380-corediv-clock",
 - reg : must be the register address of Core Divider control register
 - #clock-cells : from common clock binding; shall be set to 1
 - clocks : must be set to the parent's phandle
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index fc2910fa7e45..76477be742b2 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -1,9 +1,10 @@
 * Gated Clock bindings for Marvell EBU SoCs
-Marvell Armada 370/XP, Dove and Kirkwood allow some peripheral clocks to be
+Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
-gated to save some power. The clock consumer should specify the desired clock
+peripheral clocks to be gated to save some power. The clock consumer
-by having the clock ID in its "clocks" phandle cell. The clock ID is directly
+should specify the desired clock by having the clock ID in its
-mapped to the corresponding clock gating control bit in HW to ease manual clock
+"clocks" phandle cell. The clock ID is directly mapped to the
+corresponding clock gating control bit in HW to ease manual clock
 lookup in datasheet.
 The following is a list of provided IDs for Armada 370:
@@ -22,6 +23,60 @@ ID	Clock	Peripheral
 28      ddr     DDR Cntrl
 30      sata1   SATA Host 0
+The following is a list of provided IDs for Armada 375:
+ID      Clock           Peripheral
+-----------------------------------
+2       mu              Management Unit
+3       pp              Packet Processor
+4       ptp             PTP
+5       pex0            PCIe 0 Clock out
+6       pex1            PCIe 1 Clock out
+8       audio           Audio Cntrl
+11      nd_clk          Nand Flash Cntrl
+14      sata0_link      SATA 0 Link
+15      sata0_core      SATA 0 Core
+16      usb3            USB3 Host
+17      sdio            SDHCI Host
+18      usb             USB Host
+19      gop             Gigabit Ethernet MAC
+20      sata1_link      SATA 1 Link
+21      sata1_core      SATA 1 Core
+22      xor0            XOR DMA 0
+23      xor1            XOR DMA 0
+24      copro           Coprocessor
+25      tdm             Time Division Mplx
+28      crypto0_enc     Cryptographic Unit Port 0 Encryption
+29      crypto0_core    Cryptographic Unit Port 0 Core
+30      crypto1_enc     Cryptographic Unit Port 1 Encryption
+31      crypto1_core    Cryptographic Unit Port 1 Core
+The following is a list of provided IDs for Armada 380/385:
+ID      Clock           Peripheral
+-----------------------------------
+0       audio           Audio
+2       ge2             Gigabit Ethernet 2
+3       ge1             Gigabit Ethernet 1
+4       ge0             Gigabit Ethernet 0
+5       pex1            PCIe 1
+6       pex2            PCIe 2
+7       pex3            PCIe 3
+8       pex0            PCIe 0
+9       usb3h0          USB3 Host 0
+10      usb3h1          USB3 Host 1
+11      usb3d           USB3 Device
+13      bm              Buffer Management
+14      crypto0z        Cryptographic 0 Z
+15      sata0           SATA 0
+16      crypto1z        Cryptographic 1 Z
+17      sdio            SDIO
+18      usb2            USB 2
+21      crypto1         Cryptographic 1
+22      xor0            XOR 0
+23      crypto0         Cryptographic 0
+25      tdm             Time Division Multiplexing
+28      xor1            XOR 1
+30      sata1           SATA 1
 The following is a list of provided IDs for Armada XP:
 ID      Clock   Peripheral
 -----------------------------------
@@ -95,6 +150,8 @@ ID	Clock	Peripheral
 Required properties:
 - compatible : shall be one of the following:
        "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
+        "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
+        "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
        "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
        "marvell,dove-gating-clock" - for Dove SoC clock gating
        "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index a6a352c2771e..5992dceec7af 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -21,9 +21,9 @@ Required Properties:
    must appear in the same order as the output clocks.
  - #clock-cells: Must be 1
  - clock-output-names: The name of the clocks as free-form strings
-  - renesas,indices: Indices of the gate clocks into the group (0 to 31)
+  - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
-The clocks, clock-output-names and renesas,indices properties contain one
+The clocks, clock-output-names and renesas,clock-indices properties contain one
 entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
 gate clocks must not be declared.
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
new file mode 100644
index 000000000000..98a257492522
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -0,0 +1,29 @@
+* Renesas RZ Clock Pulse Generator (CPG)
+The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
+CPU and GPU clocks, and several fixed ratio dividers.
+Required Properties:
+  - compatible: Must be one of
+    - "renesas,r7s72100-cpg-clocks" for the r7s72100 CPG
+    - "renesas,rz-cpg-clocks" for the generic RZ CPG
+  - reg: Base address and length of the memory resource used by the CPG
+  - clocks: References to possible parent clocks. Order must match clock modes
+    in the datasheet. For the r7s72100, this is extal, usb_x1.
+  - #clock-cells: Must be 1
+  - clock-output-names: The names of the clocks. Supported clocks are "pll",
+    "i", and "g"
+Example
+-------
+        cpg_clocks: cpg_clocks@fcfe0000 {
+                #clock-cells = <1>;
+                compatible = "renesas,r7s72100-cpg-clocks",
+                             "renesas,rz-cpg-clocks";
+                reg = <0xfcfe0000 0x18>;
+                clocks = <&extal_clk>, <&usb_x1_clk>;
+                clock-output-names = "pll", "i", "g";
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
new file mode 100644
index 000000000000..ae56315fcec5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-divmux.txt
@@ -0,0 +1,49 @@
+Binding for a ST divider and multiplexer clock driver.
+This binding uses the common clock binding[1].
+Base address is located to the parent node. See clock binding[2]
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+Required properties:
+- compatible : shall be:
+        "st,clkgena-divmux-c65-hs",     "st,clkgena-divmux"
+        "st,clkgena-divmux-c65-ls",     "st,clkgena-divmux"
+        "st,clkgena-divmux-c32-odf0",   "st,clkgena-divmux"
+        "st,clkgena-divmux-c32-odf1",   "st,clkgena-divmux"
+        "st,clkgena-divmux-c32-odf2",   "st,clkgena-divmux"
+        "st,clkgena-divmux-c32-odf3",   "st,clkgena-divmux"
+- #clock-cells : From common clock binding; shall be set to 1.
+- clocks : From common clock binding
+- clock-output-names : From common clock binding.
+Example:
+        clockgenA@fd345000 {
+                reg = <0xfd345000 0xb50>;
+                CLK_M_A1_DIV1: CLK_M_A1_DIV1 {
+                        #clock-cells = <1>;
+                        compatible = "st,clkgena-divmux-c32-odf1",
+                                     "st,clkgena-divmux";
+                        clocks = <&CLK_M_A1_OSC_PREDIV>,
+                                 <&CLK_M_A1_PLL0 1>, /* PLL0 PHI1 */
+                                 <&CLK_M_A1_PLL1 1>; /* PLL1 PHI1 */
+                        clock-output-names = "CLK_M_RX_ICN_TS",
+                                             "CLK_M_RX_ICN_VDP_0",
+                                             "", /* Unused */
+                                             "CLK_M_PRV_T1_BUS",
+                                             "CLK_M_ICN_REG_12",
+                                             "CLK_M_ICN_REG_10",
+                                             "", /* Unused */
+                                             "CLK_M_ICN_ST231";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
new file mode 100644
index 000000000000..943e0808e212
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-mux.txt
@@ -0,0 +1,36 @@
+Binding for a ST multiplexed clock driver.
+This binding supports only simple indexed multiplexers, it does not
+support table based parent index to hardware value translations.
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Required properties:
+- compatible : shall be:
+        "st,stih416-clkgenc-vcc-hd",    "st,clkgen-mux"
+        "st,stih416-clkgenf-vcc-fvdp",  "st,clkgen-mux"
+        "st,stih416-clkgenf-vcc-hva",   "st,clkgen-mux"
+        "st,stih416-clkgenf-vcc-hd",    "st,clkgen-mux"
+        "st,stih416-clkgenf-vcc-sd",    "st,clkgen-mux"
+        "st,stih415-clkgen-a9-mux",     "st,clkgen-mux"
+        "st,stih416-clkgen-a9-mux",     "st,clkgen-mux"
+- #clock-cells : from common clock binding; shall be set to 0.
+- reg : A Base address and length of the register set.
+- clocks : from common clock binding
+Example:
+        CLK_M_HVA: CLK_M_HVA {
+                #clock-cells = <0>;
+                compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
+                reg = <0xfd690868 4>;
+                clocks = <&CLOCKGEN_F 1>, <&CLK_M_A1_DIV0 3>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
new file mode 100644
index 000000000000..81eb3855ab92
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -0,0 +1,48 @@
+Binding for a ST pll clock driver.
+This binding uses the common clock binding[1].
+Base address is located to the parent node. See clock binding[2]
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+Required properties:
+- compatible : shall be:
+        "st,clkgena-prediv-c65",        "st,clkgena-prediv"
+        "st,clkgena-prediv-c32",        "st,clkgena-prediv"
+        "st,clkgena-plls-c65"
+        "st,plls-c32-a1x-0",            "st,clkgen-plls-c32"
+        "st,plls-c32-a1x-1",            "st,clkgen-plls-c32"
+        "st,stih415-plls-c32-a9",       "st,clkgen-plls-c32"
+        "st,stih415-plls-c32-ddr",      "st,clkgen-plls-c32"
+        "st,stih416-plls-c32-a9",       "st,clkgen-plls-c32"
+        "st,stih416-plls-c32-ddr",      "st,clkgen-plls-c32"
+        "st,stih415-gpu-pll-c32",       "st,clkgengpu-pll-c32"
+        "st,stih416-gpu-pll-c32",       "st,clkgengpu-pll-c32"
+- #clock-cells : From common clock binding; shall be set to 1.
+- clocks : From common clock binding
+- clock-output-names : From common clock binding.
+Example:
+        clockgenA@fee62000 {
+                reg = <0xfee62000 0xb48>;
+                CLK_S_A0_PLL: CLK_S_A0_PLL {
+                        #clock-cells = <1>;
+                        compatible = "st,clkgena-plls-c65";
+                        clocks = <&CLK_SYSIN>;
+                        clock-output-names = "CLK_S_A0_PLL0_HS",
+                                             "CLK_S_A0_PLL0_LS",
+                                             "CLK_S_A0_PLL1";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
new file mode 100644
index 000000000000..566c9d79ed32
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-prediv.txt
@@ -0,0 +1,36 @@
+Binding for a ST pre-divider clock driver.
+This binding uses the common clock binding[1].
+Base address is located to the parent node. See clock binding[2]
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
+Required properties:
+- compatible : shall be:
+        "st,clkgena-prediv-c65",        "st,clkgena-prediv"
+        "st,clkgena-prediv-c32",        "st,clkgena-prediv"
+- #clock-cells : From common clock binding; shall be set to 0.
+- clocks : From common clock binding
+- clock-output-names : From common clock binding.
+Example:
+        clockgenA@fd345000 {
+                reg = <0xfd345000 0xb50>;
+                CLK_M_A2_OSC_PREDIV: CLK_M_A2_OSC_PREDIV {
+                        #clock-cells = <0>;
+                        compatible = "st,clkgena-prediv-c32",
+                                     "st,clkgena-prediv";
+                        clocks = <&CLK_SYSIN>;
+                        clock-output-names = "CLK_M_A2_OSC_PREDIV";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
new file mode 100644
index 000000000000..4e3ff28b04c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-vcc.txt
@@ -0,0 +1,53 @@
+Binding for a type of STMicroelectronics clock crossbar (VCC).
+The crossbar can take up to 4 input clocks and control up to 16
+output clocks. Not all inputs or outputs have to be in use in a
+particular instantiation. Each output can be individually enabled,
+select any of the input clocks and apply a divide (by 1,2,4 or 8) to
+that selected clock.
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Required properties:
+- compatible : shall be:
+        "st,stih416-clkgenc",           "st,vcc"
+        "st,stih416-clkgenf",           "st,vcc"
+- #clock-cells : from common clock binding; shall be set to 1.
+- reg : A Base address and length of the register set.
+- clocks : from common clock binding
+- clock-output-names : From common clock binding. The block has 16
+                       clock outputs but not all of them in a specific instance
+                       have to be used in the SoC. If a clock name is left as
+                       an empty string then no clock will be created for the
+                       output associated with that string index. If fewer than
+                       16 strings are provided then no clocks will be created
+                       for the remaining outputs.
+Example:
+        CLOCKGEN_C_VCC: CLOCKGEN_C_VCC {
+                #clock-cells = <1>;
+                compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
+                reg = <0xfe8308ac 12>;
+                clocks = <&CLK_S_VCC_HD>, <&CLOCKGEN_C 1>,
+                        <&CLK_S_TMDS_FROMPHY>, <&CLOCKGEN_C 2>;
+                clock-output-names  =
+                        "CLK_S_PIX_HDMI",  "CLK_S_PIX_DVO",
+                        "CLK_S_OUT_DVO",   "CLK_S_PIX_HD",
+                        "CLK_S_HDDAC",     "CLK_S_DENC",
+                        "CLK_S_SDDAC",     "CLK_S_PIX_MAIN",
+                        "CLK_S_PIX_AUX",   "CLK_S_STFE_FRC_0",
+                        "CLK_S_REF_MCRU",  "CLK_S_SLAVE_MCRU",
+                        "CLK_S_TMDS_HDMI", "CLK_S_HDMI_REJECT_PLL",
+                        "CLK_S_THSENS";
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
new file mode 100644
index 000000000000..49ec5ae18b5b
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen.txt
@@ -0,0 +1,83 @@
+Binding for a Clockgen hardware block found on
+certain STMicroelectronics consumer electronics SoC devices.
+A Clockgen node can contain pll, diviser or multiplexer nodes.
+We will find only the base address of the Clockgen, this base
+address is common of all subnode.
+        clockgen_node {
+                reg = <>;
+                pll_node {
+                        ...
+                };
+                prediv_node {
+                        ...
+                };
+                divmux_node {
+                        ...
+                };
+                quadfs_node {
+                        ...
+                };
+                ...
+        };
+This binding uses the common clock binding[1].
+Each subnode should use the binding discribe in [2]..[4]
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[3] Documentation/devicetree/bindings/clock/st,quadfs.txt
+[4] Documentation/devicetree/bindings/clock/st,quadfs.txt
+Required properties:
+- reg : A Base address and length of the register set.
+Example:
+        clockgenA@fee62000 {
+                reg = <0xfee62000 0xb48>;
+                CLK_S_A0_PLL: CLK_S_A0_PLL {
+                        #clock-cells = <1>;
+                        compatible = "st,clkgena-plls-c65";
+                        clocks = <&CLK_SYSIN>;
+                        clock-output-names = "CLK_S_A0_PLL0_HS",
+                                             "CLK_S_A0_PLL0_LS",
+                                             "CLK_S_A0_PLL1";
+                };
+                CLK_S_A0_OSC_PREDIV: CLK_S_A0_OSC_PREDIV {
+                        #clock-cells = <0>;
+                        compatible = "st,clkgena-prediv-c65",
+                                     "st,clkgena-prediv";
+                        clocks = <&CLK_SYSIN>;
+                        clock-output-names = "CLK_S_A0_OSC_PREDIV";
+                };
+                CLK_S_A0_HS: CLK_S_A0_HS {
+                        #clock-cells = <1>;
+                        compatible = "st,clkgena-divmux-c65-hs",
+                                     "st,clkgena-divmux";
+                        clocks = <&CLK_S_A0_OSC_PREDIV>,
+                                 <&CLK_S_A0_PLL 0>, /* PLL0 HS */
+                                 <&CLK_S_A0_PLL 2>; /* PLL1 */
+                        clock-output-names = "CLK_S_FDMA_0",
+                                             "CLK_S_FDMA_1",
+                                             ""; /* CLK_S_JIT_SENSE */
+                                             /* Fourth output unused */
+                };
+        };
diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
new file mode 100644
index 000000000000..ec86d62ca283
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt
@@ -0,0 +1,45 @@
+Binding for a type of quad channel digital frequency synthesizer found on
+certain STMicroelectronics consumer electronics SoC devices.
+This version contains a programmable PLL which can generate up to 216, 432
+or 660MHz (from a 30MHz oscillator input) as the input to the digital
+synthesizers.
+This binding uses the common clock binding[1].
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Required properties:
+- compatible : shall be:
+  "st,stih416-quadfs216",       "st,quadfs"
+  "st,stih416-quadfs432",       "st,quadfs"
+  "st,stih416-quadfs660-E",     "st,quadfs"
+  "st,stih416-quadfs660-F",     "st,quadfs"
+- #clock-cells : from common clock binding; shall be set to 1.
+- reg : A Base address and length of the register set.
+- clocks : from common clock binding
+- clock-output-names : From common clock binding. The block has 4
+                       clock outputs but not all of them in a specific instance
+                       have to be used in the SoC. If a clock name is left as
+                       an empty string then no clock will be created for the
+                       output associated with that string index. If fewer than
+                       4 strings are provided then no clocks will be created
+                       for the remaining outputs.
+Example:
+        CLOCKGEN_E: CLOCKGEN_E {
+                #clock-cells = <1>;
+                compatible = "st,stih416-quadfs660-E", "st,quadfs";
+                reg = <0xfd3208bc 0xB0>;
+                clocks = <&CLK_SYSIN>;
+                clock-output-names = "CLK_M_PIX_MDTP_0",
+                                        "CLK_M_PIX_MDTP_1",
+                                        "CLK_M_PIX_MDTP_2",
+                                        "CLK_M_MPELPC";
+        };
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index c2cb7621ad2d..a5160d8cbb5f 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -6,37 +6,41 @@ This binding uses the common clock binding[1].
 Required properties:
 - compatible : shall be one of the following:
-        "allwinner,sun4i-osc-clk" - for a gatable oscillator
+        "allwinner,sun4i-a10-osc-clk" - for a gatable oscillator
-        "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
+        "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
        "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
-        "allwinner,sun4i-pll5-clk" - for the PLL5 clock
+        "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
-        "allwinner,sun4i-pll6-clk" - for the PLL6 clock
+        "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
-        "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
+        "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
-        "allwinner,sun4i-axi-clk" - for the AXI clock
+        "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
-        "allwinner,sun4i-axi-gates-clk" - for the AXI gates
+        "allwinner,sun4i-a10-axi-clk" - for the AXI clock
-        "allwinner,sun4i-ahb-clk" - for the AHB clock
+        "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
-        "allwinner,sun4i-ahb-gates-clk" - for the AHB gates on A10
+        "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+        "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
        "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
        "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
        "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
        "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
        "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
-        "allwinner,sun4i-apb0-clk" - for the APB0 clock
+        "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
-        "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
+        "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
        "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
        "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
        "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
-        "allwinner,sun4i-apb1-clk" - for the APB1 clock
+        "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
-        "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
+        "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
-        "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates on A10
+        "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
        "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
        "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
        "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
        "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
        "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
-        "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks
+        "allwinner,sun4i-a10-mod0-clk" - for the module 0 family of clocks
        "allwinner,sun7i-a20-out-clk" - for the external output clocks
+        "allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
+        "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
+        "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
@@ -44,10 +48,17 @@ Required properties for all clocks:
        multiplexed clocks, the list order must match the hardware
        programming order.
 - #clock-cells : from common clock binding; shall be set to 0 except for
-        "allwinner,*-gates-clk" where it shall be set to 1
+        "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
+        "allwinner,sun4i-pll6-clk" where it shall be set to 1
+- clock-output-names : shall be the corresponding names of the outputs.
+        If the clock module only has one output, the name shall be the
+        module name.
-Additionally, "allwinner,*-gates-clk" clocks require:
+And "allwinner,*-usb-clk" clocks also require:
- clock-output-names : the corresponding gate names that the clock controls
+- reset-cells : shall be set to 1
+For "allwinner,sun7i-a20-gmac-clk", the parent clocks shall be fixed rate
+dummy clocks at 25 MHz and 125 MHz, respectively. See example.
 Clock consumers should specify the desired clocks they use with a
 "clocks" phandle cell. Consumers that are using a gated clock should
@@ -56,23 +67,68 @@ offset of the bit controlling this particular gate in the register.
 For example:
-osc24M: osc24M@01c20050 {
+osc24M: clk@01c20050 {
        #clock-cells = <0>;
-        compatible = "allwinner,sun4i-osc-clk";
+        compatible = "allwinner,sun4i-a10-osc-clk";
        reg = <0x01c20050 0x4>;
        clocks = <&osc24M_fixed>;
+        clock-output-names = "osc24M";
 };
-pll1: pll1@01c20000 {
+pll1: clk@01c20000 {
        #clock-cells = <0>;
-        compatible = "allwinner,sun4i-pll1-clk";
+        compatible = "allwinner,sun4i-a10-pll1-clk";
        reg = <0x01c20000 0x4>;
        clocks = <&osc24M>;
+        clock-output-names = "pll1";
+};
+pll5: clk@01c20020 {
+        #clock-cells = <1>;
+        compatible = "allwinner,sun4i-pll5-clk";
+        reg = <0x01c20020 0x4>;
+        clocks = <&osc24M>;
+        clock-output-names = "pll5_ddr", "pll5_other";
 };
 cpu: cpu@01c20054 {
        #clock-cells = <0>;
-        compatible = "allwinner,sun4i-cpu-clk";
+        compatible = "allwinner,sun4i-a10-cpu-clk";
        reg = <0x01c20054 0x4>;
        clocks = <&osc32k>, <&osc24M>, <&pll1>;
+        clock-output-names = "cpu";
+};
+mmc0_clk: clk@01c20088 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun4i-mod0-clk";
+        reg = <0x01c20088 0x4>;
+        clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+        clock-output-names = "mmc0";
+};
+mii_phy_tx_clk: clk@2 {
+        #clock-cells = <0>;
+        compatible = "fixed-clock";
+        clock-frequency = <25000000>;
+        clock-output-names = "mii_phy_tx";
+};
+gmac_int_tx_clk: clk@3 {
+        #clock-cells = <0>;
+        compatible = "fixed-clock";
+        clock-frequency = <125000000>;
+        clock-output-names = "gmac_int_tx";
+};
+gmac_clk: clk@01c20164 {
+        #clock-cells = <0>;
+        compatible = "allwinner,sun7i-a20-gmac-clk";
+        reg = <0x01c20164 0x4>;
+        /*
+         * The first clock must be fixed at 25MHz;
+         * the second clock must be fixed at 125MHz
+         */
+        clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+        clock-output-names = "gmac";
 };
diff --git a/Documentation/devicetree/bindings/clock/zynq-7000.txt b/Documentation/devicetree/bindings/clock/zynq-7000.txt
index 17b4a94916d6..d93746cf2975 100644
--- a/Documentation/devicetree/bindings/clock/zynq-7000.txt
+++ b/Documentation/devicetree/bindings/clock/zynq-7000.txt
@@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
 Required properties:
 - #clock-cells : Must be 1
 - compatible : "xlnx,ps7-clkc"
+ - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
 - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
                      (usually 33 MHz oscillators are used for Zynq platforms)
 - clock-output-names : List of strings used to name the clock outputs. Shall be
@@ -87,10 +88,11 @@ Clock outputs:
 47: dbg_apb
 Example:
-        clkc: clkc {
+        clkc: clkc@100 {
                #clock-cells = <1>;
                compatible = "xlnx,ps7-clkc";
                ps-clk-frequency = <33333333>;
+                reg = <0x100 0x100>;
                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index 68b83ecc3850..ee9be9961524 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -1,12 +1,16 @@
 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
 Required properties:
- compatible : Should be "fsl,imx31-sdma", "fsl,imx31-to1-sdma",
+- compatible : Should be one of
-  "fsl,imx31-to2-sdma", "fsl,imx35-sdma", "fsl,imx35-to1-sdma",
+      "fsl,imx25-sdma"
-  "fsl,imx35-to2-sdma", "fsl,imx51-sdma", "fsl,imx53-sdma" or
+      "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
-  "fsl,imx6q-sdma". The -to variants should be preferred since they
+      "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
-  allow to determnine the correct ROM script addresses needed for
+      "fsl,imx51-sdma"
-  the driver to work without additional firmware.
+      "fsl,imx53-sdma"
+      "fsl,imx6q-sdma"
+  The -to variants should be preferred since they allow to determnine the
+  correct ROM script addresses needed for the driver to work without additional
+  firmware.
 - reg : Should contain SDMA registers location and length
 - interrupts : Should contain SDMA interrupt
 - #dma-cells : Must be <3>.
diff --git a/Documentation/devicetree/bindings/drm/bridge/ptn3460.txt b/Documentation/devicetree/bindings/drm/bridge/ptn3460.txt
new file mode 100644
index 000000000000..52b93b2c6748
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/ptn3460.txt
@@ -0,0 +1,27 @@
+ptn3460 bridge bindings
+Required properties:
+        - compatible: "nxp,ptn3460"
+        - reg: i2c address of the bridge
+        - powerdown-gpio: OF device-tree gpio specification
+        - reset-gpio: OF device-tree gpio specification
+        - edid-emulation: The EDID emulation entry to use
+                +-------+------------+------------------+
+                | Value | Resolution | Description      |
+                |   0   |  1024x768  | NXP Generic      |
+                |   1   |  1920x1080 | NXP Generic      |
+                |   2   |  1920x1080 | NXP Generic      |
+                |   3   |  1600x900  | Samsung LTM200KT |
+                |   4   |  1920x1080 | Samsung LTM230HT |
+                |   5   |  1366x768  | NXP Generic      |
+                |   6   |  1600x900  | ChiMei M215HGE   |
+                +-------+------------+------------------+
+Example:
+        lvds-bridge@20 {
+                compatible = "nxp,ptn3460";
+                reg = <0x20>;
+                powerdown-gpio = <&gpy2 5 1 0 0>;
+                reset-gpio = <&gpx1 5 1 0 0>;
+                edid-emulation = <5>;
+        };
diff --git a/Documentation/devicetree/bindings/drm/i2c/tda998x.txt b/Documentation/devicetree/bindings/drm/i2c/tda998x.txt
new file mode 100644
index 000000000000..d7df01c5bb3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/i2c/tda998x.txt
@@ -0,0 +1,27 @@
+Device-Tree bindings for the NXP TDA998x HDMI transmitter
+Required properties;
+  - compatible: must be "nxp,tda998x"
+Optional properties:
+  - interrupts: interrupt number and trigger type
+        default: polling
+  - pinctrl-0: pin control group to be used for
+        screen plug/unplug interrupt.
+  - pinctrl-names: must contain a "default" entry.
+  - video-ports: 24 bits value which defines how the video controller
+        output is wired to the TDA998x input - default: <0x230145>
+Example:
+        tda998x: hdmi-encoder {
+                compatible = "nxp,tda998x";
+                reg = <0x70>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <27 2>;            /* falling edge */
+                pinctrl-0 = <&pmx_camera>;
+                pinctrl-names = "default";
+        };
diff --git a/Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt b/Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
new file mode 100644
index 000000000000..94ae9f82dcf8
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/cirrus,clps711x-mctrl-gpio.txt
@@ -0,0 +1,17 @@
+* ARM Cirrus Logic CLPS711X SYSFLG1 MCTRL GPIOs
+Required properties:
+- compatible: Should contain "cirrus,clps711x-mctrl-gpio".
+- gpio-controller: Marks the device node as a gpio controller.
+- #gpio-cells: Should be two. The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+    0 = Active high,
+    1 = Active low.
+Example:
+        sysgpio: sysgpio {
+                compatible = "cirrus,ep7312-mctrl-gpio",
+                             "cirrus,clps711x-mctrl-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index a2e839d6e338..5079ba7d6568 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -1,13 +1,17 @@
-Davinci GPIO controller bindings
+Davinci/Keystone GPIO controller bindings
 Required Properties:
- compatible: should be "ti,dm6441-gpio"
+- compatible: should be "ti,dm6441-gpio", "ti,keystone-gpio"
 - reg: Physical base address of the controller and the size of memory mapped
       registers.
 - gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be two.
+  - first cell is the pin number
+  - second cell is used to specify optional parameters (unused)
 - interrupt-parent: phandle of the parent interrupt controller.
 - interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are
@@ -27,6 +31,7 @@ Example:
 gpio: gpio@1e26000 {
        compatible = "ti,dm6441-gpio";
        gpio-controller;
+        #gpio-cells = <2>;
        reg = <0x226000 0x1000>;
        interrupt-parent = <&intc>;
        interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH
@@ -39,3 +44,19 @@ gpio: gpio@1e26000 {
        interrupt-controller;
        #interrupt-cells = <2>;
 };
+leds {
+        compatible = "gpio-leds";
+        led1 {
+                label = "davinci:green:usr1";
+                gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+                ...
+        };
+        led2 {
+                label = "davinci:red:debug1";
+                gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+                ...
+        };
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
new file mode 100644
index 000000000000..a37bd9ae2730
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
@@ -0,0 +1,16 @@
+Zevio GPIO controller
+Required properties:
+- compatible: Should be "lsi,zevio-gpio"
+- reg: Address and length of the register set for the device
+- #gpio-cells: Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters (currently unused).
+- gpio-controller: Marks the device node as a GPIO controller.
+Example:
+        gpio: gpio@90000000 {
+                compatible = "lsi,zevio-gpio";
+                reg = <0x90000000 0x1000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index 0c85bb6e3a80..3fb8f53071b8 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -13,11 +13,11 @@ properties, each containing a 'gpio-list':
        gpio-specifier : Array of #gpio-cells specifying specific gpio
                         (controller specific)
-GPIO properties should be named "[<name>-]gpios".  Exact
+GPIO properties should be named "[<name>-]gpios". The exact
 meaning of each gpios property must be documented in the device tree
 binding for each device.
-For example, the following could be used to describe gpios pins to use
+For example, the following could be used to describe GPIO pins used
 as chip select lines; with chip selects 0, 1 and 3 populated, and chip
 select 2 left empty:
@@ -44,35 +44,79 @@ whether pin is open-drain and whether pin is logically inverted.
 Exact meaning of each specifier cell is controller specific, and must
 be documented in the device tree binding for the device.
-Example of the node using GPIOs:
+Example of a node using GPIOs:
        node {
                gpios = <&qe_pio_e 18 0>;
        };
 In this example gpio-specifier is "18 0" and encodes GPIO pin number,
-and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
+and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
+1.1) GPIO specifier best practices
+----------------------------------
+A gpio-specifier should contain a flag indicating the GPIO polarity; active-
+high or active-low. If it does, the follow best practices should be followed:
+The gpio-specifier's polarity flag should represent the physical level at the
+GPIO controller that achieves (or represents, for inputs) a logically asserted
+value at the device. The exact definition of logically asserted should be
+defined by the binding for the device. If the board inverts the signal between
+the GPIO controller and the device, then the gpio-specifier will represent the
+opposite physical level than the signal at the device's pin.
+When the device's signal polarity is configurable, the binding for the
+device must either:
+a) Define a single static polarity for the signal, with the expectation that
+any software using that binding would statically program the device to use
+that signal polarity.
+The static choice of polarity may be either:
+a1) (Preferred) Dictated by a binding-specific DT property.
+or:
+a2) Defined statically by the DT binding itself.
+In particular, the polarity cannot be derived from the gpio-specifier, since
+that would prevent the DT from separately representing the two orthogonal
+concepts of configurable signal polarity in the device, and possible board-
+level signal inversion.
+or:
+b) Pick a single option for device signal polarity, and document this choice
+in the binding. The gpio-specifier should represent the polarity of the signal
+(at the GPIO controller) assuming that the device is configured for this
+particular signal polarity choice. If software chooses to program the device
+to generate or receive a signal of the opposite polarity, software will be
+responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
+controller.
 2) gpio-controller nodes
 ------------------------
-Every GPIO controller node must both an empty "gpio-controller"
+Every GPIO controller node must contain both an empty "gpio-controller"
-property, and have #gpio-cells contain the size of the gpio-specifier.
+property, and a #gpio-cells integer property, which indicates the number of
+cells in a gpio-specifier.
 Example of two SOC GPIO banks defined as gpio-controller nodes:
        qe_pio_a: gpio-controller@1400 {
-                #gpio-cells = <2>;
                compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
                reg = <0x1400 0x18>;
                gpio-controller;
+                #gpio-cells = <2>;
        };
        qe_pio_e: gpio-controller@1460 {
-                #gpio-cells = <2>;
                compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
                reg = <0x1460 0x18>;
                gpio-controller;
+                #gpio-cells = <2>;
        };
 2.1) gpio- and pin-controller interaction
diff --git a/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
new file mode 100644
index 000000000000..dd5d2c0394b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
@@ -0,0 +1,60 @@
+* Synopsys DesignWare APB GPIO controller
+Required properties:
+- compatible : Should contain "snps,dw-apb-gpio"
+- reg : Address and length of the register set for the device.
+- #address-cells : should be 1 (for addressing port subnodes).
+- #size-cells : should be 0 (port subnodes).
+The GPIO controller has a configurable number of ports, each of which are
+represented as child nodes with the following properties:
+Required properties:
+- compatible : "snps,dw-apb-gpio-port"
+- gpio-controller : Marks the device node as a gpio controller.
+- #gpio-cells : Should be two.  The first cell is the pin number and
+  the second cell is used to specify the gpio polarity:
+      0 = active high
+      1 = active low
+- reg : The integer port index of the port, a single cell.
+Optional properties:
+- interrupt-controller : The first port may be configured to be an interrupt
+controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt.  Shall be set to 2.  The first cell defines the interrupt number,
+  the second encodes the triger flags encoded as described in
+  Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+- interrupts : The interrupt to the parent controller raised when GPIOs
+  generate the interrupts.
+- snps,nr-gpios : The number of pins in the port, a single cell.
+Example:
+gpio: gpio@20000 {
+        compatible = "snps,dw-apb-gpio";
+        reg = <0x20000 0x1000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        porta: gpio-controller@0 {
+                compatible = "snps,dw-apb-gpio-port";
+                gpio-controller;
+                #gpio-cells = <2>;
+                snps,nr-gpios = <8>;
+                reg = <0>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                interrupt-parent = <&vic1>;
+                interrupts = <0>;
+        };
+        portb: gpio-controller@1 {
+                compatible = "snps,dw-apb-gpio-port";
+                gpio-controller;
+                #gpio-cells = <2>;
+                snps,nr-gpios = <8>;
+                reg = <1>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index efaeec8961b6..efa8b8451f93 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -190,6 +190,48 @@ of the following host1x client modules:
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel
+- sor: serial output resource
+  Required properties:
+  - compatible: "nvidia,tegra124-sor"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+  - clocks: Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: Must include the following entries:
+    - sor: clock input for the SOR hardware
+    - parent: input for the pixel clock
+    - dp: reference clock for the SOR clock
+    - safe: safe reference for the SOR clock during power up
+  - resets: Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names: Must include the following entries:
+    - sor
+  Optional properties:
+  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
+  - nvidia,edid: supplies a binary EDID blob
+  - nvidia,panel: phandle of a display panel
+  Optional properties when driving an eDP output:
+  - nvidia,dpaux: phandle to a DispayPort AUX interface
+- dpaux: DisplayPort AUX interface
+  - compatible: "nvidia,tegra124-dpaux"
+  - reg: Physical base address and length of the controller's registers.
+  - interrupts: The interrupt outputs from the controller.
+  - clocks: Must contain an entry for each entry in clock-names.
+    See ../clocks/clock-bindings.txt for details.
+  - clock-names: Must include the following entries:
+    - dpaux: clock input for the DPAUX hardware
+    - parent: reference clock
+  - resets: Must contain an entry for each entry in reset-names.
+    See ../reset/reset.txt for details.
+  - reset-names: Must include the following entries:
+    - dpaux
+  - vdd-supply: phandle of a supply that powers the DisplayPort link
 Example:
 / {
diff --git a/Documentation/devicetree/bindings/graph.txt b/Documentation/devicetree/bindings/graph.txt
new file mode 100644
index 000000000000..1a69c078adf2
--- /dev/null
+++ b/Documentation/devicetree/bindings/graph.txt
@@ -0,0 +1,129 @@
+Common bindings for device graphs
+General concept
+---------------
+The hierarchical organisation of the device tree is well suited to describe
+control flow to devices, but there can be more complex connections between
+devices that work together to form a logical compound device, following an
+arbitrarily complex graph.
+There already is a simple directed graph between devices tree nodes using
+phandle properties pointing to other nodes to describe connections that
+can not be inferred from device tree parent-child relationships. The device
+tree graph bindings described herein abstract more complex devices that can
+have multiple specifiable ports, each of which can be linked to one or more
+ports of other devices.
+These common bindings do not contain any information about the direction or
+type of the connections, they just map their existence. Specific properties
+may be described by specialized bindings depending on the type of connection.
+To see how this binding applies to video pipelines, for example, see
+Documentation/device-tree/bindings/media/video-interfaces.txt.
+Here the ports describe data interfaces, and the links between them are
+the connecting data buses. A single port with multiple connections can
+correspond to multiple devices being connected to the same physical bus.
+Organisation of ports and endpoints
+-----------------------------------
+Ports are described by child 'port' nodes contained in the device node.
+Each port node contains an 'endpoint' subnode for each remote device port
+connected to this port. If a single port is connected to more than one
+remote device, an 'endpoint' child node must be provided for each link.
+If more than one port is present in a device node or there is more than one
+endpoint at a port, or a port node needs to be associated with a selected
+hardware interface, a common scheme using '#address-cells', '#size-cells'
+and 'reg' properties is used number the nodes.
+device {
+        ...
+        #address-cells = <1>;
+        #size-cells = <0>;
+        port@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0>;
+                endpoint@0 {
+                        reg = <0>;
+                        ...
+                };
+                endpoint@1 {
+                        reg = <1>;
+                        ...
+                };
+        };
+        port@1 {
+                reg = <1>;
+                endpoint { ... };
+        };
+};
+All 'port' nodes can be grouped under an optional 'ports' node, which
+allows to specify #address-cells, #size-cells properties for the 'port'
+nodes independently from any other child device nodes a device might
+have.
+device {
+        ...
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        ...
+                        endpoint@0 { ... };
+                        endpoint@1 { ... };
+                };
+                port@1 { ... };
+        };
+};
+Links between endpoints
+-----------------------
+Each endpoint should contain a 'remote-endpoint' phandle property that points
+to the corresponding endpoint in the port of the remote device. In turn, the
+remote endpoint should contain a 'remote-endpoint' property. If it has one,
+it must not point to another than the local endpoint. Two endpoints with their
+'remote-endpoint' phandles pointing at each other form a link between the
+containing ports.
+device-1 {
+        port {
+                device_1_output: endpoint {
+                        remote-endpoint = <&device_2_input>;
+                };
+        };
+};
+device-2 {
+        port {
+                device_2_input: endpoint {
+                        remote-endpoint = <&device_1_output>;
+                };
+        };
+};
+Required properties
+-------------------
+If there is more than one 'port' or more than one 'endpoint' node or 'reg'
+property is present in port and/or endpoint nodes the following properties
+are required in a relevant parent node:
+ - #address-cells : number of cells required to define port/endpoint
+                    identifier, should be 1.
+ - #size-cells    : should be zero.
+Optional endpoint properties
+----------------------------
+- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 1a1ac2e560e9..71724d026ffa 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -18,6 +18,7 @@ atmel,24c02		i2c serial eeprom  (24cxx)
 atmel,at97sc3204t       i2c trusted platform module (TPM)
 capella,cm32181         CM32181: Ambient Light Sensor
 catalyst,24c32          i2c serial eeprom
+cirrus,cs42l51          Cirrus Logic CS42L51 audio codec
 dallas,ds1307           64 x 8, Serial, I2C Real-Time Clock
 dallas,ds1338           I2C RTC with 56-Byte NV RAM
 dallas,ds1339           I2C Serial Real-Time Clock
@@ -58,6 +59,7 @@ plx,pex8648		48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
 ramtron,24c64           i2c serial eeprom  (24cxx)
 ricoh,rs5c372a          I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
 samsung,24ad0xd1        S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
+sii,s35390a             2-wire CMOS real-time clock
 st-micro,24c256         i2c serial eeprom  (24cxx)
 stm,m41t00              Serial Access TIMEKEEPER
 stm,m41t62              Serial real-time clock (RTC) with alarm
diff --git a/Documentation/devicetree/bindings/arm/atmel-adc.txt b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt
index d1061469f63d..0f813dec5e08 100644
--- a/Documentation/devicetree/bindings/arm/atmel-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt
@@ -5,32 +5,35 @@ Required properties:
    <chip> can be "at91sam9260", "at91sam9g45" or "at91sam9x5"
  - reg: Should contain ADC registers location and length
  - interrupts: Should contain the IRQ line for the ADC
-  - atmel,adc-channels-used: Bitmask of the channels muxed and enable for this
+  - clock-names: tuple listing input clock names.
+        Required elements: "adc_clk", "adc_op_clk".
+  - clocks: phandles to input clocks.
+  - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this
    device
  - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
    defined in the datasheet
  - atmel,adc-vref: Reference voltage in millivolts for the conversions
-  - atmel,adc-res: List of resolution in bits supported by the ADC. List size
+  - atmel,adc-res: List of resolutions in bits supported by the ADC. List size
                   must be two at least.
  - atmel,adc-res-names: Contains one identifier string for each resolution
                         in atmel,adc-res property. "lowres" and "highres"
                         identifiers are required.
 Optional properties:
-  - atmel,adc-use-external: Boolean to enable of external triggers
+  - atmel,adc-use-external-triggers: Boolean to enable the external triggers
  - atmel,adc-use-res: String corresponding to an identifier from
                       atmel,adc-res-names property. If not specified, the highest
                       resolution will be used.
  - atmel,adc-sleep-mode: Boolean to enable sleep mode when no conversion
  - atmel,adc-sample-hold-time: Sample and Hold Time in microseconds
-  - atmel,adc-ts-wires: Number of touch screen wires. Should be 4 or 5. If this
+  - atmel,adc-ts-wires: Number of touchscreen wires. Should be 4 or 5. If this
-                        value is set, then adc driver will enable touch screen
+                        value is set, then the adc driver will enable touchscreen
                        support.
-    NOTE: when adc touch screen enabled, the adc hardware trigger will be
+    NOTE: when adc touchscreen is enabled, the adc hardware trigger will be
-          disabled. Since touch screen will occupied the trigger register.
+          disabled. Since touchscreen will occupy the trigger register.
  - atmel,adc-ts-pressure-threshold: a pressure threshold for touchscreen. It
-                                     make touch detect more precision.
+                                     makes touch detection more precise.
- 
 Optional trigger Nodes:
  - Required properties:
    * trigger-name: Name of the trigger exposed to the user
@@ -41,40 +44,43 @@ Optional trigger Nodes:
 Examples:
 adc0: adc@fffb0000 {
+        #address-cells = <1>;
+        #size-cells = <0>;
        compatible = "atmel,at91sam9260-adc";
        reg = <0xfffb0000 0x100>;
-        interrupts = <20 4>;
+        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
-        atmel,adc-channel-base = <0x30>;
+        clocks = <&adc_clk>, <&adc_op_clk>;
+        clock-names = "adc_clk", "adc_op_clk";
        atmel,adc-channels-used = <0xff>;
-        atmel,adc-drdy-mask = <0x10000>;
-        atmel,adc-num-channels = <8>;
        atmel,adc-startup-time = <40>;
-        atmel,adc-status-register = <0x1c>;
+        atmel,adc-use-external-triggers;
-        atmel,adc-trigger-register = <0x08>;
-        atmel,adc-use-external;
        atmel,adc-vref = <3300>;
        atmel,adc-res = <8 10>;
        atmel,adc-res-names = "lowres", "highres";
        atmel,adc-use-res = "lowres";
        trigger@0 {
+                reg = <0>;
                trigger-name = "external-rising";
                trigger-value = <0x1>;
                trigger-external;
        };
        trigger@1 {
+                reg = <1>;
                trigger-name = "external-falling";
                trigger-value = <0x2>;
                trigger-external;
        };
        trigger@2 {
+                reg = <2>;
                trigger-name = "external-any";
                trigger-value = <0x3>;
                trigger-external;
        };
        trigger@3 {
+                reg = <3>;
                trigger-name = "continuous";
                trigger-value = <0x6>;
        };
diff --git a/Documentation/devicetree/bindings/iio/adc/twl4030-madc.txt b/Documentation/devicetree/bindings/iio/adc/twl4030-madc.txt
new file mode 100644
index 000000000000..6bdd21404b57
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/twl4030-madc.txt
@@ -0,0 +1,24 @@
+* TWL4030 Monitoring Analog to Digital Converter (MADC)
+The MADC subsystem in the TWL4030 consists of a 10-bit ADC
+combined with a 16-input analog multiplexer.
+Required properties:
+  - compatible: Should contain "ti,twl4030-madc".
+  - interrupts: IRQ line for the MADC submodule.
+  - #io-channel-cells: Should be set to <1>.
+Optional properties:
+  - ti,system-uses-second-madc-irq: boolean, set if the second madc irq register
+                                    should be used, which is intended to be used
+                                    by Co-Processors (e.g. a modem).
+Example:
+&twl {
+        madc {
+                compatible = "ti,twl4030-madc";
+                interrupts = <3>;
+                #io-channel-cells = <1>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt
new file mode 100644
index 000000000000..dcebff1928e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/vf610-adc.txt
@@ -0,0 +1,22 @@
+Freescale vf610 Analog to Digital Converter bindings
+The devicetree bindings are for the new ADC driver written for
+vf610/i.MX6slx and upward SoCs from Freescale.
+Required properties:
+- compatible: Should contain "fsl,vf610-adc"
+- reg: Offset and length of the register set for the device
+- interrupts: Should contain the interrupt for the device
+- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
+- clock-names: Must contain "adc", matching entry in the clocks property.
+- vref-supply: The regulator supply ADC refrence voltage.
+Example:
+adc0: adc@4003b000 {
+        compatible = "fsl,vf610-adc";
+        reg = <0x4003b000 0x1000>;
+        interrupts = <0 53 0x04>;
+        clocks = <&clks VF610_CLK_ADC0>;
+        clock-names = "adc";
+        vref-supply = <&reg_vcc_3v3_mcu>;
+};
diff --git a/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
new file mode 100644
index 000000000000..d9ee909d2b78
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt
@@ -0,0 +1,113 @@
+Xilinx XADC device driver
+This binding document describes the bindings for both of them since the
+bindings are very similar. The Xilinx XADC is a ADC that can be found in the
+series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication.
+Currently two different frontends for the DRP interface exist. One that is only
+available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
+other one is available on all series 7 platforms and is a softmacro with a AXI
+interface. This binding document describes the bindings for both of them since
+the bindings are very similar.
+Required properties:
+        - compatible: Should be one of
+                * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
+                  configuration interface to interface to the XADC hardmacro.
+                * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
+                  interface to the XADC hardmacro.
+        - reg: Address and length of the register set for the device
+        - interrupts: Interrupt for the XADC control interface.
+        - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
+          when using the AXI-XADC pcore this must be the clock that provides the
+          clock to the AXI bus interface of the core.
+Optional properties:
+        - interrupt-parent: phandle to the parent interrupt controller
+        - xlnx,external-mux:
+                * "none": No external multiplexer is used, this is the default
+                  if the property is omitted.
+                * "single": External multiplexer mode is used with one
+                   multiplexer.
+                * "dual": External multiplexer mode is used with two
+                  multiplexers for simultaneous sampling.
+        - xlnx,external-mux-channel: Configures which pair of pins is used to
+          sample data in external mux mode.
+          Valid values for single external multiplexer mode are:
+                0: VP/VN
+                1: VAUXP[0]/VAUXN[0]
+                2: VAUXP[1]/VAUXN[1]
+                ...
+                16: VAUXP[15]/VAUXN[15]
+          Valid values for dual external multiplexer mode are:
+                1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
+                2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
+                ...
+                8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
+          This property needs to be present if the device is configured for
+          external multiplexer mode (either single or dual). If the device is
+          not using external multiplexer mode the property is ignored.
+        - xnlx,channels: List of external channels that are connected to the ADC
+          Required properties:
+                * #address-cells: Should be 1.
+                * #size-cells: Should be 0.
+          The child nodes of this node represent the external channels which are
+          connected to the ADC. If the property is no present no external
+          channels will be assumed to be connected.
+          Each child node represents one channel and has the following
+          properties:
+                Required properties:
+                        * reg: Pair of pins the the channel is connected to.
+                                0: VP/VN
+                                1: VAUXP[0]/VAUXN[0]
+                                2: VAUXP[1]/VAUXN[1]
+                                ...
+                                16: VAUXP[15]/VAUXN[15]
+                          Note each channel number should only be used at most
+                          once.
+                Optional properties:
+                        * xlnx,bipolar: If set the channel is used in bipolar
+                          mode.
+Examples:
+        xadc@f8007100 {
+                compatible = "xlnx,zynq-xadc-1.00.a";
+                reg = <0xf8007100 0x20>;
+                interrupts = <0 7 4>;
+                interrupt-parent = <&gic>;
+                clocks = <&pcap_clk>;
+                xlnx,channels {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        channel@0 {
+                                reg = <0>;
+                        };
+                        channel@1 {
+                                reg = <1>;
+                        };
+                        channel@8 {
+                                reg = <8>;
+                        };
+                };
+        };
+        xadc@43200000 {
+                compatible = "xlnx,axi-xadc-1.00.a";
+                reg = <0x43200000 0x1000>;
+                interrupts = <0 53 4>;
+                interrupt-parent = <&gic>;
+                clocks = <&fpga1_clk>;
+                xlnx,channels {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        channel@0 {
+                                reg = <0>;
+                                xlnx,bipolar;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/input/clps711x-keypad.txt b/Documentation/devicetree/bindings/input/clps711x-keypad.txt
new file mode 100644
index 000000000000..e68d2bbc6c07
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/clps711x-keypad.txt
@@ -0,0 +1,27 @@
+* Cirrus Logic CLPS711X matrix keypad device tree bindings
+Required Properties:
+- compatible:    Shall contain "cirrus,clps711x-keypad".
+- row-gpios:     List of GPIOs used as row lines.
+- poll-interval: Poll interval time in milliseconds.
+- linux,keymap:  The definition can be found at
+                 bindings/input/matrix-keymap.txt.
+Optional Properties:
+- autorepeat:    Enable autorepeat feature.
+Example:
+        keypad {
+                compatible = "cirrus,ep7312-keypad", "cirrus,clps711x-keypad";
+                autorepeat;
+                poll-interval = <120>;
+                row-gpios = <&porta 0 0>,
+                            <&porta 1 0>;
+                linux,keymap = <
+                        MATRIX_KEY(0, 0, KEY_UP)
+                        MATRIX_KEY(0, 1, KEY_DOWN)
+                        MATRIX_KEY(1, 0, KEY_LEFT)
+                        MATRIX_KEY(1, 1, KEY_RIGHT)
+                >;
+        };
diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt b/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
new file mode 100644
index 000000000000..7d8cb92831d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/qcom,pm8xxx-keypad.txt
@@ -0,0 +1,89 @@
+Qualcomm PM8xxx PMIC Keypad
+PROPERTIES
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,pm8058-keypad"
+                    "qcom,pm8921-keypad"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: address of keypad control register
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the first interrupt specifies the key sense interrupt
+                    and the second interrupt specifies the key stuck interrupt.
+                    The format of the specifier is defined by the binding
+                    document describing the node's interrupt parent.
+- linux,keymap:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the linux keymap. More information can be found in
+                    input/matrix-keymap.txt.
+- linux,keypad-no-autorepeat:
+        Usage: optional
+        Value type: <bool>
+        Definition: don't enable autorepeat feature.
+- linux,keypad-wakeup:
+        Usage: optional
+        Value type: <bool>
+        Definition: use any event on keypad as wakeup event.
+- keypad,num-rows:
+        Usage: required
+        Value type: <u32>
+        Definition: number of rows in the keymap. More information can be found
+                    in input/matrix-keymap.txt.
+- keypad,num-columns:
+        Usage: required
+        Value type: <u32>
+        Definition: number of columns in the keymap. More information can be
+                    found in input/matrix-keymap.txt.
+- debounce:
+        Usage: optional
+        Value type: <u32>
+        Definition: time in microseconds that key must be pressed or release
+                    for key sense interrupt to trigger.
+- scan-delay:
+        Usage: optional
+        Value type: <u32>
+        Definition: time in microseconds to pause between successive scans
+                    of the matrix array.
+- row-hold:
+        Usage: optional
+        Value type: <u32>
+        Definition: time in nanoseconds to pause between scans of each row in
+                    the matrix array.
+EXAMPLE
+        keypad@148 {
+                compatible = "qcom,pm8921-keypad";
+                reg = <0x148>;
+                interrupt-parent = <&pmicintc>;
+                interrupts = <74 1>, <75 1>;
+                linux,keymap = <
+                        MATRIX_KEY(0, 0, KEY_VOLUMEUP)
+                        MATRIX_KEY(0, 1, KEY_VOLUMEDOWN)
+                        MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS)
+                        MATRIX_KEY(0, 3, KEY_CAMERA)
+                        >;
+                keypad,num-rows = <1>;
+                keypad,num-columns = <5>;
+                debounce = <15>;
+                scan-delay = <32>;
+                row-hold = <91500>;
+        };
diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-pwrkey.txt b/Documentation/devicetree/bindings/input/qcom,pm8xxx-pwrkey.txt
new file mode 100644
index 000000000000..588536cc96ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/qcom,pm8xxx-pwrkey.txt
@@ -0,0 +1,46 @@
+Qualcomm PM8xxx PMIC Power Key
+PROPERTIES
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,pm8058-pwrkey"
+                    "qcom,pm8921-pwrkey"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: address of power key control register
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the first interrupt specifies the key release interrupt
+                    and the second interrupt specifies the key press interrupt.
+                    The format of the specifier is defined by the binding
+                    document describing the node's interrupt parent.
+- debounce:
+        Usage: optional
+        Value type: <u32>
+        Definition: time in microseconds that key must be pressed or release
+                    for state change interrupt to trigger.
+- pull-up:
+        Usage: optional
+        Value type: <empty>
+        Definition: presence of this property indicates that the KPDPWR_N pin
+                    should be configured for pull up.
+EXAMPLE
+        pwrkey@1c {
+                compatible = "qcom,pm8921-pwrkey";
+                reg = <0x1c>;
+                interrupt-parent = <&pmicintc>;
+                interrupts = <50 1>, <51 1>;
+                debounce = <15625>;
+                pull-up;
+        };
diff --git a/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.txt b/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.txt
new file mode 100644
index 000000000000..4ed467b1e402
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/qcom,pm8xxx-vib.txt
@@ -0,0 +1,22 @@
+Qualcomm PM8xxx PMIC Vibrator
+PROPERTIES
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,pm8058-vib"
+                    "qcom,pm8921-vib"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: address of vibration control register
+EXAMPLE
+        vibrator@4a {
+                compatible = "qcom,pm8058-vib";
+                reg = <0x4a>;
+        };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
new file mode 100644
index 000000000000..76db96704a60
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -0,0 +1,55 @@
+FocalTech EDT-FT5x06 Polytouch driver
+=====================================
+There are 3 variants of the chip for various touch panel sizes
+FT5206GE1  2.8" .. 3.8"
+FT5306DE4  4.3" .. 7"
+FT5406EE8  7"   .. 8.9"
+The software interface is identical for all those chips, so that
+currently there is no need for the driver to distinguish between the
+different chips. Nevertheless distinct compatible strings are used so
+that a distinction can be added if necessary without changing the DT
+bindings.
+Required properties:
+ - compatible:  "edt,edt-ft5206"
+           or:  "edt,edt-ft5306"
+           or:  "edt,edt-ft5406"
+ - reg:         I2C slave address of the chip (0x38)
+ - interrupt-parent: a phandle pointing to the interrupt controller
+                     serving the interrupt for this chip
+ - interrupts:       interrupt specification for the touchdetect
+                     interrupt
+Optional properties:
+ - reset-gpios: GPIO specification for the RESET input
+ - wake-gpios:  GPIO specification for the WAKE input
+ - pinctrl-names: should be "default"
+ - pinctrl-0:   a phandle pointing to the pin settings for the
+                control gpios
+ - threshold:   allows setting the "click"-threshold in the range
+                from 20 to 80.
+ - gain:        allows setting the sensitivity in the range from 0 to
+                31. Note that lower values indicate higher
+                sensitivity.
+ - offset:      allows setting the edge compensation in the range from
+                0 to 31.
+Example:
+        polytouch: edt-ft5x06@38 {
+                compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
+                reg = <0x38>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&edt_ft5x06_pins>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <5 0>;
+                reset-gpios = <&gpio2 6 1>;
+                wake-gpios = <&gpio4 9 0>;
+        };
diff --git a/Documentation/devicetree/bindings/input/touchscreen/zforce_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/zforce_ts.txt
new file mode 100644
index 000000000000..2faf1f1fa39e
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/touchscreen/zforce_ts.txt
@@ -0,0 +1,30 @@
+* Neonode infrared touchscreen controller
+Required properties:
+- compatible: must be "neonode,zforce"
+- reg: I2C address of the chip
+- interrupts: interrupt to which the chip is connected
+- gpios: gpios the chip is connected to
+  first one is the interrupt gpio and second one the reset gpio
+- x-size: horizontal resolution of touchscreen
+- y-size: vertical resolution of touchscreen
+Example:
+        i2c@00000000 {
+                /* ... */
+                zforce_ts@50 {
+                        compatible = "neonode,zforce";
+                        reg = <0x50>;
+                        interrupts = <2 0>;
+                        gpios = <&gpio5 6 0>, /* INT */
+                                <&gpio5 9 0>; /* RST */
+                        x-size = <800>;
+                        y-size = <600>;
+                };
+                /* ... */
+        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index 32cec4b26cd0..b290ca150d30 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller
 Required properties:
- compatible : should be "allwinner,sun4i-ic"
+- compatible : should be "allwinner,sun4i-a10-ic"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
@@ -11,7 +11,7 @@ Required properties:
 Example:
 intc: interrupt-controller {
-        compatible = "allwinner,sun4i-ic";
+        compatible = "allwinner,sun4i-a10-ic";
        reg = <0x01c20400 0x400>;
        interrupt-controller;
        #interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt
new file mode 100644
index 000000000000..d1c5cdabc3e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun67i-sc-nmi.txt
@@ -0,0 +1,27 @@
+Allwinner Sunxi NMI Controller
+==============================
+Required properties:
+- compatible : should be "allwinner,sun7i-a20-sc-nmi" or
+  "allwinner,sun6i-a31-sc-nmi"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 2. The first cell is the IRQ number, the
+  second cell the trigger type as defined in interrupt.txt in this directory.
+- interrupt-parent: Specifies the parent interrupt controller.
+- interrupts: Specifies the interrupt line (NMI) which is handled by
+  the interrupt controller in the parent controller's notation. This value
+  shall be the NMI.
+Example:
+sc-nmi-intc@01c00030 {
+        compatible = "allwinner,sun7i-a20-sc-nmi";
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        reg = <0x01c00030 0x0c>;
+        interrupt-parent = <&gic>;
+        interrupts = <0 0 4>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt
new file mode 100644
index 000000000000..759339c34e4f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/cirrus,clps711x-intc.txt
@@ -0,0 +1,41 @@
+Cirrus Logic CLPS711X Interrupt Controller
+Required properties:
+- compatible: Should be "cirrus,clps711x-intc".
+- reg: Specifies base physical address of the registers set.
+- interrupt-controller: Identifies the node as an interrupt controller.
+- #interrupt-cells: Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+The interrupt sources are as follows:
+ID      Name    Description
+---------------------------
+1:      BLINT   Battery low (FIQ)
+3:      MCINT   Media changed (FIQ)
+4:      CSINT   CODEC sound
+5:      EINT1   External 1
+6:      EINT2   External 2
+7:      EINT3   External 3
+8:      TC1OI   TC1 under flow
+9:      TC2OI   TC2 under flow
+10:     RTCMI   RTC compare match
+11:     TINT    64Hz tick
+12:     UTXINT1 UART1 transmit FIFO half empty
+13:     URXINT1 UART1 receive FIFO half full
+14:     UMSINT  UART1 modem status changed
+15:     SSEOTI  SSI1 end of transfer
+16:     KBDINT  Keyboard
+17:     SS2RX   SSI2 receive FIFO half or greater full
+18:     SS2TX   SSI2 transmit FIFO less than half empty
+28:     UTXINT2 UART2 transmit FIFO half empty
+29:     URXINT2 UART2 receive FIFO half full
+32:     DAIINT  DAI interface (FIQ)
+Example:
+        intc: interrupt-controller {
+                compatible = "cirrus,clps711x-intc";
+                reg = <0x80000000 0x4000>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index e34c6cdd8ba8..f284b99402bc 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -48,6 +48,12 @@ conditions.
                  from the mmu-masters towards memory) node for this
                  SMMU.
+- calxeda,smmu-secure-config-access : Enable proper handling of buggy
+                  implementations that always use secure access to
+                  SMMU configuration registers. In this case non-secure
+                  aliases of secure registers have to be used during
+                  SMMU configuration.
 Example:
        smmu {
diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt
new file mode 100644
index 000000000000..42531dc387aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt
@@ -0,0 +1,26 @@
+OMAP2+ IOMMU
+Required properties:
+- compatible : Should be one of,
+                "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
+                "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
+                "ti,dra7-iommu" for DRA7xx IOMMU instances
+- ti,hwmods  : Name of the hwmod associated with the IOMMU instance
+- reg        : Address space for the configuration registers
+- interrupts : Interrupt specifier for the IOMMU instance
+Optional properties:
+- ti,#tlb-entries : Number of entries in the translation look-aside buffer.
+                    Should be either 8 or 32 (default: 32)
+- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
+                          back a bus error response on MMU faults.
+Example:
+        /* OMAP3 ISP MMU */
+        mmu_isp: mmu@480bd400 {
+                compatible = "ti,omap2-iommu";
+                reg = <0x480bd400 0x80>;
+                interrupts = <24>;
+                ti,hwmods = "mmu_isp";
+                ti,#tlb-entries = <8>;
+        };
diff --git a/Documentation/devicetree/bindings/media/img-ir-rev1.txt b/Documentation/devicetree/bindings/media/img-ir-rev1.txt
new file mode 100644
index 000000000000..5434ce61b925
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/img-ir-rev1.txt
@@ -0,0 +1,34 @@
+* ImgTec Infrared (IR) decoder version 1
+This binding is for Imagination Technologies' Infrared decoder block,
+specifically major revision 1.
+Required properties:
+- compatible:           Should be "img,ir-rev1"
+- reg:                  Physical base address of the controller and length of
+                        memory mapped region.
+- interrupts:           The interrupt specifier to the cpu.
+Optional properties:
+- clocks:               List of clock specifiers as described in standard
+                        clock bindings.
+                        Up to 3 clocks may be specified in the following order:
+                        1st:    Core clock (defaults to 32.768KHz if omitted).
+                        2nd:    System side (fast) clock.
+                        3rd:    Power modulation clock.
+- clock-names:          List of clock names corresponding to the clocks
+                        specified in the clocks property.
+                        Accepted clock names are:
+                        "core": Core clock.
+                        "sys":  System clock.
+                        "mod":  Power modulation clock.
+Example:
+        ir@02006200 {
+                compatible = "img,ir-rev1";
+                reg = <0x02006200 0x100>;
+                interrupts = <29 4>;
+                clocks = <&clk_32khz>;
+                clock-names =  "core";
+        };
diff --git a/Documentation/devicetree/bindings/media/samsung-fimc.txt b/Documentation/devicetree/bindings/media/samsung-fimc.txt
index 96312f6c4c26..922d6f8e74be 100644
--- a/Documentation/devicetree/bindings/media/samsung-fimc.txt
+++ b/Documentation/devicetree/bindings/media/samsung-fimc.txt
@@ -15,11 +15,21 @@ Common 'camera' node
 Required properties:
- compatible    : must be "samsung,fimc", "simple-bus"
+- compatible: must be "samsung,fimc", "simple-bus"
- clocks        : list of clock specifiers, corresponding to entries in
+- clocks: list of clock specifiers, corresponding to entries in
-                  the clock-names property;
+  the clock-names property;
- clock-names   : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
+- clock-names : must contain "sclk_cam0", "sclk_cam1", "pxl_async0",
-                  "pxl_async1" entries, matching entries in the clocks property.
+  "pxl_async1" entries, matching entries in the clocks property.
+- #clock-cells: from the common clock bindings (../clock/clock-bindings.txt),
+  must be 1. A clock provider is associated with the 'camera' node and it should
+  be referenced by external sensors that use clocks provided by the SoC on
+  CAM_*_CLKOUT pins. The clock specifier cell stores an index of a clock.
+  The indices are 0, 1 for CAM_A_CLKOUT, CAM_B_CLKOUT clocks respectively.
+- clock-output-names: from the common clock bindings, should contain names of
+  clocks registered by the camera subsystem corresponding to CAM_A_CLKOUT,
+  CAM_B_CLKOUT output clocks respectively.
 The pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt must be used
 to define a required pinctrl state named "default" and optional pinctrl states:
@@ -32,6 +42,7 @@ way around.
 The 'camera' node must include at least one 'fimc' child node.
 'fimc' device nodes
 -------------------
@@ -88,8 +99,8 @@ port nodes specifies data input - 0, 1 indicates input A, B respectively.
 Optional properties
- samsung,camclk-out : specifies clock output for remote sensor,
+- samsung,camclk-out (deprecated) : specifies clock output for remote sensor,
-                       0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
+  0 - CAM_A_CLKOUT, 1 - CAM_B_CLKOUT;
 Image sensor nodes
 ------------------
@@ -97,8 +108,6 @@ Image sensor nodes
 The sensor device nodes should be added to their control bus controller (e.g.
 I2C0) nodes and linked to a port node in the csis or the parallel-ports node,
 using the common video interfaces bindings, defined in video-interfaces.txt.
-The implementation of this bindings requires clock-frequency property to be
-present in the sensor device nodes.
 Example:
@@ -114,7 +123,7 @@ Example:
                        vddio-supply = <...>;
                        clock-frequency = <24000000>;
-                        clocks = <...>;
+                        clocks = <&camera 1>;
                        clock-names = "mclk";
                        port {
@@ -135,7 +144,7 @@ Example:
                        vddio-supply = <...>;
                        clock-frequency = <24000000>;
-                        clocks = <...>;
+                        clocks = <&camera 0>;
                        clock-names = "mclk";
                        port {
@@ -149,12 +158,17 @@ Example:
        camera {
                compatible = "samsung,fimc", "simple-bus";
-                #address-cells = <1>;
+                clocks = <&clock 132>, <&clock 133>, <&clock 351>,
-                #size-cells = <1>;
+                         <&clock 352>;
-                status = "okay";
+                clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0",
+                              "pxl_async1";
+                #clock-cells = <1>;
+                clock-output-names = "cam_a_clkout", "cam_b_clkout";
                pinctrl-names = "default";
                pinctrl-0 = <&cam_port_a_clk_active>;
+                status = "okay";
+                #address-cells = <1>;
+                #size-cells = <1>;
                /* parallel camera ports */
                parallel-ports {
diff --git a/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt b/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt
new file mode 100644
index 000000000000..2c85c4538a6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/samsung-s5c73m3.txt
@@ -0,0 +1,97 @@
+Samsung S5C73M3 8Mp camera ISP
+------------------------------
+The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656) video
+data busses. The I2C bus is the main control bus and additionally the SPI bus
+is used, mostly for transferring the firmware to and from the device. Two
+slave device nodes corresponding to these control bus interfaces are required
+and should be placed under respective bus controller nodes.
+I2C slave device node
+---------------------
+Required properties:
+- compatible        : "samsung,s5c73m3";
+- reg               : I2C slave address of the sensor;
+- vdd-int-supply    : digital power supply (1.2V);
+- vdda-supply       : analog power supply (1.2V);
+- vdd-reg-supply    : regulator input power supply (2.8V);
+- vddio-host-supply : host I/O power supply (1.8V to 2.8V);
+- vddio-cis-supply  : CIS I/O power supply (1.2V to 1.8V);
+- vdd-af-supply     : lens power supply (2.8V);
+- xshutdown-gpios   : specifier of GPIO connected to the XSHUTDOWN pin;
+- standby-gpios     : specifier of GPIO connected to the STANDBY pin;
+- clocks            : should contain list of phandle and clock specifier pairs
+                      according to common clock bindings for the clocks described
+                      in the clock-names property;
+- clock-names       : should contain "cis_extclk" entry for the CIS_EXTCLK clock;
+Optional properties:
+- clock-frequency   : the frequency at which the "cis_extclk" clock should be
+                      configured to operate, in Hz; if this property is not
+                      specified default 24 MHz value will be used.
+The common video interfaces bindings (see video-interfaces.txt) should be used
+to specify link from the S5C73M3 to an external image data receiver. The S5C73M3
+device node should contain one 'port' child node with an 'endpoint' subnode for
+this purpose. The data link from a raw image sensor to the S5C73M3 can be
+similarly specified, but it is optional since the S5C73M3 ISP and a raw image
+sensor are usually inseparable and form a hybrid module.
+Following properties are valid for the endpoint node(s):
+endpoint subnode
+----------------
+- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
+  video-interfaces.txt. This sensor doesn't support data lane remapping
+  and physical lane indexes in subsequent elements of the array should
+  be only consecutive ascending values.
+SPI device node
+---------------
+Required properties:
+- compatible        : "samsung,s5c73m3";
+For more details see description of the SPI busses bindings
+(../spi/spi-bus.txt) and bindings of a specific bus controller.
+Example:
+i2c@138A000000 {
+        ...
+        s5c73m3@3c {
+                compatible = "samsung,s5c73m3";
+                reg = <0x3c>;
+                vdd-int-supply = <&buck9_reg>;
+                vdda-supply = <&ldo17_reg>;
+                vdd-reg-supply = <&cam_io_reg>;
+                vddio-host-supply = <&ldo18_reg>;
+                vddio-cis-supply = <&ldo9_reg>;
+                vdd-af-supply = <&cam_af_reg>;
+                clock-frequency = <24000000>;
+                clocks = <&clk 0>;
+                clock-names = "cis_extclk";
+                reset-gpios = <&gpf1 3 1>;
+                standby-gpios = <&gpm0 1 1>;
+                port {
+                        s5c73m3_ep: endpoint {
+                                remote-endpoint = <&csis0_ep>;
+                                data-lanes = <1 2 3 4>;
+                        };
+                };
+        };
+};
+spi@1392000 {
+        ...
+        s5c73m3_spi: s5c73m3@0 {
+                compatible = "samsung,s5c73m3";
+                reg = <0>;
+                ...
+        };
+};
diff --git a/Documentation/devicetree/bindings/media/samsung-s5k6a3.txt b/Documentation/devicetree/bindings/media/samsung-s5k6a3.txt
new file mode 100644
index 000000000000..cce01e82f3e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/samsung-s5k6a3.txt
@@ -0,0 +1,33 @@
+Samsung S5K6A3(YX) raw image sensor
+---------------------------------
+S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data interfaces
+and CCI (I2C compatible) control bus.
+Required properties:
+- compatible    : "samsung,s5k6a3";
+- reg           : I2C slave address of the sensor;
+- svdda-supply  : core voltage supply;
+- svddio-supply : I/O voltage supply;
+- afvdd-supply  : AF (actuator) voltage supply;
+- gpios         : specifier of a GPIO connected to the RESET pin;
+- clocks        : should contain list of phandle and clock specifier pairs
+                  according to common clock bindings for the clocks described
+                  in the clock-names property;
+- clock-names   : should contain "extclk" entry for the sensor's EXTCLK clock;
+Optional properties:
+- clock-frequency : the frequency at which the "extclk" clock should be
+                    configured to operate, in Hz; if this property is not
+                    specified default 24 MHz value will be used.
+The common video interfaces bindings (see video-interfaces.txt) should be
+used to specify link to the image data receiver. The S5K6A3(YX) device
+node should contain one 'port' child node with an 'endpoint' subnode.
+Following properties are valid for the endpoint node:
+- data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
+  video-interfaces.txt.  The sensor supports only one data lane.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
index d5e370450ac0..d5e370450ac0 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/ifc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
new file mode 100644
index 000000000000..9592717f483f
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
@@ -0,0 +1,210 @@
+* Device tree bindings for Texas instruments AEMIF controller
+The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
+provide a glue-less interface to a variety of asynchronous memory devices like
+ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
+can be accessed at any given time via four chip selects with 64M byte access
+per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
+and Mobile SDR are not supported.
+Documentation:
+Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
+Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
+Required properties:
+- compatible:           "ti,davinci-aemif"
+                        "ti,keystone-aemif"
+                        "ti,da850-aemif"
+- reg:                  contains offset/length value for AEMIF control registers
+                        space.
+- #address-cells:       Must be 2. The partition number has to be encoded in the
+                        first address cell and it may accept values 0..N-1
+                        (N - total number of partitions). It's recommended to
+                        assign N-1 number for the control partition. The second
+                        cell is the offset into the partition.
+- #size-cells:          Must be set to 1.
+- ranges:               Contains memory regions. There are two types of
+                        ranges/partitions:
+                        - CS-specific partition/range. If continuous, must be
+                        set up to reflect the memory layout for 4 chipselects,
+                        if not then additional range/partition can be added and
+                        child device can select the proper one.
+                        - control partition which is common for all CS
+                        interfaces.
+- clocks:               the clock feeding the controller clock. Required only
+                        if clock tree data present in device tree.
+                        See clock-bindings.txt
+- clock-names:          clock name. It has to be "aemif". Required only if clock
+                        tree data present in device tree, in another case don't
+                        use it.
+                        See clock-bindings.txt
+- clock-ranges:         Empty property indicating that child nodes can inherit
+                        named clocks. Required only if clock tree data present
+                        in device tree.
+                        See clock-bindings.txt
+Child chip-select (cs) nodes contain the memory devices nodes connected to
+such as NOR (e.g. cfi-flash) and NAND (ti,davinci-nand, see davinci-nand.txt).
+There might be board specific devices like FPGAs.
+Required child cs node properties:
+- #address-cells:       Must be 2.
+- #size-cells:          Must be 1.
+- ranges:               Empty property indicating that child nodes can inherit
+                        memory layout.
+- clock-ranges:         Empty property indicating that child nodes can inherit
+                        named clocks. Required only if clock tree data present
+                        in device tree.
+- ti,cs-chipselect:     number of chipselect. Indicates on the aemif driver
+                        which chipselect is used for accessing the memory. For
+                        compatibles "ti,davinci-aemif" and "ti,keystone-aemif"
+                        it can be in range [0-3]. For compatible
+                        "ti,da850-aemif" range is [2-5].
+Optional child cs node properties:
+- ti,cs-bus-width:              width of the asynchronous device's data bus
+                                8 or 16 if not preset 8
+- ti,cs-select-strobe-mode:     enable/disable select strobe mode
+                                In select strobe mode chip select behaves as
+                                the strobe and is active only during the strobe
+                                period. If present then enable.
+- ti,cs-extended-wait-mode:     enable/disable extended wait mode
+                                if set, the controller monitors the EMIFWAIT pin
+                                mapped to that chip select to determine if the
+                                device wants to extend the strobe period. If
+                                present then enable.
+- ti,cs-min-turnaround-ns:      minimum turn around time, ns
+                                Time between the end of one asynchronous memory
+                                access and the start of another asynchronous
+                                memory access. This delay is not incurred
+                                between a read followed by read or a write
+                                followed by a write to same chip select.
+- ti,cs-read-setup-ns:          read setup width, ns
+                                Time between the beginning of a memory cycle
+                                and the activation of read strobe.
+                                Minimum value is 1 (0 treated as 1).
+- ti,cs-read-strobe-ns:         read strobe width, ns
+                                Time between the activation and deactivation of
+                                the read strobe.
+                                Minimum value is 1 (0 treated as 1).
+- ti,cs-read-hold-ns:           read hold width, ns
+                                Time between the deactivation of the read
+                                strobe and the end of the cycle (which may be
+                                either an address change or the deactivation of
+                                the chip select signal.
+                                Minimum value is 1 (0 treated as 1).
+- ti,cs-write-setup-ns:         write setup width, ns
+                                Time between the beginning of a memory cycle
+                                and the activation of write strobe.
+                                Minimum value is 1 (0 treated as 1).
+- ti,cs-write-strobe-ns:        write strobe width, ns
+                                Time between the activation and deactivation of
+                                the write strobe.
+                                Minimum value is 1 (0 treated as 1).
+- ti,cs-write-hold-ns:          write hold width, ns
+                                Time between the deactivation of the write
+                                strobe and the end of the cycle (which may be
+                                either an address change or the deactivation of
+                                the chip select signal.
+                                Minimum value is 1 (0 treated as 1).
+If any of the above parameters are absent, current parameter value will be taken
+from the corresponding HW reg.
+Example for aemif, davinci nand and nor flash chip select shown below.
+memory-controller@21000A00 {
+        compatible = "ti,davinci-aemif";
+        #address-cells = <2>;
+        #size-cells = <1>;
+        clocks = <&clkaemif 0>;
+        clock-names = "aemif";
+        clock-ranges;
+        reg = <0x21000A00 0x00000100>;
+        ranges = <0 0 0x70000000 0x10000000
+                  1 0 0x21000A00 0x00000100>;
+                  /*
+                   * Partition0: CS-specific memory range which is
+                   * implemented as continuous physical memory region
+                   * Partition1: control memory range
+                   */
+        nand:cs2 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                clock-ranges;
+                ranges;
+                ti,cs-chipselect = <2>;
+                /* all timings in nanoseconds */
+                ti,cs-min-turnaround-ns = <0>;
+                ti,cs-read-hold-ns = <7>;
+                ti,cs-read-strobe-ns = <42>;
+                ti,cs-read-setup-ns = <14>;
+                ti,cs-write-hold-ns = <7>;
+                ti,cs-write-strobe-ns = <42>;
+                ti,cs-write-setup-ns = <14>;
+                nand@0,0x8000000 {
+                        compatible = "ti,davinci-nand";
+                        reg = <0 0x8000000 0x4000000
+                               1 0x0000000 0x0000100>;
+                        /*
+                         * Partition0, offset 0x8000000, size 0x4000000
+                         * Partition1, offset 0x0000000, size 0x0000100
+                         */
+                        .. see davinci-nand.txt
+                };
+        };
+        nor:cs0 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                clock-ranges;
+                ranges;
+                ti,cs-chipselect = <0>;
+                /* all timings in nanoseconds */
+                ti,cs-min-turnaround-ns = <0>;
+                ti,cs-read-hold-ns = <8>;
+                ti,cs-read-strobe-ns = <40>;
+                ti,cs-read-setup-ns = <14>;
+                ti,cs-write-hold-ns = <7>;
+                ti,cs-write-strobe-ns = <40>;
+                ti,cs-write-setup-ns = <14>;
+                ti,cs-bus-width = <16>;
+                flash@0,0x0000000 {
+                        compatible = "cfi-flash";
+                        reg = <0 0x0000000 0x4000000>;
+                        ...
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/mfd/arizona.txt b/Documentation/devicetree/bindings/mfd/arizona.txt
index 0e295c9d8937..36a0c3d8c726 100644
--- a/Documentation/devicetree/bindings/mfd/arizona.txt
+++ b/Documentation/devicetree/bindings/mfd/arizona.txt
@@ -5,9 +5,10 @@ of analogue I/O.
 Required properties:
-  - compatible : one of the following chip-specific strings:
+  - compatible : One of the following chip-specific strings:
-        "wlf,wm5102"
+        "wlf,wm5102"
-        "wlf,wm5110"
+        "wlf,wm5110"
+        "wlf,wm8997"
  - reg : I2C slave address when connected using I2C, chip select number when
    using SPI.
@@ -25,8 +26,9 @@ Required properties:
  - #gpio-cells : Must be 2. The first cell is the pin number and the
    second cell is used to specify optional parameters (currently unused).
-  - AVDD1-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply, CPVDD-supply,
+  - AVDD-supply, DBVDD1-supply, DBVDD2-supply, DBVDD3-supply (wm5102, wm5110),
-    SPKVDDL-supply, SPKVDDR-supply : power supplies for the device, as covered
+    CPVDD-supply, SPKVDDL-supply (wm5102, wm5110), SPKVDDR-supply (wm5102,
+    wm5110), SPKVDD-supply (wm8997) : Power supplies for the device, as covered
    in Documentation/devicetree/bindings/regulator/regulator.txt
 Optional properties:
@@ -46,6 +48,7 @@ codec: wm5102@1a {
        compatible = "wlf,wm5102";
        reg = <0x1a>;
        interrupts = <347>;
+        interrupt-controller;
        #interrupt-cells = <2>;
        interrupt-parent = <&gic>;
@@ -53,10 +56,10 @@ codec: wm5102@1a {
        #gpio-cells = <2>;
        wlf,gpio-defaults = <
-                0x00000000, /* AIF1TXLRCLK */
+                0x00000000 /* AIF1TXLRCLK */
-                0xffffffff,
+                0xffffffff
-                0xffffffff,
+                0xffffffff
-                0xffffffff,
+                0xffffffff
-                0xffffffff,
+                0xffffffff
        >;
 };
diff --git a/Documentation/devicetree/bindings/mfd/bcm590xx.txt b/Documentation/devicetree/bindings/mfd/bcm590xx.txt
new file mode 100644
index 000000000000..1fe30e2b10da
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/bcm590xx.txt
@@ -0,0 +1,37 @@
+-------------------------------
+BCM590xx Power Management Units
+-------------------------------
+Required properties:
+- compatible: "brcm,bcm59056"
+- reg: I2C slave address
+- interrupts: interrupt for the PMU. Generic interrupt client node bindings
+  are described in interrupt-controller/interrupts.txt
+------------------
+Voltage Regulators
+------------------
+Optional child nodes:
+- regulators: container node for regulators following the generic
+  regulator binding in regulator/regulator.txt
+  The valid regulator node names for BCM59056 are:
+        rfldo, camldo1, camldo2, simldo1, simldo2, sdldo, sdxldo,
+        mmcldo1, mmcldo2, audldo, micldo, usbldo, vibldo,
+        csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr
+Example:
+        pmu: bcm59056@8 {
+                compatible = "brcm,bcm59056";
+                reg = <0x08>;
+                interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+                regulators {
+                        rfldo_reg: rfldo {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        ...
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/da9055.txt b/Documentation/devicetree/bindings/mfd/da9055.txt
new file mode 100644
index 000000000000..6dab34d34fce
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/da9055.txt
@@ -0,0 +1,72 @@
+* Dialog DA9055 Power Management Integrated Circuit (PMIC)
+DA9055 consists of a large and varied group of sub-devices (I2C Only):
+Device                   Supply Names    Description
+------                   ------------    -----------
+da9055-gpio             :               : GPIOs
+da9055-regulator        :               : Regulators
+da9055-onkey            :               : On key
+da9055-rtc              :               : RTC
+da9055-hwmon            :               : ADC
+da9055-watchdog         :               : Watchdog
+The CODEC device in DA9055 has a separate, configurable I2C address and so
+is instantiated separately from the PMIC.
+For details on accompanying CODEC I2C device, see the following:
+Documentation/devicetree/bindings/sound/da9055.txt
+======
+Required properties:
+- compatible : Should be "dlg,da9055-pmic"
+- reg: Specifies the I2C slave address (defaults to 0x5a but can be modified)
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the IRQs from da9055 are delivered to.
+- interrupts: IRQ line info for da9055 chip.
+- interrupt-controller: da9055 has internal IRQs (has own IRQ domain).
+- #interrupt-cells: Should be 1, is the local IRQ number for da9055.
+Sub-nodes:
+- regulators : Contain the regulator nodes. The DA9055 regulators are
+  bound using their names as listed below:
+    buck1     : regulator BUCK1
+    buck2     : regulator BUCK2
+    ldo1      : regulator LDO1
+    ldo2      : regulator LDO2
+    ldo3      : regulator LDO3
+    ldo4      : regulator LDO4
+    ldo5      : regulator LDO5
+    ldo6      : regulator LDO6
+  The bindings details of individual regulator device can be found in:
+  Documentation/devicetree/bindings/regulator/regulator.txt
+Example:
+        pmic: da9055-pmic@5a {
+                compatible = "dlg,da9055-pmic";
+                reg = <0x5a>;
+                interrupt-parent = <&intc>;
+                interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                regulators {
+                        buck1: BUCK1 {
+                                regulator-min-microvolt = <725000>;
+                                regulator-max-microvolt = <2075000>;
+                        };
+                        buck2: BUCK2 {
+                                regulator-min-microvolt = <925000>;
+                                regulator-max-microvolt = <2500000>;
+                        };
+                        ldo1: LDO1 {
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
index b381fa696bf9..4721b2d521e4 100644
--- a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
+++ b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
@@ -32,6 +32,29 @@ Optional properties:
 - single-ulpi-bypass: Must be present if the controller contains a single
  ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+- clock-names: should include:
+  For OMAP3
+  * "usbhost_120m_fck" - 120MHz Functional clock.
+  For OMAP4+
+  * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
+  * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
+  * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
+  * "utmi_p1_gfclk" - Port 1 UTMI clock mux.
+  * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
+  * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
+  * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
+  * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
+  * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
+  * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
+  * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
+  * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
+  * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
+  * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
 Required properties if child node exists:
 - #address-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
index 62fe69724e3b..c58d70437fce 100644
--- a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
+++ b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
@@ -7,6 +7,16 @@ Required properties:
 - interrupts : should contain the TLL module's interrupt
 - ti,hwmod : must contain "usb_tll_hs"
+Optional properties:
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+  clock-names.
+- clock-names: should include:
+  * "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock
+  * "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock
+  * "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock
 Example:
        usbhstll: usbhstll@4a062000 {
diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
new file mode 100644
index 000000000000..03518dc8b6bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,pm8xxx.txt
@@ -0,0 +1,96 @@
+Qualcomm PM8xxx PMIC multi-function devices
+The PM8xxx family of Power Management ICs are used to provide regulated
+voltages and other various functionality to Qualcomm SoCs.
+= PROPERTIES
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,pm8058"
+                    "qcom,pm8921"
+- #address-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: must be 1
+- #size-cells:
+        Usage: required
+        Value type: <u32>
+        Definition: must be 0
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: specifies the interrupt that indicates a subdevice
+                    has generated an interrupt (summary interrupt). The
+                    format of the specifier is defined by the binding document
+                    describing the node's interrupt parent.
+- #interrupt-cells:
+        Usage: required
+        Value type : <u32>
+        Definition: must be 2. Specifies the number of cells needed to encode
+                    an interrupt source. The 1st cell contains the interrupt
+                    number. The 2nd cell is the trigger type and level flags
+                    encoded as follows:
+                        1 = low-to-high edge triggered
+                        2 = high-to-low edge triggered
+                        4 = active high level-sensitive
+                        8 = active low level-sensitive
+- interrupt-controller:
+        Usage: required
+        Value type: <empty>
+        Definition: identifies this node as an interrupt controller
+= SUBCOMPONENTS
+The PMIC contains multiple independent functions, each described in a subnode.
+The below bindings specify the set of valid subnodes.
+== Real-Time Clock
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,pm8058-rtc"
+                    "qcom,pm8921-rtc"
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: single entry specifying the base address of the RTC registers
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: single entry specifying the RTC's alarm interrupt
+- allow-set-time:
+        Usage: optional
+        Value type: <empty>
+        Definition: indicates that the setting of RTC time is allowed by
+                    the host CPU
+= EXAMPLE
+        pmicintc: pmic@0 {
+                compatible = "qcom,pm8921";
+                interrupts = <104 8>;
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                rtc@11d {
+                        compatible = "qcom,pm8921-rtc";
+                        reg = <0x11d>;
+                        interrupts = <0x27 0>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/s2mpa01.txt b/Documentation/devicetree/bindings/mfd/s2mpa01.txt
new file mode 100644
index 000000000000..c13d3d8c3947
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/s2mpa01.txt
@@ -0,0 +1,90 @@
+* Samsung S2MPA01 Voltage and Current Regulator
+The Samsung S2MPA01 is a multi-function device which includes high
+efficiency buck converters including Dual-Phase buck converter, various LDOs,
+and an RTC. It is interfaced to the host controller using an I2C interface.
+Each sub-block is addressed by the host system using different I2C slave
+addresses.
+Required properties:
+- compatible: Should be "samsung,s2mpa01-pmic".
+- reg: Specifies the I2C slave address of the PMIC block. It should be 0x66.
+Optional properties:
+- interrupt-parent: Specifies the phandle of the interrupt controller to which
+  the interrupts from s2mpa01 are delivered to.
+- interrupts: An interrupt specifier for the sole interrupt generated by the
+  device.
+Optional nodes:
+- regulators: The regulators of s2mpa01 that have to be instantiated should be
+  included in a sub-node named 'regulators'. Regulator nodes and constraints
+  included in this sub-node use the standard regulator bindings which are
+  documented elsewhere.
+Properties for BUCK regulator nodes:
+- regulator-ramp-delay: ramp delay in uV/us. May be 6250, 12500
+  (default), 25000, or 50000. May be 0 for disabling the ramp delay on
+  BUCK{1,2,3,4}.
+ In the absence of the regulator-ramp-delay property, the default ramp
+ delay will be used.
+  NOTE: Some BUCKs share the ramp rate setting i.e. same ramp value will be set
+  for a particular group of BUCKs. So provide same regulator-ramp-delay=<value>.
+  The following BUCKs share ramp settings:
+  * 1 and 6
+  * 2 and 4
+  * 8, 9, and 10
+The following are the names of the regulators that the s2mpa01 PMIC block
+supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
+as per the datasheet of s2mpa01.
+        - LDOn
+                  - valid values for n are 1 to 26
+                  - Example: LDO1, LD02, LDO26
+        - BUCKn
+                  - valid values for n are 1 to 10.
+                  - Example: BUCK1, BUCK2, BUCK9
+Example:
+        s2mpa01_pmic@66 {
+                compatible = "samsung,s2mpa01-pmic";
+                reg = <0x66>;
+                regulators {
+                        ldo1_reg: LDO1 {
+                                regulator-name = "VDD_ALIVE";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                        };
+                        ldo2_reg: LDO2 {
+                                regulator-name = "VDDQ_MMC2";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                        };
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <950000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                                regulator-ramp-delay = <50000>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mfd/s2mps11.txt b/Documentation/devicetree/bindings/mfd/s2mps11.txt
index 15ee89c3cc7b..802e839b0829 100644
--- a/Documentation/devicetree/bindings/mfd/s2mps11.txt
+++ b/Documentation/devicetree/bindings/mfd/s2mps11.txt
@@ -1,5 +1,5 @@
-* Samsung S2MPS11 Voltage and Current Regulator
+* Samsung S2MPS11 and S2MPS14 Voltage and Current Regulator
 The Samsung S2MPS11 is a multi-function device which includes voltage and
 current regulators, RTC, charger controller and other sub-blocks. It is
@@ -7,7 +7,7 @@ interfaced to the host controller using an I2C interface. Each sub-block is
 addressed by the host system using different I2C slave addresses.
 Required properties:
- compatible: Should be "samsung,s2mps11-pmic".
+- compatible: Should be "samsung,s2mps11-pmic" or "samsung,s2mps14-pmic".
 - reg: Specifies the I2C slave address of the pmic block. It should be 0x66.
 Optional properties:
@@ -16,20 +16,25 @@ Optional properties:
 - interrupts: Interrupt specifiers for interrupt sources.
 Optional nodes:
- clocks: s2mps11 provides three(AP/CP/BT) buffered 32.768 KHz outputs, so to
+- clocks: s2mps11 and s5m8767 provide three(AP/CP/BT) buffered 32.768 KHz
-  register these as clocks with common clock framework instantiate a sub-node
+  outputs, so to register these as clocks with common clock framework
-  named "clocks". It uses the common clock binding documented in :
+  instantiate a sub-node named "clocks". It uses the common clock binding
+  documented in :
  [Documentation/devicetree/bindings/clock/clock-bindings.txt]
+  The s2mps14 provides two (AP/BT) buffered 32.768 KHz outputs.
  - #clock-cells: should be 1.
  - The following is the list of clocks generated by the controller. Each clock
    is assigned an identifier and client nodes use this identifier to specify
    the clock which they consume.
-    Clock               ID
+    Clock               ID           Devices
-    ----------------------
+    ----------------------------------------------------------
-    32KhzAP             0
+    32KhzAP             0            S2MPS11, S2MPS14, S5M8767
-    32KhzCP             1
+    32KhzCP             1            S2MPS11, S5M8767
-    32KhzBT             2
+    32KhzBT             2            S2MPS11, S2MPS14, S5M8767
+  - compatible: Should be one of: "samsung,s2mps11-clk", "samsung,s2mps14-clk",
+                "samsung,s5m8767-clk"
 - regulators: The regulators of s2mps11 that have to be instantiated should be
 included in a sub-node named 'regulators'. Regulator nodes included in this
@@ -59,10 +64,14 @@ supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
 as per the datasheet of s2mps11.
        - LDOn
-                  - valid values for n are 1 to 38
+                  - valid values for n are:
+                        - S2MPS11: 1 to 38
+                        - S2MPS14: 1 to 25
                  - Example: LDO1, LD02, LDO28
        - BUCKn
-                  - valid values for n are 1 to 10.
+                  - valid values for n are:
+                        - S2MPS11: 1 to 10
+                        - S2MPS14: 1 to 5
                  - Example: BUCK1, BUCK2, BUCK9
 Example:
@@ -71,7 +80,8 @@ Example:
                compatible = "samsung,s2mps11-pmic";
                reg = <0x66>;
-                s2m_osc: clocks{
+                s2m_osc: clocks {
+                        compatible = "samsung,s2mps11-clk";
                        #clock-cells = 1;
                        clock-output-names = "xx", "yy", "zz";
                };
diff --git a/Documentation/devicetree/bindings/mfd/tps65910.txt b/Documentation/devicetree/bindings/mfd/tps65910.txt
index b4bd98af1cc7..38833e63a59f 100644
--- a/Documentation/devicetree/bindings/mfd/tps65910.txt
+++ b/Documentation/devicetree/bindings/mfd/tps65910.txt
@@ -11,7 +11,7 @@ Required properties:
 - #interrupt-cells: the number of cells to describe an IRQ, this should be 2.
  The first cell is the IRQ number.
  The second cell is the flags, encoded as the trigger masks from
-  Documentation/devicetree/bindings/interrupts.txt
+  Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
 - regulators: This is the list of child nodes that specify the regulator
  initialization data for defined regulators. Not all regulators for the given
  device need to be present. The definition for each of these nodes is defined
diff --git a/Documentation/devicetree/bindings/misc/allwinner,sunxi-sid.txt b/Documentation/devicetree/bindings/misc/allwinner,sunxi-sid.txt
index 68ba37295565..fabdf64a5737 100644
--- a/Documentation/devicetree/bindings/misc/allwinner,sunxi-sid.txt
+++ b/Documentation/devicetree/bindings/misc/allwinner,sunxi-sid.txt
@@ -1,12 +1,12 @@
 Allwinner sunxi-sid
 Required properties:
- compatible: "allwinner,sun4i-sid" or "allwinner,sun7i-a20-sid".
+- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid"
 - reg: Should contain registers location and length
 Example for sun4i:
        sid@01c23800 {
-                compatible = "allwinner,sun4i-sid";
+                compatible = "allwinner,sun4i-a10-sid";
                reg = <0x01c23800 0x10>
        };
diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
index 60960b2755f4..efc98ea1f23d 100644
--- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -17,6 +17,14 @@ Required properties for devices compatible with "atmel,at91sam9g45-ssc":
  See Documentation/devicetree/bindings/dma/atmel-dma.txt for details.
 - dma-names: Must be "tx", "rx".
+Optional properties:
+  - atmel,clk-from-rk-pin: bool property.
+     - When SSC works in slave mode, according to the hardware design, the
+       clock can get from TK pin, and also can get from RK pin. So, add
+       this parameter to choose where the clock from.
+     - By default the clock is from TK pin, if the clock from RK pin, this
+       property is needed.
 Examples:
 - PDC transfer:
 ssc0: ssc@fffbc000 {
diff --git a/Documentation/devicetree/bindings/misc/sram.txt b/Documentation/devicetree/bindings/misc/sram.txt
index 4d0a00e453a8..36cbe5aea990 100644
--- a/Documentation/devicetree/bindings/misc/sram.txt
+++ b/Documentation/devicetree/bindings/misc/sram.txt
@@ -8,9 +8,44 @@ Required properties:
 - reg : SRAM iomem address range
+Reserving sram areas:
+---------------------
+Each child of the sram node specifies a region of reserved memory. Each
+child node should use a 'reg' property to specify a specific range of
+reserved memory.
+Following the generic-names recommended practice, node names should
+reflect the purpose of the node. Unit address (@<address>) should be
+appended to the name.
+Required properties in the sram node:
+- #address-cells, #size-cells : should use the same values as the root node
+- ranges : standard definition, should translate from local addresses
+           within the sram to bus addresses
+Required properties in the area nodes:
+- reg : iomem address range, relative to the SRAM range
+Optional properties in the area nodes:
+- compatible : standard definition, should contain a vendor specific string
+               in the form <vendor>,[<device>-]<usage>
 Example:
 sram: sram@5c000000 {
        compatible = "mmio-sram";
        reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */
+        #adress-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 0x5c000000 0x40000>;
+        smp-sram@100 {
+                compatible = "socvendor,smp-sram";
+                reg = <0x100 0x50>;
+        };
 };
diff --git a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
index 0a85c70cd30a..07ad02075a93 100644
--- a/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
+++ b/Documentation/devicetree/bindings/mmc/atmel-hsmci.txt
@@ -13,6 +13,9 @@ Required properties:
 - #address-cells: should be one. The cell is the slot id.
 - #size-cells: should be zero.
 - at least one slot node
+- clock-names: tuple listing input clock names.
+        Required elements: "mci_clk"
+- clocks: phandles to input clocks.
 The node contains child nodes for each slot that the platform uses
@@ -24,6 +27,8 @@ mmc0: mmc@f0008000 {
        interrupts = <12 4>;
        #address-cells = <1>;
        #size-cells = <0>;
+        clock-names = "mci_clk";
+        clocks = <&mci0_clk>;
        [ child node definitions...]
 };
diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
new file mode 100644
index 000000000000..4897bea7e3f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
@@ -0,0 +1,23 @@
+* Altera SOCFPGA specific extensions to the Synopsys Designware Mobile
+  Storage Host Controller
+The Synopsys designware mobile storage host controller is used to interface
+a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
+differences between the core Synopsys dw mshc controller properties described
+by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific
+extensions to the Synopsys Designware Mobile Storage Host Controller.
+Required Properties:
+* compatible: should be
+        - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform
+Example:
+        mmc: dwmmc0@ff704000 {
+                compatible = "altr,socfpga-dw-mshc";
+                reg = <0xff704000 0x1000>;
+                interrupts = <0 129 4>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 03855c8c492a..b53f92e252d4 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -5,3 +5,17 @@
  "soft_bch".
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- nand-ecc-strength: integer representing the number of bits to correct
+                     per ECC step.
+- nand-ecc-step-size: integer representing the number of data bytes
+                      that are covered by a single ECC step.
+The ECC strength and ECC step size properties define the correction capability
+of a controller. Together, they say a controller can correct "{strength} bit
+errors per {size} bytes".
+The interpretation of these parameters is implementation-defined, so not all
+implementations must support all possible combinations. However, implementations
+are encouraged to further specify the value(s) they support.
diff --git a/Documentation/devicetree/bindings/mtd/st-fsm.txt b/Documentation/devicetree/bindings/mtd/st-fsm.txt
new file mode 100644
index 000000000000..c2489391c437
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/st-fsm.txt
@@ -0,0 +1,26 @@
+* ST-Microelectronics SPI FSM Serial (NOR) Flash Controller
+Required properties:
+  - compatible : Should be "st,spi-fsm"
+  - reg        : Contains register's location and length.
+  - reg-names  : Should contain the reg names "spi-fsm"
+  - interrupts : The interrupt number
+  - pinctrl-0  : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
+Optional properties:
+  - st,syscfg          : Phandle to boot-device system configuration registers
+  - st,boot-device-reg : Address of the aforementioned boot-device register(s)
+  - st,boot-device-spi : Expected boot-device value if booted via this device
+Example:
+        spifsm: spifsm@fe902000{
+                compatible         = "st,spi-fsm";
+                reg                =  <0xfe902000 0x1000>;
+                reg-names          = "spi-fsm";
+                pinctrl-0          = <&pinctrl_fsm>;
+                st,syscfg          = <&syscfg_rear>;
+                st,boot-device-reg = <0x958>;
+                st,boot-device-spi = <0x1a>;
+                status = "okay";
+        };
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
index b90bfcd138ff..10640b17c866 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-emac.txt
@@ -1,20 +1,17 @@
 * Allwinner EMAC ethernet controller
 Required properties:
- compatible: should be "allwinner,sun4i-emac".
+- compatible: should be "allwinner,sun4i-a10-emac" (Deprecated:
+              "allwinner,sun4i-emac")
 - reg: address and length of the register set for the device.
 - interrupts: interrupt for the device
- phy: A phandle to a phy node defining the PHY address (as the reg
+- phy: see ethernet.txt file in the same directory.
-  property, a single integer).
 - clocks: A phandle to the reference clock for this device
-Optional properties:
- (local-)mac-address: mac address to be used by this driver
 Example:
 emac: ethernet@01c0b000 {
-       compatible = "allwinner,sun4i-emac";
+       compatible = "allwinner,sun4i-a10-emac";
       reg = <0x01c0b000 0x1000>;
       interrupts = <55>;
       clocks = <&ahb_gates 17>;
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
index 00b9f9a3ec1d..4ec56413779d 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
+++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-mdio.txt
@@ -1,7 +1,8 @@
 * Allwinner A10 MDIO Ethernet Controller interface
 Required properties:
- compatible: should be "allwinner,sun4i-mdio".
+- compatible: should be "allwinner,sun4i-a10-mdio"
+              (Deprecated: "allwinner,sun4i-mdio").
 - reg: address and length of the register set for the device.
 Optional properties:
@@ -9,7 +10,7 @@ Optional properties:
 Example at the SoC level:
 mdio@01c0b080 {
-        compatible = "allwinner,sun4i-mdio";
+        compatible = "allwinner,sun4i-a10-mdio";
        reg = <0x01c0b080 0x14>;
        #address-cells = <1>;
        #size-cells = <0>;
diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt b/Documentation/devicetree/bindings/net/altera_tse.txt
new file mode 100644
index 000000000000..a706297998e9
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/altera_tse.txt
@@ -0,0 +1,114 @@
+* Altera Triple-Speed Ethernet MAC driver (TSE)
+Required properties:
+- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
+                be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
+                ALTR is supported for legacy device trees, but is deprecated.
+                altr should be used for all new designs.
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  "control_port": MAC configuration space region
+  "tx_csr":       xDMA Tx dispatcher control and status space region
+  "tx_desc":      MSGDMA Tx dispatcher descriptor space region
+  "rx_csr" :      xDMA Rx dispatcher control and status space region
+  "rx_desc":      MSGDMA Rx dispatcher descriptor space region
+  "rx_resp":      MSGDMA Rx dispatcher response space region
+  "s1":           SGDMA descriptor memory
+- interrupts: Should contain the TSE interrupts and it's mode.
+- interrupt-names: Should contain the interrupt names
+  "rx_irq":       xDMA Rx dispatcher interrupt
+  "tx_irq":       xDMA Tx dispatcher interrupt
+- rx-fifo-depth: MAC receive FIFO buffer depth in bytes
+- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
+- phy-mode: See ethernet.txt in the same directory.
+- phy-handle: See ethernet.txt in the same directory.
+- phy-addr: See ethernet.txt in the same directory. A configuration should
+                include phy-handle or phy-addr.
+- altr,has-supplementary-unicast:
+                If present, TSE supports additional unicast addresses.
+                Otherwise additional unicast addresses are not supported.
+- altr,has-hash-multicast-filter:
+                If present, TSE supports a hash based multicast filter.
+                Otherwise, hash-based multicast filtering is not supported.
+- mdio device tree subnode: When the TSE has a phy connected to its local
+                mdio, there must be device tree subnode with the following
+                required properties:
+        - compatible: Must be "altr,tse-mdio".
+        - #address-cells: Must be <1>.
+        - #size-cells: Must be <0>.
+        For each phy on the mdio bus, there must be a node with the following
+        fields:
+        - reg: phy id used to communicate to phy.
+        - device_type: Must be "ethernet-phy".
+Optional properties:
+- local-mac-address: See ethernet.txt in the same directory.
+- max-frame-size: See ethernet.txt in the same directory.
+Example:
+        tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
+                compatible = "altr,tse-msgdma-1.0";
+                reg =   <0x00000001 0x00000000 0x00000400>,
+                        <0x00000001 0x00000460 0x00000020>,
+                        <0x00000001 0x00000480 0x00000020>,
+                        <0x00000001 0x000004A0 0x00000008>,
+                        <0x00000001 0x00000400 0x00000020>,
+                        <0x00000001 0x00000420 0x00000020>;
+                reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+                interrupt-parent = <&hps_0_arm_gic_0>;
+                interrupts = <0 41 4>, <0 40 4>;
+                interrupt-names = "rx_irq", "tx_irq";
+                rx-fifo-depth = <2048>;
+                tx-fifo-depth = <2048>;
+                address-bits = <48>;
+                max-frame-size = <1500>;
+                local-mac-address = [ 00 00 00 00 00 00 ];
+                phy-mode = "gmii";
+                altr,has-supplementary-unicast;
+                altr,has-hash-multicast-filter;
+                phy-handle = <&phy0>;
+                mdio {
+                        compatible = "altr,tse-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        phy0: ethernet-phy@0 {
+                                reg = <0x0>;
+                                device_type = "ethernet-phy";
+                        };
+                        phy1: ethernet-phy@1 {
+                                reg = <0x1>;
+                                device_type = "ethernet-phy";
+                        };
+                };
+        };
+        tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
+                compatible = "altr,tse-msgdma-1.0";
+                reg =   <0x00000001 0x00001000 0x00000400>,
+                        <0x00000001 0x00001460 0x00000020>,
+                        <0x00000001 0x00001480 0x00000020>,
+                        <0x00000001 0x000014A0 0x00000008>,
+                        <0x00000001 0x00001400 0x00000020>,
+                        <0x00000001 0x00001420 0x00000020>;
+                reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
+                interrupt-parent = <&hps_0_arm_gic_0>;
+                interrupts = <0 43 4>, <0 42 4>;
+                interrupt-names = "rx_irq", "tx_irq";
+                rx-fifo-depth = <2048>;
+                tx-fifo-depth = <2048>;
+                address-bits = <48>;
+                max-frame-size = <1500>;
+                local-mac-address = [ 00 00 00 00 00 00 ];
+                phy-mode = "gmii";
+                altr,has-supplementary-unicast;
+                altr,has-hash-multicast-filter;
+                phy-handle = <&phy1>;
+        };
diff --git a/Documentation/devicetree/bindings/net/arc_emac.txt b/Documentation/devicetree/bindings/net/arc_emac.txt
index bcbc3f009158..7fbb027218a1 100644
--- a/Documentation/devicetree/bindings/net/arc_emac.txt
+++ b/Documentation/devicetree/bindings/net/arc_emac.txt
@@ -6,19 +6,12 @@ Required properties:
 - interrupts: Should contain the EMAC interrupts
 - clock-frequency: CPU frequency. It is needed to calculate and set polling
 period of EMAC.
- max-speed: Maximum supported data-rate in Mbit/s. In some HW configurations
+- max-speed: see ethernet.txt file in the same directory.
-bandwidth of external memory controller might be a limiting factor. That's why
+- phy: see ethernet.txt file in the same directory.
-it's required to specify which data-rate is supported on current SoC or FPGA.
-For example if only 10 Mbit/s is supported (10BASE-T) set "10". If 100 Mbit/s is
-supported (100BASE-TX) set "100".
- phy: PHY device attached to the EMAC via MDIO bus
 Child nodes of the driver are the individual PHY devices connected to the
 MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
-Optional properties:
- mac-address: 6 bytes, mac address
 Examples:
        ethernet@c0fc2000 {
diff --git a/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt b/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
new file mode 100644
index 000000000000..f2febb94550e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/broadcom-bcmgenet.txt
@@ -0,0 +1,121 @@
+* Broadcom BCM7xxx Ethernet Controller (GENET)
+Required properties:
+- compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
+  "brcm,genet-v3", "brcm,genet-v4".
+- reg: address and length of the register set for the device
+- interrupts: must be two cells, the first cell is the general purpose
+  interrupt line, while the second cell is the interrupt for the ring
+  RX and TX queues operating in ring mode
+- phy-mode: see ethernet.txt file in the same directory
+- #address-cells: should be 1
+- #size-cells: should be 1
+Optional properties:
+- clocks: When provided, must be two phandles to the functional clocks nodes
+  of the GENET block. The first phandle is the main GENET clock used during
+  normal operation, while the second phandle is the Wake-on-LAN clock.
+- clock-names: When provided, names of the functional clock phandles, first
+  name should be "enet" and second should be "enet-wol".
+- phy-handle: See ethernet.txt file in the same directory; used to describe
+  configurations where a PHY (internal or external) is used.
+- fixed-link: When the GENET interface is connected to a MoCA hardware block or
+  when operating in a RGMII to RGMII type of connection, or when the MDIO bus is
+  voluntarily disabled, this property should be used to describe the "fixed link".
+  See Documentation/devicetree/bindings/net/fsl-tsec-phy.txt for information on
+  the property specifics
+Required child nodes:
+- mdio bus node: this node should always be present regarless of the PHY
+  configuration of the GENET instance
+MDIO bus node required properties:
+- compatible: should contain one of "brcm,genet-mdio-v1", "brcm,genet-mdio-v2"
+  "brcm,genet-mdio-v3", "brcm,genet-mdio-v4", the version has to match the
+  parent node compatible property (e.g: brcm,genet-v4 pairs with
+  brcm,genet-mdio-v4)
+- reg: address and length relative to the parent node base register address
+- #address-cells: address cell for MDIO bus addressing, should be 1
+- #size-cells: size of the cells for MDIO bus addressing, should be 0
+Ethernet PHY node properties:
+See Documentation/devicetree/bindings/net/phy.txt for the list of required and
+optional properties.
+Internal Gigabit PHY example:
+ethernet@f0b60000 {
+        phy-mode = "internal";
+        phy-handle = <&phy1>;
+        mac-address = [ 00 10 18 36 23 1a ];
+        compatible = "brcm,genet-v4";
+        #address-cells = <0x1>;
+        #size-cells = <0x1>;
+        reg = <0xf0b60000 0xfc4c>;
+        interrupts = <0x0 0x14 0x0>, <0x0 0x15 0x0>;
+        mdio@e14 {
+                compatible = "brcm,genet-mdio-v4";
+                #address-cells = <0x1>;
+                #size-cells = <0x0>;
+                reg = <0xe14 0x8>;
+                phy1: ethernet-phy@1 {
+                        max-speed = <1000>;
+                        reg = <0x1>;
+                        compatible = "brcm,28nm-gphy", "ethernet-phy-ieee802.3-c22";
+                };
+        };
+};
+MoCA interface / MAC to MAC example:
+ethernet@f0b80000 {
+        phy-mode = "moca";
+        fixed-link = <1 0 1000 0 0>;
+        mac-address = [ 00 10 18 36 24 1a ];
+        compatible = "brcm,genet-v4";
+        #address-cells = <0x1>;
+        #size-cells = <0x1>;
+        reg = <0xf0b80000 0xfc4c>;
+        interrupts = <0x0 0x16 0x0>, <0x0 0x17 0x0>;
+        mdio@e14 {
+                compatible = "brcm,genet-mdio-v4";
+                #address-cells = <0x1>;
+                #size-cells = <0x0>;
+                reg = <0xe14 0x8>;
+        };
+};
+External MDIO-connected Gigabit PHY/switch:
+ethernet@f0ba0000 {
+        phy-mode = "rgmii";
+        phy-handle = <&phy0>;
+        mac-address = [ 00 10 18 36 26 1a ];
+        compatible = "brcm,genet-v4";
+        #address-cells = <0x1>;
+        #size-cells = <0x1>;
+        reg = <0xf0ba0000 0xfc4c>;
+        interrupts = <0x0 0x18 0x0>, <0x0 0x19 0x0>;
+        mdio@0e14 {
+                compatible = "brcm,genet-mdio-v4";
+                #address-cells = <0x1>;
+                #size-cells = <0x0>;
+                reg = <0xe14 0x8>;
+                phy0: ethernet-phy@0 {
+                        max-speed = <1000>;
+                        reg = <0x0>;
+                        compatible = "brcm,bcm53125", "ethernet-phy-ieee802.3-c22";
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/can/sja1000.txt b/Documentation/devicetree/bindings/net/can/sja1000.txt
index f2105a47ec87..b4a6d53fb01a 100644
--- a/Documentation/devicetree/bindings/net/can/sja1000.txt
+++ b/Documentation/devicetree/bindings/net/can/sja1000.txt
@@ -12,6 +12,10 @@ Required properties:
 Optional properties:
+- reg-io-width : Specify the size (in bytes) of the IO accesses that
+        should be performed on the device.  Valid value is 1, 2 or 4.
+        Default to 1 (8 bits).
 - nxp,external-clock-frequency : Frequency of the external oscillator
        clock in Hz. Note that the internal clock frequency used by the
        SJA1000 is half of that value. If not specified, a default value
diff --git a/Documentation/devicetree/bindings/net/cavium-mix.txt b/Documentation/devicetree/bindings/net/cavium-mix.txt
index 5da628db68bf..8d7c3096390f 100644
--- a/Documentation/devicetree/bindings/net/cavium-mix.txt
+++ b/Documentation/devicetree/bindings/net/cavium-mix.txt
@@ -18,12 +18,7 @@ Properties:
 - interrupts: Two interrupt specifiers.  The first is the MIX
  interrupt routing and the second the routing for the AGL interrupts.
- mac-address: Optional, the MAC address to assign to the device.
+- phy-handle: Optional, see ethernet.txt file in the same directory.
- local-mac-address: Optional, the MAC address to assign to the device
-  if mac-address is not specified.
- phy-handle: Optional, a phandle for the PHY device connected to this device.
 Example:
        ethernet@1070000100800 {
diff --git a/Documentation/devicetree/bindings/net/cavium-pip.txt b/Documentation/devicetree/bindings/net/cavium-pip.txt
index d4c53ba04b3b..7dbd158810d2 100644
--- a/Documentation/devicetree/bindings/net/cavium-pip.txt
+++ b/Documentation/devicetree/bindings/net/cavium-pip.txt
@@ -35,12 +35,7 @@ Properties for PIP port which is a child the PIP interface:
 - reg: The port number within the interface group.
- mac-address: Optional, the MAC address to assign to the device.
+- phy-handle: Optional, see ethernet.txt file in the same directory.
- local-mac-address: Optional, the MAC address to assign to the device
-  if mac-address is not specified.
- phy-handle: Optional, a phandle for the PHY device connected to this device.
 Example:
diff --git a/Documentation/devicetree/bindings/net/cdns-emac.txt b/Documentation/devicetree/bindings/net/cdns-emac.txt
index 09055c2495f0..abd67c13d344 100644
--- a/Documentation/devicetree/bindings/net/cdns-emac.txt
+++ b/Documentation/devicetree/bindings/net/cdns-emac.txt
@@ -6,11 +6,7 @@ Required properties:
  or the generic form: "cdns,emac".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
- phy-mode: String, operation mode of the PHY interface.
+- phy-mode: see ethernet.txt file in the same directory.
-  Supported values are: "mii", "rmii".
-Optional properties:
- local-mac-address: 6 bytes, mac address
 Examples:
diff --git a/Documentation/devicetree/bindings/net/cpsw.txt b/Documentation/devicetree/bindings/net/cpsw.txt
index 05d660e4ac64..ae2b8b7f9c38 100644
--- a/Documentation/devicetree/bindings/net/cpsw.txt
+++ b/Documentation/devicetree/bindings/net/cpsw.txt
@@ -28,9 +28,8 @@ Optional properties:
 Slave Properties:
 Required properties:
 - phy_id                : Specifies slave phy id
- phy-mode              : The interface between the SoC and the PHY (a string
+- phy-mode              : See ethernet.txt file in the same directory
-                          that of_get_phy_mode() can understand)
+- mac-address           : See ethernet.txt file in the same directory
- mac-address           : Specifies slave MAC address
 Optional properties:
 - dual_emac_res_vlan    : Specifies VID to be used to segregate the ports
diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
index 2d39c990e641..28767ed7c1bd 100644
--- a/Documentation/devicetree/bindings/net/davicom-dm9000.txt
+++ b/Documentation/devicetree/bindings/net/davicom-dm9000.txt
@@ -9,8 +9,6 @@ Required properties:
 - interrupts : interrupt specifier specific to interrupt controller
 Optional properties:
- local-mac-address : A bytestring of 6 bytes specifying Ethernet MAC address
-    to use (from firmware or bootloader)
 - davicom,no-eeprom : Configuration EEPROM is not available
 - davicom,ext-phy : Use external PHY
diff --git a/Documentation/devicetree/bindings/net/davinci_emac.txt b/Documentation/devicetree/bindings/net/davinci_emac.txt
index 6e356d15154a..032808843f90 100644
--- a/Documentation/devicetree/bindings/net/davinci_emac.txt
+++ b/Documentation/devicetree/bindings/net/davinci_emac.txt
@@ -17,9 +17,8 @@ Required properties:
                          Miscellaneous Interrupt>
 Optional properties:
- phy-handle: Contains a phandle to an Ethernet PHY.
+- phy-handle: See ethernet.txt file in the same directory.
              If absent, davinci_emac driver defaults to 100/FULL.
- local-mac-address : 6 bytes, mac address
 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
 - ti,davinci-no-bd-ram: boolean, does EMAC have BD RAM?
diff --git a/Documentation/devicetree/bindings/net/ethernet.txt b/Documentation/devicetree/bindings/net/ethernet.txt
new file mode 100644
index 000000000000..9ecd43d8792c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ethernet.txt
@@ -0,0 +1,25 @@
+The following properties are common to the Ethernet controllers:
+- local-mac-address: array of 6 bytes, specifies the MAC address that was
+  assigned to the network device;
+- mac-address: array of 6 bytes, specifies the MAC address that was last used by
+  the boot program; should be used in cases where the MAC address assigned to
+  the device by the boot program is different from the "local-mac-address"
+  property;
+- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
+- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
+  the maximum frame size (there's contradiction in ePAPR).
+- phy-mode: string, operation mode of the PHY interface; supported values are
+  "mii", "gmii", "sgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id",
+  "rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto
+  standard property;
+- phy-connection-type: the same as "phy-mode" property but described in ePAPR;
+- phy-handle: phandle, specifies a reference to a node representing a PHY
+  device; this property is described in ePAPR and so preferred;
+- phy: the same as "phy-handle" property, not recommended for new bindings.
+- phy-device: the same as "phy-handle" property, not recommended for new
+  bindings.
+Child nodes of the Ethernet controller are typically the individual PHY devices
+connected via the MDIO bus (sometimes the MDIO bus controller is separate).
+They are described in the phy.txt file in this same directory.
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 845ff848d895..6bc84adb10c0 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -4,12 +4,9 @@ Required properties:
 - compatible : Should be "fsl,<soc>-fec"
 - reg : Address and length of the register set for the device
 - interrupts : Should contain fec interrupt
- phy-mode : String, operation mode of the PHY interface.
+- phy-mode : See ethernet.txt file in the same directory
-  Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii",
-  "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii".
 Optional properties:
- local-mac-address : 6 bytes, mac address
 - phy-reset-gpios : Should specify the gpio for phy reset
 - phy-reset-duration : Reset duration in milliseconds.  Should present
  only if property "phy-reset-gpios" is available.  Missing the property
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index d2ea4605d078..737cdef4f903 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -38,22 +38,17 @@ Properties:
  - model : Model of the device.  Can be "TSEC", "eTSEC", or "FEC"
  - compatible : Should be "gianfar"
  - reg : Offset and length of the register set for the device
-  - local-mac-address : List of bytes representing the ethernet address of
-    this controller
  - interrupts : For FEC devices, the first interrupt is the device's
    interrupt.  For TSEC and eTSEC devices, the first interrupt is
    transmit, the second is receive, and the third is error.
-  - phy-handle : The phandle for the PHY connected to this ethernet
+  - phy-handle : See ethernet.txt file in the same directory.
-    controller.
  - fixed-link : <a b c d e> where a is emulated phy id - choose any,
    but unique to the all specified fixed-links, b is duplex - 0 half,
    1 full, c is link speed - d#10/d#100/d#1000, d is pause - 0 no
    pause, 1 pause, e is asym_pause - 0 no asym_pause, 1 asym_pause.
-  - phy-connection-type : a string naming the controller/PHY interface type,
+  - phy-connection-type : See ethernet.txt file in the same directory.
-    i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "sgmii",
+    This property is only really needed if the connection is of type
-    "tbi", or "rtbi".  This property is only really needed if the connection
+    "rgmii-id", as all other connection types are detected by hardware.
-    is of type "rgmii-id", as all other connection types are detected by
-    hardware.
  - fsl,magic-packet : If present, indicates that the hardware supports
    waking up via magic packet.
  - bd-stash : If present, indicates that the hardware supports stashing
diff --git a/Documentation/devicetree/bindings/net/lpc-eth.txt b/Documentation/devicetree/bindings/net/lpc-eth.txt
index 585021acd178..b92e927808b6 100644
--- a/Documentation/devicetree/bindings/net/lpc-eth.txt
+++ b/Documentation/devicetree/bindings/net/lpc-eth.txt
@@ -6,10 +6,9 @@ Required properties:
 - interrupts: Should contain ethernet controller interrupt
 Optional properties:
- phy-mode: String, operation mode of the PHY interface.
+- phy-mode: See ethernet.txt file in the same directory. If the property is
-  Supported values are: "mii", "rmii" (default)
+  absent, "rmii" is assumed.
 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
- local-mac-address : 6 bytes, mac address
 Example:
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 70af2ec12b09..aaa696414f57 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -8,16 +8,12 @@ Required properties:
  the Cadence GEM, or the generic form: "cdns,gem".
 - reg: Address and length of the register set for the device
 - interrupts: Should contain macb interrupt
- phy-mode: String, operation mode of the PHY interface.
+- phy-mode: See ethernet.txt file in the same directory.
-  Supported values are: "mii", "rmii", "gmii", "rgmii".
 - clock-names: Tuple listing input clock names.
        Required elements: 'pclk', 'hclk'
        Optional elements: 'tx_clk'
 - clocks: Phandles to input clocks.
-Optional properties:
- local-mac-address: 6 bytes, mac address
 Examples:
        macb0: ethernet@fffc4000 {
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index 859a6fa7569c..750d577e8083 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -4,10 +4,8 @@ Required properties:
 - compatible: should be "marvell,armada-370-neta".
 - reg: address and length of the register set for the device.
 - interrupts: interrupt for the device
- phy: A phandle to a phy node defining the PHY address (as the reg
+- phy: See ethernet.txt file in the same directory.
-  property, a single integer).
+- phy-mode: See ethernet.txt file in the same directory
- phy-mode: The interface between the SoC and the PHY (a string that
-  of_get_phy_mode() can understand)
 - clocks: a pointer to the reference clock for this device.
 Example:
diff --git a/Documentation/devicetree/bindings/net/marvell-orion-net.txt b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
index c233b6114242..bce52b2ec55e 100644
--- a/Documentation/devicetree/bindings/net/marvell-orion-net.txt
+++ b/Documentation/devicetree/bindings/net/marvell-orion-net.txt
@@ -36,7 +36,7 @@ Required port properties:
      "marvell,kirkwood-eth-port".
 - reg: port number relative to ethernet controller, shall be 0, 1, or 2.
 - interrupts: port interrupt.
- - local-mac-address: 6 bytes MAC address.
+ - local-mac-address: See ethernet.txt file in the same directory.
 Optional port properties:
 - marvell,tx-queue-size: size of the transmit ring buffer.
@@ -48,7 +48,7 @@ Optional port properties:
 and
- - phy-handle: phandle reference to ethernet PHY.
+ - phy-handle: See ethernet.txt file in the same directory.
 or
diff --git a/Documentation/devicetree/bindings/net/micrel-ks8851.txt b/Documentation/devicetree/bindings/net/micrel-ks8851.txt
index 11ace3c3d805..d54d0cc79487 100644
--- a/Documentation/devicetree/bindings/net/micrel-ks8851.txt
+++ b/Documentation/devicetree/bindings/net/micrel-ks8851.txt
@@ -6,4 +6,4 @@ Required properties:
 - interrupts : interrupt connection
 Optional properties:
- local-mac-address : Ethernet mac address to use
+- vdd-supply:   supply for Ethernet mac
diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt
new file mode 100644
index 000000000000..98a3e61f9ee8
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/micrel.txt
@@ -0,0 +1,18 @@
+Micrel PHY properties.
+These properties cover the base properties Micrel PHYs.
+Optional properties:
+ - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
+              Configure the LED mode with single value. The list of PHYs and
+              the bits that are currently supported:
+              KSZ8001: register 0x1e, bits 15..14
+              KSZ8041: register 0x1e, bits 15..14
+              KSZ8021: register 0x1f, bits 5..4
+              KSZ8031: register 0x1f, bits 5..4
+              KSZ8051: register 0x1f, bits 5..4
+              See the respective PHY datasheet for the mode values.
diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
new file mode 100644
index 000000000000..8dd3ef7bc56b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
@@ -0,0 +1,34 @@
+* Texas Instruments TRF7970A RFID/NFC/15693 Transceiver
+Required properties:
+- compatible: Should be "ti,trf7970a".
+- spi-max-frequency: Maximum SPI frequency (<= 2000000).
+- interrupt-parent: phandle of parent interrupt handler.
+- interrupts: A single interrupt specifier.
+- ti,enable-gpios: Two GPIO entries used for 'EN' and 'EN2' pins on the
+  TRF7970A.
+- vin-supply: Regulator for supply voltage to VIN pin
+Optional SoC Specific Properties:
+- pinctrl-names: Contains only one value - "default".
+- pintctrl-0: Specifies the pin control groups used for this controller.
+Example (for ARM-based BeagleBone with TRF7970A on SPI1):
+&spi1 {
+        status = "okay";
+        nfc@0 {
+                compatible = "ti,trf7970a";
+                reg = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&trf7970a_default>;
+                spi-max-frequency = <2000000>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <14 0>;
+                ti,enable-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>,
+                                  <&gpio2 5 GPIO_ACTIVE_LOW>;
+                vin-supply = <&ldo3_reg>;
+                status = "okay";
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/opencores-ethoc.txt b/Documentation/devicetree/bindings/net/opencores-ethoc.txt
new file mode 100644
index 000000000000..2dc127c30d9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/opencores-ethoc.txt
@@ -0,0 +1,22 @@
+* OpenCores MAC 10/100 Mbps
+Required properties:
+- compatible: Should be "opencores,ethoc".
+- reg: two memory regions (address and length),
+  first region is for the device registers and descriptor rings,
+  second is for the device packet memory.
+- interrupts: interrupt for the device.
+Optional properties:
+- clocks: phandle to refer to the clk used as per
+  Documentation/devicetree/bindings/clock/clock-bindings.txt
+Examples:
+        enet0: ethoc@fd030000 {
+                compatible = "opencores,ethoc";
+                reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
+                interrupts = <1>;
+                local-mac-address = [00 50 c2 13 6f 00];
+                clocks = <&osc>;
+        };
diff --git a/Documentation/devicetree/bindings/net/phy.txt b/Documentation/devicetree/bindings/net/phy.txt
index 58307d0931c8..5b8c58903077 100644
--- a/Documentation/devicetree/bindings/net/phy.txt
+++ b/Documentation/devicetree/bindings/net/phy.txt
@@ -21,10 +21,18 @@ Optional Properties:
  elements.
 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
+  If the phy's identifier is known then the list may contain an entry
+  of the form: "ethernet-phy-idAAAA.BBBB" where
+     AAAA - The value of the 16 bit Phy Identifier 1 register as
+            4 hex digits. This is the chip vendor OUI bits 3:18
+     BBBB - The value of the 16 bit Phy Identifier 2 register as
+            4 hex digits. This is the chip vendor OUI bits 19:24,
+            followed by 10 bits of a vendor specific ID.
 Example:
 ethernet-phy@0 {
-        compatible = "ethernet-phy-ieee802.3-c22";
+        compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22";
        interrupt-parent = <40000>;
        interrupts = <35 1>;
        reg = <0>;
diff --git a/Documentation/devicetree/bindings/net/samsung-sxgbe.txt b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
new file mode 100644
index 000000000000..989f6c95cfd5
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/samsung-sxgbe.txt
@@ -0,0 +1,52 @@
+* Samsung 10G Ethernet driver (SXGBE)
+Required properties:
+- compatible: Should be "samsung,sxgbe-v2.0a"
+- reg: Address and length of the register set for the device
+- interrupt-parent: Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- interrupts: Should contain the SXGBE interrupts
+  These interrupts are ordered by fixed and follows variable
+  trasmit DMA interrupts, receive DMA interrupts and lpi interrupt.
+  index 0 - this is fixed common interrupt of SXGBE and it is always
+  available.
+  index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts
+  and 1 optional lpi interrupt.
+- phy-mode: String, operation mode of the PHY interface.
+  Supported values are: "sgmii", "xgmii".
+- samsung,pbl: Integer, Programmable Burst Length.
+  Supported values are 1, 2, 4, 8, 16, or 32.
+- samsung,burst-map: Integer, Program the possible bursts supported by sxgbe
+  This is an interger and represents allowable DMA bursts when fixed burst.
+  Allowable range is 0x01-0x3F. When this field is set fixed burst is enabled.
+  When fixed length is needed for burst mode, it can be set within allowable
+  range.
+Optional properties:
+- mac-address: 6 bytes, mac address
+- max-frame-size: Maximum Transfer Unit (IEEE defined MTU), rather
+                  than the maximum frame size.
+Example:
+        aliases {
+                ethernet0 = <&sxgbe0>;
+        };
+        sxgbe0: ethernet@1a040000 {
+                compatible = "samsung,sxgbe-v2.0a";
+                reg = <0 0x1a040000 0 0x10000>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 209 4>, <0 185 4>, <0 186 4>, <0 187 4>,
+                             <0 188 4>, <0 189 4>, <0 190 4>, <0 191 4>,
+                             <0 192 4>, <0 193 4>, <0 194 4>, <0 195 4>,
+                             <0 196 4>, <0 197 4>, <0 198 4>, <0 199 4>,
+                             <0 200 4>, <0 201 4>, <0 202 4>, <0 203 4>,
+                             <0 204 4>, <0 205 4>, <0 206 4>, <0 207 4>,
+                             <0 208 4>, <0 210 4>;
+                samsung,pbl = <0x08>
+                samsung,burst-map = <0x20>
+                mac-address = [ 00 11 22 33 44 55 ]; /* Filled in by U-Boot */
+                max-frame-size = <9000>;
+                phy-mode = "xgmii";
+        };
diff --git a/Documentation/devicetree/bindings/net/sh_eth.txt b/Documentation/devicetree/bindings/net/sh_eth.txt
new file mode 100644
index 000000000000..e7106b50dbdc
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sh_eth.txt
@@ -0,0 +1,55 @@
+* Renesas Electronics SH EtherMAC
+This file provides information on what the device node for the SH EtherMAC
+interface contains.
+Required properties:
+- compatible: "renesas,gether-r8a7740" if the device is a part of R8A7740 SoC.
+              "renesas,ether-r8a7778"  if the device is a part of R8A7778 SoC.
+              "renesas,ether-r8a7779"  if the device is a part of R8A7779 SoC.
+              "renesas,ether-r8a7790"  if the device is a part of R8A7790 SoC.
+              "renesas,ether-r8a7791"  if the device is a part of R8A7791 SoC.
+              "renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
+- reg: offset and length of (1) the E-DMAC/feLic register block (required),
+       (2) the TSU register block (optional).
+- interrupts: interrupt specifier for the sole interrupt.
+- phy-mode: see ethernet.txt file in the same directory.
+- phy-handle: see ethernet.txt file in the same directory.
+- #address-cells: number of address cells for the MDIO bus, must be equal to 1.
+- #size-cells: number of size cells on the MDIO bus, must be equal to 0.
+- clocks: clock phandle and specifier pair.
+- pinctrl-0: phandle, referring to a default pin configuration node.
+Optional properties:
+- interrupt-parent: the phandle for the interrupt controller that services
+                    interrupts for this device.
+- pinctrl-names: pin configuration state name ("default").
+- renesas,no-ether-link: boolean, specify when a board does not provide a proper
+                         Ether LINK signal.
+- renesas,ether-link-active-low: boolean, specify when the Ether LINK signal is
+                                 active-low instead of normal active-high.
+Example (Lager board):
+        ethernet@ee700000 {
+                compatible = "renesas,ether-r8a7790";
+                reg = <0 0xee700000 0 0x400>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
+                phy-mode = "rmii";
+                phy-handle = <&phy1>;
+                pinctrl-0 = <&ether_pins>;
+                pinctrl-names = "default";
+                renesas,ether-link-active-low;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                phy1: ethernet-phy@1 {
+                        reg = <1>;
+                        interrupt-parent = <&irqc0>;
+                        interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                        pinctrl-0 = <&phy1_pins>;
+                        pinctrl-names = "default";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
index 5a41a8658daa..0f8487b88822 100644
--- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
+++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
@@ -6,8 +6,7 @@ Required properties:
 - interrupts : interrupt connection
 Optional properties:
- phy-device : phandle to Ethernet phy
+- phy-device : see ethernet.txt file in the same directory
- local-mac-address : Ethernet mac address to use
 - reg-io-width : Mask of sizes (in bytes) of the IO accesses that
  are supported on the device.  Valid value for SMSC LAN91c111 are
  1, 2 or 4.  If it's omitted or invalid, the size would be 2 meaning
diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt
index adb5b5744ecd..3fed3c124411 100644
--- a/Documentation/devicetree/bindings/net/smsc911x.txt
+++ b/Documentation/devicetree/bindings/net/smsc911x.txt
@@ -6,9 +6,7 @@ Required properties:
 - interrupts : Should contain SMSC LAN interrupt line
 - interrupt-parent : Should be the phandle for the interrupt controller
  that services interrupts for this device
- phy-mode : String, operation mode of the PHY interface.
+- phy-mode : See ethernet.txt file in the same directory
-  Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii",
-  "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii".
 Optional properties:
 - reg-shift : Specify the quantity to shift the register offsets by
@@ -23,7 +21,6 @@ Optional properties:
  external PHY
 - smsc,save-mac-address : Indicates that mac address needs to be saved
  before resetting the controller
- local-mac-address : 6 bytes, mac address
 Examples:
diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
new file mode 100644
index 000000000000..636f0ac4e223
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
@@ -0,0 +1,27 @@
+Altera SOCFPGA SoC DWMAC controller
+This is a variant of the dwmac/stmmac driver an inherits all descriptions
+present in Documentation/devicetree/bindings/net/stmmac.txt.
+The device node has additional properties:
+Required properties:
+ - compatible   : Should contain "altr,socfpga-stmmac" along with
+                  "snps,dwmac" and any applicable more detailed
+                  designware version numbers documented in stmmac.txt
+ - altr,sysmgr-syscon : Should be the phandle to the system manager node that
+   encompasses the glue register, the register offset, and the register shift.
+Example:
+gmac0: ethernet@ff700000 {
+        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+        altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+        status = "disabled";
+        reg = <0xff700000 0x2000>;
+        interrupts = <0 115 4>;
+        interrupt-names = "macirq";
+        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+        clocks = <&emac_0_clk>;
+        clocks-names = "stmmaceth";
+};
diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
new file mode 100644
index 000000000000..3dd3d0bf112f
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -0,0 +1,58 @@
+STMicroelectronics SoC DWMAC glue layer controller
+The device node has following properties.
+Required properties:
+ - compatible   : Can be "st,stih415-dwmac", "st,stih416-dwmac" or
+   "st,stid127-dwmac".
+ - reg          : Offset of the glue configuration register map in system
+   configuration regmap pointed by st,syscon property and size.
+ - reg-names    : Should be "sti-ethconf".
+ - st,syscon    : Should be phandle to system configuration node which
+   encompases this glue registers.
+ - st,tx-retime-src: On STi Parts for Giga bit speeds, 125Mhz clocks can be
+   wired up in from different sources. One via TXCLK pin and other via CLK_125
+   pin. This wiring is totally board dependent. However the retiming glue
+   logic should be configured accordingly. Possible values for this property
+           "txclk" - if 125Mhz clock is wired up via txclk line.
+           "clk_125" - if 125Mhz clock is wired up via clk_125 line.
+   This property is only valid for Giga bit setup( GMII, RGMII), and it is
+   un-used for non-giga bit (MII and RMII) setups. Also note that internal
+   clockgen can not generate stable 125Mhz clock.
+ - st,ext-phyclk: This boolean property indicates who is generating the clock
+  for tx and rx. This property is only valid for RMII case where the clock can
+  be generated from the MAC or PHY.
+ - clock-names: should be "sti-ethclk".
+ - clocks: Should point to ethernet clockgen which can generate phyclk.
+Example:
+ethernet0: dwmac@fe810000 {
+        device_type     = "network";
+        compatible      = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+        reg             = <0xfe810000 0x8000>, <0x8bc 0x4>;
+        reg-names       = "stmmaceth", "sti-ethconf";
+        interrupts      = <0 133 0>, <0 134 0>, <0 135 0>;
+        interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+        phy-mode        = "mii";
+        st,syscon       = <&syscfg_rear>;
+        snps,pbl        = <32>;
+        snps,mixed-burst;
+        resets          = <&softreset STIH416_ETH0_SOFTRESET>;
+        reset-names     = "stmmaceth";
+        pinctrl-0       = <&pinctrl_mii0>;
+        pinctrl-names   = "default";
+        clocks          = <&CLK_S_GMAC0_PHY>;
+        clock-names     = "stmmaceth";
+};
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
index 9d92d42140f2..80c1fb8bfbb8 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -10,8 +10,7 @@ Required properties:
 - interrupt-names: Should contain the interrupt names "macirq"
  "eth_wake_irq" if this interrupt is supported in the "interrupts"
  property
- phy-mode: String, operation mode of the PHY interface.
+- phy-mode: See ethernet.txt file in the same directory.
-  Supported values are: "mii", "rmii", "gmii", "rgmii".
 - snps,reset-gpio       gpio number for phy reset.
 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
 - snps,reset-delays-us  is triplet of delays
@@ -28,12 +27,14 @@ Required properties:
                                ignored if force_thresh_dma_mode is set.
 Optional properties:
- mac-address: 6 bytes, mac address
 - resets: Should contain a phandle to the STMMAC reset signal, if any
 - reset-names: Should contain the reset signal name "stmmaceth", if a
        reset phandle is given
- max-frame-size:       Maximum Transfer Unit (IEEE defined MTU), rather
+- max-frame-size: See ethernet.txt file in the same directory
-                        than the maximum frame size.
+- clocks: If present, the first clock should be the GMAC main clock,
+  further clocks may be specified in derived bindings.
+- clocks-names: One name for each entry in the clocks property, the
+  first one should be "stmmaceth".
 Examples:
@@ -46,4 +47,6 @@ Examples:
                mac-address = [000000000000]; /* Filled in by U-Boot */
                max-frame-size = <3800>;
                phy-mode = "gmii";
+                clocks = <&clock>;
+                clock-names = "stmmaceth">;
        };
diff --git a/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt b/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt
new file mode 100644
index 000000000000..189ae5cad8f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/wireless/ti,wl1251.txt
@@ -0,0 +1,39 @@
+* Texas Instruments wl1251 wireless lan controller
+The wl1251 chip can be connected via SPI or via SDIO. This
+document describes the binding for the SPI connected chip.
+Required properties:
+- compatible :        Should be "ti,wl1251"
+- reg :               Chip select address of device
+- spi-max-frequency : Maximum SPI clocking speed of device in Hz
+- interrupts :        Should contain interrupt line
+- interrupt-parent :  Should be the phandle for the interrupt controller
+                      that services interrupts for this device
+- vio-supply :        phandle to regulator providing VIO
+- ti,power-gpio :     GPIO connected to chip's PMEN pin
+Optional properties:
+- ti,wl1251-has-eeprom : boolean, the wl1251 has an eeprom connected, which
+                         provides configuration data (calibration, MAC, ...)
+- Please consult Documentation/devicetree/bindings/spi/spi-bus.txt
+  for optional SPI connection related properties,
+Examples:
+&spi1 {
+        wl1251@0 {
+                compatible = "ti,wl1251";
+                reg = <0>;
+                spi-max-frequency = <48000000>;
+                spi-cpol;
+                spi-cpha;
+                interrupt-parent = <&gpio2>;
+                interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
+                vio-supply = <&vio>;
+                ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
+        };
+};
diff --git a/Documentation/devicetree/bindings/panel/lg,ld070wx3-sl01.txt b/Documentation/devicetree/bindings/panel/lg,ld070wx3-sl01.txt
new file mode 100644
index 000000000000..5e649cb9aa1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/lg,ld070wx3-sl01.txt
@@ -0,0 +1,7 @@
+LG Corporation 7" WXGA TFT LCD panel
+Required properties:
+- compatible: should be "lg,ld070wx3-sl01"
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/lg,lh500wx1-sd03.txt b/Documentation/devicetree/bindings/panel/lg,lh500wx1-sd03.txt
new file mode 100644
index 000000000000..a04fd2b2e73d
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/lg,lh500wx1-sd03.txt
@@ -0,0 +1,7 @@
+LG Corporation 5" HD TFT LCD panel
+Required properties:
+- compatible: should be "lg,lh500wx1-sd03"
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/lg,lp129qe.txt b/Documentation/devicetree/bindings/panel/lg,lp129qe.txt
new file mode 100644
index 000000000000..9f262e0c5a2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/lg,lp129qe.txt
@@ -0,0 +1,7 @@
+LG 12.9" (2560x1700 pixels) TFT LCD panel
+Required properties:
+- compatible: should be "lg,lp129qe"
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/Documentation/devicetree/bindings/panel/samsung,ld9040.txt b/Documentation/devicetree/bindings/panel/samsung,ld9040.txt
new file mode 100644
index 000000000000..07c36c3f7b52
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,ld9040.txt
@@ -0,0 +1,66 @@
+Samsung LD9040 AMOLED LCD parallel RGB panel with SPI control bus
+Required properties:
+  - compatible: "samsung,ld9040"
+  - reg: address of the panel on SPI bus
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - display-timings: timings for the connected panel according to [1]
+The panel must obey rules for SPI slave device specified in document [2].
+Optional properties:
+  - power-on-delay: delay after turning regulators on [ms]
+  - reset-delay: delay after reset sequence [ms]
+  - panel-width-mm: physical panel width [mm]
+  - panel-height-mm: physical panel height [mm]
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [3]. This
+node should describe panel's video bus.
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/spi/spi-bus.txt
+[3]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Example:
+        lcd@0 {
+                compatible = "samsung,ld9040";
+                reg = <0>;
+                vdd3-supply = <&ldo7_reg>;
+                vci-supply = <&ldo17_reg>;
+                reset-gpios = <&gpy4 5 0>;
+                spi-max-frequency = <1200000>;
+                spi-cpol;
+                spi-cpha;
+                power-on-delay = <10>;
+                reset-delay = <10>;
+                panel-width-mm = <90>;
+                panel-height-mm = <154>;
+                display-timings {
+                        timing {
+                                clock-frequency = <23492370>;
+                                hactive = <480>;
+                                vactive = <800>;
+                                hback-porch = <16>;
+                                hfront-porch = <16>;
+                                vback-porch = <2>;
+                                vfront-porch = <28>;
+                                hsync-len = <2>;
+                                vsync-len = <1>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <0>;
+                                pixelclk-active = <0>;
+                        };
+                };
+                port {
+                        lcd_ep: endpoint {
+                                remote-endpoint = <&fimd_dpi_ep>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt b/Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt
new file mode 100644
index 000000000000..e7ee988e3156
--- /dev/null
+++ b/Documentation/devicetree/bindings/panel/samsung,s6e8aa0.txt
@@ -0,0 +1,56 @@
+Samsung S6E8AA0 AMOLED LCD 5.3 inch panel
+Required properties:
+  - compatible: "samsung,s6e8aa0"
+  - reg: the virtual channel number of a DSI peripheral
+  - vdd3-supply: core voltage supply
+  - vci-supply: voltage supply for analog circuits
+  - reset-gpios: a GPIO spec for the reset pin
+  - display-timings: timings for the connected panel as described by [1]
+Optional properties:
+  - power-on-delay: delay after turning regulators on [ms]
+  - reset-delay: delay after reset sequence [ms]
+  - init-delay: delay after initialization sequence [ms]
+  - panel-width-mm: physical panel width [mm]
+  - panel-height-mm: physical panel height [mm]
+  - flip-horizontal: boolean to flip image horizontally
+  - flip-vertical: boolean to flip image vertically
+The device node can contain one 'port' child node with one child
+'endpoint' node, according to the bindings defined in [2]. This
+node should describe panel's video bus.
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Example:
+        panel {
+                compatible = "samsung,s6e8aa0";
+                reg = <0>;
+                vdd3-supply = <&vcclcd_reg>;
+                vci-supply = <&vlcd_reg>;
+                reset-gpios = <&gpy4 5 0>;
+                power-on-delay= <50>;
+                reset-delay = <100>;
+                init-delay = <100>;
+                panel-width-mm = <58>;
+                panel-height-mm = <103>;
+                flip-horizontal;
+                flip-vertical;
+                display-timings {
+                        timing0: timing-0 {
+                                clock-frequency = <57153600>;
+                                hactive = <720>;
+                                vactive = <1280>;
+                                hfront-porch = <5>;
+                                hback-porch = <5>;
+                                hsync-len = <5>;
+                                vfront-porch = <13>;
+                                vback-porch = <1>;
+                                vsync-len = <2>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 24cee06915c9..c300391e8d3e 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -42,6 +42,10 @@ Required properties:
    - 0xc2000000: prefetchable memory region
  Please refer to the standard PCI bus binding document for a more detailed
  explanation.
+- #interrupt-cells: Size representation for interrupts (must be 1)
+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
+  Please refer to the standard PCI bus binding document for a more detailed
+  explanation.
 - clocks: Must contain an entry for each entry in clock-names.
  See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
@@ -86,6 +90,10 @@ SoC DTSI:
                              0 99 0x04>; /* MSI interrupt */
                interrupt-names = "intr", "msi";
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                bus-range = <0x00 0xff>;
                #address-cells = <3>;
                #size-cells = <2>;
diff --git a/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
new file mode 100644
index 000000000000..5f3a65a9dd88
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
@@ -0,0 +1,79 @@
+* APM X-Gene 15Gbps Multi-purpose PHY nodes
+PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
+PHY (pair of lanes) has its own node.
+Required properties:
+- compatible            : Shall be "apm,xgene-phy".
+- reg                   : PHY memory resource is the SDS PHY access resource.
+- #phy-cells            : Shall be 1 as it expects one argument for setting
+                          the mode of the PHY. Possible values are 0 (SATA),
+                          1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
+Optional properties:
+- status                : Shall be "ok" if enabled or "disabled" if disabled.
+                          Default is "ok".
+- clocks                : Reference to the clock entry.
+- apm,tx-eye-tuning     : Manual control to fine tune the capture of the serial
+                          bit lines from the automatic calibrated position.
+                          Two set of 3-tuple setting for each (up to 3)
+                          supported link speed on the host. Range from 0 to
+                          127 in unit of one bit period. Default is 10.
+- apm,tx-eye-direction  : Eye tuning manual control direction. 0 means sample
+                          data earlier than the nominal sampling point. 1 means
+                          sample data later than the nominal sampling point.
+                          Two set of 3-tuple setting for each (up to 3)
+                          supported link speed on the host. Default is 0.
+- apm,tx-boost-gain     : Frequency boost AC (LSB 3-bit) and DC (2-bit)
+                          gain control. Two set of 3-tuple setting for each
+                          (up to 3) supported link speed on the host. Range is
+                          between 0 to 31 in unit of dB. Default is 3.
+- apm,tx-amplitude      : Amplitude control. Two set of 3-tuple setting for
+                          each (up to 3) supported link speed on the host.
+                          Range is between 0 to 199500 in unit of uV.
+                          Default is 199500 uV.
+- apm,tx-pre-cursor1    : 1st pre-cursor emphasis taps control. Two set of
+                          3-tuple setting for each (up to 3) supported link
+                          speed on the host. Range is 0 to 273000 in unit of
+                          uV. Default is 0.
+- apm,tx-pre-cursor2    : 2st pre-cursor emphasis taps control. Two set of
+                          3-tuple setting for each (up to 3) supported link
+                          speed on the host. Range is 0 to 127400 in unit uV.
+                          Default is 0x0.
+- apm,tx-post-cursor    : Post-cursor emphasis taps control. Two set of
+                          3-tuple setting for Gen1, Gen2, and Gen3. Range is
+                          between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
+- apm,tx-speed          : Tx operating speed. One set of 3-tuple for each
+                          supported link speed on the host.
+                           0 = 1-2Gbps
+                           1 = 2-4Gbps (1st tuple default)
+                           2 = 4-8Gbps
+                           3 = 8-15Gbps (2nd tuple default)
+                           4 = 2.5-4Gbps
+                           5 = 4-5Gbps
+                           6 = 5-6Gbps
+                           7 = 6-16Gbps (3rd tuple default)
+NOTE: PHY override parameters are board specific setting.
+Example:
+                phy1: phy@1f21a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f21a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                        status = "disabled";
+                };
+                phy2: phy@1f22a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f22a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                        status = "ok";
+                };
+                phy3: phy@1f23a000 {
+                        compatible = "apm,xgene-phy";
+                        reg = <0x0 0x1f23a000 0x0 0x100>;
+                        #phy-cells = <1>;
+                        status = "ok";
+                };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa1671e..b422e38946d7 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,97 @@ Required properties:
 - compatible : should be "samsung,exynos5250-dp-video-phy";
 - reg : offset and length of the Display Port PHY register set;
 - #phy-cells : from the generic PHY bindings, must be 0;
+Samsung S5P/EXYNOS SoC series USB PHY
+-------------------------------------------------
+Required properties:
+- compatible : should be one of the listed compatibles:
+        - "samsung,exynos4210-usb2-phy"
+        - "samsung,exynos4x12-usb2-phy"
+        - "samsung,exynos5250-usb2-phy"
+- reg : a list of registers used by phy driver
+        - first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+        - the "phy" clock is required by the phy module, used as a gate
+        - the "ref" clock is used to get the rate of the clock provided to the
+          PHY module
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
+and Exynos 4212) it is as follows:
+  0 - USB device ("device"),
+  1 - USB host ("host"),
+  2 - HSIC0 ("hsic0"),
+  3 - HSIC1 ("hsic1"),
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+Example:
+For Exynos 4412 (compatible with Exynos 4212):
+usbphy: phy@125b0000 {
+        compatible = "samsung,exynos4x12-usb2-phy";
+        reg = <0x125b0000 0x100>;
+        clocks = <&clock 305>, <&clock 2>;
+        clock-names = "phy", "ref";
+        status = "okay";
+        #phy-cells = <1>;
+        samsung,sysreg-phandle = <&sys_reg>;
+        samsung,pmureg-phandle = <&pmu_reg>;
+};
+Then the PHY can be used in other nodes such as:
+phy-consumer@12340000 {
+        phys = <&usbphy 2>;
+        phy-names = "phy";
+};
+Refer to DT bindings documentation of particular PHY consumer devices for more
+information about required PHYs and the way of specification.
+Samsung SATA PHY Controller
+---------------------------
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+Required properties:
+- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : must be zero
+- clocks : must be exactly one entry
+- clock-names : must be "sata_phyctrl"
+- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
+- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
+Example:
+        sata_phy: sata-phy@12170000 {
+                compatible = "samsung,exynos5250-sata-phy";
+                reg = <0x12170000 0x1ff>;
+                clocks = <&clock 287>;
+                clock-names = "sata_phyctrl";
+                #phy-cells = <0>;
+                samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
+                samsung,syscon-phandle = <&pmu_syscon>;
+        };
+Device-Tree bindings for sataphy i2c client driver
+--------------------------------------------------
+Required properties:
+compatible: Should be "samsung,exynos-sataphy-i2c"
+- reg: I2C address of the sataphy i2c device.
+Example:
+        sata_phy_i2c:sata-phy@38 {
+                compatible = "samsung,exynos-sataphy-i2c";
+                reg = <0x38>;
+        };
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
new file mode 100644
index 000000000000..a82361b62015
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -0,0 +1,26 @@
+Allwinner sun4i USB PHY
+-----------------------
+Required properties:
+- compatible : should be one of "allwinner,sun4i-a10-usb-phy",
+  "allwinner,sun5i-a13-usb-phy" or "allwinner,sun7i-a20-usb-phy"
+- reg : a list of offset + length pairs
+- reg-names : "phy_ctrl", "pmu1" and for sun4i or sun7i "pmu2"
+- #phy-cells : from the generic phy bindings, must be 1
+- clocks : phandle + clock specifier for the phy clock
+- clock-names : "usb_phy"
+- resets : a list of phandle + reset specifier pairs
+- reset-names : "usb0_reset", "usb1_reset" and for sun4i or sun7i "usb2_reset"
+Example:
+        usbphy: phy@0x01c13400 {
+                #phy-cells = <1>;
+                compatible = "allwinner,sun4i-a10-usb-phy";
+                /* phy base regs, phy1 pmu reg, phy2 pmu reg */
+                reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+                reg-names = "phy_ctrl", "pmu1", "pmu2";
+                clocks = <&usb_clk 8>;
+                clock-names = "usb_phy";
+                resets = <&usb_clk 1>, <&usb_clk 2>;
+                reset-names = "usb1_reset", "usb2_reset";
+        };
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
new file mode 100644
index 000000000000..788fb0fa3762
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -0,0 +1,86 @@
+TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
+OMAP CONTROL PHY
+Required properties:
+ - compatible: Should be one of
+ "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
+ "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
+                        e.g. USB2_PHY on OMAP5.
+ "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
+                        e.g. USB3 PHY and SATA PHY on OMAP5.
+ "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
+                        DRA7 platform.
+ "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
+                        AM437 platform.
+ - reg : Address and length of the register set for the device. It contains
+   the address of "otghs_control" for control-phy-otghs or "power" register
+   for other types.
+ - reg-names: should be "otghs_control" control-phy-otghs and "power" for
+   other types.
+omap_control_usb: omap-control-usb@4a002300 {
+        compatible = "ti,control-phy-otghs";
+        reg = <0x4a00233c 0x4>;
+        reg-names = "otghs_control";
+};
+OMAP USB2 PHY
+Required properties:
+ - compatible: Should be "ti,omap-usb2"
+ - reg : Address and length of the register set for the device.
+ - #phy-cells: determine the number of cells that should be given in the
+   phandle while referencing this phy.
+Optional properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+   the PHY.
+This is usually a subnode of ocp2scp to which it is connected.
+usb2phy@4a0ad080 {
+        compatible = "ti,omap-usb2";
+        reg = <0x4a0ad080 0x58>;
+        ctrl-module = <&omap_control_usb>;
+        #phy-cells = <0>;
+};
+TI PIPE3 PHY
+Required properties:
+ - compatible: Should be "ti,phy-usb3" or "ti,phy-pipe3-sata".
+   "ti,omap-usb3" is deprecated.
+ - reg : Address and length of the register set for the device.
+ - reg-names: The names of the register addresses corresponding to the registers
+   filled in "reg".
+ - #phy-cells: determine the number of cells that should be given in the
+   phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+   clock-names.
+ - clock-names: should include:
+   * "wkupclk" - wakeup clock.
+   * "sysclk" - system clock.
+   * "refclk" - reference clock.
+Optional properties:
+ - ctrl-module : phandle of the control module used by PHY driver to power on
+   the PHY.
+This is usually a subnode of ocp2scp to which it is connected.
+usb3phy@4a084400 {
+        compatible = "ti,phy-usb3";
+        reg = <0x4a084400 0x80>,
+              <0x4a084800 0x64>,
+              <0x4a084c00 0x40>;
+        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+        ctrl-module = <&omap_control_usb>;
+        #phy-cells = <0>;
+        clocks = <&usb_phy_cm_clk32k>,
+                 <&sys_clkin>,
+                 <&usb_otg_ss_refclk960m>;
+        clock-names =   "wkupclk",
+                        "sysclk",
+                        "refclk";
+};
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
index 9e9e9ef9f852..c119debe6bab 100644
--- a/Documentation/devicetree/bindings/pinctrl/brcm,capri-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
@@ -1,4 +1,4 @@
-Broadcom Capri Pin Controller
+Broadcom BCM281xx Pin Controller
 This is a pin controller for the Broadcom BCM281xx SoC family, which includes
 BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
@@ -7,14 +7,14 @@ BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
 Required Properties:
- compatible:   Must be "brcm,capri-pinctrl".
+- compatible:   Must be "brcm,bcm11351-pinctrl"
 - reg:          Base address of the PAD Controller register block and the size
                of the block.
 For example, the following is the bare minimum node:
        pinctrl@35004800 {
-                compatible = "brcm,capri-pinctrl";
+                compatible = "brcm,bcm11351-pinctrl";
                reg = <0x35004800 0x430>;
        };
@@ -119,7 +119,7 @@ Optional Properties (for HDMI pins):
 Example:
 // pin controller node
 pinctrl@35004800 {
-        compatible = "brcm,capri-pinctrl";
+        compatible = "brcmbcm11351-pinctrl";
        reg = <0x35004800 0x430>;
        // pin configuration node
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
index 01ef408e205f..adda2a8d1d52 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -5,6 +5,7 @@ part and usage.
 Required properties:
 - compatible: "marvell,88f6710-pinctrl"
+- reg: register specifier of MPP registers
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
new file mode 100644
index 000000000000..7de0cda4a379
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
@@ -0,0 +1,82 @@
+* Marvell Armada 375 SoC pinctrl driver for mpp
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+Required properties:
+- compatible: "marvell,88f6720-pinctrl"
+- reg: register specifier of MPP registers
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+name          pins     functions
+================================================================================
+mpp0          0        gpio, dev(ad2), spi0(cs1), spi1(cs1)
+mpp1          1        gpio, dev(ad3), spi0(mosi), spi1(mosi)
+mpp2          2        gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
+mpp3          3        gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
+mpp4          4        gpio, dev(ad6), spi0(miso), spi1(miso)
+mpp5          5        gpio, dev(ad7), spi0(cs2), spi1(cs2)
+mpp6          6        gpio, dev(ad0), led(p1), audio(rclk)
+mpp7          7        gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
+mpp8          8        gpio, dev (bootcs), spi0(cs0), spi1(cs0)
+mpp9          9        gpio, nf(wen), spi0(sck), spi1(sck)
+mpp10        10        gpio, nf(ren), dram(vttctrl), led(c1)
+mpp11        11        gpio, dev(a0), led(c2), audio(sdo)
+mpp12        12        gpio, dev(a1), audio(bclk)
+mpp13        13        gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
+mpp14        14        gpio, i2c0(sda), uart1(txd)
+mpp15        15        gpio, i2c0(sck), uart1(rxd)
+mpp16        16        gpio, uart0(txd)
+mpp17        17        gpio, uart0(rxd)
+mpp18        18        gpio, tdm(intn)
+mpp19        19        gpio, tdm(rstn)
+mpp20        20        gpio, tdm(pclk)
+mpp21        21        gpio, tdm(fsync)
+mpp22        22        gpio, tdm(drx)
+mpp23        23        gpio, tdm(dtx)
+mpp24        24        gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
+mpp25        25        gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
+mpp26        26        gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
+mpp27        27        gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
+mpp28        28        gpio, led(p3), ge1(txctl), sd(clk)
+mpp29        29        gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
+mpp30        30        gpio, ge1(txd0), spi1(cs0)
+mpp31        31        gpio, ge1(txd1), spi1(mosi)
+mpp32        32        gpio, ge1(txd2), spi1(sck), ptp(triggen)
+mpp33        33        gpio, ge1(txd3), spi1(miso)
+mpp34        34        gpio, ge1(txclkout), spi1(sck)
+mpp35        35        gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
+mpp36        36        gpio, pcie0(clkreq)
+mpp37        37        gpio, pcie0(clkreq), tdm(intn), ge(mdc)
+mpp38        38        gpio, pcie1(clkreq), ge(mdio)
+mpp39        39        gpio, ref(clkout)
+mpp40        40        gpio, uart1(txd)
+mpp41        41        gpio, uart1(rxd)
+mpp42        42        gpio, spi1(cs2), led(c0)
+mpp43        43        gpio, sata0(prsnt), dram(vttctrl)
+mpp44        44        gpio, sata0(prsnt)
+mpp45        45        gpio, spi0(cs2), pcie0(rstoutn)
+mpp46        46        gpio, led(p0), ge0(txd0), ge1(txd0)
+mpp47        47        gpio, led(p1), ge0(txd1), ge1(txd1)
+mpp48        48        gpio, led(p2), ge0(txd2), ge1(txd2)
+mpp49        49        gpio, led(p3), ge0(txd3), ge1(txd3)
+mpp50        50        gpio, led(c0), ge0(rxd0), ge1(rxd0)
+mpp51        51        gpio, led(c1), ge0(rxd1), ge1(rxd1)
+mpp52        52        gpio, led(c2), ge0(rxd2), ge1(rxd2)
+mpp53        53        gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
+mpp54        54        gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
+mpp55        55        gpio, ge0(rxclk), ge1(rxclk)
+mpp56        56        gpio, ge0(txclkout), ge1(txclkout)
+mpp57        57        gpio, ge0(txctl), ge1(txctl)
+mpp58        58        gpio, led(c0)
+mpp59        59        gpio, led(c1)
+mpp60        60        gpio, uart1(txd), led(c2)
+mpp61        61        gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
+mpp62        62        gpio, i2c1(sck), led(p1)
+mpp63        63        gpio, ptp(triggen), led(p2)
+mpp64        64        gpio, dram(vttctrl), led(p3)
+mpp65        65        gpio, sata1(prsnt)
+mpp66        66        gpio, ptp(eventreq), spi1(cs3)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
new file mode 100644
index 000000000000..b17c96849fc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
@@ -0,0 +1,80 @@
+* Marvell Armada 380/385 SoC pinctrl driver for mpp
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+Required properties:
+- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
+  "marvell,88f6828-pinctrl" depending on the specific variant of the
+  SoC being used.
+- reg: register specifier of MPP registers
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ua0(rxd)
+mpp1          1        gpio, ua0(txd)
+mpp2          2        gpio, i2c0(sck)
+mpp3          3        gpio, i2c0(sda)
+mpp4          4        gpio, ge(mdc), ua1(txd), ua0(rts)
+mpp5          5        gpio, ge(mdio), ua1(rxd), ua0(cts)
+mpp6          6        gpio, ge0(txclkout), ge0(crs), dev(cs3)
+mpp7          7        gpio, ge0(txd0), dev(ad9)
+mpp8          8        gpio, ge0(txd1), dev(ad10)
+mpp9          9        gpio, ge0(txd2), dev(ad11)
+mpp10         10       gpio, ge0(txd3), dev(ad12)
+mpp11         11       gpio, ge0(txctl), dev(ad13)
+mpp12         12       gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
+mpp13         13       gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
+mpp14         14       gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
+mpp15         15       gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
+mpp16         16       gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
+mpp17         17       gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
+mpp18         18       gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
+mpp19         19       gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
+mpp20         20       gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
+mpp21         21       gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
+mpp22         22       gpio, spi0(mosi), dev(ad0)
+mpp23         23       gpio, spi0(sck), dev(ad2)
+mpp24         24       gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
+mpp25         25       gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
+mpp26         26       gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
+mpp27         27       gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
+mpp28         28       gpio, ge1(txd0), sd0(clk), dev(ad5)
+mpp29         29       gpio, ge1(txd1), dev(ale0)
+mpp30         30       gpio, ge1(txd2), dev(oen)
+mpp31         31       gpio, ge1(txd3), dev(ale1)
+mpp32         32       gpio, ge1(txctl), dev(wen0)
+mpp33         33       gpio, m(decc_err), dev(ad3)
+mpp34         34       gpio, dev(ad1)
+mpp35         35       gpio, ref(clk_out1), dev(a1)
+mpp36         36       gpio, ptp(trig_gen), dev(a0)
+mpp37         37       gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
+mpp38         38       gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
+mpp39         39       gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
+mpp40         40       gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
+mpp41         41       gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
+mpp42         42       gpio, ua1(txd), ua0(rts), dev(ad7)
+mpp43         43       gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
+mpp44         44       gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
+mpp45         45       gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
+mpp46         46       gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
+mpp47         47       gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
+mpp48         48       gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
+mpp49         49       gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
+mpp50         50       gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
+mpp51         51       gpio, tdm2c(dtx), audio(sdo), m(decc_err)
+mpp52         52       gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
+mpp53         53       gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
+mpp54         54       gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
+mpp55         55       gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
+mpp56         56       gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
+mpp57         57       gpio, spi1(sck), sd0(clk)
+mpp58         58       gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
+mpp59         59       gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
+[1]: only available on 88F6820 and 88F6828
+[2]: only available on 88F6828
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index bfa0a2e5e0cb..373dbccd7ab0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
 Required properties:
 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
              "marvell,mv78460-pinctrl"
+- reg: register specifier of MPP registers
 This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index 50ec3512a292..cf52477cc7ee 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
 Required properties:
 - compatible: "marvell,dove-pinctrl"
 - clocks: (optional) phandle of pdma clock
+- reg: register specifiers of MPP, MPP4, and PMU MPP registers
 Available mpp pins/groups and functions:
 Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 95daf6335c37..730444a9a4de 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -8,6 +8,7 @@ Required properties:
              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
              "marvell,98dx4122-pinctrl"
+- reg: register specifier of MPP registers
 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
index 0a26c3aa4e6d..0c09f4eb2af0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -37,7 +37,7 @@ uart1: serial@12100 {
 pinctrl: pinctrl@d0200 {
        compatible = "marvell,dove-pinctrl";
-        reg = <0xd0200 0x20>;
+        reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
        pmx_uart1_sw: pmx-uart1-sw {
                marvell,pins = "mpp_uart1";
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index bc0dfdfdb148..66dcaa9efd74 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -63,6 +63,13 @@ Optional properties:
                /* input, enable bits, disable bits, mask */
                pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
+- pinctrl-single,low-power-mode : array of value that are used to configure
+  low power mode of this pin. For some silicons, the low power mode will
+  control the output of the pin when the pad including the pin enter low
+  power mode.
+                /* low power mode value, mask */
+                pinctrl-single,low-power-mode = <0x288 0x388>;
 - pinctrl-single,gpio-range : list of value that are used to configure a GPIO
  range. They're value of subnode phandle, pin base in pinctrl device, pin
  number in this range, GPIO function value of this GPIO range.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
index 05bf82a07dfd..4bd5be0e5e7d 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt
@@ -11,18 +11,68 @@ Pull Up (PU) are driven by the related PIO block.
 ST pinctrl driver controls PIO multiplexing block and also interacts with
 gpio driver to configure a pin.
-Required properties: (PIO multiplexing block)
+GPIO bank can have one of the two possible types of interrupt-wirings.
+First type is via irqmux, single interrupt is used by multiple gpio banks. This
+reduces number of overall interrupts numbers required. All these banks belong to
+a single pincontroller.
+                  _________
+                 |         |----> [gpio-bank (n)    ]
+                 |         |----> [gpio-bank (n + 1)]
+        [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
+                 |         |----> [gpio-bank (...  )]
+                 |_________|----> [gpio-bank (n + 7)]
+Second type has a dedicated interrupt per gpio bank.
+        [irqN]----> [gpio-bank (n)]
+Pin controller node:
+Required properties:
 - compatible    : should be "st,<SOC>-<pio-block>-pinctrl"
        like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
- gpio-controller : Indicates this device is a GPIO controller
+- st,syscfg             : Should be a phandle of the syscfg node.
- #gpio-cells     : Should be one. The first cell is the pin number.
 - st,retime-pin-mask    : Should be mask to specify which pins can be retimed.
        If the property is not present, it is assumed that all the pins in the
        bank are capable of retiming. Retiming is mainly used to improve the
        IO timing margins of external synchronous interfaces.
- st,bank-name          : Should be a name string for this bank as
+- ranges : defines mapping between pin controller node (parent) to gpio-bank
-                        specified in datasheet.
+  node (children).
- st,syscfg             : Should be a phandle of the syscfg node.
+Optional properties:
+- interrupts    : Interrupt number of the irqmux. If the interrupt is shared
+  with other gpio banks via irqmux.
+  a irqline and gpio banks.
+- reg           : irqmux memory resource. If irqmux is present.
+- reg-names     : irqmux resource should be named as "irqmux".
+GPIO controller/bank node.
+Required properties:
+- gpio-controller : Indicates this device is a GPIO controller
+- #gpio-cells     : Should be one. The first cell is the pin number.
+- st,bank-name    : Should be a name string for this bank as specified in
+  datasheet.
+Optional properties:
+- interrupts    : Interrupt number for this gpio bank. If there is a dedicated
+  interrupt wired up for this gpio bank.
+- interrupt-controller : Indicates this device is a interrupt controller. GPIO
+  bank can be an interrupt controller iff one of the interrupt type either via
+irqmux or a dedicated interrupt per bank is specified.
+- #interrupt-cells: the value of this property should be 2.
+     - First Cell: represents the external gpio interrupt number local to the
+       gpio interrupt space of the controller.
+     - Second Cell: flags to identify the type of the interrupt
+       - 1 = rising edge triggered
+       - 2 = falling edge triggered
+       - 3 = rising and falling edge triggered
+       - 4 = high level triggered
+       - 8 = low level triggered
+for related macros look in:
+include/dt-bindings/interrupt-controller/irq.h
 Example:
        pin-controller-sbc {
@@ -30,10 +80,17 @@ Example:
                #size-cells     = <1>;
                compatible      = "st,stih415-sbc-pinctrl";
                st,syscfg       = <&syscfg_sbc>;
+                reg             = <0xfe61f080 0x4>;
+                reg-names       = "irqmux";
+                interrupts      = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+                interrupts-names = "irqmux";
                ranges          = <0 0xfe610000 0x5000>;
                PIO0: gpio@fe610000 {
                        gpio-controller;
                        #gpio-cells     = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                        reg             = <0 0x100>;
                        st,bank-name    = "PIO0";
                };
@@ -105,6 +162,10 @@ pin-controller {
 sdhci0:sdhci@fe810000{
        ...
+        interrupt-parent = <&PIO3>;
+        #interrupt-cells = <2>;
+        interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
+        interrupts-names = "card-detect";
        pinctrl-names = "default";
        pinctrl-0       = <&pinctrl_mmc>;
 };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
index 4c352be5dd61..9fb89e3f61ea 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.txt
@@ -1,7 +1,7 @@
 Qualcomm MSM8974 TLMM block
 Required properties:
- compatible: "qcom,msm8x74-pinctrl"
+- compatible: "qcom,msm8974-pinctrl"
 - reg: Should be the base address and length of the TLMM block.
 - interrupts: Should be the parent IRQ of the TLMM block.
 - interrupt-controller: Marks the device node as an interrupt controller.
@@ -42,14 +42,14 @@ Non-empty subnodes must specify the 'pins' property.
 Note that not all properties are valid for all pins.
-Valid values for qcom,pins are:
+Valid values for pins are:
  gpio0-gpio145
    Supports mux, bias and drive-strength
  sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data
    Supports bias and drive-strength
-Valid values for qcom,function are:
+Valid values for function are:
  blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus
  (Note that this is not yet the complete list of functions)
@@ -73,18 +73,18 @@ Example:
                uart2_default: uart2_default {
                        mux {
-                                qcom,pins = "gpio4", "gpio5";
+                                pins = "gpio4", "gpio5";
-                                qcom,function = "blsp_uart2";
+                                function = "blsp_uart2";
                        };
                        tx {
-                                qcom,pins = "gpio4";
+                                pins = "gpio4";
                                drive-strength = <4>;
                                bias-disable;
                        };
                        rx {
-                                qcom,pins = "gpio5";
+                                pins = "gpio5";
                                drive-strength = <2>;
                                bias-pull-up;
                        };
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index 257677de3e6b..2b32783ba821 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -16,6 +16,7 @@ Required Properties:
  - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
  - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
  - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
+  - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
  - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
 - reg: Base address of the pin controller hardware module and length of
diff --git a/Documentation/devicetree/bindings/power/bq2415x.txt b/Documentation/devicetree/bindings/power/bq2415x.txt
new file mode 100644
index 000000000000..d0327f0b59ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/bq2415x.txt
@@ -0,0 +1,47 @@
+Binding for TI bq2415x Li-Ion Charger
+Required properties:
+- compatible: Should contain one of the following:
+ * "ti,bq24150"
+ * "ti,bq24150"
+ * "ti,bq24150a"
+ * "ti,bq24151"
+ * "ti,bq24151a"
+ * "ti,bq24152"
+ * "ti,bq24153"
+ * "ti,bq24153a"
+ * "ti,bq24155"
+ * "ti,bq24156"
+ * "ti,bq24156a"
+ * "ti,bq24158"
+- reg:                     integer, i2c address of the device.
+- ti,current-limit:        integer, initial maximum current charger can pull
+                           from power supply in mA.
+- ti,weak-battery-voltage: integer, weak battery voltage threshold in mV.
+                           The chip will use slow precharge if battery voltage
+                           is below this value.
+- ti,battery-regulation-voltage: integer, maximum charging voltage in mV.
+- ti,charge-current:       integer, maximum charging current in mA.
+- ti,termination-current:  integer, charge will be terminated when current in
+                           constant-voltage phase drops below this value (in mA).
+- ti,resistor-sense:       integer, value of sensing resistor in milliohm.
+Optional properties:
+- ti,usb-charger-detection: phandle to usb charger detection device.
+                            (required for auto mode)
+Example from Nokia N900:
+bq24150a {
+        compatible = "ti,bq24150a";
+        reg = <0x6b>;
+        ti,current-limit = <100>;
+        ti,weak-battery-voltage = <3400>;
+        ti,battery-regulation-voltage = <4200>;
+        ti,charge-current = <650>;
+        ti,termination-current = <100>;
+        ti,resistor-sense = <68>;
+        ti,usb-charger-detection = <&isp1704>;
+};
diff --git a/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt b/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt
index 0347d8350d94..af25e77c0e0c 100644
--- a/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt
+++ b/Documentation/devicetree/bindings/power_supply/qnap-poweroff.txt
@@ -6,8 +6,11 @@ Orion5x SoCs. Sending the character 'A', at 19200 baud, tells the
 microcontroller to turn the power off. This driver adds a handler to
 pm_power_off which is called to turn the power off.
+Synology NAS devices use a similar scheme, but a different baud rate,
+9600, and a different character, '1'.
 Required Properties:
- compatible: Should be "qnap,power-off"
+- compatible: Should be "qnap,power-off" or "synology,power-off"
 - reg: Address and length of the register set for UART1
 - clocks: tclk clock
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
new file mode 100644
index 000000000000..c41b2187eaa8
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
@@ -0,0 +1,23 @@
+Freescale L2 Cache Controller
+L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
+The cache bindings explained below are ePAPR compliant
+Required Properties:
+- compatible    : Should include "fsl,chip-l2-cache-controller" and "cache"
+                  where chip is the processor (bsc9132, npc8572 etc.)
+- reg           : Address and size of L2 cache controller registers
+- cache-size    : Size of the entire L2 cache
+- interrupts    : Error interrupt of L2 controller
+- cache-line-size : Size of L2 cache lines
+Example:
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,bsc9132-l2-cache-controller", "cache";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 1 0>;
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt
new file mode 100644
index 000000000000..f87856faf1ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/mem-ctrlr.txt
@@ -0,0 +1,27 @@
+Freescale DDR memory controller
+Properties:
+- compatible    : Should include "fsl,chip-memory-controller" where
+                  chip is the processor (bsc9132, mpc8572 etc.), or
+                  "fsl,qoriq-memory-controller".
+- reg           : Address and size of DDR controller registers
+- interrupts    : Error interrupt of DDR controller
+Example 1:
+        memory-controller@2000 {
+                compatible = "fsl,bsc9132-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 1 8>;
+        };
+Example 2:
+        ddr1: memory-controller@8000 {
+                compatible = "fsl,qoriq-memory-controller-v4.7",
+                                "fsl,qoriq-memory-controller";
+                reg = <0x8000 0x1000>;
+                interrupts = <16 2 1 23>;
+        };
diff --git a/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt
new file mode 100644
index 000000000000..a183db48f910
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/cirrus,clps711x-pwm.txt
@@ -0,0 +1,16 @@
+* Cirris Logic CLPS711X PWM controller
+Required properties:
+- compatible: Shall contain "cirrus,clps711x-pwm".
+- reg: Physical base address and length of the controller's registers.
+- clocks: phandle + clock specifier pair of the PWM reference clock.
+- #pwm-cells: Should be 1. The cell specifies the index of the channel.
+Example:
+        pwm: pwm@80000400 {
+                compatible = "cirrus,ep7312-pwm",
+                             "cirrus,clps711x-pwm";
+                reg = <0x80000400 0x4>;
+                clocks = <&clks 8>;
+                #pwm-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
new file mode 100644
index 000000000000..0bda229a6171
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
@@ -0,0 +1,35 @@
+Freescale FlexTimer Module (FTM) PWM controller
+Required properties:
+- compatible: Should be "fsl,vf610-ftm-pwm".
+- reg: Physical base address and length of the controller's registers
+- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of
+  the cells format.
+- clock-names: Should include the following module clock source entries:
+    "ftm_sys" (module clock, also can be used as counter clock),
+    "ftm_ext" (external counter clock),
+    "ftm_fix" (fixed counter clock),
+    "ftm_cnt_clk_en" (external and fixed counter clock enable/disable).
+- clocks: Must contain a phandle and clock specifier for each entry in
+  clock-names, please see clock/clock-bindings.txt for details of the property
+  values.
+- pinctrl-names: Must contain a "default" entry.
+- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
+  See pinctrl/pinctrl-bindings.txt for details of the property values.
+Example:
+pwm0: pwm@40038000 {
+                compatible = "fsl,vf610-ftm-pwm";
+                reg = <0x40038000 0x1000>;
+                #pwm-cells = <3>;
+                clock-names = "ftm_sys", "ftm_ext",
+                                "ftm_fix", "ftm_cnt_clk_en";
+                clocks = <&clks VF610_CLK_FTM0>,
+                        <&clks VF610_CLK_FTM0_EXT_SEL>,
+                        <&clks VF610_CLK_FTM0_FIX_SEL>,
+                        <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pwm0_1>;
+};
diff --git a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
index 63c659800c03..e5cac1e0ca8a 100644
--- a/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/gpio-regulator.txt
@@ -8,8 +8,12 @@ Required properties:
 Optional properties:
 - enable-gpio           : GPIO to use to enable/disable the regulator.
 - gpios                 : GPIO group used to control voltage.
+- gpios-states          : gpios pin's initial states array. 0: LOW, 1: HIGH.
+                          defualt is LOW if nothing is specified.
 - startup-delay-us      : Startup time in microseconds.
 - enable-active-high    : Polarity of GPIO is active high (default is low).
+- regulator-type        : Specifies what is being regulated, must be either
+                          "voltage" or "current", defaults to current.
 Any property defined as part of the core regulator binding defined in
 regulator.txt can also be used.
diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt
index fc989b2e8057..34ef5d16d0f1 100644
--- a/Documentation/devicetree/bindings/regulator/pfuze100.txt
+++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt
@@ -1,7 +1,7 @@
 PFUZE100 family of regulators
 Required properties:
- compatible: "fsl,pfuze100"
+- compatible: "fsl,pfuze100" or "fsl,pfuze200"
 - reg: I2C slave address
 Required child node:
@@ -10,11 +10,14 @@ Required child node:
  Documentation/devicetree/bindings/regulator/regulator.txt.
  The valid names for regulators are:
+  --PFUZE100
  sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
+  --PFUZE200
+  sw1ab,sw2,sw3a,sw3b,swbst,vsnvs,vrefddr,vgen1~vgen6
 Each regulator is defined using the standard binding for regulators.
-Example:
+Example 1: PFUZE100
        pmic: pfuze100@08 {
                compatible = "fsl,pfuze100";
@@ -113,3 +116,92 @@ Example:
                        };
                };
        };
+Example 2: PFUZE200
+        pmic: pfuze200@08 {
+                compatible = "fsl,pfuze200";
+                reg = <0x08>;
+                regulators {
+                        sw1a_reg: sw1ab {
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                                regulator-ramp-delay = <6250>;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3a_reg: sw3a {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3b_reg: sw3b {
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        swbst_reg: swbst {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        snvs_reg: vsnvs {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vgen4_reg: vgen4 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen5_reg: vgen5 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vgen6_reg: vgen6 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt b/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt
index fc6b38f035bd..d290988ed975 100644
--- a/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/s5m8767-regulator.txt
@@ -69,13 +69,16 @@ sub-node should be of the format as listed below.
                };
        };
 The above regulator entries are defined in regulator bindings documentation
-except op_mode description.
+except these properties:
        - op_mode: describes the different operating modes of the LDO's with
                power mode change in SOC. The different possible values are,
                0 - always off mode
                1 - on in normal mode
                2 - low power mode
                3 - suspend mode
+        - s5m8767,pmic-ext-control-gpios: (optional) GPIO specifier for one
+                GPIO controlling this regulator (enable/disable); This is
+                valid only for buck9.
 The following are the names of the regulators that the s5m8767 pmic block
 supports. Note: The 'n' in LDOn and BUCKn represents the LDO or BUCK number
@@ -148,5 +151,13 @@ Example:
                                regulator-always-on;
                                regulator-boot-on;
                        };
+                        vemmc_reg: BUCK9 {
+                                regulator-name = "VMEM_VDD_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                op_mode = <3>; /* Standby Mode */
+                                s5m8767,pmic-ext-control-gpios = <&gpk0 2 0>;
+                        };
                };
        };
diff --git a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
index 2e57a33e9029..c58db75f959e 100644
--- a/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/ti-abb-regulator.txt
@@ -4,10 +4,14 @@ Required Properties:
 - compatible: Should be one of:
  - "ti,abb-v1" for older SoCs like OMAP3
  - "ti,abb-v2" for newer SoCs like OMAP4, OMAP5
+  - "ti,abb-v3" for a generic definition where setup and control registers are
+     provided (example: DRA7)
 - reg: Address and length of the register set for the device. It contains
  the information of registers in the same order as described by reg-names
 - reg-names: Should contain the reg names
-  - "base-address"      - contains base address of ABB module
+  - "base-address"      - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
+  - "control-address"   - contains control register address of ABB module (ti,abb-v3)
+  - "setup-address"     - contains setup register address of ABB module (ti,abb-v3)
  - "int-address"       - contains address of interrupt register for ABB module
  (also see Optional properties)
 - #address-cell: should be 0
diff --git a/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
new file mode 100644
index 000000000000..3da0ebdba8d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
@@ -0,0 +1,133 @@
+*** Reserved memory regions ***
+Reserved memory is specified as a node under the /reserved-memory node.
+The operating system shall exclude reserved memory from normal usage
+one can create child nodes describing particular reserved (excluded from
+normal use) memory regions. Such memory regions are usually designed for
+the special usage by various device drivers.
+Parameters for each memory region can be encoded into the device tree
+with the following nodes:
+/reserved-memory node
+---------------------
+#address-cells, #size-cells (required) - standard definition
+    - Should use the same values as the root node
+ranges (required) - standard definition
+    - Should be empty
+/reserved-memory/ child nodes
+-----------------------------
+Each child of the reserved-memory node specifies one or more regions of
+reserved memory. Each child node may either use a 'reg' property to
+specify a specific range of reserved memory, or a 'size' property with
+optional constraints to request a dynamically allocated block of memory.
+Following the generic-names recommended practice, node names should
+reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). Unit
+address (@<address>) should be appended to the name if the node is a
+static allocation.
+Properties:
+Requires either a) or b) below.
+a) static allocation
+   reg (required) - standard definition
+b) dynamic allocation
+   size (required) - length based on parent's #size-cells
+                   - Size in bytes of memory to reserve.
+   alignment (optional) - length based on parent's #size-cells
+                        - Address boundary for alignment of allocation.
+   alloc-ranges (optional) - prop-encoded-array (address, length pairs).
+                           - Specifies regions of memory that are
+                             acceptable to allocate from.
+If both reg and size are present, then the reg property takes precedence
+and size is ignored.
+Additional properties:
+compatible (optional) - standard definition
+    - may contain the following strings:
+        - shared-dma-pool: This indicates a region of memory meant to be
+          used as a shared pool of DMA buffers for a set of devices. It can
+          be used by an operating system to instanciate the necessary pool
+          management subsystem if necessary.
+        - vendor specific string in the form <vendor>,[<device>-]<usage>
+no-map (optional) - empty property
+    - Indicates the operating system must not create a virtual mapping
+      of the region as part of its standard mapping of system memory,
+      nor permit speculative access to it under any circumstances other
+      than under the control of the device driver using the region.
+reusable (optional) - empty property
+    - The operating system can use the memory in this region with the
+      limitation that the device driver(s) owning the region need to be
+      able to reclaim it back. Typically that means that the operating
+      system can use that region to store volatile or cached data that
+      can be otherwise regenerated or migrated elsewhere.
+Linux implementation note:
+- If a "linux,cma-default" property is present, then Linux will use the
+  region for the default pool of the contiguous memory allocator.
+Device node references to reserved memory
+-----------------------------------------
+Regions in the /reserved-memory node may be referenced by other device
+nodes by adding a memory-region property to the device node.
+memory-region (optional) - phandle, specifier pairs to children of /reserved-memory
+Example
+-------
+This example defines 3 contiguous regions are defined for Linux kernel:
+one default of all device drivers (named linux,cma@72000000 and 64MiB in size),
+one dedicated to the framebuffer device (named framebuffer@78000000, 8MiB), and
+one for multimedia processing (named multimedia-memory@77000000, 64MiB).
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+        reserved-memory {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                /* global autoconfigured region for contiguous allocations */
+                linux,cma {
+                        compatible = "shared-dma-pool";
+                        reusable;
+                        size = <0x4000000>;
+                        alignment = <0x2000>;
+                        linux,cma-default;
+                };
+                display_reserved: framebuffer@78000000 {
+                        reg = <0x78000000 0x800000>;
+                };
+                multimedia_reserved: multimedia@77000000 {
+                        compatible = "acme,multimedia-memory";
+                        reg = <0x77000000 0x4000000>;
+                };
+        };
+        /* ... */
+        fb0: video@12300000 {
+                memory-region = <&display_reserved>;
+                /* ... */
+        };
+        scaler: scaler@12500000 {
+                memory-region = <&multimedia_reserved>;
+                /* ... */
+        };
+        codec: codec@12600000 {
+                memory-region = <&multimedia_reserved>;
+                /* ... */
+        };
+};
diff --git a/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/Documentation/devicetree/bindings/reset/sirf,rstc.txt
new file mode 100644
index 000000000000..0505de742d30
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/sirf,rstc.txt
@@ -0,0 +1,42 @@
+CSR SiRFSoC Reset Controller
+======================================
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+Required properties:
+- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
+- reg: should be register base and length as documented in the
+  datasheet
+- #reset-cells: 1, see below
+example:
+rstc: reset-controller@88010000 {
+        compatible = "sirf,prima2-rstc";
+        reg = <0x88010000 0x1000>;
+        #reset-cells = <1>;
+};
+Specifying reset lines connected to IP modules
+==============================================
+The reset controller(rstc) manages various reset sources. This module provides
+reset signals for most blocks in system. Those device nodes should specify the
+reset line on the rstc in their resets property, containing a phandle to the
+rstc device node and a RESET_INDEX specifying which module to reset, as described
+in reset.txt.
+For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
+For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
+rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
+example:
+vpp@90020000 {
+        compatible = "sirf,prima2-vpp";
+        reg = <0x90020000 0x10000>;
+        interrupts = <31>;
+        clocks = <&clks 35>;
+        resets = <&rstc 6>;
+};
diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
new file mode 100644
index 000000000000..5ab26b7e9d35
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
@@ -0,0 +1,47 @@
+STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller
+=============================================================================
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"powerdown" control bits found in the STi family SoC system configuration
+registers. These have been grouped together into a single reset controller
+device for convenience.
+The actual action taken when powerdown is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+Required properties:
+- compatible: Should be "st,<chip>-powerdown"
+        ex: "st,stih415-powerdown", "st,stih416-powerdown"
+- #reset-cells: 1, see below
+example:
+        powerdown: powerdown-controller {
+                #reset-cells = <1>;
+                compatible = "st,stih415-powerdown";
+        };
+Specifying powerdown control of devices
+=======================================
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the powerdown device node and an
+index specifying which channel to use, as described in reset.txt
+example:
+        usb1: usb@fe200000 {
+                resets  = <&powerdown STIH41X_USB1_POWERDOWN>;
+        };
+Macro definitions for the supported reset channels can be found in:
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
new file mode 100644
index 000000000000..a8d3d3c25ca2
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt
@@ -0,0 +1,46 @@
+STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller
+=============================================================================
+This binding describes a reset controller device that is used to enable and
+disable on-chip peripheral controllers such as USB and SATA, using
+"softreset" control bits found in the STi family SoC system configuration
+registers.
+The actual action taken when softreset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers and after an assert/deassert sequence the hardware's previous state
+may no longer be valid.
+Please refer to reset.txt in this directory for common reset
+controller binding usage.
+Required properties:
+- compatible: Should be "st,<chip>-softreset" example:
+        "st,stih415-softreset" or "st,stih416-softreset";
+- #reset-cells: 1, see below
+example:
+        softreset: softreset-controller {
+                #reset-cells = <1>;
+                compatible = "st,stih415-softreset";
+        };
+Specifying softreset control of devices
+=======================================
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the softreset device node and an
+index specifying which channel to use, as described in reset.txt
+example:
+        ethernet0{
+                resets                  = <&softreset STIH415_ETH0_SOFTRESET>;
+        };
+Macro definitions for the supported reset channels can be found in:
+include/dt-bindings/reset-controller/stih415-resets.h
+include/dt-bindings/reset-controller/stih416-resets.h
diff --git a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
index 7cb9dbf34878..6983aad376c3 100644
--- a/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
+++ b/Documentation/devicetree/bindings/rtc/sunxi-rtc.txt
@@ -3,7 +3,7 @@
 RTC controller for the Allwinner A10/A20
 Required properties:
- compatible : Should be "allwinner,sun4i-rtc" or "allwinner,sun7i-a20-rtc"
+- compatible : Should be "allwinner,sun4i-a10-rtc" or "allwinner,sun7i-a20-rtc"
 - reg: physical base address of the controller and length of memory mapped
  region.
 - interrupts: IRQ line for the RTC.
@@ -11,7 +11,7 @@ Required properties:
 Example:
 rtc: rtc@01c20d00 {
-        compatible = "allwinner,sun4i-rtc";
+        compatible = "allwinner,sun4i-a10-rtc";
        reg = <0x01c20d00 0x20>;
        interrupts = <24>;
 };
diff --git a/Documentation/devicetree/bindings/serial/atmel-usart.txt b/Documentation/devicetree/bindings/serial/atmel-usart.txt
index 9c5d19ac935c..17c1042b2df8 100644
--- a/Documentation/devicetree/bindings/serial/atmel-usart.txt
+++ b/Documentation/devicetree/bindings/serial/atmel-usart.txt
@@ -13,6 +13,8 @@ Required properties:
 Optional properties:
 - atmel,use-dma-rx: use of PDC or DMA for receiving data
 - atmel,use-dma-tx: use of PDC or DMA for transmitting data
+- rts-gpios: specify a GPIO for RTS line. It will use specified PIO instead of the peripheral
+  function pin for the USART RTS feature. If unsure, don't specify this property.
 - add dma bindings for dma transfer:
        - dmas: DMA specifier, consisting of a phandle to DMA controller node,
                memory peripheral interface and USART DMA channel ID, FIFO configuration.
@@ -33,6 +35,7 @@ Example:
                clock-names = "usart";
                atmel,use-dma-rx;
                atmel,use-dma-tx;
+                rts-gpios = <&pioD 15 0>;
        };
 - use DMA:
diff --git a/Documentation/devicetree/bindings/serial/efm32-uart.txt b/Documentation/devicetree/bindings/serial/efm32-uart.txt
index 8e080b893b49..1984bdfbd545 100644
--- a/Documentation/devicetree/bindings/serial/efm32-uart.txt
+++ b/Documentation/devicetree/bindings/serial/efm32-uart.txt
@@ -6,7 +6,7 @@ Required properties:
 - interrupts : Should contain uart interrupt
 Optional properties:
- location : Decides the location of the USART I/O pins.
+- efm32,location : Decides the location of the USART I/O pins.
  Allowed range : [0 .. 5]
  Default: 0
@@ -16,5 +16,5 @@ uart@0x4000c400 {
        compatible = "efm32,uart";
        reg = <0x4000c400 0x400>;
        interrupts = <15>;
-        location = <0>;
+        efm32,location = <0>;
 };
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
index 6fd1dd1638dd..a1d1205d8185 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.txt
@@ -4,11 +4,24 @@ Required properties:
 - compatible : Should be "fsl,<soc>-lpuart"
 - reg : Address and length of the register set for the device
 - interrupts : Should contain uart interrupt
+- clocks : phandle + clock specifier pairs, one for each entry in clock-names
+- clock-names : should contain: "ipg" - the uart clock
+Optional properties:
+- dmas: A list of two dma specifiers, one for each entry in dma-names.
+- dma-names: should contain "tx" and "rx".
+Note: Optional properties for DMA support. Write them both or both not.
 Example:
 uart0: serial@40027000 {
-               compatible = "fsl,vf610-lpuart";
+                compatible = "fsl,vf610-lpuart";
-               reg = <0x40027000 0x1000>;
+                reg = <0x40027000 0x1000>;
-               interrupts = <0 61 0x00>;
+                interrupts = <0 61 0x00>;
-       };
+                clocks = <&clks VF610_CLK_UART0>;
+                clock-names = "ipg";
+                dmas = <&edma0 0 2>,
+                        <&edma0 0 3>;
+                dma-names = "rx","tx";
+        };
diff --git a/Documentation/devicetree/bindings/serial/maxim,max310x.txt b/Documentation/devicetree/bindings/serial/maxim,max310x.txt
new file mode 100644
index 000000000000..83a919c241b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/maxim,max310x.txt
@@ -0,0 +1,36 @@
+* Maxim MAX310X advanced Universal Asynchronous Receiver-Transmitter (UART)
+Required properties:
+- compatible: Should be one of the following:
+  - "maxim,max3107" for Maxim MAX3107,
+  - "maxim,max3108" for Maxim MAX3108,
+  - "maxim,max3109" for Maxim MAX3109,
+  - "maxim,max14830" for Maxim MAX14830.
+- reg: SPI chip select number.
+- interrupt-parent: The phandle for the interrupt controller that
+  services interrupts for this IC.
+- interrupts: Specifies the interrupt source of the parent interrupt
+  controller. The format of the interrupt specifier depends on the
+  parent interrupt controller.
+- clocks: phandle to the IC source clock.
+- clock-names: Should be "xtal" if clock is an external crystal or
+  "osc" if an external clock source is used.
+Optional properties:
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be two. The first cell is the GPIO number and
+  the second cell is used to specify the GPIO polarity:
+    0 = active high,
+    1 = active low.
+Example:
+        max14830: max14830@0 {
+                compatible = "maxim,max14830";
+                reg = <0>;
+                clocks = <&clk20m>;
+                clock-names = "osc";
+                interrupt-parent = <&gpio3>;
+                interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index f372cf29068d..53e6c175db6c 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -37,7 +37,7 @@ Example:
        };
        scifa0: serial@e6c40000 {
-                compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
+                compatible = "renesas,scifa-r8a7790", "renesas,scifa";
                reg = <0 0xe6c40000 0 64>;
                interrupt-parent = <&gic>;
                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/sound/armada-370db-audio.txt b/Documentation/devicetree/bindings/sound/armada-370db-audio.txt
new file mode 100644
index 000000000000..bf984d238620
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/armada-370db-audio.txt
@@ -0,0 +1,27 @@
+Device Tree bindings for the Armada 370 DB audio
+================================================
+These Device Tree bindings are used to describe the audio complex
+found on the Armada 370 DB platform.
+Mandatory properties:
+ * compatible: must be "marvell,a370db-audio"
+ * marvell,audio-controller: a phandle that points to the audio
+   controller of the Armada 370 SoC.
+ * marvell,audio-codec: a set of three phandles that points to:
+    1/ the analog audio codec connected to the Armada 370 SoC
+    2/ the S/PDIF transceiver
+    3/ the S/PDIF receiver
+Example:
+        sound {
+              compatible = "marvell,a370db-audio";
+              marvell,audio-controller = <&audio_controller>;
+              marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>;
+              status = "okay";
+        };
diff --git a/Documentation/devicetree/bindings/sound/cs42xx8.txt b/Documentation/devicetree/bindings/sound/cs42xx8.txt
new file mode 100644
index 000000000000..f631fbca6284
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/cs42xx8.txt
@@ -0,0 +1,28 @@
+CS42448/CS42888 audio CODEC
+Required properties:
+  - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888"
+  - reg : the I2C address of the device for I2C
+  - clocks : a list of phandles + clock-specifiers, one for each entry in
+    clock-names
+  - clock-names : must contain "mclk"
+  - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device,
+    as covered in Documentation/devicetree/bindings/regulator/regulator.txt
+Example:
+codec: cs42888@48 {
+        compatible = "cirrus,cs42888";
+        reg = <0x48>;
+        clocks = <&codec_mclk 0>;
+        clock-names = "mclk";
+        VA-supply = <&reg_audio>;
+        VD-supply = <&reg_audio>;
+        VLS-supply = <&reg_audio>;
+        VLC-supply = <&reg_audio>;
+};
diff --git a/Documentation/devicetree/bindings/sound/da9055.txt b/Documentation/devicetree/bindings/sound/da9055.txt
new file mode 100644
index 000000000000..ed1b7cc6f249
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/da9055.txt
@@ -0,0 +1,22 @@
+* Dialog DA9055 Audio CODEC
+DA9055 provides Audio CODEC support (I2C only).
+The Audio CODEC device in DA9055 has it's own I2C address which is configurable,
+so the device is instantiated separately from the PMIC (MFD) device.
+For details on accompanying PMIC I2C device, see the following:
+Documentation/devicetree/bindings/mfd/da9055.txt
+Required properties:
+  - compatible: "dlg,da9055-codec"
+  - reg: Specifies the I2C slave address
+Example:
+        codec: da9055-codec@1a {
+                compatible = "dlg,da9055-codec";
+                reg = <0x1a>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
index 865178d5cdf3..963e100514c2 100644
--- a/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
+++ b/Documentation/devicetree/bindings/sound/davinci-evm-audio.txt
@@ -5,12 +5,19 @@ Required properties:
 - ti,model : The user-visible name of this sound complex.
 - ti,audio-codec : The phandle of the TLV320AIC3x audio codec
 - ti,mcasp-controller : The phandle of the McASP controller
- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec
 - ti,audio-routing : A list of the connections between audio components.
  Each entry is a pair of strings, the first being the connection's sink,
  the second being the connection's source. Valid names for sources and
  sinks are the codec's pins, and the jacks on the board:
+Optional properties:
+- ti,codec-clock-rate : The Codec Clock rate (in Hz) applied to the Codec.
+- clocks : Reference to the master clock
+- clock-names : The clock should be named "mclk"
+- Either codec-clock-rate or the codec-clock reference has to be defined. If
+  the both are defined the driver attempts to set referenced clock to the
+  defined rate and takes the rate from the clock reference.
  Board connectors:
  * Headphone Jack
diff --git a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt b/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt
new file mode 100644
index 000000000000..0d7985c864af
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt
@@ -0,0 +1,21 @@
+Audio complex for Eukrea boards with tlv320aic23 codec.
+Required properties:
+- compatible : "eukrea,asoc-tlv320"
+- eukrea,model : The user-visible name of this sound complex.
+- ssi-controller : The phandle of the SSI controller.
+- fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX).
+- fsl,mux-ext-port : The external port of the i.MX audio muxer.
+Note: The AUDMUX port numbering should start at 1, which is consistent with
+hardware manual.
+Example:
+        sound {
+                compatible = "eukrea,asoc-tlv320";
+                eukrea,model = "imx51-eukrea-tlv320aic23";
+                ssi-controller = <&ssi2>;
+                fsl,mux-int-port = <2>;
+                fsl,mux-ext-port = <3>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt
index d7b99fa637b5..aeb8c4a0b88d 100644
--- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
@@ -34,6 +34,10 @@ Required properties:
    that ESAI would work in the synchronous mode, which means all the settings
    for Receiving would be duplicated from Transmition related registers.
+  - big-endian : If this property is absent, the native endian mode will
+    be in use as default, or the big endian mode will be in use for all the
+    device registers.
 Example:
 esai: esai@02024000 {
@@ -46,5 +50,6 @@ esai: esai@02024000 {
        dma-names = "rx", "tx";
        fsl,fifo-depth = <128>;
        fsl,esai-synchronous;
+        big-endian;
        status = "disabled";
 };
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
index f2ae335670f5..3e9e82c8eab3 100644
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -29,6 +29,10 @@ Required properties:
                        can also be referred to TxClk_Source
                        bit of register SPDIF_STC.
+   - big-endian : If this property is absent, the native endian mode will
+   be in use as default, or the big endian mode will be in use for all the
+   device registers.
 Example:
 spdif: spdif@02004000 {
@@ -50,5 +54,6 @@ spdif: spdif@02004000 {
                "rxtx5", "rxtx6",
                "rxtx7";
+        big-endian;
        status = "okay";
 };
diff --git a/Documentation/devicetree/bindings/sound/mvebu-audio.txt b/Documentation/devicetree/bindings/sound/mvebu-audio.txt
index f0062c5871b4..cb8c07c81ce4 100644
--- a/Documentation/devicetree/bindings/sound/mvebu-audio.txt
+++ b/Documentation/devicetree/bindings/sound/mvebu-audio.txt
@@ -5,6 +5,7 @@ Required properties:
 - compatible:
  "marvell,kirkwood-audio" for Kirkwood platforms
  "marvell,dove-audio" for Dove platforms
+  "marvell,armada370-audio" for Armada 370 platforms
 - reg: physical base address of the controller and length of memory mapped
  region.
diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt
new file mode 100644
index 000000000000..faff75e64573
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/pcm512x.txt
@@ -0,0 +1,30 @@
+PCM512x audio CODECs
+These devices support both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : One of "ti,pcm5121" or "ti,pcm5122"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+  - AVDD-supply, DVDD-supply, and CPVDD-supply : power supplies for the
+    device, as covered in bindings/regulator/regulator.txt
+Optional properties:
+  - clocks : A clock specifier for the clock connected as SCLK.  If this
+    is absent the device will be configured to clock from BCLK.
+Example:
+        pcm5122: pcm5122@4c {
+                compatible = "ti,pcm5122";
+                reg = <0x4c>;
+                AVDD-supply = <&reg_3v3_analog>;
+                DVDD-supply = <&reg_1v8>;
+                CPVDD-supply = <&reg_3v3>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/renesas,rsnd.txt b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
new file mode 100644
index 000000000000..a44e9179faf5
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/renesas,rsnd.txt
@@ -0,0 +1,105 @@
+Renesas R-Car sound
+Required properties:
+- compatible                    : "renesas,rcar_sound-gen1" if generation1
+                                  "renesas,rcar_sound-gen2" if generation2
+- reg                           : Should contain the register physical address.
+                                  required register is
+                                   SRU/ADG/SSI      if generation1
+                                   SRU/ADG/SSIU/SSI if generation2
+- rcar_sound,ssi                : Should contain SSI feature.
+                                  The number of SSI subnode should be same as HW.
+                                  see below for detail.
+- rcar_sound,src                : Should contain SRC feature.
+                                  The number of SRC subnode should be same as HW.
+                                  see below for detail.
+- rcar_sound,dai                : DAI contents.
+                                  The number of DAI subnode should be same as HW.
+                                  see below for detail.
+SSI subnode properties:
+- interrupts                    : Should contain SSI interrupt for PIO transfer
+- shared-pin                    : if shared clock pin
+SRC subnode properties:
+no properties at this point
+DAI subnode properties:
+- playback                      : list of playback modules
+- capture                       : list of capture  modules
+Example:
+rcar_sound: rcar_sound@0xffd90000 {
+        #sound-dai-cells = <1>;
+        compatible = "renesas,rcar_sound-gen2";
+        reg =   <0 0xec500000 0 0x1000>, /* SCU */
+                <0 0xec5a0000 0 0x100>,  /* ADG */
+                <0 0xec540000 0 0x1000>, /* SSIU */
+                <0 0xec541000 0 0x1280>; /* SSI */
+        rcar_sound,src {
+                src0: src@0 { };
+                src1: src@1 { };
+                src2: src@2 { };
+                src3: src@3 { };
+                src4: src@4 { };
+                src5: src@5 { };
+                src6: src@6 { };
+                src7: src@7 { };
+                src8: src@8 { };
+                src9: src@9 { };
+        };
+        rcar_sound,ssi {
+                ssi0: ssi@0 {
+                        interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi1: ssi@1 {
+                        interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi2: ssi@2 {
+                        interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi3: ssi@3 {
+                        interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi4: ssi@4 {
+                        interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi5: ssi@5 {
+                        interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi6: ssi@6 {
+                        interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi7: ssi@7 {
+                        interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi8: ssi@8 {
+                        interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                ssi9: ssi@9 {
+                        interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>;
+                };
+        };
+        rcar_sound,dai {
+                dai0 {
+                        playback = <&ssi5 &src5>;
+                        capture  = <&ssi6>;
+                };
+                dai1 {
+                        playback = <&ssi3>;
+                };
+                dai2 {
+                        capture  = <&ssi4>;
+                };
+                dai3 {
+                        playback = <&ssi7>;
+                };
+                dai4 {
+                        capture  = <&ssi8>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/sound/simple-card.txt b/Documentation/devicetree/bindings/sound/simple-card.txt
index 19c84df5fffa..131aa2ad7f1a 100644
--- a/Documentation/devicetree/bindings/sound/simple-card.txt
+++ b/Documentation/devicetree/bindings/sound/simple-card.txt
@@ -8,16 +8,26 @@ Required properties:
 Optional properties:
+- simple-audio-card,name                : User specified audio sound card name, one string
+                                          property.
 - simple-audio-card,format              : CPU/CODEC common audio format.
                                          "i2s", "right_j", "left_j" , "dsp_a"
                                          "dsp_b", "ac97", "pdm", "msb", "lsb"
+- simple-audio-card,widgets             : Please refer to widgets.txt.
 - simple-audio-card,routing             : A list of the connections between audio components.
                                          Each entry is a pair of strings, the first being the
                                          connection's sink, the second being the connection's
                                          source.
+- dai-tdm-slot-num                      : Please refer to tdm-slot.txt.
+- dai-tdm-slot-width                    : Please refer to tdm-slot.txt.
 Required subnodes:
+- simple-audio-card,dai-link            : container for the CPU and CODEC sub-nodes
+                                          This container may be omitted when the
+                                          card has only one DAI link.
+                                          See the examples.
 - simple-audio-card,cpu                 : CPU   sub-node
 - simple-audio-card,codec               : CODEC sub-node
@@ -38,15 +48,29 @@ Optional CPU/CODEC subnodes properties:
                                          clock node (= common clock), or "system-clock-frequency"
                                          (if system doens't support common clock)
-Example:
+Note:
+ * For 'format', 'frame-master', 'bitclock-master', 'bitclock-inversion' and
+   'frame-inversion', the simple card will use the settings of CODEC for both
+   CPU and CODEC sides as we need to keep the settings identical for both ends
+   of the link.
+Example 1 - single DAI link:
 sound {
        compatible = "simple-audio-card";
+        simple-audio-card,name = "VF610-Tower-Sound-Card";
        simple-audio-card,format = "left_j";
+        simple-audio-card,widgets =
+                "Microphone", "Microphone Jack",
+                "Headphone", "Headphone Jack",
+                "Speaker", "External Speaker";
        simple-audio-card,routing =
-                "MIC_IN", "Mic Jack",
+                "MIC_IN", "Microphone Jack",
                "Headphone Jack", "HP_OUT",
-                "Ext Spk", "LINE_OUT";
+                "External Speaker", "LINE_OUT";
+        dai-tdm-slot-num = <2>;
+        dai-tdm-slot-width = <8>;
        simple-audio-card,cpu {
                sound-dai = <&sh_fsi2 0>;
@@ -75,3 +99,38 @@ sh_fsi2: sh_fsi2@ec230000 {
        interrupt-parent = <&gic>;
        interrupts = <0 146 0x4>;
 };
+Example 2 - many DAI links:
+sound {
+        compatible = "simple-audio-card";
+        simple-audio-card,name = "Cubox Audio";
+        simple-audio-card,format = "i2s";
+        simple-audio-card,dai-link@0 {          /* I2S - HDMI */
+                simple-audio-card,cpu {
+                        sound-dai = <&audio1 0>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&tda998x 0>;
+                };
+        };
+        simple-audio-card,dai-link@1 {          /* S/PDIF - HDMI */
+                simple-audio-card,cpu {
+                        sound-dai = <&audio1 1>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&tda998x 1>;
+                };
+        };
+        simple-audio-card,dai-link@2 {          /* S/PDIF - S/PDIF */
+                simple-audio-card,cpu {
+                        sound-dai = <&audio1 1>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&spdif_codec>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/sound/sirf-audio-codec.txt b/Documentation/devicetree/bindings/sound/sirf-audio-codec.txt
new file mode 100644
index 000000000000..062f5ec36f9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sirf-audio-codec.txt
@@ -0,0 +1,17 @@
+SiRF internal audio CODEC
+Required properties:
+  - compatible : "sirf,atlas6-audio-codec" or "sirf,prima2-audio-codec"
+  - reg : the register address of the device.
+  - clocks: the clock of SiRF internal audio codec
+Example:
+audiocodec: audiocodec@b0040000 {
+        compatible = "sirf,atlas6-audio-codec";
+        reg = <0xb0040000 0x10000>;
+        clocks = <&clks 27>;
+};
diff --git a/Documentation/devicetree/bindings/sound/sirf-audio-port.txt b/Documentation/devicetree/bindings/sound/sirf-audio-port.txt
new file mode 100644
index 000000000000..1f66de3c8f00
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sirf-audio-port.txt
@@ -0,0 +1,20 @@
+* SiRF SoC audio port
+Required properties:
+- compatible: "sirf,audio-port"
+- reg: Base address and size entries:
+- dmas: List of DMA controller phandle and DMA request line ordered pairs.
+- dma-names: Identifier string for each DMA request line in the dmas property.
+  These strings correspond 1:1 with the ordered pairs in dmas.
+  One of the DMA channels will be responsible for transmission (should be
+  named "tx") and one for reception (should be named "rx").
+Example:
+audioport: audioport@b0040000 {
+        compatible = "sirf,audio-port";
+        reg = <0xb0040000 0x10000>;
+        dmas = <&dmac1 3>, <&dmac1 8>;
+        dma-names = "rx", "tx";
+};
diff --git a/Documentation/devicetree/bindings/sound/sirf-audio.txt b/Documentation/devicetree/bindings/sound/sirf-audio.txt
new file mode 100644
index 000000000000..c88882ca3704
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/sirf-audio.txt
@@ -0,0 +1,41 @@
+* SiRF atlas6 and prima2 internal audio codec and port based audio setups
+Required properties:
+- compatible: "sirf,sirf-audio-card"
+- sirf,audio-platform: phandle for the platform node
+- sirf,audio-codec: phandle for the SiRF internal codec node
+Optional properties:
+- hp-pa-gpios: Need to be present if the board need control external
+  headphone amplifier.
+- spk-pa-gpios: Need to be present if the board need control external
+  speaker amplifier.
+- hp-switch-gpios: Need to be present if the board capable to detect jack
+  insertion, removal.
+Available audio endpoints for the audio-routing table:
+Board connectors:
+ * Headset Stereophone
+ * Ext Spk
+ * Line In
+ * Mic
+SiRF internal audio codec pins:
+ * HPOUTL
+ * HPOUTR
+ * SPKOUT
+ * Ext Mic
+ * Mic Bias
+Example:
+sound {
+                compatible = "sirf,sirf-audio-card";
+                sirf,audio-codec = <&audiocodec>;
+                sirf,audio-platform = <&audioport>;
+                hp-pa-gpios = <&gpio 44 0>;
+                spk-pa-gpios = <&gpio 46 0>;
+                hp-switch-gpios = <&gpio 45 0>;
+};
diff --git a/Documentation/devicetree/bindings/sound/tdm-slot.txt b/Documentation/devicetree/bindings/sound/tdm-slot.txt
new file mode 100644
index 000000000000..6a2c84247f91
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tdm-slot.txt
@@ -0,0 +1,20 @@
+TDM slot:
+This specifies audio DAI's TDM slot.
+TDM slot properties:
+dai-tdm-slot-num : Number of slots in use.
+dai-tdm-slot-width :  Width in bits for each slot.
+For instance:
+        dai-tdm-slot-num = <2>;
+        dai-tdm-slot-width = <8>;
+And for each spcified driver, there could be one .of_xlate_tdm_slot_mask()
+to specify a explicit mapping of the channels and the slots. If it's absent
+the default snd_soc_of_xlate_tdm_slot_mask() will be used to generating the
+tx and rx masks.
+For snd_soc_of_xlate_tdm_slot_mask(), the tx and rx masks will use a 1 bit
+for an active slot as default, and the default active bits are at the LSB of
+the masks.
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
new file mode 100644
index 000000000000..74c66dee3e14
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tlv320aic31xx.txt
@@ -0,0 +1,61 @@
+Texas Instruments - tlv320aic31xx Codec module
+The tlv320aic31xx serial control bus communicates through I2C protocols
+Required properties:
+- compatible - "string" - One of:
+    "ti,tlv320aic310x" - Generic TLV320AIC31xx with mono speaker amp
+    "ti,tlv320aic311x" - Generic TLV320AIC31xx with stereo speaker amp
+    "ti,tlv320aic3100" - TLV320AIC3100 (mono speaker amp, no MiniDSP)
+    "ti,tlv320aic3110" - TLV320AIC3110 (stereo speaker amp, no MiniDSP)
+    "ti,tlv320aic3120" - TLV320AIC3120 (mono speaker amp, MiniDSP)
+    "ti,tlv320aic3111" - TLV320AIC3111 (stereo speaker amp, MiniDSP)
+- reg - <int> -  I2C slave address
+Optional properties:
+- gpio-reset - gpio pin number used for codec reset
+- ai31xx-micbias-vg - MicBias Voltage setting
+        1 or MICBIAS_2_0V - MICBIAS output is powered to 2.0V
+        2 or MICBIAS_2_5V - MICBIAS output is powered to 2.5V
+        3 or MICBIAS_AVDD - MICBIAS output is connected to AVDD
+        If this node is not mentioned or if the value is unknown, then
+        micbias is set to 2.0V.
+- HPVDD-supply, SPRVDD-supply, SPLVDD-supply, AVDD-supply, IOVDD-supply,
+  DVDD-supply : power supplies for the device as covered in
+  Documentation/devicetree/bindings/regulator/regulator.txt
+CODEC output pins:
+  * HPL
+  * HPR
+  * SPL, devices with stereo speaker amp
+  * SPR, devices with stereo speaker amp
+  * SPK, devices with mono speaker amp
+  * MICBIAS
+CODEC input pins:
+  * MIC1LP
+  * MIC1RP
+  * MIC1LM
+The pins can be used in referring sound node's audio-routing property.
+Example:
+#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
+tlv320aic31xx: tlv320aic31xx@18 {
+        compatible = "ti,tlv320aic311x";
+        reg = <0x18>;
+        ai31xx-micbias-vg = <MICBIAS_OFF>;
+        HPVDD-supply = <&regulator>;
+        SPRVDD-supply = <&regulator>;
+        SPLVDD-supply = <&regulator>;
+        AVDD-supply = <&regulator>;
+        IOVDD-supply = <&regulator>;
+        DVDD-supply = <&regulator>;
+};
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt b/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt
new file mode 100644
index 000000000000..5e2741af27be
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tlv320aic32x4.txt
@@ -0,0 +1,30 @@
+Texas Instruments - tlv320aic32x4 Codec module
+The tlv320aic32x4 serial control bus communicates through I2C protocols
+Required properties:
+ - compatible: Should be "ti,tlv320aic32x4"
+ - reg: I2C slave address
+ - supply-*: Required supply regulators are:
+    "iov" - digital IO power supply
+    "ldoin" - LDO power supply
+    "dv" - Digital core power supply
+    "av" - Analog core power supply
+    If you supply ldoin, dv and av are optional. Otherwise they are required
+   See regulator/regulator.txt for more information about the detailed binding
+   format.
+Optional properties:
+ - reset-gpios: Reset-GPIO phandle with args as described in gpio/gpio.txt
+ - clocks/clock-names: Clock named 'mclk' for the master clock of the codec.
+   See clock/clock-bindings.txt for information about the detailed format.
+Example:
+codec: tlv320aic32x4@18 {
+        compatible = "ti,tlv320aic32x4";
+        reg = <0x18>;
+        clocks = <&clks 201>;
+        clock-names = "mclk";
+};
diff --git a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
index 9d8ea14db490..5e6040c2c2e9 100644
--- a/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
+++ b/Documentation/devicetree/bindings/sound/tlv320aic3x.txt
@@ -6,7 +6,6 @@ Required properties:
 - compatible - "string" - One of:
    "ti,tlv320aic3x" - Generic TLV320AIC3x device
-    "ti,tlv320aic32x4" - TLV320AIC32x4
    "ti,tlv320aic33" - TLV320AIC33
    "ti,tlv320aic3007" - TLV320AIC3007
    "ti,tlv320aic3106" - TLV320AIC3106
diff --git a/Documentation/devicetree/bindings/sound/widgets.txt b/Documentation/devicetree/bindings/sound/widgets.txt
new file mode 100644
index 000000000000..b6de5ba3b2de
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/widgets.txt
@@ -0,0 +1,20 @@
+Widgets:
+This mainly specifies audio off-codec DAPM widgets.
+Each entry is a pair of strings in DT:
+        "template-wname", "user-supplied-wname"
+The "template-wname" being the template widget name and currently includes:
+"Microphone", "Line", "Headphone" and "Speaker".
+The "user-supplied-wname" being the user specified widget name.
+For instance:
+        simple-audio-widgets =
+                "Microphone", "Microphone Jack",
+                "Line", "Line In Jack",
+                "Line", "Line Out Jack",
+                "Headphone", "Headphone Jack",
+                "Speaker", "Speaker External";
diff --git a/Documentation/devicetree/bindings/spi/efm32-spi.txt b/Documentation/devicetree/bindings/spi/efm32-spi.txt
index a590ca51be75..8f081c96a4fa 100644
--- a/Documentation/devicetree/bindings/spi/efm32-spi.txt
+++ b/Documentation/devicetree/bindings/spi/efm32-spi.txt
@@ -3,24 +3,24 @@
 Required properties:
 - #address-cells: see spi-bus.txt
 - #size-cells: see spi-bus.txt
- compatible: should be "efm32,spi"
+- compatible: should be "energymicro,efm32-spi"
 - reg: Offset and length of the register set for the controller
 - interrupts: pair specifying rx and tx irq
 - clocks: phandle to the spi clock
 - cs-gpios: see spi-bus.txt
- location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.
+- efm32,location: Value to write to the ROUTE register's LOCATION bitfield to configure the pinmux for the device, see datasheet for values.
 Example:
 spi1: spi@0x4000c400 { /* USART1 */
        #address-cells = <1>;
        #size-cells = <0>;
-        compatible = "efm32,spi";
+        compatible = "energymicro,efm32-spi";
        reg = <0x4000c400 0x400>;
        interrupts = <15 16>;
        clocks = <&cmu 20>;
        cs-gpios = <&gpio 51 1>; // D3
-        location = <1>;
+        efm32,location = <1>;
        status = "ok";
        ks8851@0 {
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
new file mode 100644
index 000000000000..b82a268f1bd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -0,0 +1,85 @@
+Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
+The QUP core is an AHB slave that provides a common data path (an output FIFO
+and an input FIFO) for serial peripheral interface (SPI) mini-core.
+SPI in master mode supports up to 50MHz, up to four chip selects, programmable
+data path from 4 bits to 32 bits and numerous protocol variants.
+Required properties:
+- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
+- reg:            Should contain base register location and length
+- interrupts:     Interrupt number used by this controller
+- clocks:         Should contain the core clock and the AHB clock.
+- clock-names:    Should be "core" for the core clock and "iface" for the
+                  AHB clock.
+- #address-cells: Number of cells required to define a chip select
+                  address on the SPI bus. Should be set to 1.
+- #size-cells:    Should be zero.
+Optional properties:
+- spi-max-frequency: Specifies maximum SPI clock frequency,
+                     Units - Hz. Definition as per
+                     Documentation/devicetree/bindings/spi/spi-bus.txt
+SPI slave nodes must be children of the SPI master node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
+Example:
+        spi_8: spi@f9964000 { /* BLSP2 QUP2 */
+                compatible = "qcom,spi-qup-v2";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0xf9964000 0x1000>;
+                interrupts = <0 102 0>;
+                spi-max-frequency = <19200000>;
+                clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
+                clock-names = "core", "iface";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi8_default>;
+                device@0 {
+                        compatible = "arm,pl022-dummy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0>; /* Chip select 0 */
+                        spi-max-frequency = <19200000>;
+                        spi-cpol;
+                };
+                device@1 {
+                        compatible = "arm,pl022-dummy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <1>; /* Chip select 1 */
+                        spi-max-frequency = <9600000>;
+                        spi-cpha;
+                };
+                device@2 {
+                        compatible = "arm,pl022-dummy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <2>; /* Chip select 2 */
+                        spi-max-frequency = <19200000>;
+                        spi-cpol;
+                        spi-cpha;
+                };
+                device@3 {
+                        compatible = "arm,pl022-dummy";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <3>; /* Chip select 3 */
+                        spi-max-frequency = <19200000>;
+                        spi-cpol;
+                        spi-cpha;
+                        spi-cs-high;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/spi/sh-hspi.txt b/Documentation/devicetree/bindings/spi/sh-hspi.txt
index 30b57b1c8a13..319bad4af875 100644
--- a/Documentation/devicetree/bindings/spi/sh-hspi.txt
+++ b/Documentation/devicetree/bindings/spi/sh-hspi.txt
@@ -1,7 +1,29 @@
 Renesas HSPI.
 Required properties:
- compatible :  "renesas,hspi"
+- compatible       : "renesas,hspi-<soctype>", "renesas,hspi" as fallback.
- reg : Offset and length of the register set for the device
+                     Examples with soctypes are:
- interrupts : interrupt line used by HSPI
+                       - "renesas,hspi-r8a7778" (R-Car M1)
+                       - "renesas,hspi-r8a7779" (R-Car H1)
+- reg              : Offset and length of the register set for the device
+- interrupt-parent : The phandle for the interrupt controller that
+                     services interrupts for this device
+- interrupts       : Interrupt specifier
+- #address-cells   : Must be <1>
+- #size-cells      : Must be <0>
+Pinctrl properties might be needed, too.  See
+Documentation/devicetree/bindings/pinctrl/renesas,*.
+Example:
+        hspi0: spi@fffc7000 {
+                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
+                reg = <0xfffc7000 0x18>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index e6222106ca36..f24baf3b6cc1 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -1,12 +1,40 @@
 Renesas MSIOF spi controller
 Required properties:
- compatible :  "renesas,sh-msiof" for SuperH or
+- compatible           : "renesas,msiof-<soctype>" for SoCs,
-                "renesas,sh-mobile-msiof" for SH Mobile series
+                         "renesas,sh-msiof" for SuperH, or
- reg : Offset and length of the register set for the device
+                         "renesas,sh-mobile-msiof" for SH Mobile series.
- interrupts : interrupt line used by MSIOF
+                         Examples with soctypes are:
+                         "renesas,msiof-r8a7790" (R-Car H2)
+                         "renesas,msiof-r8a7791" (R-Car M2)
+- reg                  : Offset and length of the register set for the device
+- interrupt-parent     : The phandle for the interrupt controller that
+                         services interrupts for this device
+- interrupts           : Interrupt specifier
+- #address-cells       : Must be <1>
+- #size-cells          : Must be <0>
 Optional properties:
- num-cs                : total number of chip-selects
+- clocks               : Must contain a reference to the functional clock.
- renesas,tx-fifo-size  : Overrides the default tx fifo size given in words
+- num-cs               : Total number of chip-selects (default is 1)
- renesas,rx-fifo-size  : Overrides the default rx fifo size given in words
+Optional properties, deprecated for soctype-specific bindings:
+- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
+                         (default is 64)
+- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
+                         (default is 64, or 256 on R-Car H2 and M2)
+Pinctrl properties might be needed, too.  See
+Documentation/devicetree/bindings/pinctrl/renesas,*.
+Example:
+        msiof0: spi@e6e20000 {
+                compatible = "renesas,msiof-r8a7791";
+                reg = <0 0xe6e20000 0 0x0064>;
+                interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index a1fb3035a42b..5376de40f10b 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -10,6 +10,7 @@ Required properties:
 - pinctrl-names: must contain a "default" entry.
 - spi-num-chipselects : the number of the chipselect signals.
 - bus-num : the slave chip chipselect signal number.
+- big-endian : if DSPI modudle is big endian, the bool will be set in node.
 Example:
 dspi0@4002c000 {
@@ -24,6 +25,7 @@ dspi0@4002c000 {
        bus-num = <0>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_dspi0_1>;
+        big-endian;
        status = "okay";
        sflash: at26df081a@0 {
diff --git a/Documentation/devicetree/bindings/spi/spi-rspi.txt b/Documentation/devicetree/bindings/spi/spi-rspi.txt
new file mode 100644
index 000000000000..d57d82a74054
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-rspi.txt
@@ -0,0 +1,61 @@
+Device tree configuration for Renesas RSPI/QSPI driver
+Required properties:
+- compatible       : For Renesas Serial Peripheral Interface on legacy SH:
+                     "renesas,rspi-<soctype>", "renesas,rspi" as fallback.
+                     For Renesas Serial Peripheral Interface on RZ/A1H:
+                     "renesas,rspi-<soctype>", "renesas,rspi-rz" as fallback.
+                     For Quad Serial Peripheral Interface on R-Car Gen2:
+                     "renesas,qspi-<soctype>", "renesas,qspi" as fallback.
+                     Examples with soctypes are:
+                        - "renesas,rspi-sh7757" (SH)
+                        - "renesas,rspi-r7s72100" (RZ/A1H)
+                        - "renesas,qspi-r8a7790" (R-Car H2)
+                        - "renesas,qspi-r8a7791" (R-Car M2)
+- reg              : Address start and address range size of the device
+- interrupts       : A list of interrupt-specifiers, one for each entry in
+                     interrupt-names.
+                     If interrupt-names is not present, an interrupt specifier
+                     for a single muxed interrupt.
+- interrupt-names  : A list of interrupt names. Should contain (if present):
+                       - "error" for SPEI,
+                       - "rx" for SPRI,
+                       - "tx" to SPTI,
+                       - "mux" for a single muxed interrupt.
+- interrupt-parent : The phandle for the interrupt controller that
+                     services interrupts for this device.
+- num-cs           : Number of chip selects. Some RSPI cores have more than 1.
+- #address-cells   : Must be <1>
+- #size-cells      : Must be <0>
+Optional properties:
+- clocks           : Must contain a reference to the functional clock.
+Pinctrl properties might be needed, too.  See
+Documentation/devicetree/bindings/pinctrl/renesas,*.
+Examples:
+        spi0: spi@e800c800 {
+                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
+                reg = <0xe800c800 0x24>;
+                interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 239 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 240 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "error", "rx", "tx";
+                interrupt-parent = <&gic>;
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+        spi: spi@e6b10000 {
+                compatible = "renesas,qspi-r8a7791", "renesas,qspi";
+                reg = <0 0xe6b10000 0 0x2c>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
+                num-cs = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/spi/spi-sun4i.txt b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
new file mode 100644
index 000000000000..de827f5a301e
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-sun4i.txt
@@ -0,0 +1,24 @@
+Allwinner A10 SPI controller
+Required properties:
+- compatible: Should be "allwinner,sun4-a10-spi".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks: phandle to the clocks feeding the SPI controller. Two are
+          needed:
+  - "ahb": the gated AHB parent clock
+  - "mod": the parent module clock
+- clock-names: Must contain the clock names described just above
+Example:
+spi1: spi@01c06000 {
+        compatible = "allwinner,sun4i-a10-spi";
+        reg = <0x01c06000 0x1000>;
+        interrupts = <11>;
+        clocks = <&ahb_gates 21>, <&spi1_clk>;
+        clock-names = "ahb", "mod";
+        status = "disabled";
+        #address-cells = <1>;
+        #size-cells = <0>;
+};
diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
new file mode 100644
index 000000000000..21de73db6a05
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -0,0 +1,24 @@
+Allwinner A31 SPI controller
+Required properties:
+- compatible: Should be "allwinner,sun6i-a31-spi".
+- reg: Should contain register location and length.
+- interrupts: Should contain interrupt.
+- clocks: phandle to the clocks feeding the SPI controller. Two are
+          needed:
+  - "ahb": the gated AHB parent clock
+  - "mod": the parent module clock
+- clock-names: Must contain the clock names described just above
+- resets: phandle to the reset controller asserting this device in
+          reset
+Example:
+spi1: spi@01c69000 {
+        compatible = "allwinner,sun6i-a31-spi";
+        reg = <0x01c69000 0x1000>;
+        interrupts = <0 66 4>;
+        clocks = <&ahb1_gates 21>, <&spi1_clk>;
+        clock-names = "ahb", "mod";
+        resets = <&ahb1_rst 21>;
+};
diff --git a/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
new file mode 100644
index 000000000000..b6ebe2bc7041
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-xtensa-xtfpga.txt
@@ -0,0 +1,9 @@
+Cadence Xtensa XTFPGA platform SPI controller.
+This simple SPI master controller is built into xtfpga bitstreams and is used
+to control daughterboard audio codec.
+Required properties:
+- compatible: should be "cdns,xtfpga-spi".
+- reg: physical base address of the controller and length of memory mapped
+  region.
diff --git a/Documentation/devicetree/bindings/spi/spi_atmel.txt b/Documentation/devicetree/bindings/spi/spi_atmel.txt
index 07e04cdc0c9e..4f8184d069cb 100644
--- a/Documentation/devicetree/bindings/spi/spi_atmel.txt
+++ b/Documentation/devicetree/bindings/spi/spi_atmel.txt
@@ -5,6 +5,9 @@ Required properties:
 - reg: Address and length of the register set for the device
 - interrupts: Should contain spi interrupt
 - cs-gpios: chipselects
+- clock-names: tuple listing input clock names.
+        Required elements: "spi_clk"
+- clocks: phandles to input clocks.
 Example:
@@ -14,6 +17,8 @@ spi1: spi@fffcc000 {
        interrupts = <13 4 5>;
        #address-cells = <1>;
        #size-cells = <0>;
+        clocks = <&spi1_clk>;
+        clock-names = "spi_clk";
        cs-gpios = <&pioB 3 0>;
        status = "okay";
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
new file mode 100644
index 000000000000..715d0998af8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
@@ -0,0 +1,61 @@
+Qualcomm SPMI Controller (PMIC Arbiter)
+The SPMI PMIC Arbiter is found on the Snapdragon 800 Series.  It is an SPMI
+controller with wrapping arbitration logic to allow for multiple on-chip
+devices to control a single SPMI master.
+The PMIC Arbiter can also act as an interrupt controller, providing interrupts
+to slave devices.
+See spmi.txt for the generic SPMI controller binding requirements for child
+nodes.
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+generic interrupt controller binding documentation.
+Required properties:
+- compatible : should be "qcom,spmi-pmic-arb".
+- reg-names  : must contain:
+     "core" - core registers
+     "intr" - interrupt controller registers
+     "cnfg" - configuration registers
+- reg : address + size pairs describing the PMIC arb register sets; order must
+        correspond with the order of entries in reg-names
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+- qcom,ee : indicates the active Execution Environment identifier (0-5)
+- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
+- interrupts : interrupt list for the PMIC Arb controller, must contain a
+               single interrupt entry for the peripheral interrupt
+- interrupt-names : corresponding interrupt names for the interrupts
+                    listed in the 'interrupts' property, must contain:
+     "periph_irq" - summary interrupt for PMIC peripherals
+- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
+- #interrupt-cells :  must be set to 4. Interrupts are specified as a 4-tuple:
+    cell 1: slave ID for the requested interrupt (0-15)
+    cell 2: peripheral ID for requested interrupt (0-255)
+    cell 3: the requested peripheral interrupt (0-7)
+    cell 4: interrupt flags indicating level-sense information, as defined in
+            dt-bindings/interrupt-controller/irq.h
+Example:
+        spmi {
+                compatible = "qcom,spmi-pmic-arb";
+                reg-names = "core", "intr", "cnfg";
+                reg = <0xfc4cf000 0x1000>,
+                      <0xfc4cb000 0x1000>,
+                      <0xfc4ca000 0x1000>;
+                interrupt-names = "periph_irq";
+                interrupts = <0 190 0>;
+                qcom,ee = <0>;
+                qcom,channel = <0>;
+                #address-cells = <2>;
+                #size-cells = <0>;
+                interrupt-controller;
+                #interrupt-cells = <4>;
+        };
diff --git a/Documentation/devicetree/bindings/spmi/spmi.txt b/Documentation/devicetree/bindings/spmi/spmi.txt
new file mode 100644
index 000000000000..462a42fb3a1e
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/spmi.txt
@@ -0,0 +1,41 @@
+System Power Management Interface (SPMI) Controller
+This document defines a generic set of bindings for use by SPMI controllers.  A
+controller is modelled in device tree as a node with zero or more child nodes,
+each representing a unique slave on the bus.
+Required properties:
+- #address-cells : must be set to 2
+- #size-cells : must be set to 0
+Child nodes:
+An SPMI controller node can contain zero or more child nodes representing slave
+devices on the bus.  Child 'reg' properties are specified as an address, type
+pair.  The address must be in the range 0-15 (4 bits).  The type must be one of
+SPMI_USID (0) or SPMI_GSID (1) for Unique Slave ID or Group Slave ID respectively.
+These are the identifiers "statically assigned by the system integrator", as
+per the SPMI spec.
+Each child node must have one and only one 'reg' entry of type SPMI_USID.
+#include <dt-bindings/spmi/spmi.h>
+        spmi@.. {
+                compatible = "...";
+                reg = <...>;
+                #address-cells = <2>;
+                #size-cells <0>;
+                child@0 {
+                        compatible = "...";
+                        reg = <0 SPMI_USID>;
+                };
+                child@7 {
+                        compatible = "...";
+                        reg = <7 SPMI_USID
+                               3 SPMI_GSID>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
index b876d4925a57..3be5ce7a9654 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
@@ -1,3 +1,22 @@
+Freescale i.MX DRM master device
+================================
+The freescale i.MX DRM master device is a virtual device needed to list all
+IPU or other display interface nodes that comprise the graphics subsystem.
+Required properties:
+- compatible: Should be "fsl,imx-display-subsystem"
+- ports: Should contain a list of phandles pointing to display interface ports
+  of IPU devices
+example:
+display-subsystem {
+        compatible = "fsl,display-subsystem";
+        ports = <&ipu_di0>;
+};
 Freescale i.MX IPUv3
 ====================
@@ -7,18 +26,31 @@ Required properties:
  datasheet
 - interrupts: Should contain sync interrupt and error interrupt,
  in this order.
- #crtc-cells: 1, See below
 - resets: phandle pointing to the system reset controller and
          reset line index, see reset/fsl,imx-src.txt for details
+Optional properties:
+- port@[0-3]: Port nodes with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+  Ports 0 and 1 should correspond to CSI0 and CSI1,
+  ports 2 and 3 should correspond to DI0 and DI1, respectively.
 example:
 ipu: ipu@18000000 {
-        #crtc-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
        compatible = "fsl,imx53-ipu";
        reg = <0x18000000 0x080000000>;
        interrupts = <11 10>;
        resets = <&src 2>;
+        ipu_di0: port@2 {
+                reg = <2>;
+                ipu_di0_disp0: endpoint {
+                        remote-endpoint = <&display_in>;
+                };
+        };
 };
 Parallel display support
@@ -26,19 +58,25 @@ Parallel display support
 Required properties:
 - compatible: Should be "fsl,imx-parallel-display"
- crtc: the crtc this display is connected to, see below
 Optional properties:
 - interface_pix_fmt: How this display is connected to the
-  crtc. Currently supported types: "rgb24", "rgb565", "bgr666"
+  display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
 - edid: verbatim EDID data block describing attached display.
 - ddc: phandle describing the i2c bus handling the display data
  channel
+- port: A port node with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
 example:
 display@di0 {
        compatible = "fsl,imx-parallel-display";
        edid = [edid-data];
-        crtc = <&ipu 0>;
        interface-pix-fmt = "rgb24";
+        port {
+                display_in: endpoint {
+                        remote-endpoint = <&ipu_di0_disp0>;
+                };
+        };
 };
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt b/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt
new file mode 100644
index 000000000000..1b756cf9afb0
--- /dev/null
+++ b/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt
@@ -0,0 +1,58 @@
+Device-Tree bindings for HDMI Transmitter
+HDMI Transmitter
+================
+The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with accompanying PHY IP.
+Required properties:
+ - #address-cells : should be <1>
+ - #size-cells : should be <0>
+ - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
+ - gpr : should be <&gpr>.
+   The phandle points to the iomuxc-gpr region containing the HDMI
+   multiplexer control register.
+ - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
+   in Documentation/devicetree/bindings/clock/clock-bindings.txt and
+   Documentation/devicetree/bindings/clock/imx6q-clock.txt.
+ - port@[0-4]: Up to four port nodes with endpoint definitions as defined in
+   Documentation/devicetree/bindings/media/video-interfaces.txt,
+   corresponding to the four inputs to the HDMI multiplexer.
+Optional properties:
+ - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
+example:
+        gpr: iomuxc-gpr@020e0000 {
+                /* ... */
+        };
+        hdmi: hdmi@0120000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,imx6q-hdmi";
+                reg = <0x00120000 0x9000>;
+                interrupts = <0 115 0x04>;
+                gpr = <&gpr>;
+                clocks = <&clks 123>, <&clks 124>;
+                clock-names = "iahb", "isfr";
+                ddc-i2c-bus = <&i2c2>;
+                port@0 {
+                        reg = <0>;
+                        hdmi_mux_0: endpoint {
+                                remote-endpoint = <&ipu1_di0_hdmi>;
+                        };
+                };
+                port@1 {
+                        reg = <1>;
+                        hdmi_mux_1: endpoint {
+                                remote-endpoint = <&ipu1_di1_hdmi>;
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
index ed9377811ee2..578a1fca366e 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
@@ -50,12 +50,14 @@ have a look at Documentation/devicetree/bindings/video/display-timing.txt.
 Required properties:
 - reg : should be <0> or <1>
- - crtcs : a list of phandles with index pointing to the IPU display interfaces
-           that can be used as video source for this channel.
 - fsl,data-mapping : should be "spwg" or "jeida"
                      This describes how the color bits are laid out in the
                      serialized LVDS signal.
 - fsl,data-width : should be <18> or <24>
+ - port: A port node with endpoint definitions as defined in
+   Documentation/devicetree/bindings/media/video-interfaces.txt.
+   On i.MX6, there should be four ports (port@[0-3]) that correspond
+   to the four LVDS multiplexer inputs.
 example:
@@ -77,23 +79,33 @@ ldb: ldb@53fa8008 {
        lvds-channel@0 {
                reg = <0>;
-                crtcs = <&ipu 0>;
                fsl,data-mapping = "spwg";
                fsl,data-width = <24>;
                display-timings {
                        /* ... */
                };
+                port {
+                        lvds0_in: endpoint {
+                                remote-endpoint = <&ipu_di0_lvds0>;
+                        };
+                };
        };
        lvds-channel@1 {
                reg = <1>;
-                crtcs = <&ipu 1>;
                fsl,data-mapping = "spwg";
                fsl,data-width = <24>;
                display-timings {
                        /* ... */
                };
+                port {
+                        lvds1_in: endpoint {
+                                remote-endpoint = <&ipu_di1_lvds1>;
+                        };
+                };
        };
 };
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
index 48aeb7884ed3..5c2e23574ca0 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
@@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller
 Required properties:
- compatible : should be "allwinner,sun4i-timer"
+- compatible : should be "allwinner,sun4i-a10-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The interrupt of the first timer
 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
@@ -10,7 +10,7 @@ Required properties:
 Example:
 timer {
-        compatible = "allwinner,sun4i-timer";
+        compatible = "allwinner,sun4i-a10-timer";
        reg = <0x01c20c00 0x400>;
        interrupts = <22>;
        clocks = <&osc>;
diff --git a/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
new file mode 100644
index 000000000000..5fbe361252b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ti,keystone-timer.txt
@@ -0,0 +1,29 @@
+* Device tree bindings for Texas instruments Keystone timer
+This document provides bindings for the 64-bit timer in the KeyStone
+architecture devices. The timer can be configured as a general-purpose 64-bit
+timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
+timers, each half can operate in conjunction (chain mode) or independently
+(unchained mode) of each other.
+It is global timer is a free running up-counter and can generate interrupt
+when the counter reaches preset counter values.
+Documentation:
+http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
+Required properties:
+- compatible : should be "ti,keystone-timer".
+- reg : specifies base physical address and count of the registers.
+- interrupts : interrupt generated by the timer.
+- clocks : the clock feeding the timer clock.
+Example:
+timer@22f0000 {
+        compatible = "ti,keystone-timer";
+        reg = <0x022f0000 0x80>;
+        interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
+        clocks = <&clktimer15>;
+};
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 55f51af08bc7..bc2222ca3f2a 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -57,8 +57,8 @@ Required properties:
 - ep childnode: To specify the number of endpoints and their properties.
 Optional properties:
- - atmel,vbus-gpio: If present, specifies a gpio that needs to be
+ - atmel,vbus-gpio: If present, specifies a gpio that allows to detect whether
-   activated for the bus to be powered.
+   vbus is present (USB is connected).
 Required child node properties:
 - name: Name of the endpoint.
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
index b4b5b7906c88..a6a32cb7f777 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
@@ -18,6 +18,7 @@ Optional properties:
 - vbus-supply: regulator for vbus
 - disable-over-current: disable over current detect
 - external-vbus-divider: enables off-chip resistor divider for Vbus
+- maximum-speed: limit the maximum connection speed to "full-speed".
 Examples:
 usb@02184000 { /* USB OTG */
@@ -28,4 +29,5 @@ usb@02184000 { /* USB OTG */
        fsl,usbmisc = <&usbmisc 0>;
        disable-over-current;
        external-vbus-divider;
+        maximum-speed = "full-speed";
 };
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt
new file mode 100644
index 000000000000..abbcb2aea38c
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-zevio.txt
@@ -0,0 +1,17 @@
+* LSI Zevio USB OTG Controller
+Required properties:
+- compatible: Should be "lsi,zevio-usb"
+- reg: Should contain registers location and length
+- interrupts: Should contain controller interrupt
+Optional properties:
+- vbus-supply: regulator for vbus
+Examples:
+                usb0: usb@b0000000 {
+                        reg = <0xb0000000 0x1000>;
+                        compatible = "lsi,zevio-usb";
+                        interrupts = <8>;
+                        vbus-supply = <&vbus_reg>;
+                };
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index e807635f9e1c..471366d6a129 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -6,11 +6,13 @@ Required properties:
 - compatible: must be "snps,dwc3"
 - reg : Address and length of the register set for the device
 - interrupts: Interrupts used by the dwc3 controller.
+Optional properties:
 - usb-phy : array of phandle for the PHY device.  The first element
   in the array is expected to be a handle to the USB2/HS PHY and
   the second element is expected to be a handle to the USB3/SS PHY
+ - phys: from the *Generic PHY* bindings
-Optional properties:
+ - phy-names: from the *Generic PHY* bindings
 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
 This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/Documentation/devicetree/bindings/usb/ehci-omap.txt b/Documentation/devicetree/bindings/usb/ehci-omap.txt
index 485a9a1efa7a..3dc231c832b0 100644
--- a/Documentation/devicetree/bindings/usb/ehci-omap.txt
+++ b/Documentation/devicetree/bindings/usb/ehci-omap.txt
@@ -21,7 +21,7 @@ Documentation/devicetree/bindings/mfd/omap-usb-host.txt
 Example for OMAP4:
 usbhsehci: ehci@4a064c00 {
-        compatible = "ti,ehci-omap", "usb-ehci";
+        compatible = "ti,ehci-omap";
        reg = <0x4a064c00 0x400>;
        interrupts = <0 77 0x4>;
 };
diff --git a/Documentation/devicetree/bindings/usb/fsl-usb.txt b/Documentation/devicetree/bindings/usb/fsl-usb.txt
index bd5723f0b67e..4779c029b675 100644
--- a/Documentation/devicetree/bindings/usb/fsl-usb.txt
+++ b/Documentation/devicetree/bindings/usb/fsl-usb.txt
@@ -8,7 +8,9 @@ and additions :
 Required properties :
 - compatible : Should be "fsl-usb2-mph" for multi port host USB
   controllers, or "fsl-usb2-dr" for dual role USB controllers
-   or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121
+   or "fsl,mpc5121-usb2-dr" for dual role USB controllers of MPC5121.
+   Wherever applicable, the IP version of the USB controller should
+   also be mentioned (for eg. fsl-usb2-dr-v2.2 for bsc9132).
 - phy_type : For multi port host USB controllers, should be one of
   "ulpi", or "serial". For dual role USB controllers, should be
   one of "ulpi", "utmi", "utmi_wide", or "serial".
diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt
index 5835b27146ea..cef181a9d8bd 100644
--- a/Documentation/devicetree/bindings/usb/mxs-phy.txt
+++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt
@@ -1,13 +1,19 @@
 * Freescale MXS USB Phy Device
 Required properties:
- compatible: Should be "fsl,imx23-usbphy"
+- compatible: should contain:
+        * "fsl,imx23-usbphy" for imx23 and imx28
+        * "fsl,imx6q-usbphy" for imx6dq and imx6dl
+        * "fsl,imx6sl-usbphy" for imx6sl
+  "fsl,imx23-usbphy" is still a fallback for other strings
 - reg: Should contain registers location and length
 - interrupts: Should contain phy interrupt
+- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
 Example:
 usbphy1: usbphy@020c9000 {
        compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
        reg = <0x020c9000 0x1000>;
        interrupts = <0 44 0x04>;
+        fsl,anatop = <&anatop>;
 };
diff --git a/Documentation/devicetree/bindings/usb/ohci-omap3.txt b/Documentation/devicetree/bindings/usb/ohci-omap3.txt
index 14ab42812a8e..ce8c47cff6d0 100644
--- a/Documentation/devicetree/bindings/usb/ohci-omap3.txt
+++ b/Documentation/devicetree/bindings/usb/ohci-omap3.txt
@@ -9,7 +9,7 @@ Required properties:
 Example for OMAP4:
 usbhsohci: ohci@4a064800 {
-        compatible = "ti,ohci-omap3", "usb-ohci";
+        compatible = "ti,ohci-omap3";
        reg = <0x4a064800 0x400>;
        interrupts = <0 76 0x4>;
 };
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index c495135115cb..38b2faec4199 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -76,27 +76,3 @@ omap_dwc3 {
        ranges;
 };
-OMAP CONTROL USB
-Required properties:
- - compatible: Should be one of
- "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
- "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
-                        e.g. USB2_PHY on OMAP5.
- "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
-                        e.g. USB3 PHY and SATA PHY on OMAP5.
- "ti,control-phy-dra7usb2" - if it has power down register like USB2 PHY on
-                        DRA7 platform.
- "ti,control-phy-am437usb2" - if it has power down register like USB2 PHY on
-                        AM437 platform.
- - reg : Address and length of the register set for the device. It contains
-   the address of "otghs_control" for control-phy-otghs or "power" register
-   for other types.
- - reg-names: should be "otghs_control" control-phy-otghs and "power" for
-   other types.
-omap_control_usb: omap-control-usb@4a002300 {
-        compatible = "ti,control-phy-otghs";
-        reg = <0x4a00233c 0x4>;
-        reg-names = "otghs_control";
-};
diff --git a/Documentation/devicetree/bindings/usb/usb-ehci.txt b/Documentation/devicetree/bindings/usb/usb-ehci.txt
index fa18612f757b..ff151ec084c4 100644
--- a/Documentation/devicetree/bindings/usb/usb-ehci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-ehci.txt
@@ -1,19 +1,20 @@
 USB EHCI controllers
 Required properties:
-  - compatible : should be "usb-ehci".
+  - compatible : should be "generic-ehci".
  - reg : should contain at least address and length of the standard EHCI
    register set for the device. Optional platform-dependent registers
    (debug-port or other) can be also specified here, but only after
    definition of standard EHCI registers.
  - interrupts : one EHCI interrupt should be described here.
-If device registers are implemented in big endian mode, the device
-node should have "big-endian-regs" property.
+Optional properties:
-If controller implementation operates with big endian descriptors,
+ - big-endian-regs : boolean, set this for hcds with big-endian registers
-"big-endian-desc" property should be specified.
+ - big-endian-desc : boolean, set this for hcds with big-endian descriptors
-If both big endian registers and descriptors are used by the controller
+ - big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
-implementation, "big-endian" property can be specified instead of having
+ - clocks : a list of phandle + clock specifier pairs
-both "big-endian-regs" and "big-endian-desc".
+ - phys : phandle + phy specifier pair
+ - phy-names : "usb"
 Example (Sequoia 440EPx):
    ehci@e0000300 {
@@ -23,3 +24,13 @@ Example (Sequoia 440EPx):
           reg = <0 e0000300 90 0 e0000390 70>;
           big-endian;
   };
+Example (Allwinner sun4i A10 SoC):
+   ehci0: usb@01c14000 {
+           compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
+           reg = <0x01c14000 0x100>;
+           interrupts = <39>;
+           clocks = <&ahb_gates 1>;
+           phys = <&usbphy 1>;
+           phy-names = "usb";
+   };
diff --git a/Documentation/devicetree/bindings/usb/usb-ohci.txt b/Documentation/devicetree/bindings/usb/usb-ohci.txt
new file mode 100644
index 000000000000..45f67d91e888
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/usb-ohci.txt
@@ -0,0 +1,25 @@
+USB OHCI controllers
+Required properties:
+- compatible : "generic-ohci"
+- reg : ohci controller register range (address and length)
+- interrupts : ohci controller interrupt
+Optional properties:
+- big-endian-regs : boolean, set this for hcds with big-endian registers
+- big-endian-desc : boolean, set this for hcds with big-endian descriptors
+- big-endian : boolean, for hcds with big-endian-regs + big-endian-desc
+- clocks : a list of phandle + clock specifier pairs
+- phys : phandle + phy specifier pair
+- phy-names : "usb"
+Example:
+        ohci0: usb@01c14400 {
+                compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
+                reg = <0x01c14400 0x100>;
+                interrupts = <64>;
+                clocks = <&usb_clk 6>, <&ahb_gates 2>;
+                phys = <&usbphy 1>;
+                phy-names = "usb";
+        };
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt b/Documentation/devicetree/bindings/usb/usb-phy.txt
deleted file mode 100644
index c0245c888982..000000000000
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-USB PHY
-OMAP USB2 PHY
-Required properties:
- - compatible: Should be "ti,omap-usb2"
- - reg : Address and length of the register set for the device.
- - #phy-cells: determine the number of cells that should be given in the
-   phandle while referencing this phy.
-Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
-   the PHY.
-This is usually a subnode of ocp2scp to which it is connected.
-usb2phy@4a0ad080 {
-        compatible = "ti,omap-usb2";
-        reg = <0x4a0ad080 0x58>;
-        ctrl-module = <&omap_control_usb>;
-        #phy-cells = <0>;
-};
-OMAP USB3 PHY
-Required properties:
- - compatible: Should be "ti,omap-usb3"
- - reg : Address and length of the register set for the device.
- - reg-names: The names of the register addresses corresponding to the registers
-   filled in "reg".
- - #phy-cells: determine the number of cells that should be given in the
-   phandle while referencing this phy.
-Optional properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
-   the PHY.
-This is usually a subnode of ocp2scp to which it is connected.
-usb3phy@4a084400 {
-        compatible = "ti,omap-usb3";
-        reg = <0x4a084400 0x80>,
-              <0x4a084800 0x64>,
-              <0x4a084c00 0x40>;
-        reg-names = "phy_rx", "phy_tx", "pll_ctrl";
-        ctrl-module = <&omap_control_usb>;
-        #phy-cells = <0>;
-};
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/usb-uhci.txt
index a4fb0719d157..298133416c97 100644
--- a/Documentation/devicetree/bindings/usb/platform-uhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-uhci.txt
@@ -2,14 +2,14 @@ Generic Platform UHCI Controller
 -----------------------------------------------------
 Required properties:
- compatible : "platform-uhci"
+- compatible : "generic-uhci" (deprecated: "platform-uhci")
 - reg : Should contain 1 register ranges(address and length)
 - interrupts : UHCI controller interrupt
 Example:
        uhci@d8007b00 {
-                compatible = "platform-uhci";
+                compatible = "generic-uhci";
                reg = <0xd8007b00 0x200>;
                interrupts = <43>;
        };
diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
index 5752df0e17a2..90f8f607d125 100644
--- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
@@ -1,14 +1,14 @@
 USB xHCI controllers
 Required properties:
-  - compatible: should be "xhci-platform".
+  - compatible: should be "generic-xhci" (deprecated: "xhci-platform").
  - reg: should contain address and length of the standard XHCI
    register set for the device.
  - interrupts: one XHCI interrupt should be described here.
 Example:
        usb@f0931000 {
-                compatible = "xhci-platform";
+                compatible = "generic-xhci";
                reg = <0xf0931000 0x8c8>;
                interrupts = <0x0 0x4e 0x0>;
        };
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
deleted file mode 100644
index 17b3ad1d97e7..000000000000
--- a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-VIA/Wondermedia VT8500 EHCI Controller
-----------------------------------------------------
-Required properties:
- compatible : "via,vt8500-ehci"
- reg : Should contain 1 register ranges(address and length)
- interrupts : ehci controller interrupt
-Example:
-        ehci@d8007900 {
-                compatible = "via,vt8500-ehci";
-                reg = <0xd8007900 0x200>;
-                interrupts = <43>;
-        };
diff --git a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
deleted file mode 100644
index 5fb8fd6e250c..000000000000
--- a/Documentation/devicetree/bindings/usb/vt8500-ehci.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-VIA VT8500 and Wondermedia WM8xxx SoC USB controllers.
-Required properties:
- - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci".
- - reg: Address range of the ehci registers. size should be 0x200
- - interrupts: Should contain the ehci interrupt.
-usb: ehci@D8007100 {
-        compatible = "wm,prizm-ehci", "usb-ehci";
-        reg = <0xD8007100 0x200>;
-        interrupts = <1>;
-};
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 3f900cd51bf0..0f01c9bf19c8 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -3,21 +3,26 @@ Device tree binding vendor prefix registry.  Keep list in alphabetical order.
 This isn't an exhaustive list, but you should add new prefixes to it before
 using them to avoid name-space collisions.
+abilis  Abilis Systems
 active-semi     Active-Semi International Inc
 ad      Avionic Design GmbH
 adi     Analog Devices, Inc.
 aeroflexgaisler Aeroflex Gaisler AB
 ak      Asahi Kasei Corp.
+allwinner       Allwinner Technology Co., Ltd.
 altr    Altera Corp.
 amcc    Applied Micro Circuits Corporation (APM, formally AMCC)
+amd     Advanced Micro Devices (AMD), Inc.
 amstaos AMS-Taos Inc.
 apm     Applied Micro Circuits Corporation (APM)
 arm     ARM Ltd.
+armadeus        ARMadeus Systems SARL
 atmel   Atmel Corporation
 auo     AU Optronics Corporation
 avago   Avago Technologies
 bosch   Bosch Sensortec GmbH
 brcm    Broadcom Corporation
+calxeda Calxeda
 capella Capella Microsystems, Inc
 cavium  Cavium, Inc.
 cdns    Cadence Design Systems Inc.
@@ -25,28 +30,38 @@ chrp	Common Hardware Reference Platform
 chunghwa        Chunghwa Picture Tubes Ltd.
 cirrus  Cirrus Logic, Inc.
 cortina Cortina Systems, Inc.
+crystalfontz    Crystalfontz America, Inc.
 dallas  Maxim Integrated Products (formerly Dallas Semiconductor)
 davicom DAVICOM Semiconductor, Inc.
+dlink   D-Link Systems, Inc.
 denx    Denx Software Engineering
+dmo     Data Modul AG
 edt     Emerging Display Technologies
 emmicro EM Microelectronic
 epfl    Ecole Polytechnique Fédérale de Lausanne
 epson   Seiko Epson Corp.
 est     ESTeem Wireless Modems
+eukrea  Eukréa Electromatique
 fsl     Freescale Semiconductor
 GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
 gef     GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+globalscale     Globalscale Technologies, Inc.
 gmt     Global Mixed-mode Technology, Inc.
+google  Google, Inc.
 gumstix Gumstix, Inc.
 haoyu   Haoyu Microelectronic Co. Ltd.
 hisilicon       Hisilicon Limited.
+honeywell       Honeywell
 hp      Hewlett Packard
 ibm     International Business Machines (IBM)
 idt     Integrated Device Technologies, Inc.
 img     Imagination Technologies Ltd.
+intel   Intel Corporation
 intercontrol    Inter Control Group
 isl     Intersil
 karo    Ka-Ro electronics GmbH
+lacie   LaCie
+lantiq  Lantiq Semiconductor
 lg      LG Corporation
 linux   Linux-specific binding
 lsi     LSI Corp. (LSI Logic)
@@ -54,21 +69,28 @@ marvell	Marvell Technology Group Ltd.
 maxim   Maxim Integrated Products
 microchip       Microchip Technology Inc.
 mosaixtech      Mosaix Technologies, Inc.
+moxa    Moxa
 national        National Semiconductor
+neonode         Neonode Inc.
+netgear NETGEAR
 nintendo        Nintendo
+nokia   Nokia
 nvidia  NVIDIA
 nxp     NXP Semiconductors
 onnn    ON Semiconductor Corp.
+opencores       OpenCores.org
 panasonic       Panasonic Corporation
 phytec  PHYTEC Messtechnik GmbH
 picochip        Picochip Ltd
 powervr PowerVR (deprecated, use img)
 qca     Qualcomm Atheros, Inc.
-qcom    Qualcomm, Inc.
+qcom    Qualcomm Technologies, Inc
+qnap    QNAP Systems, Inc.
 ralink  Mediatek/Ralink Technology Corp.
 ramtron Ramtron International
 realtek Realtek Semiconductor Corp.
 renesas Renesas Electronics Corporation
+ricoh   Ricoh Co. Ltd.
 rockchip        Fuzhou Rockchip Electronics Co., Ltd
 samsung Samsung Semiconductor
 sbs     Smart Battery System
@@ -76,18 +98,24 @@ schindler	Schindler
 sil     Silicon Image
 silabs  Silicon Laboratories
 simtek
+sii     Seiko Instruments, Inc.
 sirf    SiRF Technology, Inc.
+smsc    Standard Microsystems Corporation
 snps    Synopsys, Inc.
+spansion        Spansion Inc.
 st      STMicroelectronics
 ste     ST-Ericsson
 stericsson      ST-Ericsson
+synology        Synology, Inc.
 ti      Texas Instruments
 tlm     Trusted Logic Mobility
 toshiba Toshiba Corporation
 toumaz  Toumaz
 v3      V3 Semiconductor
 via     VIA Technologies, Inc.
+voipac  Voipac Technologies s.r.o.
 winbond Winbond Electronics corp.
 wlf     Wolfson Microelectronics
 wm      Wondermedia Technologies, Inc.
+xes     Extreme Engineering Solutions (X-ES)
 xlnx    Xilinx
diff --git a/Documentation/devicetree/bindings/video/analog-tv-connector.txt b/Documentation/devicetree/bindings/video/analog-tv-connector.txt
new file mode 100644
index 000000000000..0218fcdc1299
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/analog-tv-connector.txt
@@ -0,0 +1,25 @@
+Analog TV Connector
+===================
+Required properties:
+- compatible: "composite-connector" or "svideo-connector"
+Optional properties:
+- label: a symbolic name for the connector
+Required nodes:
+- Video port for TV input
+Example
+-------
+tv: connector {
+        compatible = "composite-connector";
+        label = "tv";
+        port {
+                tv_connector_in: endpoint {
+                        remote-endpoint = <&venc_out>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/dvi-connector.txt b/Documentation/devicetree/bindings/video/dvi-connector.txt
new file mode 100644
index 000000000000..fc53f7c60bc6
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/dvi-connector.txt
@@ -0,0 +1,35 @@
+DVI Connector
+==============
+Required properties:
+- compatible: "dvi-connector"
+Optional properties:
+- label: a symbolic name for the connector
+- ddc-i2c-bus: phandle to the i2c bus that is connected to DVI DDC
+- analog: the connector has DVI analog pins
+- digital: the connector has DVI digital pins
+- dual-link: the connector has pins for DVI dual-link
+Required nodes:
+- Video port for DVI input
+Note: One (or both) of 'analog' or 'digital' must be set.
+Example
+-------
+dvi0: connector@0 {
+        compatible = "dvi-connector";
+        label = "dvi";
+        digital;
+        ddc-i2c-bus = <&i2c3>;
+        port {
+                dvi_connector_in: endpoint {
+                        remote-endpoint = <&tfp410_out>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/exynos_dp.txt b/Documentation/devicetree/bindings/video/exynos_dp.txt
index 3289d76a21d0..57ccdde02c3a 100644
--- a/Documentation/devicetree/bindings/video/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/video/exynos_dp.txt
@@ -49,6 +49,8 @@ Required properties for dp-controller:
        -samsung,lane-count:
                number of lanes supported by the panel.
                        LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
+        - display-timings: timings for the connected panel as described by
+                Documentation/devicetree/bindings/video/display-timing.txt
 Optional properties for dp-controller:
        -interlaced:
@@ -84,4 +86,19 @@ Board Specific portion:
                samsung,color-depth = <1>;
                samsung,link-rate = <0x0a>;
                samsung,lane-count = <4>;
+                display-timings {
+                        native-mode = <&lcd_timing>;
+                        lcd_timing: 1366x768 {
+                                clock-frequency = <70589280>;
+                                hactive = <1366>;
+                                vactive = <768>;
+                                hfront-porch = <40>;
+                                hback-porch = <40>;
+                                hsync-len = <32>;
+                                vback-porch = <10>;
+                                vfront-porch = <12>;
+                                vsync-len = <6>;
+                        };
+                };
        };
diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt
new file mode 100644
index 000000000000..33b5730d07ba
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt
@@ -0,0 +1,80 @@
+Exynos MIPI DSI Master
+Required properties:
+  - compatible: "samsung,exynos4210-mipi-dsi"
+  - reg: physical base address and length of the registers set for the device
+  - interrupts: should contain DSI interrupt
+  - clocks: list of clock specifiers, must contain an entry for each required
+    entry in clock-names
+  - clock-names: should include "bus_clk"and "pll_clk" entries
+  - phys: list of phy specifiers, must contain an entry for each required
+    entry in phy-names
+  - phy-names: should include "dsim" entry
+  - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
+  - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
+  - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock
+  - #address-cells, #size-cells: should be set respectively to <1> and <0>
+    according to DSI host bindings (see MIPI DSI bindings [1])
+Optional properties:
+  - samsung,power-domain: a phandle to DSIM power domain node
+Child nodes:
+  Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
+Video interfaces:
+  Device node can contain video interface port nodes according to [2].
+  The following are properties specific to those nodes:
+  port node:
+    - reg: (required) can be 0 for input RGB/I80 port or 1 for DSI port;
+  endpoint node of DSI port (reg = 1):
+    - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
+      mode
+    - samsung,esc-clock-frequency: specifies DSI frequency in escape mode
+[1]: Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Example:
+        dsi@11C80000 {
+                compatible = "samsung,exynos4210-mipi-dsi";
+                reg = <0x11C80000 0x10000>;
+                interrupts = <0 79 0>;
+                clocks = <&clock 286>, <&clock 143>;
+                clock-names = "bus_clk", "pll_clk";
+                phys = <&mipi_phy 1>;
+                phy-names = "dsim";
+                vddcore-supply = <&vusb_reg>;
+                vddio-supply = <&vmipi_reg>;
+                samsung,power-domain = <&pd_lcd0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,pll-clock-frequency = <24000000>;
+                panel@1 {
+                        reg = <0>;
+                        ...
+                        port {
+                                panel_ep: endpoint {
+                                        remote-endpoint = <&dsi_ep>;
+                                };
+                        };
+                };
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@1 {
+                                dsi_ep: endpoint {
+                                        reg = <0>;
+                                        samsung,burst-clock-frequency = <500000000>;
+                                        samsung,esc-clock-frequency = <20000000>;
+                                        remote-endpoint = <&panel_ep>;
+                                };
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8e1b90..f9187a259259 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,9 @@ Required properties:
                sclk_pixel.
 - clock-names: aliases as per driver requirements for above clock IDs:
        "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
+- ddc: phandle to the hdmi ddc node
+- phy: phandle to the hdmi phy node
 Example:
        hdmi {
@@ -32,4 +35,6 @@ Example:
                reg = <0x14530000 0x100000>;
                interrupts = <0 95 0>;
                hpd-gpio = <&gpx3 7 1>;
+                ddc = <&hdmi_ddc_node>;
+                phy = <&hdmi_phy_node>;
        };
diff --git a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
index 46da08db186a..0329f60d431e 100644
--- a/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
+++ b/Documentation/devicetree/bindings/video/fsl,imx-fb.txt
@@ -15,8 +15,12 @@ Required nodes:
        - fsl,pcr: LCDC PCR value
 Optional properties:
+- lcd-supply: Regulator for LCD supply voltage.
 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
        register is not modified as recommended by the datasheet.
+- fsl,lpccr: Contrast Control Register value. This property provides the
+        default value for the contrast control register.
+        If that property is ommited, the register is zeroed.
 - fsl,lscr1: LCDC Sharp Configuration Register value.
 Example:
diff --git a/Documentation/devicetree/bindings/video/hdmi-connector.txt b/Documentation/devicetree/bindings/video/hdmi-connector.txt
new file mode 100644
index 000000000000..ccccc19e2573
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/hdmi-connector.txt
@@ -0,0 +1,28 @@
+HDMI Connector
+==============
+Required properties:
+- compatible: "hdmi-connector"
+- type: the HDMI connector type: "a", "b", "c", "d" or "e"
+Optional properties:
+- label: a symbolic name for the connector
+Required nodes:
+- Video port for HDMI input
+Example
+-------
+hdmi0: connector@1 {
+        compatible = "hdmi-connector";
+        label = "hdmi";
+        type = "a";
+        port {
+                hdmi_connector_in: endpoint {
+                        remote-endpoint = <&tpd12s015_out>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/panel-dsi-cm.txt b/Documentation/devicetree/bindings/video/panel-dsi-cm.txt
new file mode 100644
index 000000000000..dce48eb9db57
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/panel-dsi-cm.txt
@@ -0,0 +1,29 @@
+Generic MIPI DSI Command Mode Panel
+===================================
+Required properties:
+- compatible: "panel-dsi-cm"
+Optional properties:
+- label: a symbolic name for the panel
+- reset-gpios: panel reset gpio
+- te-gpios: panel TE gpio
+Required nodes:
+- Video port for DSI input
+Example
+-------
+lcd0: display {
+        compatible = "tpo,taal", "panel-dsi-cm";
+        label = "lcd0";
+        reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+        port {
+                lcd0_in: endpoint {
+                        remote-endpoint = <&dsi1_out_ep>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 778838a0336a..2dad41b689af 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -39,6 +39,23 @@ Required properties:
 Optional Properties:
 - samsung,power-domain: a phandle to FIMD power domain node.
+- samsung,invert-vden: video enable signal is inverted
+- samsung,invert-vclk: video clock signal is inverted
+- display-timings: timing settings for FIMD, as described in document [1].
+                Can be used in case timings cannot be provided otherwise
+                or to override timings provided by the panel.
+The device node can contain 'port' child nodes according to the bindings defined
+in [2]. The following are properties specific to those nodes:
+- reg: (required) port index, can be:
+                0 - for CAMIF0 input,
+                1 - for CAMIF1 input,
+                2 - for CAMIF2 input,
+                3 - for parallel output,
+                4 - for write-back interface
+[1]: Documentation/devicetree/bindings/video/display-timing.txt
+[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
 Example:
diff --git a/Documentation/devicetree/bindings/video/sony,acx565akm.txt b/Documentation/devicetree/bindings/video/sony,acx565akm.txt
new file mode 100644
index 000000000000..e12333280749
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/sony,acx565akm.txt
@@ -0,0 +1,30 @@
+Sony ACX565AKM SDI Panel
+========================
+Required properties:
+- compatible: "sony,acx565akm"
+Optional properties:
+- label: a symbolic name for the panel
+- reset-gpios: panel reset gpio
+Required nodes:
+- Video port for SDI input
+Example
+-------
+acx565akm@2 {
+        compatible = "sony,acx565akm";
+        spi-max-frequency = <6000000>;
+        reg = <2>;
+        label = "lcd";
+        reset-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* 90 */
+        port {
+                lcd_in: endpoint {
+                        remote-endpoint = <&sdi_out>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/ti,omap-dss.txt b/Documentation/devicetree/bindings/video/ti,omap-dss.txt
new file mode 100644
index 000000000000..d5f1a3fe3109
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ti,omap-dss.txt
@@ -0,0 +1,211 @@
+Texas Instruments OMAP Display Subsystem
+========================================
+Generic Description
+-------------------
+This document is a generic description of the OMAP Display Subsystem bindings.
+Binding details for each OMAP SoC version are described in respective binding
+documentation.
+The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
+a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
+the encoder modules vary.
+The DSS Core is the parent of the other DSS modules, and manages clock routing,
+integration to the SoC, etc.
+DISPC is the display controller, which reads pixels from the memory and outputs
+a RGB pixel stream to encoders.
+The encoder modules encode the received RGB pixel stream to a video output like
+HDMI, MIPI DPI, etc.
+Video Ports
+-----------
+The DSS Core and the encoders have video port outputs. The structure of the
+video ports is described in Documentation/devicetree/bindings/video/video-
+ports.txt, and the properties for the ports and endpoints for each encoder are
+described in the SoC's DSS binding documentation.
+The video ports are used to describe the connections to external hardware, like
+panels or external encoders.
+Aliases
+-------
+The board dts file may define aliases for displays to assign "displayX" style
+name for each display. If no aliases are defined, a semi-random number is used
+for the display.
+Example
+-------
+A shortened example of the DSS description for OMAP4, with non-relevant parts
+removed, defined in omap4.dtsi:
+dss: dss@58000000 {
+        compatible = "ti,omap4-dss";
+        reg = <0x58000000 0x80>;
+        status = "disabled";
+        ti,hwmods = "dss_core";
+        clocks = <&dss_dss_clk>;
+        clock-names = "fck";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        dispc@58001000 {
+                compatible = "ti,omap4-dispc";
+                reg = <0x58001000 0x1000>;
+                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                ti,hwmods = "dss_dispc";
+                clocks = <&dss_dss_clk>;
+                clock-names = "fck";
+        };
+        hdmi: encoder@58006000 {
+                compatible = "ti,omap4-hdmi";
+                reg = <0x58006000 0x200>,
+                      <0x58006200 0x100>,
+                      <0x58006300 0x100>,
+                      <0x58006400 0x1000>;
+                reg-names = "wp", "pll", "phy", "core";
+                interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+                status = "disabled";
+                ti,hwmods = "dss_hdmi";
+                clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
+                clock-names = "fck", "sys_clk";
+        };
+};
+A shortened example of the board description for OMAP4 Panda board, defined in
+omap4-panda.dts.
+The Panda board has a DVI and a HDMI connector, and the board contains a TFP410
+chip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level
+shifter). The video pipelines for the connectors are formed as follows:
+DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
+OMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI Connector
+/ {
+        aliases {
+                display0 = &dvi0;
+                display1 = &hdmi0;
+        };
+        tfp410: encoder@0 {
+                compatible = "ti,tfp410";
+                gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;     /* 0, power-down */
+                pinctrl-names = "default";
+                pinctrl-0 = <&tfp410_pins>;
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tfp410_in: endpoint@0 {
+                                        remote-endpoint = <&dpi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tfp410_out: endpoint@0 {
+                                        remote-endpoint = <&dvi_connector_in>;
+                                };
+                        };
+                };
+        };
+        dvi0: connector@0 {
+                compatible = "dvi-connector";
+                label = "dvi";
+                i2c-bus = <&i2c3>;
+                port {
+                        dvi_connector_in: endpoint {
+                                remote-endpoint = <&tfp410_out>;
+                        };
+                };
+        };
+        tpd12s015: encoder@1 {
+                compatible = "ti,tpd12s015";
+                pinctrl-names = "default";
+                pinctrl-0 = <&tpd12s015_pins>;
+                gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,   /* 60, CT CP HPD */
+                        <&gpio2 9 GPIO_ACTIVE_HIGH>,    /* 41, LS OE */
+                        <&gpio2 31 GPIO_ACTIVE_HIGH>;   /* 63, HPD */
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                tpd12s015_in: endpoint@0 {
+                                        remote-endpoint = <&hdmi_out>;
+                                };
+                        };
+                        port@1 {
+                                reg = <1>;
+                                tpd12s015_out: endpoint@0 {
+                                        remote-endpoint = <&hdmi_connector_in>;
+                                };
+                        };
+                };
+        };
+        hdmi0: connector@1 {
+                compatible = "hdmi-connector";
+                label = "hdmi";
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&tpd12s015_out>;
+                        };
+                };
+        };
+};
+&dss {
+        status = "ok";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_dpi_pins>;
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&tfp410_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+&hdmi {
+        status = "ok";
+        vdda-supply = <&vdac>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_hdmi_pins>;
+        port {
+                hdmi_out: endpoint {
+                        remote-endpoint = <&tpd12s015_in>;
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/ti,omap2-dss.txt b/Documentation/devicetree/bindings/video/ti,omap2-dss.txt
new file mode 100644
index 000000000000..fa8bb2ed1170
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ti,omap2-dss.txt
@@ -0,0 +1,54 @@
+Texas Instruments OMAP2 Display Subsystem
+=========================================
+See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+description about OMAP Display Subsystem bindings.
+DSS Core
+--------
+Required properties:
+- compatible: "ti,omap2-dss"
+- reg: address and length of the register space
+- ti,hwmods: "dss_core"
+Optional nodes:
+- Video port for DPI output
+DPI Endpoint required properties:
+- data-lines: number of lines used
+DISPC
+-----
+Required properties:
+- compatible: "ti,omap2-dispc"
+- reg: address and length of the register space
+- ti,hwmods: "dss_dispc"
+- interrupts: the DISPC interrupt
+RFBI
+----
+Required properties:
+- compatible: "ti,omap2-rfbi"
+- reg: address and length of the register space
+- ti,hwmods: "dss_rfbi"
+VENC
+----
+Required properties:
+- compatible: "ti,omap2-venc"
+- reg: address and length of the register space
+- ti,hwmods: "dss_venc"
+- vdda-supply: power supply for DAC
+VENC Endpoint required properties:
+Required properties:
+- ti,invert-polarity: invert the polarity of the video signal
+- ti,channels: 1 for composite, 2 for s-video
diff --git a/Documentation/devicetree/bindings/video/ti,omap3-dss.txt b/Documentation/devicetree/bindings/video/ti,omap3-dss.txt
new file mode 100644
index 000000000000..0023fa4b1328
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ti,omap3-dss.txt
@@ -0,0 +1,83 @@
+Texas Instruments OMAP3 Display Subsystem
+=========================================
+See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+description about OMAP Display Subsystem bindings.
+DSS Core
+--------
+Required properties:
+- compatible: "ti,omap3-dss"
+- reg: address and length of the register space
+- ti,hwmods: "dss_core"
+- clocks: handle to fclk
+- clock-names: "fck"
+Optional nodes:
+- Video ports:
+        - Port 0: DPI output
+        - Port 1: SDI output
+DPI Endpoint required properties:
+- data-lines: number of lines used
+SDI Endpoint required properties:
+- datapairs: number of datapairs used
+DISPC
+-----
+Required properties:
+- compatible: "ti,omap3-dispc"
+- reg: address and length of the register space
+- ti,hwmods: "dss_dispc"
+- interrupts: the DISPC interrupt
+- clocks: handle to fclk
+- clock-names: "fck"
+RFBI
+----
+Required properties:
+- compatible: "ti,omap3-rfbi"
+- reg: address and length of the register space
+- ti,hwmods: "dss_rfbi"
+- clocks: handles to fclk and iclk
+- clock-names: "fck", "ick"
+VENC
+----
+Required properties:
+- compatible: "ti,omap3-venc"
+- reg: address and length of the register space
+- ti,hwmods: "dss_venc"
+- vdda-supply: power supply for DAC
+- clocks: handle to fclk
+- clock-names: "fck"
+VENC Endpoint required properties:
+- ti,invert-polarity: invert the polarity of the video signal
+- ti,channels: 1 for composite, 2 for s-video
+DSI
+---
+Required properties:
+- compatible: "ti,omap3-dsi"
+- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
+- reg-names: "proto", "phy", "pll"
+- interrupts: the DSI interrupt line
+- ti,hwmods: "dss_dsi1"
+- vdd-supply: power supply for DSI
+- clocks: handles to fclk and pll clock
+- clock-names: "fck", "sys_clk"
+DSI Endpoint required properties:
+- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
+  DATA1+, DATA1-, ...
diff --git a/Documentation/devicetree/bindings/video/ti,omap4-dss.txt b/Documentation/devicetree/bindings/video/ti,omap4-dss.txt
new file mode 100644
index 000000000000..f85d6fcfa705
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ti,omap4-dss.txt
@@ -0,0 +1,111 @@
+Texas Instruments OMAP4 Display Subsystem
+=========================================
+See Documentation/devicetree/bindings/video/ti,omap-dss.txt for generic
+description about OMAP Display Subsystem bindings.
+DSS Core
+--------
+Required properties:
+- compatible: "ti,omap4-dss"
+- reg: address and length of the register space
+- ti,hwmods: "dss_core"
+- clocks: handle to fclk
+- clock-names: "fck"
+Required nodes:
+- DISPC
+Optional nodes:
+- DSS Submodules: RFBI, VENC, DSI, HDMI
+- Video port for DPI output
+DPI Endpoint required properties:
+- data-lines: number of lines used
+DISPC
+-----
+Required properties:
+- compatible: "ti,omap4-dispc"
+- reg: address and length of the register space
+- ti,hwmods: "dss_dispc"
+- interrupts: the DISPC interrupt
+- clocks: handle to fclk
+- clock-names: "fck"
+RFBI
+----
+Required properties:
+- compatible: "ti,omap4-rfbi"
+- reg: address and length of the register space
+- ti,hwmods: "dss_rfbi"
+- clocks: handles to fclk and iclk
+- clock-names: "fck", "ick"
+Optional nodes:
+- Video port for RFBI output
+- RFBI controlled peripherals
+VENC
+----
+Required properties:
+- compatible: "ti,omap4-venc"
+- reg: address and length of the register space
+- ti,hwmods: "dss_venc"
+- vdda-supply: power supply for DAC
+- clocks: handle to fclk
+- clock-names: "fck"
+Optional nodes:
+- Video port for VENC output
+VENC Endpoint required properties:
+- ti,invert-polarity: invert the polarity of the video signal
+- ti,channels: 1 for composite, 2 for s-video
+DSI
+---
+Required properties:
+- compatible: "ti,omap4-dsi"
+- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
+- reg-names: "proto", "phy", "pll"
+- interrupts: the DSI interrupt line
+- ti,hwmods: "dss_dsi1" or "dss_dsi2"
+- vdd-supply: power supply for DSI
+- clocks: handles to fclk and pll clock
+- clock-names: "fck", "sys_clk"
+Optional nodes:
+- Video port for DSI output
+- DSI controlled peripherals
+DSI Endpoint required properties:
+- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
+  DATA1+, DATA1-, ...
+HDMI
+----
+Required properties:
+- compatible: "ti,omap4-hdmi"
+- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
+       'core'
+- reg-names: "wp", "pll", "phy", "core"
+- interrupts: the HDMI interrupt line
+- ti,hwmods: "dss_hdmi"
+- vdda-supply: vdda power supply
+- clocks: handles to fclk and pll clock
+- clock-names: "fck", "sys_clk"
+Optional nodes:
+- Video port for HDMI output
diff --git a/Documentation/devicetree/bindings/video/ti,tfp410.txt b/Documentation/devicetree/bindings/video/ti,tfp410.txt
new file mode 100644
index 000000000000..2cbe32a3d0bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ti,tfp410.txt
@@ -0,0 +1,41 @@
+TFP410 DPI to DVI encoder
+=========================
+Required properties:
+- compatible: "ti,tfp410"
+Optional properties:
+- powerdown-gpios: power-down gpio
+Required nodes:
+- Video port 0 for DPI input
+- Video port 1 for DVI output
+Example
+-------
+tfp410: encoder@0 {
+        compatible = "ti,tfp410";
+        powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        reg = <0>;
+                        tfp410_in: endpoint@0 {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+                port@1 {
+                        reg = <1>;
+                        tfp410_out: endpoint@0 {
+                                remote-endpoint = <&dvi_connector_in>;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/video/ti,tpd12s015.txt b/Documentation/devicetree/bindings/video/ti,tpd12s015.txt
new file mode 100644
index 000000000000..26e6d32e3f20
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/ti,tpd12s015.txt
@@ -0,0 +1,44 @@
+TPD12S015 HDMI level shifter and ESD protection chip
+====================================================
+Required properties:
+- compatible: "ti,tpd12s015"
+Optional properties:
+- gpios: CT CP HPD, LS OE and HPD gpios
+Required nodes:
+- Video port 0 for HDMI input
+- Video port 1 for HDMI output
+Example
+-------
+tpd12s015: encoder@1 {
+        compatible = "ti,tpd12s015";
+        gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,   /* 60, CT CP HPD */
+                <&gpio2 9 GPIO_ACTIVE_HIGH>,    /* 41, LS OE */
+                <&gpio2 31 GPIO_ACTIVE_HIGH>;   /* 63, HPD */
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        reg = <0>;
+                        tpd12s015_in: endpoint@0 {
+                                remote-endpoint = <&hdmi_out>;
+                        };
+                };
+                port@1 {
+                        reg = <1>;
+                        tpd12s015_out: endpoint@0 {
+                                remote-endpoint = <&hdmi_connector_in>;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/watchdog/marvel.txt b/Documentation/devicetree/bindings/watchdog/marvel.txt
index 5dc8d30061ce..de11eb4c121f 100644
--- a/Documentation/devicetree/bindings/watchdog/marvel.txt
+++ b/Documentation/devicetree/bindings/watchdog/marvel.txt
@@ -3,17 +3,24 @@
 Required Properties:
 - Compatibility : "marvell,orion-wdt"
- reg           : Address of the timer registers
+                  "marvell,armada-370-wdt"
+                  "marvell,armada-xp-wdt"
+- reg           : Should contain two entries: first one with the
+                  timer control address, second one with the
+                  rstout enable address.
 Optional properties:
+- interrupts    : Contains the IRQ for watchdog expiration
 - timeout-sec   : Contains the watchdog timeout in seconds
 Example:
        wdt@20300 {
                compatible = "marvell,orion-wdt";
-                reg = <0x20300 0x28>;
+                reg = <0x20300 0x28>, <0x20108 0x4>;
+                interrupts = <3>;
                timeout-sec = <10>;
                status = "okay";
        };
diff --git a/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
new file mode 100644
index 000000000000..6d63782a7378
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
@@ -0,0 +1,23 @@
+Xilinx AXI/PLB soft-core watchdog Device Tree Bindings
+---------------------------------------------------------
+Required properties:
+- compatible            : Should be "xlnx,xps-timebase-wdt-1.00.a" or
+                          "xlnx,xps-timebase-wdt-1.01.a".
+- reg                   : Physical base address and size
+Optional properties:
+- clock-frequency       : Frequency of clock in Hz
+- xlnx,wdt-enable-once  : 0 - Watchdog can be restarted
+                          1 - Watchdog can be enabled just once
+- xlnx,wdt-interval     : Watchdog timeout interval in 2^<val> clock cycles,
+                          <val> is integer from 8 to 31.
+Example:
+axi-timebase-wdt@40100000 {
+        clock-frequency = <50000000>;
+        compatible = "xlnx,xps-timebase-wdt-1.00.a";
+        reg = <0x40100000 0x10000>;
+        xlnx,wdt-enable-once = <0x0>;
+        xlnx,wdt-interval = <0x1b>;
+} ;
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
index e39cb266c8f4..b8f75c51453a 100644
--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
@@ -2,13 +2,13 @@ Allwinner SoCs Watchdog timer
 Required properties:
- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
+- compatible : should be either "allwinner,sun4i-a10-wdt" or
-  SoC families being sun4i and sun6i
+               "allwinner,sun6i-a31-wdt"
 - reg : Specifies base physical address and size of the registers.
 Example:
 wdt: watchdog@01c20c90 {
-        compatible = "allwinner,sun4i-wdt";
+        compatible = "allwinner,sun4i-a10-wdt";
        reg = <0x01c20c90 0x10>;
 };