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-rw-r--r--Documentation/devicetree/bindings/arm/mrvl/tauros2.txt17
-rw-r--r--Documentation/devicetree/bindings/arm/msm/timer.txt38
-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/imx23-clock.txt76
-rw-r--r--Documentation/devicetree/bindings/clock/imx28-clock.txt99
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt222
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-samsung.txt43
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-twl4030.txt6
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt1
-rw-r--r--Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt52
-rw-r--r--Documentation/devicetree/bindings/lpddr2/lpddr2.txt102
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/ti/emif.txt55
-rw-r--r--Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt31
-rw-r--r--Documentation/devicetree/bindings/rtc/pxa-rtc.txt14
14 files changed, 759 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
new file mode 100644
index 000000000000..31af1cbb60bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
@@ -0,0 +1,17 @@
1* Marvell Tauros2 Cache
2
3Required properties:
4- compatible : Should be "marvell,tauros2-cache".
5- marvell,tauros2-cache-features : Specify the features supported for the
6 tauros2 cache.
7 The features including
8 CACHE_TAUROS2_PREFETCH_ON (1 << 0)
9 CACHE_TAUROS2_LINEFILL_BURST8 (1 << 1)
10 The definition can be found at
11 arch/arm/include/asm/hardware/cache-tauros2.h
12
13Example:
14 L2: l2-cache {
15 compatible = "marvell,tauros2-cache";
16 marvell,tauros2-cache-features = <0x3>;
17 };
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt
new file mode 100644
index 000000000000..8c5907b9cae8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/timer.txt
@@ -0,0 +1,38 @@
1* MSM Timer
2
3Properties:
4
5- compatible : Should at least contain "qcom,msm-timer". More specific
6 properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
7 purpose timer and a debug timer respectively.
8
9- interrupts : Interrupt indicating a match event.
10
11- reg : Specifies the base address of the timer registers. The second region
12 specifies an optional register used to configure the clock divider.
13
14- clock-frequency : The frequency of the timer in Hz.
15
16Optional:
17
18- cpu-offset : per-cpu offset used when the timer is accessed without the
19 CPU remapping facilities. The offset is cpu-offset * cpu-nr.
20
21Example:
22
23 timer@200a004 {
24 compatible = "qcom,msm-gpt", "qcom,msm-timer";
25 interrupts = <1 2 0x301>;
26 reg = <0x0200a004 0x10>;
27 clock-frequency = <32768>;
28 cpu-offset = <0x40000>;
29 };
30
31 timer@200a024 {
32 compatible = "qcom,msm-dgt", "qcom,msm-timer";
33 interrupts = <1 3 0x301>;
34 reg = <0x0200a024 0x10>,
35 <0x0200a034 0x4>;
36 clock-frequency = <6750000>;
37 cpu-offset = <0x40000>;
38 };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index ccdd0e53451f..d0051a750587 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -36,6 +36,9 @@ Boards:
36- OMAP3 BeagleBoard : Low cost community board 36- OMAP3 BeagleBoard : Low cost community board
37 compatible = "ti,omap3-beagle", "ti,omap3" 37 compatible = "ti,omap3-beagle", "ti,omap3"
38 38
39- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
40 compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
41
39- OMAP4 SDP : Software Developement Board 42- OMAP4 SDP : Software Developement Board
40 compatible = "ti,omap4-sdp", "ti,omap4430" 43 compatible = "ti,omap4-sdp", "ti,omap4430"
41 44
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
new file mode 100644
index 000000000000..a0b867ef8d96
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -0,0 +1,76 @@
1* Clock bindings for Freescale i.MX23
2
3Required properties:
4- compatible: Should be "fsl,imx23-clkctrl"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7
8The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. The following is a full list of i.MX23
10clocks and IDs.
11
12 Clock ID
13 ------------------
14 ref_xtal 0
15 pll 1
16 ref_cpu 2
17 ref_emi 3
18 ref_pix 4
19 ref_io 5
20 saif_sel 6
21 lcdif_sel 7
22 gpmi_sel 8
23 ssp_sel 9
24 emi_sel 10
25 cpu 11
26 etm_sel 12
27 cpu_pll 13
28 cpu_xtal 14
29 hbus 15
30 xbus 16
31 lcdif_div 17
32 ssp_div 18
33 gpmi_div 19
34 emi_pll 20
35 emi_xtal 21
36 etm_div 22
37 saif_div 23
38 clk32k_div 24
39 rtc 25
40 adc 26
41 spdif_div 27
42 clk32k 28
43 dri 29
44 pwm 30
45 filt 31
46 uart 32
47 ssp 33
48 gpmi 34
49 spdif 35
50 emi 36
51 saif 37
52 lcdif 38
53 etm 39
54 usb 40
55 usb_pwr 41
56
57Examples:
58
59clks: clkctrl@80040000 {
60 compatible = "fsl,imx23-clkctrl";
61 reg = <0x80040000 0x2000>;
62 #clock-cells = <1>;
63 clock-output-names =
64 ...
65 "uart", /* 32 */
66 ...
67 "end_of_list";
68};
69
70auart0: serial@8006c000 {
71 compatible = "fsl,imx23-auart";
72 reg = <0x8006c000 0x2000>;
73 interrupts = <24 25 23>;
74 clocks = <&clks 32>;
75 status = "disabled";
76};
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
new file mode 100644
index 000000000000..aa2af2866fe8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -0,0 +1,99 @@
1* Clock bindings for Freescale i.MX28
2
3Required properties:
4- compatible: Should be "fsl,imx28-clkctrl"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7
8The clock consumer should specify the desired clock by having the clock
9ID in its "clocks" phandle cell. The following is a full list of i.MX28
10clocks and IDs.
11
12 Clock ID
13 ------------------
14 ref_xtal 0
15 pll0 1
16 pll1 2
17 pll2 3
18 ref_cpu 4
19 ref_emi 5
20 ref_io0 6
21 ref_io1 7
22 ref_pix 8
23 ref_hsadc 9
24 ref_gpmi 10
25 saif0_sel 11
26 saif1_sel 12
27 gpmi_sel 13
28 ssp0_sel 14
29 ssp1_sel 15
30 ssp2_sel 16
31 ssp3_sel 17
32 emi_sel 18
33 etm_sel 19
34 lcdif_sel 20
35 cpu 21
36 ptp_sel 22
37 cpu_pll 23
38 cpu_xtal 24
39 hbus 25
40 xbus 26
41 ssp0_div 27
42 ssp1_div 28
43 ssp2_div 29
44 ssp3_div 30
45 gpmi_div 31
46 emi_pll 32
47 emi_xtal 33
48 lcdif_div 34
49 etm_div 35
50 ptp 36
51 saif0_div 37
52 saif1_div 38
53 clk32k_div 39
54 rtc 40
55 lradc 41
56 spdif_div 42
57 clk32k 43
58 pwm 44
59 uart 45
60 ssp0 46
61 ssp1 47
62 ssp2 48
63 ssp3 49
64 gpmi 50
65 spdif 51
66 emi 52
67 saif0 53
68 saif1 54
69 lcdif 55
70 etm 56
71 fec 57
72 can0 58
73 can1 59
74 usb0 60
75 usb1 61
76 usb0_pwr 62
77 usb1_pwr 63
78 enet_out 64
79
80Examples:
81
82clks: clkctrl@80040000 {
83 compatible = "fsl,imx28-clkctrl";
84 reg = <0x80040000 0x2000>;
85 #clock-cells = <1>;
86 clock-output-names =
87 ...
88 "uart", /* 45 */
89 ...
90 "end_of_list";
91};
92
93auart0: serial@8006a000 {
94 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
95 reg = <0x8006a000 0x2000>;
96 interrupts = <112 70 71>;
97 clocks = <&clks 45>;
98 status = "disabled";
99};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
new file mode 100644
index 000000000000..492bd991d52a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -0,0 +1,222 @@
1* Clock bindings for Freescale i.MX6 Quad
2
3Required properties:
4- compatible: Should be "fsl,imx6q-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 dummy 0
16 ckil 1
17 ckih 2
18 osc 3
19 pll2_pfd0_352m 4
20 pll2_pfd1_594m 5
21 pll2_pfd2_396m 6
22 pll3_pfd0_720m 7
23 pll3_pfd1_540m 8
24 pll3_pfd2_508m 9
25 pll3_pfd3_454m 10
26 pll2_198m 11
27 pll3_120m 12
28 pll3_80m 13
29 pll3_60m 14
30 twd 15
31 step 16
32 pll1_sw 17
33 periph_pre 18
34 periph2_pre 19
35 periph_clk2_sel 20
36 periph2_clk2_sel 21
37 axi_sel 22
38 esai_sel 23
39 asrc_sel 24
40 spdif_sel 25
41 gpu2d_axi 26
42 gpu3d_axi 27
43 gpu2d_core_sel 28
44 gpu3d_core_sel 29
45 gpu3d_shader_sel 30
46 ipu1_sel 31
47 ipu2_sel 32
48 ldb_di0_sel 33
49 ldb_di1_sel 34
50 ipu1_di0_pre_sel 35
51 ipu1_di1_pre_sel 36
52 ipu2_di0_pre_sel 37
53 ipu2_di1_pre_sel 38
54 ipu1_di0_sel 39
55 ipu1_di1_sel 40
56 ipu2_di0_sel 41
57 ipu2_di1_sel 42
58 hsi_tx_sel 43
59 pcie_axi_sel 44
60 ssi1_sel 45
61 ssi2_sel 46
62 ssi3_sel 47
63 usdhc1_sel 48
64 usdhc2_sel 49
65 usdhc3_sel 50
66 usdhc4_sel 51
67 enfc_sel 52
68 emi_sel 53
69 emi_slow_sel 54
70 vdo_axi_sel 55
71 vpu_axi_sel 56
72 cko1_sel 57
73 periph 58
74 periph2 59
75 periph_clk2 60
76 periph2_clk2 61
77 ipg 62
78 ipg_per 63
79 esai_pred 64
80 esai_podf 65
81 asrc_pred 66
82 asrc_podf 67
83 spdif_pred 68
84 spdif_podf 69
85 can_root 70
86 ecspi_root 71
87 gpu2d_core_podf 72
88 gpu3d_core_podf 73
89 gpu3d_shader 74
90 ipu1_podf 75
91 ipu2_podf 76
92 ldb_di0_podf 77
93 ldb_di1_podf 78
94 ipu1_di0_pre 79
95 ipu1_di1_pre 80
96 ipu2_di0_pre 81
97 ipu2_di1_pre 82
98 hsi_tx_podf 83
99 ssi1_pred 84
100 ssi1_podf 85
101 ssi2_pred 86
102 ssi2_podf 87
103 ssi3_pred 88
104 ssi3_podf 89
105 uart_serial_podf 90
106 usdhc1_podf 91
107 usdhc2_podf 92
108 usdhc3_podf 93
109 usdhc4_podf 94
110 enfc_pred 95
111 enfc_podf 96
112 emi_podf 97
113 emi_slow_podf 98
114 vpu_axi_podf 99
115 cko1_podf 100
116 axi 101
117 mmdc_ch0_axi_podf 102
118 mmdc_ch1_axi_podf 103
119 arm 104
120 ahb 105
121 apbh_dma 106
122 asrc 107
123 can1_ipg 108
124 can1_serial 109
125 can2_ipg 110
126 can2_serial 111
127 ecspi1 112
128 ecspi2 113
129 ecspi3 114
130 ecspi4 115
131 ecspi5 116
132 enet 117
133 esai 118
134 gpt_ipg 119
135 gpt_ipg_per 120
136 gpu2d_core 121
137 gpu3d_core 122
138 hdmi_iahb 123
139 hdmi_isfr 124
140 i2c1 125
141 i2c2 126
142 i2c3 127
143 iim 128
144 enfc 129
145 ipu1 130
146 ipu1_di0 131
147 ipu1_di1 132
148 ipu2 133
149 ipu2_di0 134
150 ldb_di0 135
151 ldb_di1 136
152 ipu2_di1 137
153 hsi_tx 138
154 mlb 139
155 mmdc_ch0_axi 140
156 mmdc_ch1_axi 141
157 ocram 142
158 openvg_axi 143
159 pcie_axi 144
160 pwm1 145
161 pwm2 146
162 pwm3 147
163 pwm4 148
164 per1_bch 149
165 gpmi_bch_apb 150
166 gpmi_bch 151
167 gpmi_io 152
168 gpmi_apb 153
169 sata 154
170 sdma 155
171 spba 156
172 ssi1 157
173 ssi2 158
174 ssi3 159
175 uart_ipg 160
176 uart_serial 161
177 usboh3 162
178 usdhc1 163
179 usdhc2 164
180 usdhc3 165
181 usdhc4 166
182 vdo_axi 167
183 vpu_axi 168
184 cko1 169
185 pll1_sys 170
186 pll2_bus 171
187 pll3_usb_otg 172
188 pll4_audio 173
189 pll5_video 174
190 pll6_mlb 175
191 pll7_usb_host 176
192 pll8_enet 177
193 ssi1_ipg 178
194 ssi2_ipg 179
195 ssi3_ipg 180
196 rom 181
197 usbphy1 182
198 usbphy2 183
199 ldb_di0_div_3_5 184
200 ldb_di1_div_3_5 185
201
202Examples:
203
204clks: ccm@020c4000 {
205 compatible = "fsl,imx6q-ccm";
206 reg = <0x020c4000 0x4000>;
207 interrupts = <0 87 0x04 0 88 0x04>;
208 #clock-cells = <1>;
209 clock-output-names = ...
210 "uart_ipg",
211 "uart_serial",
212 ...;
213};
214
215uart1: serial@02020000 {
216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
217 reg = <0x02020000 0x4000>;
218 interrupts = <0 26 0x04>;
219 clocks = <&clks 160>, <&clks 161>;
220 clock-names = "ipg", "per";
221 status = "disabled";
222};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625e8cd2..f1e5dfecf55d 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,46 @@ Example:
39 #gpio-cells = <4>; 39 #gpio-cells = <4>;
40 gpio-controller; 40 gpio-controller;
41 }; 41 };
42
43
44Samsung S3C24XX GPIO Controller
45
46Required properties:
47- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
48
49- reg: Physical base address of the controller and length of memory mapped
50 region.
51
52- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
53 should be the following with values derived from the SoC user manual.
54 <[phandle of the gpio controller node]
55 [pin number within the gpio controller]
56 [mux function]
57 [flags and pull up/down]
58
59 Values for gpio specifier:
60 - Pin number: depending on the controller a number from 0 up to 15.
61 - Mux function: Depending on the SoC and the gpio bank the gpio can be set
62 as input, output or a special function
63 - Flags and Pull Up/Down: the values to use differ for the individual SoCs
64 example S3C2416/S3C2450:
65 0 - Pull Up/Down Disabled.
66 1 - Pull Down Enabled.
67 2 - Pull Up Enabled.
68 Bit 16 (0x00010000) - Input is active low.
69 Consult the user manual for the correct values of Mux and Pull Up/Down.
70
71- gpio-controller: Specifies that the node is a gpio controller.
72- #address-cells: should be 1.
73- #size-cells: should be 1.
74
75Example:
76
77 gpa: gpio-controller@56000000 {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "samsung,s3c24xx-gpio";
81 reg = <0x56000000 0x10>;
82 #gpio-cells = <3>;
83 gpio-controller;
84 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
index 16695d9cf1e8..66788fda1db3 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
@@ -11,6 +11,11 @@ Required properties:
11- interrupt-controller: Mark the device node as an interrupt controller 11- interrupt-controller: Mark the device node as an interrupt controller
12 The first cell is the GPIO number. 12 The first cell is the GPIO number.
13 The second cell is not used. 13 The second cell is not used.
14- ti,use-leds : Enables LEDA and LEDB outputs if set
15- ti,debounce : if n-th bit is set, debounces GPIO-n
16- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
17- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
18- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
14 19
15Example: 20Example:
16 21
@@ -20,4 +25,5 @@ twl_gpio: gpio {
20 gpio-controller; 25 gpio-controller;
21 #interrupt-cells = <2>; 26 #interrupt-cells = <2>;
22 interrupt-controller; 27 interrupt-controller;
28 ti,use-leds;
23}; 29};
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 1a85f986961b..2f5322b119eb 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -56,3 +56,4 @@ stm,m41t00 Serial Access TIMEKEEPER
56stm,m41t62 Serial real-time clock (RTC) with alarm 56stm,m41t62 Serial real-time clock (RTC) with alarm
57stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS 57stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
58ti,tsc2003 I2C Touch-Screen Controller 58ti,tsc2003 I2C Touch-Screen Controller
59ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
new file mode 100644
index 000000000000..9ceb19e0c7fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
@@ -0,0 +1,52 @@
1* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
2
3Required properties:
4- compatible : Should be "jedec,lpddr2-timings"
5- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
7
8Optional properties:
9
10The following properties represent AC timing parameters from the memory
11data-sheet of the device for a given speed-bin. All these properties are
12of type <u32> and the default unit is ps (pico seconds). Parameters with
13a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
14- tRCD
15- tWR
16- tRAS-min
17- tRRD
18- tWTR
19- tXP
20- tRTP
21- tDQSCK-max
22- tFAW
23- tZQCS
24- tZQinit
25- tRPab
26- tZQCL
27- tCKESR
28- tRAS-max-ns
29- tDQSCK-max-derated
30
31Example:
32
33timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
34 compatible = "jedec,lpddr2-timings";
35 min-freq = <10000000>;
36 max-freq = <400000000>;
37 tRPab = <21000>;
38 tRCD = <18000>;
39 tWR = <15000>;
40 tRAS-min = <42000>;
41 tRRD = <10000>;
42 tWTR = <7500>;
43 tXP = <7500>;
44 tRTP = <7500>;
45 tCKESR = <15000>;
46 tDQSCK-max = <5500>;
47 tFAW = <50000>;
48 tZQCS = <90000>;
49 tZQCL = <360000>;
50 tZQinit = <1000000>;
51 tRAS-max-ns = <70000>;
52};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
new file mode 100644
index 000000000000..58354a075e13
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
@@ -0,0 +1,102 @@
1* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
2
3Required properties:
4- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
5 "jedec,lpddr2-s4"
6
7 "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
8
9 "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
10
11 "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
12
13- density : <u32> representing density in Mb (Mega bits)
14
15- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
16
17Optional properties:
18
19The following optional properties represent the minimum value of some AC
20timing parameters of the DDR device in terms of number of clock cycles.
21These values shall be obtained from the device data-sheet.
22- tRRD-min-tck
23- tWTR-min-tck
24- tXP-min-tck
25- tRTP-min-tck
26- tCKE-min-tck
27- tRPab-min-tck
28- tRCD-min-tck
29- tWR-min-tck
30- tRASmin-min-tck
31- tCKESR-min-tck
32- tFAW-min-tck
33
34Child nodes:
35- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
36 "lpddr2-timings" provides AC timing parameters of the device for
37 a given speed-bin. The user may provide the timings for as many
38 speed-bins as is required. Please see Documentation/devicetree/
39 bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
40
41Example:
42
43elpida_ECB240ABACN : lpddr2 {
44 compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
45 density = <2048>;
46 io-width = <32>;
47
48 tRPab-min-tck = <3>;
49 tRCD-min-tck = <3>;
50 tWR-min-tck = <3>;
51 tRASmin-min-tck = <3>;
52 tRRD-min-tck = <2>;
53 tWTR-min-tck = <2>;
54 tXP-min-tck = <2>;
55 tRTP-min-tck = <2>;
56 tCKE-min-tck = <3>;
57 tCKESR-min-tck = <3>;
58 tFAW-min-tck = <8>;
59
60 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
61 compatible = "jedec,lpddr2-timings";
62 min-freq = <10000000>;
63 max-freq = <400000000>;
64 tRPab = <21000>;
65 tRCD = <18000>;
66 tWR = <15000>;
67 tRAS-min = <42000>;
68 tRRD = <10000>;
69 tWTR = <7500>;
70 tXP = <7500>;
71 tRTP = <7500>;
72 tCKESR = <15000>;
73 tDQSCK-max = <5500>;
74 tFAW = <50000>;
75 tZQCS = <90000>;
76 tZQCL = <360000>;
77 tZQinit = <1000000>;
78 tRAS-max-ns = <70000>;
79 };
80
81 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
82 compatible = "jedec,lpddr2-timings";
83 min-freq = <10000000>;
84 max-freq = <200000000>;
85 tRPab = <21000>;
86 tRCD = <18000>;
87 tWR = <15000>;
88 tRAS-min = <42000>;
89 tRRD = <10000>;
90 tWTR = <10000>;
91 tXP = <7500>;
92 tRTP = <7500>;
93 tCKESR = <15000>;
94 tDQSCK-max = <5500>;
95 tFAW = <50000>;
96 tZQCS = <90000>;
97 tZQCL = <360000>;
98 tZQinit = <1000000>;
99 tRAS-max-ns = <70000>;
100 };
101
102}
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 000000000000..938f8e1ba205
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,55 @@
1* EMIF family of TI SDRAM controllers
2
3EMIF - External Memory Interface - is an SDRAM controller used in
4TI SoCs. EMIF supports, based on the IP revision, one or more of
5DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
6of the EMIF IP and memory parts attached to it.
7
8Required properties:
9- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
10 is the IP revision of the specific EMIF instance.
11
12- phy-type : <u32> indicating the DDR phy type. Following are the
13 allowed values
14 <1> : Attila PHY
15 <2> : Intelli PHY
16
17- device-handle : phandle to a "lpddr2" node representing the memory part
18
19- ti,hwmods : For TI hwmods processing and omap device creation
20 the value shall be "emif<n>" where <n> is the number of the EMIF
21 instance with base 1.
22
23Optional properties:
24- cs1-used : Have this property if CS1 of this EMIF
25 instance has a memory part attached to it. If there is a memory
26 part attached to CS1, it should be the same type as the one on CS0,
27 so there is no need to give the details of this memory part.
28
29- cal-resistor-per-cs : Have this property if the board has one
30 calibration resistor per chip-select.
31
32- hw-caps-read-idle-ctrl: Have this property if the controller
33 supports read idle window programming
34
35- hw-caps-dll-calib-ctrl: Have this property if the controller
36 supports dll calibration control
37
38- hw-caps-ll-interface : Have this property if the controller
39 has a low latency interface and corresponding interrupt events
40
41- hw-caps-temp-alert : Have this property if the controller
42 has capability for generating SDRAM temperature alerts
43
44Example:
45
46emif1: emif@0x4c000000 {
47 compatible = "ti,emif-4d";
48 ti,hwmods = "emif2";
49 phy-type = <1>;
50 device-handle = <&elpida_ECB240ABACN>;
51 cs1-used;
52 hw-caps-read-idle-ctrl;
53 hw-caps-ll-interface;
54 hw-caps-temp-alert;
55};
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
new file mode 100644
index 000000000000..f1421e2bbab7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -0,0 +1,31 @@
1PXA3xx NAND DT bindings
2
3Required properties:
4
5 - compatible: Should be "marvell,pxa3xx-nand"
6 - reg: The register base for the controller
7 - interrupts: The interrupt to map
8 - #address-cells: Set to <1> if the node includes partitions
9
10Optional properties:
11
12 - marvell,nand-enable-arbiter: Set to enable the bus arbiter
13 - marvell,nand-keep-config: Set to keep the NAND controller config as set
14 by the bootloader
15 - num-cs: Number of chipselect lines to usw
16
17Example:
18
19 nand0: nand@43100000 {
20 compatible = "marvell,pxa3xx-nand";
21 reg = <0x43100000 90>;
22 interrupts = <45>;
23 #address-cells = <1>;
24
25 marvell,nand-enable-arbiter;
26 marvell,nand-keep-config;
27 num-cs = <1>;
28
29 /* partitions (optional) */
30 };
31
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
new file mode 100644
index 000000000000..8c6672a1b7d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
@@ -0,0 +1,14 @@
1* PXA RTC
2
3PXA specific RTC driver.
4
5Required properties:
6- compatible : Should be "marvell,pxa-rtc"
7
8Examples:
9
10rtc@40900000 {
11 compatible = "marvell,pxa-rtc";
12 reg = <0x40900000 0x3c>;
13 interrupts = <30 31>;
14};
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-14 09:02:14 -0500