86 files changed, 3022 insertions, 64 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
new file mode 100644
index 000000000000..4755caaccba6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/calxeda.txt
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+Required root node properties:
+    - compatible = "calxeda,highbank";
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
new file mode 100644
index 000000000000..54bdddadf1cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -0,0 +1,30 @@
+Freescale i.MX Platforms Device Tree Bindings
+-----------------------------------------------
+i.MX51 Babbage Board
+Required root node properties:
+    - compatible = "fsl,imx51-babbage", "fsl,imx51";
+i.MX53 Automotive Reference Design Board
+Required root node properties:
+    - compatible = "fsl,imx53-ard", "fsl,imx53";
+i.MX53 Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx53-evk", "fsl,imx53";
+i.MX53 Quick Start Board
+Required root node properties:
+    - compatible = "fsl,imx53-qsb", "fsl,imx53";
+i.MX53 Smart Mobile Reference Design Board
+Required root node properties:
+    - compatible = "fsl,imx53-smd", "fsl,imx53";
+i.MX6 Quad Armadillo2 Board
+Required root node properties:
+    - compatible = "fsl,imx6q-arm2", "fsl,imx6q";
+i.MX6 Quad SABRE Lite Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
new file mode 100644
index 000000000000..9b4b82a721b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -0,0 +1,59 @@
+* ARM Generic Interrupt Controller
+ARM SMP cores are often associated with a GIC, providing per processor
+interrupts (PPI), shared processor interrupts (SPI) and software
+generated interrupts (SGI).
+Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
+Secondary GICs are cascaded into the upward interrupt controller and do not
+have PPIs or SGIs.
+Main node required properties:
+- compatible : should be one of:
+        "arm,cortex-a9-gic"
+        "arm,arm11mp-gic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.  The type shall be a <u32> and the value shall be 3.
+  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
+  interrupts.
+  The 2nd cell contains the interrupt number for the interrupt type.
+  SPI interrupts are in the range [0-987].  PPI interrupts are in the
+  range [0-15].
+  The 3rd cell is the flags, encoded as follows:
+        bits[3:0] trigger type and level flags.
+                1 = low-to-high edge triggered
+                2 = high-to-low edge triggered
+                4 = active high level-sensitive
+                8 = active low level-sensitive
+        bits[15:8] PPI interrupt cpu mask.  Each bit corresponds to each of
+        the 8 possible cpus attached to the GIC.  A bit set to '1' indicated
+        the interrupt is wired to that CPU.  Only valid for PPI interrupts.
+- reg : Specifies base physical address(s) and size of the GIC registers. The
+  first region is the GIC distributor register base and size. The 2nd region is
+  the GIC cpu interface register base and size.
+Optional
+- interrupts    : Interrupt source of the parent interrupt controller. Only
+  present on secondary GICs.
+- cpu-offset    : per-cpu offset within the distributor and cpu interface
+  regions, used when the GIC doesn't have banked registers. The offset is
+  cpu-offset * cpu-nr.
+Example:
+        intc: interrupt-controller@fff11000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0xfff11000 0x1000>,
+                      <0xfff10100 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/insignal-boards.txt b/Documentation/devicetree/bindings/arm/insignal-boards.txt
new file mode 100644
index 000000000000..524c3dc5d808
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/insignal-boards.txt
@@ -0,0 +1,8 @@
+* Insignal's Exynos4210 based Origen evaluation board
+Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
+Required root node properties:
+    - compatible = should be one or more of the following.
+        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
+        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
new file mode 100644
index 000000000000..7ca52161e7ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -0,0 +1,44 @@
+* ARM L2 Cache Controller
+ARM cores often have a separate level 2 cache controller. There are various
+implementations of the L2 cache controller with compatible programming models.
+The ARM L2 cache representation in the device tree should be done as follows:
+Required properties:
+- compatible : should be one of:
+        "arm,pl310-cache"
+        "arm,l220-cache"
+        "arm,l210-cache"
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+  registers.
+Optional properties:
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
+  read, write and setup latencies. Minimum valid values are 1. Controllers
+  without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
+  read, write and setup latencies. Controllers without setup latency control
+  should use 0. Controllers without separate read and write Tag RAM latency
+  values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : <start length> Starting address and length of window to
+  filter. Addresses in the filter window are directed to the M1 port. Other
+  addresses will go to the M0 port.
+- interrupts : 1 combined interrupt.
+Example:
+L2: cache-controller {
+        compatible = "arm,pl310-cache";
+        reg = <0xfff12000 0x1000>;
+        arm,data-latency = <1 1 1>;
+        arm,tag-latency = <2 2 2>;
+        arm,filter-latency = <0x80000000 0x8000000>;
+        cache-unified;
+        cache-level = <2>;
+        interrupts = <45>;
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/dsp.txt b/Documentation/devicetree/bindings/arm/omap/dsp.txt
new file mode 100644
index 000000000000..d3830a32ce08
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/dsp.txt
@@ -0,0 +1,14 @@
+* TI - DSP (Digital Signal Processor)
+TI DSP included in OMAP SoC
+Required properties:
+- compatible : Should be "ti,omap3-c64" for OMAP3 & 4
+- ti,hwmods: "dsp"
+Examples:
+dsp {
+    compatible = "ti,omap3-c64";
+    ti,hwmods = "dsp";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/iva.txt b/Documentation/devicetree/bindings/arm/omap/iva.txt
new file mode 100644
index 000000000000..6d6295171358
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/iva.txt
@@ -0,0 +1,19 @@
+* TI - IVA (Imaging and Video Accelerator) subsystem
+The IVA contain various audio, video or imaging HW accelerator
+depending of the version.
+Required properties:
+- compatible : Should be:
+  - "ti,ivahd" for OMAP4
+  - "ti,iva2.2" for OMAP3
+  - "ti,iva2.1" for OMAP2430
+  - "ti,iva1" for OMAP2420
+- ti,hwmods: "iva"
+Examples:
+iva {
+    compatible = "ti,ivahd", "ti,iva";
+    ti,hwmods = "iva";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/l3-noc.txt b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
new file mode 100644
index 000000000000..6888a5efc860
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/l3-noc.txt
@@ -0,0 +1,19 @@
+* TI - L3 Network On Chip (NoC)
+This version is an implementation of the generic NoC IP
+provided by Arteris.
+Required properties:
+- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
+               Should be "ti,omap4-l3-noc" for OMAP4 family
+- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
+Examples:
+ocp {
+        compatible = "ti,omap4-l3-noc", "simple-bus";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+        ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
new file mode 100644
index 000000000000..1a5a42ce21bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -0,0 +1,27 @@
+* TI - MPU (Main Processor Unit) subsystem
+The MPU subsystem contain one or several ARM cores
+depending of the version.
+The MPU contain CPUs, GIC, L2 cache and a local PRCM.
+Required properties:
+- compatible : Should be "ti,omap3-mpu" for OMAP3
+               Should be "ti,omap4-mpu" for OMAP4
+- ti,hwmods: "mpu"
+Examples:
+- For an OMAP4 SMP system:
+mpu {
+    compatible = "ti,omap4-mpu";
+    ti,hwmods = "mpu";
+};
+- For an OMAP3 monocore system:
+mpu {
+    compatible = "ti,omap3-mpu";
+    ti,hwmods = "mpu";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
new file mode 100644
index 000000000000..dbdab40ed3a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -0,0 +1,43 @@
+* Texas Instruments OMAP
+OMAP is currently using a static file per SoC family to describe the
+IPs present in the SoC.
+On top of that an omap_device is created to extend the platform_device
+capabilities and to allow binding with one or several hwmods.
+The hwmods will contain all the information to build the device:
+adresse range, irq lines, dma lines, interconnect, PRCM register,
+clock domain, input clocks.
+For the moment just point to the existing hwmod, the next step will be
+to move data from hwmod to device-tree representation.
+Required properties:
+- compatible: Every devices present in OMAP SoC should be in the
+  form: "ti,XXX"
+- ti,hwmods: list of hwmod names (ascii strings), that comes from the OMAP
+  HW documentation, attached to a device. Must contain at least
+  one hwmod.
+Optional properties:
+- ti,no_idle_on_suspend: When present, it prevents the PM to idle the module
+  during suspend.
+Example:
+spinlock@1 {
+    compatible = "ti,omap4-spinlock";
+    ti,hwmods = "spinlock";
+};
+Boards:
+- OMAP3 BeagleBoard : Low cost community board
+  compatible = "ti,omap3-beagle", "ti,omap3"
+- OMAP4 SDP : Software Developement Board
+  compatible = "ti,omap4-sdp", "ti,omap4430"
+- OMAP4 PandaBoard : Low cost community board
+  compatible = "ti,omap4-panda", "ti,omap4430"
diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt
new file mode 100644
index 000000000000..e75c0ef51e69
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/picoxcell.txt
@@ -0,0 +1,24 @@
+Picochip picoXcell device tree bindings.
+========================================
+Required root node properties:
+    - compatible:
+        - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
+        - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
+        - "picochip,pc3x3" : picoXcell PC3X3 device based board.
+        - "picochip,pc3x2" : picoXcell PC3X2 device based board.
+Timers required properties:
+    - compatible = "picochip,pc3x2-timer"
+    - interrupts : The single IRQ line for the timer.
+    - clock-freq : The frequency in HZ of the timer.
+    - reg : The register bank for the timer.
+Note: two timers are required - one for the scheduler clock and one for the
+event tick/NOHZ.
+VIC required properties:
+    - compatible = "arm,pl192-vic".
+    - interrupt-controller.
+    - reg : The register bank for the device.
+    - #interrupt-cells : Must be 1.
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
index 1d5d7a870ec7..951ca46789d4 100644
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ b/Documentation/devicetree/bindings/arm/primecell.txt
@@ -6,7 +6,9 @@ driver matching.
 Required properties:
- compatible : should be a specific value for peripheral and "arm,primecell"
+- compatible : should be a specific name for the peripheral and
+               "arm,primecell".  The specific name will match the ARM
+               engineering name for the logic block in the form: "arm,pl???"
 Optional properties:
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt
new file mode 100644
index 000000000000..0bf68be56fd1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
@@ -0,0 +1,8 @@
+* Samsung's Exynos4210 based SMDKV310 evaluation board
+SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC.
+Required root node properties:
+    - compatible = should be one or more of the following.
+        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
+        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
new file mode 100644
index 000000000000..6e69d2e5e766
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -0,0 +1,14 @@
+NVIDIA Tegra device tree bindings
+-------------------------------------------
+Boards with the tegra20 SoC shall have the following properties:
+Required root node property:
+compatible = "nvidia,tegra20";
+Boards with the tegra30 SoC shall have the following properties:
+Required root node property:
+compatible = "nvidia,tegra30";
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
new file mode 100644
index 000000000000..266716b23437
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vic.txt
@@ -0,0 +1,29 @@
+* ARM Vectored Interrupt Controller
+One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
+system for interrupt routing.  For multiple controllers they can either be
+nested or have the outputs wire-OR'd together.
+Required properties:
+- compatible : should be one of
+        "arm,pl190-vic"
+        "arm,pl192-vic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : The number of cells to define the interrupts.  Must be 1 as
+  the VIC has no configuration options for interrupt sources.  The cell is a u32
+  and defines the interrupt number.
+- reg : The register bank for the VIC.
+Optional properties:
+- interrupts : Interrupt source for parent controllers if the VIC is nested.
+Example:
+        vic0: interrupt-controller@60000 {
+                compatible = "arm,pl192-vic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x60000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/ata/calxeda-sata.txt b/Documentation/devicetree/bindings/ata/calxeda-sata.txt
new file mode 100644
index 000000000000..79caa5651f53
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/calxeda-sata.txt
@@ -0,0 +1,17 @@
+* Calxeda SATA Controller
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller should have its own node.
+Required properties:
+- compatible        : compatible list, contains "calxeda,hb-ahci"
+- interrupts        : <interrupt mapping for SATA IRQ>
+- reg               : <registers mapping>
+Example:
+        sata@ffe08000 {
+                compatible = "calxeda,hb-ahci";
+                reg = <0xffe08000 0x1000>;
+                interrupts = <115>;
+        };
diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt
new file mode 100644
index 000000000000..a04f5fd30122
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/clocks.txt
@@ -0,0 +1,40 @@
+C6X PLL Clock Controllers
+-------------------------
+This is a first-cut support for the SoC clock controllers. This is still
+under development and will probably change as the common device tree
+clock support is added to the kernel.
+Required properties:
+- compatible: "ti,c64x+pll"
+    May also have SoC-specific value to support SoC-specific initialization
+    in the driver. One of:
+        "ti,c6455-pll"
+        "ti,c6457-pll"
+        "ti,c6472-pll"
+        "ti,c6474-pll"
+- reg: base address and size of register area
+- clock-frequency: input clock frequency in hz
+Optional properties:
+- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
+- ti,c64x+pll-reset-delay:  CPU cycles to delay after PLL reset
+- ti,c64x+pll-lock-delay:   CPU cycles to delay after PLL frequency change
+Example:
+        clock-controller@29a0000 {
+                compatible = "ti,c6472-pll", "ti,c64x+pll";
+                reg = <0x029a0000 0x200>;
+                clock-frequency = <25000000>;
+                ti,c64x+pll-bypass-delay = <200>;
+                ti,c64x+pll-reset-delay = <12000>;
+                ti,c64x+pll-lock-delay = <80000>;
+        };
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt
new file mode 100644
index 000000000000..d847758f2b20
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/dscr.txt
@@ -0,0 +1,127 @@
+Device State Configuration Registers
+------------------------------------
+TI C6X SoCs contain a region of miscellaneous registers which provide various
+function for SoC control or status. Details vary considerably among from SoC
+to SoC with no two being alike.
+In general, the Device State Configuraion Registers (DSCR) will provide one or
+more configuration registers often protected by a lock register where one or
+more key values must be written to a lock register in order to unlock the
+configuration register for writes. These configuration register may be used to
+enable (and disable in some cases) SoC pin drivers, select peripheral clock
+sources (internal or pin), etc. In some cases, a configuration register is
+write once or the individual bits are write once. In addition to device config,
+the DSCR block may provide registers which which are used to reset peripherals,
+provide device ID information, provide ethernet MAC addresses, as well as other
+miscellaneous functions.
+For device state control (enable/disable), each device control is assigned an
+id which is used by individual device drivers to control the state as needed.
+Required properties:
+- compatible: must be "ti,c64x+dscr"
+- reg: register area base and size
+Optional properties:
+  NOTE: These are optional in that not all SoCs will have all properties. For
+        SoCs which do support a given property, leaving the property out of the
+        device tree will result in reduced functionality or possibly driver
+        failure.
+- ti,dscr-devstat
+    offset of the devstat register
+- ti,dscr-silicon-rev
+    offset, start bit, and bitsize of silicon revision field
+- ti,dscr-rmii-resets
+    offset and bitmask of RMII reset field. May have multiple tuples if more
+    than one ethernet port is available.
+- ti,dscr-locked-regs
+    possibly multiple tuples describing registers which are write protected by
+    a lock register. Each tuple consists of the register offset, lock register
+    offsset, and the key value used to unlock the register.
+- ti,dscr-kick-regs
+    offset and key values of two "kick" registers used to write protect other
+    registers in DSCR. On SoCs using kick registers, the first key must be
+    written to the first kick register and the second key must be written to
+    the second register before other registers in the area are write-enabled.
+- ti,dscr-mac-fuse-regs
+    MAC addresses are contained in two registers. Each element of a MAC address
+    is contained in a single byte. This property has two tuples. Each tuple has
+    a register offset and four cells representing bytes in the register from
+    most significant to least. The value of these four cells is the MAC byte
+    index (1-6) of the byte within the register. A value of 0 means the byte
+    is unused in the MAC address.
+- ti,dscr-devstate-ctl-regs
+    This property describes the bitfields used to control the state of devices.
+    Each tuple describes a range of identical bitfields used to control one or
+    more devices (one bitfield per device). The layout of each tuple is:
+        start_id num_ids reg enable disable start_bit nbits
+    Where:
+        start_id is device id for the first device control in the range
+        num_ids is the number of device controls in the range
+        reg is the offset of the register holding the control bits
+        enable is the value to enable a device
+        disable is the value to disable a device (0xffffffff if cannot disable)
+        start_bit is the bit number of the first bit in the range
+        nbits is the number of bits per device control
+- ti,dscr-devstate-stat-regs
+    This property describes the bitfields used to provide device state status
+    for device states controlled by the DSCR. Each tuple describes a range of
+    identical bitfields used to provide status for one or more devices (one
+    bitfield per device). The layout of each tuple is:
+        start_id num_ids reg enable disable start_bit nbits
+    Where:
+        start_id is device id for the first device status in the range
+        num_ids is the number of devices covered by the range
+        reg is the offset of the register holding the status bits
+        enable is the value indicating device is enabled
+        disable is the value indicating device is disabled
+        start_bit is the bit number of the first bit in the range
+        nbits is the number of bits per device status
+- ti,dscr-privperm
+    Offset and default value for register used to set access privilege for
+    some SoC devices.
+Example:
+        device-state-config-regs@2a80000 {
+                compatible = "ti,c64x+dscr";
+                reg = <0x02a80000 0x41000>;
+                ti,dscr-devstat = <0>;
+                ti,dscr-silicon-rev = <8 28 0xf>;
+                ti,dscr-rmii-resets = <0x40020 0x00040000>;
+                ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
+                ti,dscr-devstate-ctl-regs =
+                         <0 12 0x40008 1 0  0  2
+                          12 1 0x40008 3 0 30  2
+                          13 2 0x4002c 1 0xffffffff 0 1>;
+                ti,dscr-devstate-stat-regs =
+                        <0 10 0x40014 1 0  0  3
+                         10 2 0x40018 1 0  0  3>;
+                ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
+                                         0x704 5 6 0 0>;
+                ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
+                ti,dscr-kick-regs = <0x38 0x83E70B13
+                                     0x3c 0x95A4F1E0>;
+        };
diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt
new file mode 100644
index 000000000000..0ff6e9b9a13f
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/emifa.txt
@@ -0,0 +1,62 @@
+External Memory Interface
+-------------------------
+The emifa node describes a simple external bus controller found on some C6X
+SoCs. This interface provides external busses with a number of chip selects.
+Required properties:
+- compatible: must be "ti,c64x+emifa", "simple-bus"
+- reg: register area base and size
+- #address-cells: must be 2 (chip-select + offset)
+- #size-cells: must be 1
+- ranges: mapping from EMIFA space to parent space
+Optional properties:
+- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
+- ti,emifa-burst-priority:
+      Number of memory transfers after which the EMIF will elevate the priority
+      of the oldest command in the command FIFO. Setting this field to 255
+      disables this feature, thereby allowing old commands to stay in the FIFO
+      indefinitely.
+- ti,emifa-ce-config:
+      Configuration values for each of the supported chip selects.
+Example:
+        emifa@70000000 {
+                compatible = "ti,c64x+emifa", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0x70000000 0x100>;
+                ranges = <0x2 0x0 0xa0000000 0x00000008
+                          0x3 0x0 0xb0000000 0x00400000
+                          0x4 0x0 0xc0000000 0x10000000
+                          0x5 0x0 0xD0000000 0x10000000>;
+                ti,dscr-dev-enable = <13>;
+                ti,emifa-burst-priority = <255>;
+                ti,emifa-ce-config = <0x00240120
+                                      0x00240120
+                                      0x00240122
+                                      0x00240122>;
+                flash@3,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x3 0x0 0x400000>;
+                        bank-width = <1>;
+                        device-width = <1>;
+                        partition@0 {
+                                reg = <0x0 0x400000>;
+                                label = "NOR";
+                        };
+                };
+        };
+This shows a flash chip attached to chip select 3.
diff --git a/Documentation/devicetree/bindings/c6x/interrupt.txt b/Documentation/devicetree/bindings/c6x/interrupt.txt
new file mode 100644
index 000000000000..42bb796cc4ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/interrupt.txt
@@ -0,0 +1,104 @@
+C6X Interrupt Chips
+-------------------
+* C64X+ Core Interrupt Controller
+  The core interrupt controller provides 16 prioritized interrupts to the
+  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
+  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
+  sources coming from outside the core.
+  Required properties:
+  --------------------
+  - compatible: Should be "ti,c64x+core-pic";
+  - #interrupt-cells: <1>
+  Interrupt Specifier Definition
+  ------------------------------
+  Single cell specifying the core interrupt priority level (4-15) where
+  4 is highest priority and 15 is lowest priority.
+  Example
+  -------
+  core_pic: interrupt-controller@0 {
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        compatible = "ti,c64x+core-pic";
+  };
+* C64x+ Megamodule Interrupt Controller
+  The megamodule PIC consists of four interrupt mupliplexers each of which
+  combine up to 32 interrupt inputs into a single interrupt output which
+  may be cascaded into the core interrupt controller. The megamodule PIC
+  has a total of 12 outputs cascading into the core interrupt controller.
+  One for each core interrupt priority level. In addition to the combined
+  interrupt sources, individual megamodule interrupts may be cascaded to
+  the core interrupt controller. When an individual interrupt is cascaded,
+  it is no longer handled through a megamodule interrupt combiner and is
+  considered to have the core interrupt controller as the parent.
+  Required properties:
+  --------------------
+  - compatible: "ti,c64x+megamod-pic"
+  - interrupt-controller
+  - #interrupt-cells: <1>
+  - reg: base address and size of register area
+  - interrupt-parent: must be core interrupt controller
+  - interrupts: This should have four cells; one for each interrupt combiner.
+                The cells contain the core priority interrupt to which the
+                corresponding combiner output is wired.
+  Optional properties:
+  --------------------
+  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
+                             priority interrupts. The first cell corresponds to
+                             core priority 4 and the last cell corresponds to
+                             core priority 15. The value of each cell is the
+                             megamodule interrupt source which is MUXed to
+                             the core interrupt corresponding to the cell
+                             position. Allowed values are 4 - 127. Mapping for
+                             interrupts 0 - 3 (combined interrupt sources) are
+                             ignored.
+  Interrupt Specifier Definition
+  ------------------------------
+  Single cell specifying the megamodule interrupt source (4-127). Note that
+  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
+  use the core interrupt controller as their parent and the specifier will
+  be the core priority level, not the megamodule interrupt number.
+  Examples
+  --------
+  megamod_pic: interrupt-controller@1800000 {
+        compatible = "ti,c64x+megamod-pic";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        reg = <0x1800000 0x1000>;
+        interrupt-parent = <&core_pic>;
+        interrupts = < 12 13 14 15 >;
+  };
+  This is a minimal example where all individual interrupts go through a
+  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
+  to interrupt 13, etc.
+  megamod_pic: interrupt-controller@1800000 {
+        compatible = "ti,c64x+megamod-pic";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        reg = <0x1800000 0x1000>;
+        interrupt-parent = <&core_pic>;
+        interrupts = < 12 13 14 15 >;
+        ti,c64x+megamod-pic-mux = <  0  0  0  0
+                                    32  0  0  0
+                                     0  0  0  0 >;
+  };
+  This the same as the first example except that megamodule interrupt 32 is
+  mapped directly to core priority interrupt 8. The node using this interrupt
+  must set the core controller as its interrupt parent and use 8 in the
+  interrupt specifier value.
diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt
new file mode 100644
index 000000000000..b1e4973b5769
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/soc.txt
@@ -0,0 +1,28 @@
+C6X System-on-Chip
+------------------
+Required properties:
+- compatible: "simple-bus"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- ranges
+Optional properties:
+- model: specific SoC model
+- nodes for IP blocks within SoC
+Example:
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6455";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
new file mode 100644
index 000000000000..95911fe70224
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/timer64.txt
@@ -0,0 +1,26 @@
+Timer64
+-------
+The timer64 node describes C6X event timers.
+Required properties:
+- compatible: must be "ti,c64x+timer64"
+- reg: base address and size of register region
+- interrupt-parent: interrupt controller
+- interrupts: interrupt id
+Optional properties:
+- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
+- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
+Example:
+        timer0: timer@25e0000 {
+                compatible = "ti,c64x+timer64";
+                ti,core-mask = < 0x01 >;
+                reg = <0x25e0000 0x40>;
+                interrupt-parent = <&megamod_pic>;
+                interrupts = < 16 >;
+        };
diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
new file mode 100644
index 000000000000..d8609ece1f4c
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
@@ -0,0 +1,23 @@
+Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
+Picochip picoXcell devices contain crypto offload engines that may be used for
+IPSEC and femtocell layer 2 ciphering.
+Required properties:
+  - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
+    "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
+  - reg : Offset and length of the register set for this device
+  - interrupt-parent : The interrupt controller that controls the SPAcc
+    interrupt.
+  - interrupts : The interrupt line from the SPAcc.
+  - ref-clock : The input clock that drives the SPAcc.
+Example SPAcc node:
+spacc@10000 {
+        compatible = "picochip,spacc-ipsec";
+        reg = <0x100000 0x10000>;
+        interrupt-parent = <&vic0>;
+        interrupts = <24>;
+        ref-clock = <&ipsec_clk>, "ref";
+};
diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt b/Documentation/devicetree/bindings/dma/arm-pl330.txt
new file mode 100644
index 000000000000..a4cd273b2a67
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/arm-pl330.txt
@@ -0,0 +1,30 @@
+* ARM PrimeCell PL330 DMA Controller
+The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
+between memory and peripherals or memory to memory.
+Required properties:
+  - compatible: should include both "arm,pl330" and "arm,primecell".
+  - reg: physical base address of the controller and length of memory mapped
+    region.
+  - interrupts: interrupt number to the cpu.
+Example:
+        pdma0: pdma@12680000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0x12680000 0x1000>;
+                interrupts = <99>;
+        };
+Client drivers (device nodes requiring dma transfers from dev-to-mem or
+mem-to-dev) should specify the DMA channel numbers using a two-value pair
+as shown below.
+  [property name]  = <[phandle of the dma controller] [dma request id]>;
+      where 'dma request id' is the dma request number which is connected
+      to the client controller. The 'property name' is recommended to be
+      of the form <name>-dma-channel.
+  Example:  tx-dma-channel = <&pdma0 12>;
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
new file mode 100644
index 000000000000..8f50fe5e6c42
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -0,0 +1,40 @@
+Samsung Exynos4 GPIO Controller
+Required properties:
+- compatible: Compatible property value should be "samsung,exynos4-gpio>".
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
+  should be the following with values derived from the SoC user manual.
+     <[phandle of the gpio controller node]
+      [pin number within the gpio controller]
+      [mux function]
+      [pull up/down]
+      [drive strength]>
+  Values for gpio specifier:
+  - Pin number: is a value between 0 to 7.
+  - Pull Up/Down: 0 - Pull Up/Down Disabled.
+                  1 - Pull Down Enabled.
+                  3 - Pull Up Enabled.
+  - Drive Strength: 0 - 1x,
+                    1 - 3x,
+                    2 - 2x,
+                    3 - 4x
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+Example:
+        gpa0: gpio-controller@11400000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "samsung,exynos4-gpio";
+                reg = <0x11400000 0x20>;
+                #gpio-cells = <4>;
+                gpio-controller;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/led.txt b/Documentation/devicetree/bindings/gpio/led.txt
index 064db928c3c1..141087cf3107 100644
--- a/Documentation/devicetree/bindings/gpio/led.txt
+++ b/Documentation/devicetree/bindings/gpio/led.txt
@@ -8,7 +8,7 @@ node's name represents the name of the corresponding LED.
 LED sub-node properties:
 - gpios :  Should specify the LED's GPIO, see "Specifying GPIO information
-  for devices" in Documentation/powerpc/booting-without-of.txt.  Active
+  for devices" in Documentation/devicetree/booting-without-of.txt.  Active
  low LEDs should be indicated using flags in the GPIO specifier.
 - label :  (optional) The label for this LED.  If omitted, the label is
  taken from the node name (excluding the unit address).
diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt
new file mode 100644
index 000000000000..a2c416bcbccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt
@@ -0,0 +1,10 @@
+ARM PL061 GPIO controller
+Required properties:
+- compatible : "arm,pl061", "arm,primecell"
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional parameters:
+  - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupts : Interrupt mapping for GPIO IRQ.
diff --git a/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt b/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
new file mode 100644
index 000000000000..f3cf43b66f7e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt
@@ -0,0 +1,25 @@
+* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX
+Required properties:
+- compatible : Should be "fsl,<chip>-i2c"
+- reg : Should contain I2C/HS-I2C registers location and length
+- interrupts : Should contain I2C/HS-I2C interrupt
+Optional properties:
+- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
+  The absence of the propoerty indicates the default frequency 100 kHz.
+Examples:
+i2c@83fc4000 { /* I2C2 on i.MX51 */
+        compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+        reg = <0x83fc4000 0x4000>;
+        interrupts = <63>;
+};
+i2c@70038000 { /* HS-I2C on i.MX51 */
+        compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
+        reg = <0x70038000 0x4000>;
+        interrupts = <64>;
+        clock-frequency = <400000>;
+};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
new file mode 100644
index 000000000000..e42a2ee233e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
@@ -0,0 +1,22 @@
+* Synopsys DesignWare I2C
+Required properties :
+ - compatible : should be "snps,designware-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number.
+Recommended properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+Example :
+        i2c@f0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,designware-i2c";
+                reg = <0xf0000 0x1000>;
+                interrupts = <11>;
+                clock-frequency = <400000>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/samsung-i2c.txt b/Documentation/devicetree/bindings/i2c/samsung-i2c.txt
new file mode 100644
index 000000000000..38832c712919
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/samsung-i2c.txt
@@ -0,0 +1,39 @@
+* Samsung's I2C controller
+The Samsung's I2C controller is used to interface with I2C devices.
+Required properties:
+  - compatible: value should be either of the following.
+      (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
+      (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
+  - reg: physical base address of the controller and length of memory mapped
+    region.
+  - interrupts: interrupt number to the cpu.
+  - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
+  - gpios: The order of the gpios should be the following: <SDA, SCL>.
+    The gpio specifier depends on the gpio controller.
+Optional properties:
+  - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not
+    specified, default value is 0.
+  - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
+    specified, the default value in Hz is 100000.
+Example:
+        i2c@13870000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13870000 0x100>;
+                interrupts = <345>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <100000>;
+                gpios = <&gpd1 2 0 /* SDA */
+                         &gpd1 3 0 /* SCL */>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                wm8994@1a {
+                        compatible = "wlf,wm8994";
+                        reg = <0x1a>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
new file mode 100644
index 000000000000..1a85f986961b
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -0,0 +1,58 @@
+This is a list of trivial i2c devices that have simple device tree
+bindings, consisting only of a compatible field, an address and
+possibly an interrupt line.
+If a device needs more specific bindings, such as properties to
+describe some aspect of it, there needs to be a specific binding
+document for it just like any other devices.
+Compatible              Vendor / Chip
+==========              =============
+ad,ad7414               SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
+ad,adm9240              ADM9240:  Complete System Hardware Monitor for uProcessor-Based Systems
+adi,adt7461             +/-1C TDM Extended Temp Range I.C
+adt7461                 +/-1C TDM Extended Temp Range I.C
+at,24c08                i2c serial eeprom  (24cxx)
+atmel,24c02             i2c serial eeprom  (24cxx)
+catalyst,24c32          i2c serial eeprom
+dallas,ds1307           64 x 8, Serial, I2C Real-Time Clock
+dallas,ds1338           I2C RTC with 56-Byte NV RAM
+dallas,ds1339           I2C Serial Real-Time Clock
+dallas,ds1340           I2C RTC with Trickle Charger
+dallas,ds1374           I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
+dallas,ds1631           High-Precision Digital Thermometer
+dallas,ds1682           Total-Elapsed-Time Recorder with Alarm
+dallas,ds1775           Tiny Digital Thermometer and Thermostat
+dallas,ds3232           Extremely Accurate I²C RTC with Integrated Crystal and SRAM
+dallas,ds4510           CPU Supervisor with Nonvolatile Memory and Programmable I/O
+dallas,ds75             Digital Thermometer and Thermostat
+dialog,da9053           DA9053: flexible system level PMIC with multicore support
+epson,rx8025            High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
+epson,rx8581            I2C-BUS INTERFACE REAL TIME CLOCK MODULE
+fsl,mag3110             MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
+fsl,mc13892             MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
+fsl,mma8450             MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
+fsl,mpr121              MPR121: Proximity Capacitive Touch Sensor Controller
+fsl,sgtl5000            SGTL5000: Ultra Low-Power Audio Codec
+maxim,ds1050            5 Bit Programmable, Pulse-Width Modulator
+maxim,max1237           Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
+maxim,max6625           9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
+mc,rv3029c2             Real Time Clock Module with I2C-Bus
+national,lm75           I2C TEMP SENSOR
+national,lm80           Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
+national,lm92           ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
+nxp,pca9556             Octal SMBus and I2C registered interface
+nxp,pca9557             8-bit I2C-bus and SMBus I/O port with reset
+nxp,pcf8563             Real-time clock/calendar
+ovti,ov5642             OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
+pericom,pt7c4338        Real-time Clock Module
+plx,pex8648             48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
+ramtron,24c64           i2c serial eeprom  (24cxx)
+ricoh,rs5c372a          I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+samsung,24ad0xd1        S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
+st-micro,24c256         i2c serial eeprom  (24cxx)
+stm,m41t00              Serial Access TIMEKEEPER
+stm,m41t62              Serial real-time clock (RTC) with alarm
+stm,m41t80              M41T80 - SERIAL ACCESS RTC WITH ALARMS
+ti,tsc2003              I2C Touch-Screen Controller
diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt
new file mode 100644
index 000000000000..ce3e394c0e64
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/samsung-keypad.txt
@@ -0,0 +1,88 @@
+* Samsung's Keypad Controller device tree bindings
+Samsung's Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+Required SoC Specific Properties:
+- compatible: should be one of the following
+  - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
+    controller.
+  - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
+    controller.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: The interrupt number to the cpu.
+Required Board Specific Properties:
+- samsung,keypad-num-rows: Number of row lines connected to the keypad
+  controller.
+- samsung,keypad-num-columns: Number of column lines connected to the
+  keypad controller.
+- row-gpios: List of gpios used as row lines. The gpio specifier for
+  this property depends on the gpio controller to which these row lines
+  are connected.
+- col-gpios: List of gpios used as column lines. The gpio specifier for
+  this property depends on the gpio controller to which these column
+  lines are connected.
+- Keys represented as child nodes: Each key connected to the keypad
+  controller is represented as a child node to the keypad controller
+  device node and should include the following properties.
+  - keypad,row: the row number to which the key is connected.
+  - keypad,column: the column number to which the key is connected.
+  - linux,code: the key-code to be reported when the key is pressed
+    and released.
+Optional Properties specific to linux:
+- linux,keypad-no-autorepeat: do no enable autorepeat feature.
+- linux,keypad-wakeup: use any event on keypad as wakeup event.
+Example:
+        keypad@100A0000 {
+                compatible = "samsung,s5pv210-keypad";
+                reg = <0x100A0000 0x100>;
+                interrupts = <173>;
+                samsung,keypad-num-rows = <2>;
+                samsung,keypad-num-columns = <8>;
+                linux,input-no-autorepeat;
+                linux,input-wakeup;
+                row-gpios = <&gpx2 0 3 3 0
+                             &gpx2 1 3 3 0>;
+                col-gpios = <&gpx1 0 3 0 0
+                             &gpx1 1 3 0 0
+                             &gpx1 2 3 0 0
+                             &gpx1 3 3 0 0
+                             &gpx1 4 3 0 0
+                             &gpx1 5 3 0 0
+                             &gpx1 6 3 0 0
+                             &gpx1 7 3 0 0>;
+                key_1 {
+                        keypad,row = <0>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+                key_2 {
+                        keypad,row = <0>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+                key_3 {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/input/tegra-kbc.txt b/Documentation/devicetree/bindings/input/tegra-kbc.txt
new file mode 100644
index 000000000000..5ecfa99089b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/tegra-kbc.txt
@@ -0,0 +1,18 @@
+* Tegra keyboard controller
+Required properties:
+- compatible: "nvidia,tegra20-kbc"
+Optional properties:
+- debounce-delay: delay in milliseconds per row scan for debouncing
+- repeat-delay: delay in milliseconds before repeat starts
+- ghost-filter: enable ghost filtering for this device
+- wakeup-source: configure keyboard as a wakeup source for suspend/resume
+Example:
+keyboard: keyboard {
+        compatible = "nvidia,tegra20-kbc";
+        reg = <0x7000e200 0x100>;
+        ghost-filter;
+};
diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt
new file mode 100644
index 000000000000..19f6af47a792
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mc13xxx.txt
@@ -0,0 +1,78 @@
+* Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC)
+Required properties:
+- compatible : Should be "fsl,mc13783" or "fsl,mc13892"
+Optional properties:
+- fsl,mc13xxx-uses-adc : Indicate the ADC is being used
+- fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
+- fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
+- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
+Sub-nodes:
+- regulators : Contain the regulator nodes.  The MC13892 regulators are
+  bound using their names as listed below with their registers and bits
+  for enabling.
+    vcoincell : regulator VCOINCELL (register 13, bit 23)
+    sw1       : regulator SW1       (register 24, bit 0)
+    sw2       : regulator SW2       (register 25, bit 0)
+    sw3       : regulator SW3       (register 26, bit 0)
+    sw4       : regulator SW4       (register 27, bit 0)
+    swbst     : regulator SWBST     (register 29, bit 20)
+    vgen1     : regulator VGEN1     (register 32, bit 0)
+    viohi     : regulator VIOHI     (register 32, bit 3)
+    vdig      : regulator VDIG      (register 32, bit 9)
+    vgen2     : regulator VGEN2     (register 32, bit 12)
+    vpll      : regulator VPLL      (register 32, bit 15)
+    vusb2     : regulator VUSB2     (register 32, bit 18)
+    vgen3     : regulator VGEN3     (register 33, bit 0)
+    vcam      : regulator VCAM      (register 33, bit 6)
+    vvideo    : regulator VVIDEO    (register 33, bit 12)
+    vaudio    : regulator VAUDIO    (register 33, bit 15)
+    vsd       : regulator VSD       (register 33, bit 18)
+    gpo1      : regulator GPO1      (register 34, bit 6)
+    gpo2      : regulator GPO2      (register 34, bit 8)
+    gpo3      : regulator GPO3      (register 34, bit 10)
+    gpo4      : regulator GPO4      (register 34, bit 12)
+    pwgt1spi  : regulator PWGT1SPI  (register 34, bit 15)
+    pwgt2spi  : regulator PWGT2SPI  (register 34, bit 16)
+    vusb      : regulator VUSB      (register 50, bit 3)
+  The bindings details of individual regulator device can be found in:
+  Documentation/devicetree/bindings/regulator/regulator.txt
+Examples:
+ecspi@70010000 { /* ECSPI1 */
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
+                   <&gpio3 25 0>; /* GPIO4_25 */
+        status = "okay";
+        pmic: mc13892@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mc13892";
+                spi-max-frequency = <6000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <8>;
+                regulators {
+                        sw1_reg: mc13892__sw1 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1375000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: mc13892__sw2 {
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1850000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/mfd/twl-familly.txt b/Documentation/devicetree/bindings/mfd/twl-familly.txt
new file mode 100644
index 000000000000..a66fcf946759
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/twl-familly.txt
@@ -0,0 +1,47 @@
+Texas Instruments TWL family
+The TWLs are Integrated Power Management Chips.
+Some version might contain much more analog function like
+USB transceiver or Audio amplifier.
+These chips are connected to an i2c bus.
+Required properties:
+- compatible : Must be "ti,twl4030";
+  For Integrated power-management/audio CODEC device used in OMAP3
+  based boards
+- compatible : Must be "ti,twl6030";
+  For Integrated power-management used in OMAP4 based boards
+- interrupts : This i2c device has an IRQ line connected to the main SoC
+- interrupt-controller : Since the twl support several interrupts internally,
+  it is considered as an interrupt controller cascaded to the SoC one.
+- #interrupt-cells = <1>;
+- interrupt-parent : The parent interrupt controller.
+Optional node:
+- Child nodes contain in the twl. The twl family is made of several variants
+  that support a different number of features.
+  The children nodes will thus depend of the capability of the variant.
+Example:
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+twl@48 {
+    compatible = "ti,twl6030";
+    reg = <0x48>;
+    interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
+    interrupt-controller;
+    #interrupt-cells = <1>;
+    interrupt-parent = <&gic>;
+    #address-cells = <1>;
+    #size-cells = <0>;
+    twl_rtc {
+        compatible = "ti,twl_rtc";
+        interrupts = <11>;
+        reg = <0>;
+    };
+};
diff --git a/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
new file mode 100644
index 000000000000..7e51154679a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt
@@ -0,0 +1,27 @@
+* NVIDIA Tegra Secure Digital Host Controller
+This controller on Tegra family SoCs provides an interface for MMC, SD,
+and SDIO types of memory cards.
+Required properties:
+- compatible : Should be "nvidia,<chip>-sdhci"
+- reg : Should contain SD/MMC registers location and length
+- interrupts : Should contain SD/MMC interrupt
+Optional properties:
+- cd-gpios : Specify GPIOs for card detection
+- wp-gpios : Specify GPIOs for write protection
+- power-gpios : Specify GPIOs for power control
+- support-8bit : Boolean, indicates if 8-bit mode should be used.
+Example:
+sdhci@c8000200 {
+        compatible = "nvidia,tegra20-sdhci";
+        reg = <0xc8000200 0x200>;
+        interrupts = <47>;
+        cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+        wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+        power-gpios = <&gpio 155 0>; /* gpio PT3 */
+        support-8bit;
+};
diff --git a/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
new file mode 100644
index 000000000000..ef66ddd01da0
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/atmel-dataflash.txt
@@ -0,0 +1,14 @@
+* Atmel Data Flash
+Required properties:
+- compatible : "atmel,<model>", "atmel,<series>", "atmel,dataflash".
+Example:
+flash@1 {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
+        spi-max-frequency = <25000000>;
+        reg = <1>;
+};
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
new file mode 100644
index 000000000000..719f4dc58df7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
@@ -0,0 +1,44 @@
+GPIO assisted NAND flash
+The GPIO assisted NAND flash uses a memory mapped interface to
+read/write the NAND commands and data and GPIO pins for the control
+signals.
+Required properties:
+- compatible : "gpio-control-nand"
+- reg : should specify localbus chip select and size used for the chip.  The
+  resource describes the data bus connected to the NAND flash and all accesses
+  are made in native endianness.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+  representing partitions.
+- gpios : specifies the gpio pins to control the NAND device.  nwp is an
+  optional gpio and may be set to 0 if not present.
+Optional properties:
+- bank-width : Width (in bytes) of the device.  If not present, the width
+  defaults to 1 byte.
+- chip-delay : chip dependent delay for transferring data from array to
+  read registers (tR).  If not present then a default of 20us is used.
+- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
+  location used to guard against bus reordering with regards to accesses to
+  the GPIO's and the NAND flash data bus.  If present, then after changing
+  GPIO state and before and after command byte writes, this register will be
+  read to ensure that the GPIO accesses have completed.
+Examples:
+gpio-nand@1,0 {
+        compatible = "gpio-control-nand";
+        reg = <1 0x0000 0x2>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        gpios = <&banka 1 0     /* rdy */
+                 &banka 2 0     /* nce */
+                 &banka 3 0     /* ale */
+                 &banka 4 0     /* cle */
+                 0              /* nwp */>;
+        partition@0 {
+        ...
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
new file mode 100644
index 000000000000..411727a3f82d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
@@ -0,0 +1,15 @@
+* Calxeda Highbank 10Gb XGMAC Ethernet
+Required properties:
+- compatible : Should be "calxeda,hb-xgmac"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
+  The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
+Example:
+ethernet@fff50000 {
+        compatible = "calxeda,hb-xgmac";
+        reg = <0xfff50000 0x1000>;
+        interrupts = <0 77 4  0 78 4  0 79 4>;
+};
diff --git a/Documentation/devicetree/bindings/net/can/cc770.txt b/Documentation/devicetree/bindings/net/can/cc770.txt
new file mode 100644
index 000000000000..77027bf6460a
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/cc770.txt
@@ -0,0 +1,53 @@
+Memory mapped Bosch CC770 and Intel AN82527 CAN controller
+Note: The CC770 is a CAN controller from Bosch, which is 100%
+compatible with the old AN82527 from Intel, but with "bugs" being fixed.
+Required properties:
+- compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
+        for the AN82527.
+- reg : should specify the chip select, address offset and size required
+        to map the registers of the controller. The size is usually 0x80.
+- interrupts : property with a value describing the interrupt source
+        (number and sensitivity) required for the controller.
+Optional properties:
+- bosch,external-clock-frequency : frequency of the external oscillator
+        clock in Hz. Note that the internal clock frequency used by the
+        controller is half of that value. If not specified, a default
+        value of 16000000 (16 MHz) is used.
+- bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
+        If not specified or if the specified value is 0, the CLKOUT pin
+        will be disabled.
+- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
+        a resonable value will be calculated.
+- bosch,disconnect-rx0-input : see data sheet.
+- bosch,disconnect-rx1-input : see data sheet.
+- bosch,disconnect-tx1-output : see data sheet.
+- bosch,polarity-dominant : see data sheet.
+- bosch,divide-memory-clock : see data sheet.
+- bosch,iso-low-speed-mux : see data sheet.
+For further information, please have a look to the CC770 or AN82527.
+Examples:
+can@3,100 {
+        compatible = "bosch,cc770";
+        reg = <3 0x100 0x80>;
+        interrupts = <2 0>;
+        interrupt-parent = <&mpic>;
+        bosch,external-clock-frequency = <16000000>;
+};
diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
index 1a729f089866..1ad80d5865a9 100644
--- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
@@ -1,61 +1,24 @@
-CAN Device Tree Bindings
+Flexcan CAN contoller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
------------------------
-2011 Freescale Semiconductor, Inc.
-fsl,flexcan-v1.0 nodes
+Required properties:
-----------------------
-In addition to the required compatible-, reg- and interrupt-properties, you can
-also specify which clock source shall be used for the controller.
-CPI Clock- Can Protocol Interface Clock
+- compatible : Should be "fsl,<processor>-flexcan"
-        This CLK_SRC bit of CTRL(control register) selects the clock source to
-        the CAN Protocol Interface(CPI) to be either the peripheral clock
-        (driven by the PLL) or the crystal oscillator clock. The selected clock
-        is the one fed to the prescaler to generate the Serial Clock (Sclock).
-        The PRESDIV field of CTRL(control register) controls a prescaler that
-        generates the Serial Clock (Sclock), whose period defines the
-        time quantum used to compose the CAN waveform.
-Can Engine Clock Source
+  An implementation should also claim any of the following compatibles
-        There are two sources for CAN clock
+  that it is fully backwards compatible with:
-        - Platform Clock  It represents the bus clock
-        - Oscillator Clock
-        Peripheral Clock (PLL)
+  - fsl,p1010-flexcan
-        --------------
-                     |
-                    ---------                 -------------
-                    |       |CPI Clock        | Prescaler |       Sclock
-                    |       |---------------->| (1.. 256) |------------>
-                    ---------                 -------------
-                     |  |
-        --------------  ---------------------CLK_SRC
-        Oscillator Clock
- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
+- reg : Offset and length of the register set for this device
-                             the peripheral clock. PLL clock is fed to the
+- interrupts : Interrupt tuple for this device
-                             prescaler to generate the Serial Clock (Sclock).
+- clock-frequency : The oscillator frequency driving the flexcan device
-                             Valid values are "oscillator" and "platform"
-                             "oscillator": CAN engine clock source is oscillator clock.
-                             "platform" The CAN engine clock source is the bus clock
-                             (platform clock).
- fsl,flexcan-clock-divider : for the reference and system clock, an additional
+Example:
-                              clock divider can be specified.
- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
-Note:
+        can@1c000 {
-        - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
+                compatible = "fsl,p1010-flexcan";
-        - P1010 does not have oscillator as the Clock Source.So the default
-          Clock Source is platform clock.
-Examples:
-        can0@1c000 {
-                compatible = "fsl,flexcan-v1.0";
                reg = <0x1c000 0x1000>;
                interrupts = <48 0x2>;
                interrupt-parent = <&mpic>;
-                fsl,flexcan-clock-source = "platform";
+                clock-frequency = <200000000>; // filled in by bootloader
-                fsl,flexcan-clock-divider = <2>;
-                clock-frequency = <fixed by u-boot>;
        };
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
new file mode 100644
index 000000000000..44afa0e5057d
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -0,0 +1,25 @@
+* Cadence MACB/GEM Ethernet controller
+Required properties:
+- compatible: Should be "cdns,[<chip>-]{macb|gem}"
+  Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs.
+  Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
+  Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
+  the Cadence GEM, or the generic form: "cdns,gem".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
+- phy-mode: String, operation mode of the PHY interface.
+  Supported values are: "mii", "rmii", "gmii", "rgmii".
+Optional properties:
+- local-mac-address: 6 bytes, mac address
+Examples:
+        macb0: ethernet@fffc4000 {
+                compatible = "cdns,at32ap7000-macb";
+                reg = <0xfffc4000 0x4000>;
+                interrupts = <21>;
+                phy-mode = "rmii";
+                local-mac-address = [3a 0e 03 04 05 06];
+        };
diff --git a/Documentation/devicetree/bindings/net/smsc911x.txt b/Documentation/devicetree/bindings/net/smsc911x.txt
new file mode 100644
index 000000000000..adb5b5744ecd
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/smsc911x.txt
@@ -0,0 +1,38 @@
+* Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
+Required properties:
+- compatible : Should be "smsc,lan<model>", "smsc,lan9115"
+- reg : Address and length of the io space for SMSC LAN
+- interrupts : Should contain SMSC LAN interrupt line
+- interrupt-parent : Should be the phandle for the interrupt controller
+  that services interrupts for this device
+- phy-mode : String, operation mode of the PHY interface.
+  Supported values are: "mii", "gmii", "sgmii", "tbi", "rmii",
+  "rgmii", "rgmii-id", "rgmii-rxid", "rgmii-txid", "rtbi", "smii".
+Optional properties:
+- reg-shift : Specify the quantity to shift the register offsets by
+- reg-io-width : Specify the size (in bytes) of the IO accesses that
+  should be performed on the device.  Valid value for SMSC LAN is
+  2 or 4.  If it's omitted or invalid, the size would be 2.
+- smsc,irq-active-high : Indicates the IRQ polarity is active-high
+- smsc,irq-push-pull : Indicates the IRQ type is push-pull
+- smsc,force-internal-phy : Forces SMSC LAN controller to use
+  internal PHY
+- smsc,force-external-phy : Forces SMSC LAN controller to use
+  external PHY
+- smsc,save-mac-address : Indicates that mac address needs to be saved
+  before resetting the controller
+- local-mac-address : 6 bytes, mac address
+Examples:
+lan9220@f4000000 {
+        compatible = "smsc,lan9220", "smsc,lan9115";
+        reg = <0xf4000000 0x2000000>;
+        phy-mode = "mii";
+        interrupt-parent = <&gpio1>;
+        interrupts = <31>;
+        reg-io-width = <4>;
+        smsc,irq-push-pull;
+};
diff --git a/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt b/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt
new file mode 100644
index 000000000000..5aeee53ff9f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt
@@ -0,0 +1,9 @@
+NVIDIA compliant embedded controller
+Required properties:
+- compatible : should be "nvidia,nvec".
+- reg : the iomem of the i2c slave controller
+- interrupts : the interrupt line of the i2c slave controller
+- clock-frequency : the frequency of the i2c bus
+- gpios : the gpio used for ec request
+- slave-addr: the i2c address of the slave controller
diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
new file mode 100644
index 000000000000..36f82dbdd14d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt
@@ -0,0 +1,5 @@
+NVIDIA Tegra 2 pinmux controller
+Required properties:
+- compatible : "nvidia,tegra20-pinmux"
diff --git a/Documentation/devicetree/bindings/power_supply/olpc_battery.txt b/Documentation/devicetree/bindings/power_supply/olpc_battery.txt
new file mode 100644
index 000000000000..c8901b3992d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/olpc_battery.txt
@@ -0,0 +1,5 @@
+OLPC battery
+~~~~~~~~~~~~
+Required properties:
+  - compatible : "olpc,xo1-battery"
diff --git a/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt b/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt
new file mode 100644
index 000000000000..c40e8926facf
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt
@@ -0,0 +1,23 @@
+SBS sbs-battery
+~~~~~~~~~~
+Required properties :
+ - compatible : "sbs,sbs-battery"
+Optional properties :
+ - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c
+   IO failure.
+ - sbs,poll-retry-count : The number of times to try looking for new status
+   after an external change notification.
+ - sbs,battery-detect-gpios : The gpio which signals battery detection and
+   a flag specifying its polarity.
+Example:
+        bq20z75@b {
+                compatible = "sbs,sbs-battery";
+                reg = < 0xb >;
+                sbs,i2c-retry-count = <2>;
+                sbs,poll-retry-count = <10>;
+                sbs,battery-detect-gpios = <&gpio-controller 122 1>;
+        }
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
index 39e941515a36..380914e965e0 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
@@ -1,3 +1,8 @@
+Freescale Reference Board Bindings
+This document describes device tree bindings for various devices that
+exist on some Freescale reference boards.
 * Board Control and Status (BCSR)
 Required properties:
@@ -12,25 +17,26 @@ Example:
                reg = <f8000000 8000>;
        };
-* Freescale on board FPGA
+* Freescale on-board FPGA
 This is the memory-mapped registers for on board FPGA.
 Required properities:
- compatible : should be "fsl,fpga-pixis".
+- compatible: should be a board-specific string followed by a string
- reg : should contain the address and the length of the FPPGA register
+  indicating the type of FPGA.  Example:
-  set.
+        "fsl,<board>-fpga", "fsl,fpga-pixis"
+- reg: should contain the address and the length of the FPGA register set.
 - interrupt-parent: should specify phandle for the interrupt controller.
- interrupts : should specify event (wakeup) IRQ.
+- interrupts: should specify event (wakeup) IRQ.
-Example (MPC8610HPCD):
+Example (P1022DS):
-        board-control@e8000000 {
+         board-control@3,0 {
-                compatible = "fsl,fpga-pixis";
+                 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
-                reg = <0xe8000000 32>;
+                 reg = <3 0 0x30>;
-                interrupt-parent = <&mpic>;
+                 interrupt-parent = <&mpic>;
-                interrupts = <8 8>;
+                 interrupts = <8 8 0 0>;
-        };
+         };
 * Freescale BCSR GPIO banks
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
new file mode 100644
index 000000000000..9d54eb5a295f
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/dcsr.txt
@@ -0,0 +1,395 @@
+===================================================================
+Debug Control and Status Register (DCSR) Binding
+Copyright 2011 Freescale Semiconductor Inc.
+NOTE: The bindings described in this document are preliminary and subject
+to change.  Some of the compatible strings that contain only generic names
+may turn out to be inappropriate, or need additional properties to describe
+the integration of the block with the rest of the chip.
+=====================================================================
+Debug Control and Status Register Memory Map
+Description
+This node defines the base address and range for the
+defined DCSR Memory Map. Child nodes will describe the individual
+debug blocks defined within this memory space.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr" and "simple-bus".
+        The DCSR space exists in the memory-mapped bus.
+        - #address-cells
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property.  Defines the number of cells
+        or representing physical addresses in child nodes.
+        - #size-cells
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property.  Defines the number of cells
+        or representing the size of physical addresses in
+        child nodes.
+        - ranges
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property. Specifies the physical address
+        range of the DCSR space.
+EXAMPLE
+        dcsr: dcsr@f00000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,dcsr", "simple-bus";
+                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+        };
+=====================================================================
+Event Processing Unit
+This node represents the region of DCSR space allocated to the EPU
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-epu"
+        - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by the EPU.
+        The value of the interrupts property consists of three
+        interrupt specifiers. The format of the specifier is defined
+        by the binding document describing the node's interrupt parent.
+        The EPU counters can be configured to assert the performance
+        monitor interrupt signal based on either counter overflow or value
+        match. Which counter asserted the interrupt is captured in an EPU
+        Counter Interrupt Status Register (EPCPUISR).
+        The EPU unit can also be configured to assert either or both of
+        two interrupt signals based on debug event sources within the SoC.
+        The interrupt signals are epu_xt_int0 and epu_xt_int1.
+        Which event source asserted the interrupt is captured in an EPU
+        Interrupt Status Register (EPISR0,EPISR1).
+        Interrupt numbers are lised in order (perfmon, event0, event1).
+        - interrupt-parent
+        Usage: required
+        Value type: <phandle>
+        Definition: A single <phandle> value that points
+        to the interrupt parent to which the child domain
+        is being mapped. Value must be "&mpic"
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+        dcsr-epu@0 {
+                compatible = "fsl,dcsr-epu";
+                interrupts = <52 2 0 0
+                              84 2 0 0
+                              85 2 0 0>;
+                interrupt-parent = <&mpic>;
+                reg = <0x0 0x1000>;
+        };
+=======================================================================
+Nexus Port Controller
+This node represents the region of DCSR space allocated to the NPC
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-npc"
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+        The Nexus Port controller occupies two regions in the DCSR space
+        with distinct functionality.
+        The first register range describes the Nexus Port Controller
+        control and status registers.
+        The second register range describes the Nexus Port Controller
+        internal trace buffer. The NPC trace buffer is a small memory buffer
+        which stages the nexus trace data for transmission via the Aurora port
+        or to a DDR based trace buffer. In some configurations the NPC trace
+        buffer can be the only trace buffer used.
+EXAMPLE
+                dcsr-npc {
+                        compatible = "fsl,dcsr-npc";
+                        reg = <0x1000 0x1000 0x1000000 0x8000>;
+                };
+=======================================================================
+Nexus Concentrator
+This node represents the region of DCSR space allocated to the NXC
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-nxc"
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-nxc@2000 {
+                        compatible = "fsl,dcsr-nxc";
+                        reg = <0x2000 0x1000>;
+                };
+=======================================================================
+CoreNet Debug Controller
+This node represents the region of DCSR space allocated to
+the CoreNet Debug controller.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-corenet"
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+        The CoreNet Debug controller occupies two regions in the DCSR space
+        with distinct functionality.
+        The first register range describes the CoreNet Debug Controller
+        functionalty to perform transaction and transaction attribute matches.
+        The second register range describes the CoreNet Debug Controller
+        functionalty to trigger event notifications and debug traces.
+EXAMPLE
+                dcsr-corenet {
+                        compatible = "fsl,dcsr-corenet";
+                        reg = <0x8000 0x1000 0xB0000 0x1000>;
+                };
+=======================================================================
+Data Path Debug controller
+This node represents the region of DCSR space allocated to
+the DPAA Debug Controller. This controller controls debug configuration
+for the QMAN and FMAN blocks.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
+        generic compatible string "fsl,dcsr-dpaa".
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-dpaa@9000 {
+                        compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
+                        reg = <0x9000 0x1000>;
+                };
+=======================================================================
+OCeaN Debug controller
+This node represents the region of DCSR space allocated to
+the OCN Debug Controller.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
+        generic compatible string "fsl,dcsr-ocn".
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-ocn@11000 {
+                        compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
+                        reg = <0x11000 0x1000>;
+                };
+=======================================================================
+DDR Controller Debug controller
+This node represents the region of DCSR space allocated to
+the OCN Debug Controller.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,dcsr-ddr"
+        - dev-handle
+        Usage: required
+        Definition: A phandle to associate this debug node with its
+        component controller.
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-ddr@12000 {
+                        compatible = "fsl,dcsr-ddr";
+                        dev-handle = <&ddr1>;
+                        reg = <0x12000 0x1000>;
+                };
+=======================================================================
+Nexus Aurora Link Controller
+This node represents the region of DCSR space allocated to
+the NAL Controller.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
+        generic compatible string "fsl,dcsr-nal".
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-nal@18000 {
+                        compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
+                        reg = <0x18000 0x1000>;
+                };
+=======================================================================
+Run Control and Power Management
+This node represents the region of DCSR space allocated to
+the RCPM Debug Controller. This functionlity is limited to the
+control the debug operations of the SoC and cores.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the SoC
+        or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
+        generic compatible string "fsl,dcsr-rcpm".
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-rcpm@22000 {
+                        compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
+                        reg = <0x22000 0x1000>;
+                };
+=======================================================================
+Core Service Bridge Proxy
+This node represents the region of DCSR space allocated to
+the Core Service Bridge Proxies.
+There is one Core Service Bridge Proxy device for each CPU in the system.
+This functionlity provides access to the debug operations of the CPU.
+PROPERTIES
+        - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include both an identifier specific to the cpu
+        of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
+        generic compatible string "fsl,dcsr-cpu-sb-proxy".
+        - cpu-handle
+        Usage: required
+        Definition: A phandle to associate this debug node with its cpu.
+        - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address
+        offset and length of the DCSR space registers of the device
+        configuration block.
+EXAMPLE
+                dcsr-cpu-sb-proxy@40000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy",
+                                     "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu0>;
+                        reg = <0x40000 0x1000>;
+                };
+                dcsr-cpu-sb-proxy@41000 {
+                        compatible = "fsl,dcsr-e500mc-sb-proxy",
+                                     "fsl,dcsr-cpu-sb-proxy";
+                        cpu-handle = <&cpu1>;
+                        reg = <0x41000 0x1000>;
+                };
+=======================================================================
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 70558c3f3682..5d586e1ccaf5 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -25,6 +25,16 @@ Required properties:
  are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
  to MPIC.
+Optional properties:
+- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
+  is used for MSI messaging.  The address of MSIIR in PCI address space is
+  the MSI message address.
+  This property may be used in virtualized environments where the hypervisor
+  has created an alternate mapping for the MSIR block.  See below for an
+  explanation.
 Example:
        msi@41600 {
                compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
@@ -41,3 +51,35 @@ Example:
                        0xe7 0>;
                interrupt-parent = <&mpic>;
        };
+The Freescale hypervisor and msi-address-64
+-------------------------------------------
+Normally, PCI devices have access to all of CCSR via an ATMU mapping.  The
+Freescale MSI driver calculates the address of MSIIR (in the MSI register
+block) and sets that address as the MSI message address.
+In a virtualized environment, the hypervisor may need to create an IOMMU
+mapping for MSIIR.  The Freescale ePAPR hypervisor has this requirement
+because of hardware limitations of the Peripheral Access Management Unit
+(PAMU), which is currently the only IOMMU that the hypervisor supports.
+The ATMU is programmed with the guest physical address, and the PAMU
+intercepts transactions and reroutes them to the true physical address.
+In the PAMU, each PCI controller is given only one primary window.  The
+PAMU restricts DMA operations so that they can only occur within a window.
+Because PCI devices must be able to DMA to memory, the primary window must
+be used to cover all of the guest's memory space.
+PAMU primary windows can be divided into 256 subwindows, and each
+subwindow can have its own address mapping ("guest physical" to "true
+physical").  However, each subwindow has to have the same alignment, which
+means they cannot be located at just any address.  Because of these
+restrictions, it is usually impossible to create a 4KB subwindow that
+covers MSIIR where it's normally located.
+Therefore, the hypervisor has to create a subwindow inside the same
+primary window used for memory, but mapped to the MSIR block (where MSIIR
+lives).  The first subwindow after the end of guest memory is used for
+this.  The address specified in the msi-address-64 property is the PCI
+address of MSIIR.  The hypervisor configures the PAMU to map that address to
+the true physical address of MSIIR.
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
new file mode 100644
index 000000000000..b9a8a2bcfae7
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
@@ -0,0 +1,163 @@
+Message unit node:
+For SRIO controllers that implement the message unit as part of the controller
+this node is required.  For devices with RMAN this node should NOT exist.  The
+node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
+"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
+See srio.txt for more details about generic SRIO controller details.
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - fsl,liodn
+        Usage: optional-but-recommended (for devices with PAMU)
+        Value type: <prop-encoded-array>
+        Definition: The logical I/O device number for the PAMU (IOMMU) to be
+                correctly configured for SRIO accesses.  The property should
+                not exist on devices that do not support PAMU.
+                The LIODN value is associated with all RMU transactions
+                (msg-unit, doorbell, port-write).
+Sub-Nodes for RMU:  The RMU node is composed of multiple sub-nodes that
+correspond to the actual sub-controllers in the RMU.  The manual for a given
+SoC will detail which and how many of these sub-controllers are implemented.
+Message Unit:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit".
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A pair of IRQs are specified in this property.  The first
+                element is associated with the transmit (TX) interrupt and the
+                second element is associated with the receive (RX) interrupt.
+Doorbell Unit:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include:
+                "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit"
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A pair of IRQs are specified in this property.  The first
+                element is associated with the transmit (TX) interrupt and the
+                second element is associated with the receive (RX) interrupt.
+Port-Write Unit:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include:
+                 "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit"
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A single IRQ that handles port-write conditions is
+                specified by this property.  (Typically shared with error).
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+Example:
+        rmu: rmu@d3000 {
+                compatible = "fsl,srio-rmu";
+                reg = <0xd3000 0x400>;
+                ranges = <0x0 0xd3000 0x400>;
+                fsl,liodn = <0xc8>;
+                message-unit@0 {
+                        compatible = "fsl,srio-msg-unit";
+                        reg = <0x0 0x100>;
+                        interrupts = <
+                                60 2 0 0  /* msg1_tx_irq */
+                                61 2 0 0>;/* msg1_rx_irq */
+                };
+                message-unit@100 {
+                        compatible = "fsl,srio-msg-unit";
+                        reg = <0x100 0x100>;
+                        interrupts = <
+                                62 2 0 0  /* msg2_tx_irq */
+                                63 2 0 0>;/* msg2_rx_irq */
+                };
+                doorbell-unit@400 {
+                        compatible = "fsl,srio-dbell-unit";
+                        reg = <0x400 0x80>;
+                        interrupts = <
+                                56 2 0 0  /* bell_outb_irq */
+                                57 2 0 0>;/* bell_inb_irq */
+                };
+                port-write-unit@4e0 {
+                        compatible = "fsl,srio-port-write-unit";
+                        reg = <0x4e0 0x20>;
+                        interrupts = <16 2 1 11>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
new file mode 100644
index 000000000000..b039bcbee134
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
@@ -0,0 +1,103 @@
+* Freescale Serial RapidIO (SRIO) Controller
+RapidIO port node:
+Properties:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,srio" for IP blocks with IP Block
+        Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
+        Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major
+        version in IP Block Revision Register and Y is Minor version.  If this
+        compatiable is provided it should be ordered before "fsl,srio".
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers.  The size should
+                be set to 0x11000.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A single IRQ that handles error conditions is specified by this
+                property.  (Typically shared with port-write).
+   - fsl,srio-rmu-handle:
+        Usage: required if rmu node is defined
+        Value type: <phandle>
+        Definition: A single <phandle> value that points to the RMU.
+        (See srio-rmu.txt for more details on RMU node binding)
+Port Child Nodes:  There should a port child node for each port that exists in
+the controller.  The ports are numbered starting at one (1) and should have
+the following properties:
+   - cell-index
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property.  Matches the port id.
+   - ranges
+        Usage: required if local access windows preset
+        Value type: <prop-encoded-array>
+        Definition: A standard property. Utilized to describe the memory mapped
+                IO space utilized by the controller.  This corresponds to the
+                setting of the local access windows that are targeted to this
+                SRIO port.
+   - fsl,liodn
+        Usage: optional-but-recommended (for devices with PAMU)
+        Value type: <prop-encoded-array>
+        Definition: The logical I/O device number for the PAMU (IOMMU) to be
+                correctly configured for SRIO accesses.  The property should
+                not exist on devices that do not support PAMU.
+                For HW (ie, the P4080) that only supports a LIODN for both
+                memory and maintenance transactions then a single LIODN is
+                represented in the property for both transactions.
+                For HW (ie, the P304x/P5020, etc) that supports an LIODN for
+                memory transactions and a unique LIODN for maintenance
+                transactions then a pair of LIODNs are represented in the
+                property.  Within the pair, the first element represents the
+                LIODN associated with memory transactions and the second element
+                represents the LIODN associated with maintenance transactions
+                for the port.
+Note: All other standard properties (see ePAPR) are allowed but are optional.
+Example:
+        rapidio: rapidio@ffe0c0000 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+                compatible = "fsl,srio";
+                interrupts = <16 2 1 11>; /* err_irq */
+                fsl,srio-rmu-handle = <&rmu>;
+                ranges;
+                port1 {
+                        cell-index = <1>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        fsl,liodn = <34>;
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        cell-index = <2>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        fsl,liodn = <48>;
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
new file mode 100644
index 000000000000..9cf57fd042d2
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -0,0 +1,29 @@
+Fixed Voltage regulators
+Required properties:
+- compatible: Must be "regulator-fixed";
+Optional properties:
+- gpio: gpio to use for enable control
+- startup-delay-us: startup time in microseconds
+- enable-active-high: Polarity of GPIO is Active high
+If this property is missing, the default assumed is Active low.
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+However a fixed voltage regulator is expected to have the
+regulator-min-microvolt and regulator-max-microvolt
+to be the same.
+Example:
+        abc: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio1 16 0>;
+                startup-delay-us = <70000>;
+                enable-active-high;
+                regulator-boot-on
+        };
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt
new file mode 100644
index 000000000000..5b7a408acdaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/regulator.txt
@@ -0,0 +1,54 @@
+Voltage/Current Regulators
+Optional properties:
+- regulator-name: A string used as a descriptive name for regulator outputs
+- regulator-min-microvolt: smallest voltage consumers may set
+- regulator-max-microvolt: largest voltage consumers may set
+- regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops
+- regulator-min-microamp: smallest current consumers may set
+- regulator-max-microamp: largest current consumers may set
+- regulator-always-on: boolean, regulator should never be disabled
+- regulator-boot-on: bootloader/firmware enabled regulator
+- <name>-supply: phandle to the parent supply/regulator node
+Example:
+        xyzreg: regulator@0 {
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <2500000>;
+                regulator-always-on;
+                vin-supply = <&vin>;
+        };
+Regulator Consumers:
+Consumer nodes can reference one or more of its supplies/
+regulators using the below bindings.
+- <name>-supply: phandle to the regulator node
+These are the same bindings that a regulator in the above
+example used to reference its own supply, in which case
+its just seen as a special case of a regulator being a
+consumer itself.
+Example of a consumer device node (mmc) referencing two
+regulators (twl_reg1 and twl_reg2),
+        twl_reg1: regulator@0 {
+                ...
+                ...
+                ...
+        };
+        twl_reg2: regulator@1 {
+                ...
+                ...
+                ...
+        };
+        mmc: mmc@0x0 {
+                ...
+                ...
+                vmmc-supply = <&twl_reg1>;
+                vmmcaux-supply = <&twl_reg2>;
+        };
diff --git a/Documentation/devicetree/bindings/resource-names.txt b/Documentation/devicetree/bindings/resource-names.txt
new file mode 100644
index 000000000000..e280fef6f265
--- /dev/null
+++ b/Documentation/devicetree/bindings/resource-names.txt
@@ -0,0 +1,54 @@
+Some properties contain an ordered list of 1 or more datum which are
+normally accessed by index.  However, some devices will have multiple
+values which are more naturally accessed by name.  Device nodes can
+include a supplemental property for assigning names to each of the list
+items.  The names property consists of a list of strings in the same
+order as the data in the resource property.
+The following supplemental names properties are defined.
+Resource Property       Supplemental Names Property
+-----------------       ---------------------------
+reg                     reg-names
+clocks                  clock-names
+interrupts              interrupt-names
+Usage:
+The -names property must be used in conjunction with the normal resource
+property. If not it will be ignored.
+Examples:
+l4-abe {
+        compatible = "simple-bus";
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
+                 <1 0 0x49000000 0x00001000>; /* L3 path */
+        mcasp {
+                compatible = "ti,mcasp";
+                reg = <0 0x10 0x10>, <0 0x20 0x10>,
+                      <1 0x10 0x10>, <1 0x20 0x10>;
+                reg-names = "mpu", "dat",
+                            "dma", "dma_dat";
+                interrupts = <11>, <12>;
+                interrupt-names = "rx", "tx";
+        };
+        timer {
+                compatible = "ti,timer";
+                reg = <0 0x40 0x10>, <1 0x40 0x10>;
+                reg-names = "mpu", "dma";
+        };
+};
+usb {
+        compatible = "ti,usb-host";
+        reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
+              <0x4a064c00 0x200>;
+        reg-names = "config", "ohci", "ehci";
+        interrupts = <14>, <15>;
+        interrupt-names = "ohci", "ehci";
+};
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
new file mode 100644
index 000000000000..90ec45fd33ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
@@ -0,0 +1,20 @@
+* Samsung's S3C Real Time Clock controller
+Required properties:
+- compatible: should be one of the following.
+    * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
+    * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: Two interrupt numbers to the cpu should be specified. First
+  interrupt number is the rtc alarm interupt and second interrupt number
+  is the rtc tick interrupt. The number of cells representing a interrupt
+  depends on the parent interrupt controller.
+Example:
+        rtc@10070000 {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x10070000 0x100>;
+                interrupts = <44 0 45 0>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt
new file mode 100644
index 000000000000..596e0c97be7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/twl-rtc.txt
@@ -0,0 +1,12 @@
+* TI twl RTC
+The TWL family (twl4030/6030) contains a RTC.
+Required properties:
+- compatible : Should be twl4030-rtc
+Examples:
+rtc@0 {
+    compatible = "ti,twl4030-rtc";
+};
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
new file mode 100644
index 000000000000..342eedd10050
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -0,0 +1,10 @@
+OMAP UART controller
+Required properties:
+- compatible : should be "ti,omap2-uart" for OMAP2 controllers
+- compatible : should be "ti,omap3-uart" for OMAP3 controllers
+- compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
+Optional properties:
+- clock-frequency : frequency of the clock input to the UART
diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt
new file mode 100644
index 000000000000..1e753c69fc83
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/rs485.txt
@@ -0,0 +1,31 @@
+* RS485 serial communications
+The RTS signal is capable of automatically controlling line direction for
+the built-in half-duplex mode.
+The properties described hereafter shall be given to a half-duplex capable
+UART node.
+Required properties:
+- rs485-rts-delay: prop-encoded-array <a b> where:
+  * a is the delay beteween rts signal and beginning of data sent in milliseconds.
+      it corresponds to the delay before sending data.
+  * b is the delay between end of data sent and rts signal in milliseconds
+      it corresponds to the delay after sending data and actual release of the line.
+Optional properties:
+- linux,rs485-enabled-at-boot-time: empty property telling to enable the rs485
+  feature at boot time. It can be disabled later with proper ioctl.
+- rs485-rx-during-tx: empty property that enables the receiving of data even
+  whilst sending data.
+RS485 example for Atmel USART:
+        usart0: serial@fff8c000 {
+                compatible = "atmel,at91sam9260-usart";
+                reg = <0xfff8c000 0x4000>;
+                interrupts = <7>;
+                atmel,use-dma-rx;
+                atmel,use-dma-tx;
+                linux,rs485-enabled-at-boot-time;
+                rs485-rts-delay = <0 200>;              // in milliseconds
+        };
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt b/Documentation/devicetree/bindings/serial/samsung_uart.txt
new file mode 100644
index 000000000000..2c8a17cf5cb5
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.txt
@@ -0,0 +1,14 @@
+* Samsung's UART Controller
+The Samsung's UART controller is used for interfacing SoC with serial communicaion
+devices.
+Required properties:
+- compatible: should be
+  - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports.
+- reg: base physical address of the controller and length of memory mapped
+  region.
+- interrupts: interrupt number to the cpu. The interrupt specifier format depends
+  on the interrupt controller parent.
diff --git a/Documentation/devicetree/bindings/sound/soc/codecs/fsl-sgtl5000.txt b/Documentation/devicetree/bindings/sound/soc/codecs/fsl-sgtl5000.txt
new file mode 100644
index 000000000000..2c3cd413f042
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/soc/codecs/fsl-sgtl5000.txt
@@ -0,0 +1,11 @@
+* Freescale SGTL5000 Stereo Codec
+Required properties:
+- compatible : "fsl,sgtl5000".
+Example:
+codec: sgtl5000@0a {
+        compatible = "fsl,sgtl5000";
+        reg = <0x0a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt
new file mode 100644
index 000000000000..d5b0da8bf1d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt
@@ -0,0 +1,71 @@
+NVIDIA Tegra audio complex
+Required properties:
+- compatible : "nvidia,tegra-audio-wm8903"
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the WM8903's pins, and the jacks on the board:
+  WM8903 pins:
+  * IN1L
+  * IN1R
+  * IN2L
+  * IN2R
+  * IN3L
+  * IN3R
+  * DMICDAT
+  * HPOUTL
+  * HPOUTR
+  * LINEOUTL
+  * LINEOUTR
+  * LOP
+  * LON
+  * ROP
+  * RON
+  * MICBIAS
+  Board connectors:
+  * Headphone Jack
+  * Int Spk
+  * Mic Jack
+- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
+- nvidia,audio-codec : The phandle of the WM8903 audio codec
+Optional properties:
+- nvidia,spkr-en-gpios : The GPIO that enables the speakers
+- nvidia,hp-mute-gpios : The GPIO that mutes the headphones
+- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone
+- nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone
+Example:
+sound {
+        compatible = "nvidia,tegra-audio-wm8903-harmony",
+                     "nvidia,tegra-audio-wm8903"
+        nvidia,model = "tegra-wm8903-harmony";
+        nvidia,audio-routing =
+                "Headphone Jack", "HPOUTR",
+                "Headphone Jack", "HPOUTL",
+                "Int Spk", "ROP",
+                "Int Spk", "RON",
+                "Int Spk", "LOP",
+                "Int Spk", "LON",
+                "Mic Jack", "MICBIAS",
+                "IN1L", "Mic Jack";
+        nvidia,i2s-controller = <&i2s1>;
+        nvidia,audio-codec = <&wm8903>;
+        nvidia,spkr-en-gpios = <&codec 2 0>;
+        nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+        nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+};
diff --git a/Documentation/devicetree/bindings/sound/tegra20-das.txt b/Documentation/devicetree/bindings/sound/tegra20-das.txt
new file mode 100644
index 000000000000..6de3a7ee4efb
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tegra20-das.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra 20 DAS (Digital Audio Switch) controller
+Required properties:
+- compatible : "nvidia,tegra20-das"
+- reg : Should contain DAS registers location and length
+Example:
+das@70000c00 {
+        compatible = "nvidia,tegra20-das";
+        reg = <0x70000c00 0x80>;
+};
diff --git a/Documentation/devicetree/bindings/sound/tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/tegra20-i2s.txt
new file mode 100644
index 000000000000..0df2b5c816e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tegra20-i2s.txt
@@ -0,0 +1,17 @@
+NVIDIA Tegra 20 I2S controller
+Required properties:
+- compatible : "nvidia,tegra20-i2s"
+- reg : Should contain I2S registers location and length
+- interrupts : Should contain I2S interrupt
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this I2S controller
+Example:
+i2s@70002800 {
+        compatible = "nvidia,tegra20-i2s";
+        reg = <0x70002800 0x200>;
+        interrupts = < 45 >;
+        nvidia,dma-request-selector = < &apbdma 2 >;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8510.txt b/Documentation/devicetree/bindings/sound/wm8510.txt
new file mode 100644
index 000000000000..fa1a32b85577
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8510.txt
@@ -0,0 +1,18 @@
+WM8510 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8510"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8510@1a {
+        compatible = "wlf,wm8510";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8523.txt b/Documentation/devicetree/bindings/sound/wm8523.txt
new file mode 100644
index 000000000000..04746186b283
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8523.txt
@@ -0,0 +1,16 @@
+WM8523 audio CODEC
+This device supports I2C only.
+Required properties:
+  - compatible : "wlf,wm8523"
+  - reg : the I2C address of the device.
+Example:
+codec: wm8523@1a {
+        compatible = "wlf,wm8523";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt
new file mode 100644
index 000000000000..7d9821f348da
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8580.txt
@@ -0,0 +1,16 @@
+WM8580 audio CODEC
+This device supports I2C only.
+Required properties:
+  - compatible : "wlf,wm8580"
+  - reg : the I2C address of the device.
+Example:
+codec: wm8580@1a {
+        compatible = "wlf,wm8580";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8711.txt b/Documentation/devicetree/bindings/sound/wm8711.txt
new file mode 100644
index 000000000000..8ed9998cd23c
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8711.txt
@@ -0,0 +1,18 @@
+WM8711 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8711"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8711@1a {
+        compatible = "wlf,wm8711";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8728.txt b/Documentation/devicetree/bindings/sound/wm8728.txt
new file mode 100644
index 000000000000..a8b5c3668e60
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8728.txt
@@ -0,0 +1,18 @@
+WM8728 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8728"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8728@1a {
+        compatible = "wlf,wm8728";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8731.txt b/Documentation/devicetree/bindings/sound/wm8731.txt
new file mode 100644
index 000000000000..15f70048469b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8731.txt
@@ -0,0 +1,18 @@
+WM8731 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8731"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8731@1a {
+        compatible = "wlf,wm8731";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8737.txt b/Documentation/devicetree/bindings/sound/wm8737.txt
new file mode 100644
index 000000000000..4bc2cea3b140
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8737.txt
@@ -0,0 +1,18 @@
+WM8737 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8737"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8737@1a {
+        compatible = "wlf,wm8737";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8741.txt b/Documentation/devicetree/bindings/sound/wm8741.txt
new file mode 100644
index 000000000000..74bda58c1bcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8741.txt
@@ -0,0 +1,18 @@
+WM8741 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8741"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8741@1a {
+        compatible = "wlf,wm8741";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8750.txt b/Documentation/devicetree/bindings/sound/wm8750.txt
new file mode 100644
index 000000000000..8db239fd5ecd
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8750.txt
@@ -0,0 +1,18 @@
+WM8750 and WM8987 audio CODECs
+These devices support both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8750" or "wlf,wm8987"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8750@1a {
+        compatible = "wlf,wm8750";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8753.txt b/Documentation/devicetree/bindings/sound/wm8753.txt
new file mode 100644
index 000000000000..e65277a0fb60
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8753.txt
@@ -0,0 +1,18 @@
+WM8753 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8753"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8737@1a {
+        compatible = "wlf,wm8753";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8770.txt b/Documentation/devicetree/bindings/sound/wm8770.txt
new file mode 100644
index 000000000000..866e00ca150b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8770.txt
@@ -0,0 +1,16 @@
+WM8770 audio CODEC
+This device supports SPI.
+Required properties:
+  - compatible : "wlf,wm8770"
+  - reg : the chip select number.
+Example:
+codec: wm8770@1 {
+        compatible = "wlf,wm8770";
+        reg = <1>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8776.txt b/Documentation/devicetree/bindings/sound/wm8776.txt
new file mode 100644
index 000000000000..3b9ca49abc2b
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8776.txt
@@ -0,0 +1,18 @@
+WM8776 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8776"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8776@1a {
+        compatible = "wlf,wm8776";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8804.txt b/Documentation/devicetree/bindings/sound/wm8804.txt
new file mode 100644
index 000000000000..4d3a56f38adc
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8804.txt
@@ -0,0 +1,18 @@
+WM8804 audio CODEC
+This device supports both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm8804"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8804@1a {
+        compatible = "wlf,wm8804";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8903.txt b/Documentation/devicetree/bindings/sound/wm8903.txt
new file mode 100644
index 000000000000..f102cbc42694
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8903.txt
@@ -0,0 +1,50 @@
+WM8903 audio CODEC
+This device supports I2C only.
+Required properties:
+  - compatible : "wlf,wm8903"
+  - reg : the I2C address of the device.
+  - gpio-controller : Indicates this device is a GPIO controller.
+  - #gpio-cells : Should be two. The first cell is the pin number and the
+    second cell is used to specify optional parameters (currently unused).
+Optional properties:
+  - interrupts : The interrupt line the codec is connected to.
+  - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the
+    default is 0.
+  - micdet-delay : The debounce delay for microphone detection in mS. If
+    absent, the default is 100.
+  - gpio-cfg : A list of GPIO configuration register values. The list must
+    be 5 entries long. If absent, no configuration of these registers is
+    performed. If any entry has the value 0xffffffff, that GPIO's
+    configuration will not be modified.
+Example:
+codec: wm8903@1a {
+        compatible = "wlf,wm8903";
+        reg = <0x1a>;
+        interrupts = < 347 >;
+        gpio-controller;
+        #gpio-cells = <2>;
+        micdet-cfg = <0>;
+        micdet-delay = <100>;
+        gpio-cfg = <
+                0x0600 /* DMIC_LR, output */
+                0x0680 /* DMIC_DAT, input */
+                0x0000 /* GPIO, output, low */
+                0x0200 /* Interrupt, output */
+                0x01a0 /* BCLK, input, active high */
+        >;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt
new file mode 100644
index 000000000000..7a7eb1e7bda6
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8994.txt
@@ -0,0 +1,18 @@
+WM1811/WM8994/WM8958 audio CODEC
+These devices support both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm1811", "wlf,wm8994", "wlf,wm8958"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8994@1a {
+        compatible = "wlf,wm8994";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/spi/spi_pl022.txt b/Documentation/devicetree/bindings/spi/spi_pl022.txt
new file mode 100644
index 000000000000..306ec3ff3c0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi_pl022.txt
@@ -0,0 +1,12 @@
+ARM PL022 SPI controller
+Required properties:
+- compatible : "arm,pl022", "arm,primecell"
+- reg : Offset and length of the register set for the device
+- interrupts : Should contain SPI controller interrupt
+Optional properties:
+- cs-gpios : should specify GPIOs used for chipselects.
+  The gpios will be referred to as reg = <index> in the SPI child nodes.
+  If unspecified, a single SPI device without a chip select can be used.
diff --git a/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
new file mode 100644
index 000000000000..a49d9a1d4ccf
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/atmel-usart.txt
@@ -0,0 +1,27 @@
+* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART)
+Required properties:
+- compatible: Should be "atmel,<chip>-usart"
+  The compatible <chip> indicated will be the first SoC to support an
+  additional mode or an USART new feature.
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt
+Optional properties:
+- atmel,use-dma-rx: use of PDC or DMA for receiving data
+- atmel,use-dma-tx: use of PDC or DMA for transmitting data
+<chip> compatible description:
+- at91rm9200:  legacy USART support
+- at91sam9260: generic USART implementation for SAM9 SoCs
+Example:
+        usart0: serial@fff8c000 {
+                compatible = "atmel,at91sam9260-usart";
+                reg = <0xfff8c000 0x4000>;
+                interrupts = <7>;
+                atmel,use-dma-rx;
+                atmel,use-dma-tx;
+        };
diff --git a/Documentation/devicetree/bindings/tty/serial/msm_serial.txt b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
new file mode 100644
index 000000000000..aef383eb8876
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/msm_serial.txt
@@ -0,0 +1,27 @@
+* Qualcomm MSM UART
+Required properties:
+- compatible :
+        - "qcom,msm-uart", and one of "qcom,msm-hsuart" or
+          "qcom,msm-lsuart".
+- reg : offset and length of the register set for the device
+        for the hsuart operating in compatible mode, there should be a
+        second pair describing the gsbi registers.
+- interrupts : should contain the uart interrupt.
+There are two different UART blocks used in MSM devices,
+"qcom,msm-hsuart" and "qcom,msm-lsuart".  The msm-serial driver is
+able to handle both of these, and matches against the "qcom,msm-uart"
+as the compatibility.
+The registers for the "qcom,msm-hsuart" device need to specify both
+register blocks, even for the common driver.
+Example:
+        uart@19c400000 {
+                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+                reg = <0x19c40000 0x1000>,
+                      <0x19c00000 0x1000>;
+                interrupts = <195>;
+        };
diff --git a/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt
new file mode 100644
index 000000000000..f13f1c5be91c
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/snps-dw-apb-uart.txt
@@ -0,0 +1,25 @@
+* Synopsys DesignWare ABP UART
+Required properties:
+- compatible : "snps,dw-apb-uart"
+- reg : offset and length of the register set for the device.
+- interrupts : should contain uart interrupt.
+- clock-frequency : the input clock frequency for the UART.
+Optional properties:
+- reg-shift : quantity to shift the register offsets by.  If this property is
+  not present then the register offsets are not shifted.
+- reg-io-width : the size (in bytes) of the IO accesses that should be
+  performed on the device.  If this property is not present then single byte
+  accesses are used.
+Example:
+        uart@80230000 {
+                compatible = "snps,dw-apb-uart";
+                reg = <0x80230000 0x100>;
+                clock-frequency = <3686400>;
+                interrupts = <10>;
+                reg-shift = <2>;
+                reg-io-width = <4>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt
new file mode 100644
index 000000000000..035d63d5646d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt
@@ -0,0 +1,13 @@
+Tegra SOC USB controllers
+The device node for a USB controller that is part of a Tegra
+SOC is as described in the document "Open Firmware Recommended
+Practice : Universal Serial Bus" with the following modifications
+and additions :
+Required properties :
+ - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
+   used in host mode.
+ - phy_type : Should be one of "ulpi" or "utmi".
+ - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
new file mode 100644
index 000000000000..ecc6a6cd26c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -0,0 +1,46 @@
+Device tree binding vendor prefix registry.  Keep list in alphabetical order.
+This isn't an exhaustive list, but you should add new prefixes to it before
+using them to avoid name-space collisions.
+adi     Analog Devices, Inc.
+amcc    Applied Micro Circuits Corporation (APM, formally AMCC)
+apm     Applied Micro Circuits Corporation (APM)
+arm     ARM Ltd.
+atmel   Atmel Corporation
+cavium  Cavium, Inc.
+chrp    Common Hardware Reference Platform
+cortina Cortina Systems, Inc.
+dallas  Maxim Integrated Products (formerly Dallas Semiconductor)
+denx    Denx Software Engineering
+epson   Seiko Epson Corp.
+est     ESTeem Wireless Modems
+fsl     Freescale Semiconductor
+GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+gef     GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+hp      Hewlett Packard
+ibm     International Business Machines (IBM)
+idt     Integrated Device Technologies, Inc.
+intercontrol    Inter Control Group
+linux   Linux-specific binding
+marvell Marvell Technology Group Ltd.
+maxim   Maxim Integrated Products
+mosaixtech      Mosaix Technologies, Inc.
+national        National Semiconductor
+nintendo        Nintendo
+nvidia  NVIDIA
+nxp     NXP Semiconductors
+powervr Imagination Technologies
+qcom    Qualcomm, Inc.
+ramtron Ramtron International
+samsung Samsung Semiconductor
+sbs     Smart Battery System
+schindler       Schindler
+sil     Silicon Image
+simtek
+sirf    SiRF Technology, Inc.
+st      STMicroelectronics
+stericsson      ST-Ericsson
+ti      Texas Instruments
+wlf     Wolfson Microelectronics
+xlnx    Xilinx
diff --git a/Documentation/devicetree/bindings/virtio/mmio.txt b/Documentation/devicetree/bindings/virtio/mmio.txt
new file mode 100644
index 000000000000..5069c1b8e193
--- /dev/null
+++ b/Documentation/devicetree/bindings/virtio/mmio.txt
@@ -0,0 +1,17 @@
+* virtio memory mapped device
+See http://ozlabs.org/~rusty/virtio-spec/ for more details.
+Required properties:
+- compatible:   "virtio,mmio" compatibility string
+- reg:          control registers base address and size including configuration space
+- interrupts:   interrupt generated by the device
+Example:
+        virtio_block@3000 {
+                compatible = "virtio,mmio";
+                reg = <0x3000 0x100>;
+                interrupts = <41>;
+        }