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-rw-r--r--Documentation/devicetree/bindings/video/samsung-fimd.txt30
1 files changed, 28 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b689af..ecc899b9817b 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -8,8 +8,6 @@ Required properties:
8- compatible: value should be one of the following 8- compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ 9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ 10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
12 "samsung,s5pc100-fimd"; /* for S5PC100 SoC */
13 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ 11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
14 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ 12 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
15 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ 13 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
@@ -44,6 +42,34 @@ Optional Properties:
44- display-timings: timing settings for FIMD, as described in document [1]. 42- display-timings: timing settings for FIMD, as described in document [1].
45 Can be used in case timings cannot be provided otherwise 43 Can be used in case timings cannot be provided otherwise
46 or to override timings provided by the panel. 44 or to override timings provided by the panel.
45- samsung,sysreg: handle to syscon used to control the system registers
46- i80-if-timings: timing configuration for lcd i80 interface support.
47 - cs-setup: clock cycles for the active period of address signal is enabled
48 until chip select is enabled.
49 If not specified, the default value(0) will be used.
50 - wr-setup: clock cycles for the active period of CS signal is enabled until
51 write signal is enabled.
52 If not specified, the default value(0) will be used.
53 - wr-active: clock cycles for the active period of CS is enabled.
54 If not specified, the default value(1) will be used.
55 - wr-hold: clock cycles for the active period of CS is disabled until write
56 signal is disabled.
57 If not specified, the default value(0) will be used.
58
59 The parameters are defined as:
60
61 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
62 : : : : :
63 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
64 | cs-setup+1 | : : :
65 |<---------->| : : :
66 Chip Select ???????????????|____________:____________:____________|??
67 | wr-setup+1 | | wr-hold+1 |
68 |<---------->| |<---------->|
69 Write Enable ????????????????????????????|____________|???????????????
70 | wr-active+1|
71 |<---------->|
72 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
47 73
48The device node can contain 'port' child nodes according to the bindings defined 74The device node can contain 'port' child nodes according to the bindings defined
49in [2]. The following are properties specific to those nodes: 75in [2]. The following are properties specific to those nodes: