aboutsummaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
diff options
context:
space:
mode:
Diffstat (limited to 'Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt')
-rw-r--r--Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt17
1 files changed, 13 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
index c4c9e9e664aa..ba797d3e6326 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt
@@ -3,7 +3,7 @@ Tegra SOC USB PHY
3The device node for Tegra SOC USB PHY: 3The device node for Tegra SOC USB PHY:
4 4
5Required properties : 5Required properties :
6 - compatible : Should be "nvidia,tegra20-usb-phy". 6 - compatible : Should be "nvidia,tegra<chip>-usb-phy".
7 - reg : Defines the following set of registers, in the order listed: 7 - reg : Defines the following set of registers, in the order listed:
8 - The PHY's own register set. 8 - The PHY's own register set.
9 Always present. 9 Always present.
@@ -24,17 +24,26 @@ Required properties :
24Required properties for phy_type == ulpi: 24Required properties for phy_type == ulpi:
25 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. 25 - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.
26 26
27Required PHY timing params for utmi phy: 27Required PHY timing params for utmi phy, for all chips:
28 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before 28 - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
29 start of sync launches RxActive 29 start of sync launches RxActive
30 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store 30 - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
31 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait 31 - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
32 before declare IDLE. 32 before declare IDLE.
33 - nvidia,term-range-adj : Range adjusment on terminations 33 - nvidia,term-range-adj : Range adjusment on terminations
34 - nvidia,xcvr-setup : HS driver output control 34 - Either one of the following for HS driver output control:
35 - nvidia,xcvr-setup : integer, uses the provided value.
36 - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
37 from the on-chip fuses
38 If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
35 - nvidia,xcvr-lsfslew : LS falling slew rate control. 39 - nvidia,xcvr-lsfslew : LS falling slew rate control.
36 - nvidia,xcvr-lsrslew : LS rising slew rate control. 40 - nvidia,xcvr-lsrslew : LS rising slew rate control.
37 41
42Required PHY timing params for utmi phy, only on Tegra30 and above:
43 - nvidia,xcvr-hsslew : HS slew rate control.
44 - nvidia,hssquelch-level : HS squelch detector level.
45 - nvidia,hsdiscon-level : HS disconnect detector level.
46
38Optional properties: 47Optional properties:
39 - nvidia,has-legacy-mode : boolean indicates whether this controller can 48 - nvidia,has-legacy-mode : boolean indicates whether this controller can
40 operate in legacy mode (as APX 2500 / 2600). In legacy mode some 49 operate in legacy mode (as APX 2500 / 2600). In legacy mode some
@@ -48,5 +57,5 @@ Optional properties:
48 peripheral means it is device controller 57 peripheral means it is device controller
49 otg means it can operate as either ("on the go") 58 otg means it can operate as either ("on the go")
50 59
51Required properties for dr_mode == otg: 60VBUS control (required for dr_mode == otg, optional for dr_mode == host):
52 - vbus-supply: regulator for VBUS 61 - vbus-supply: regulator for VBUS