7 files changed, 147 insertions, 30 deletions

diff --git a/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt b/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt
new file mode 100644
index 000000000000..5c52e5eef16d
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/bcm63xx-uart.txt
@@ -0,0 +1,30 @@
+* BCM63xx UART
+
+Required properties:
+
+- compatible: "brcm,bcm6345-uart"
+
+- reg: The base address of the UART register bank.
+
+- interrupts: A single interrupt specifier.
+
+- clocks: Clock driving the hardware; used to figure out the baud rate
+  divisor.
+
+Example:
+
+        uart0: serial@14e00520 {
+                compatible = "brcm,bcm6345-uart";
+                reg = <0x14e00520 0x18>;
+                interrupt-parent = <&periph_intc>;
+                interrupts = <2>;
+                clocks = <&periph_clk>;
+        };
+
+        clocks {
+                periph_clk: periph_clk@0 {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <54000000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt
index 59a40f18d551..7c408c87e613 100644
--- a/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt
+++ b/Documentation/devicetree/bindings/serial/fsl-mxs-auart.txt
@@ -11,8 +11,13 @@ Required properties:
 - dma-names: "rx" for RX channel, "tx" for TX channel.
 
 Optional properties:
-- fsl,uart-has-rtscts : Indicate the UART has RTS and CTS lines,
+- fsl,uart-has-rtscts : Indicate the UART has RTS and CTS lines
+  for hardware flow control,
         it also means you enable the DMA support for this UART.
+- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
+  line respectively. It will use specified PIO instead of the peripheral
+  function pin for the USART feature.
+  If unsure, don't specify this property.
 
 Example:
 auart0: serial@8006a000 {
@@ -21,6 +26,9 @@ auart0: serial@8006a000 {
         interrupts = <112>;
         dmas = <&dma_apbx 8>, <&dma_apbx 9>;
         dma-names = "rx", "tx";
+        cts-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+        dsr-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
+        dcd-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
 };
 
 Note: Each auart port should have an alias correctly numbered in "aliases"
diff --git a/Documentation/devicetree/bindings/serial/of-serial.txt b/Documentation/devicetree/bindings/serial/of-serial.txt
index 8c4fd0332028..b52b98234b9b 100644
--- a/Documentation/devicetree/bindings/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/serial/of-serial.txt
@@ -10,6 +10,7 @@ Required properties:
         - "ns16850"
         - "nvidia,tegra20-uart"
         - "nxp,lpc3220-uart"
+        - "ralink,rt2880-uart"
         - "ibm,qpace-nwp-serial"
         - "altr,16550-FIFO32"
         - "altr,16550-FIFO64"
diff --git a/Documentation/devicetree/bindings/serial/pl011.txt b/Documentation/devicetree/bindings/serial/pl011.txt
index 5d2e840ae65c..ba3ecb8cb5a1 100644
--- a/Documentation/devicetree/bindings/serial/pl011.txt
+++ b/Documentation/devicetree/bindings/serial/pl011.txt
@@ -6,12 +6,46 @@ Required properties:
 - interrupts: exactly one interrupt specifier
 
 Optional properties:
-- pinctrl: When present, must have one state named "sleep"
-           and one state named "default"
-- clocks:  When present, must refer to exactly one clock named
+- pinctrl:
+           When present, must have one state named "default",
+           and may contain a second name named "sleep". The former
+           state sets up pins for ordinary operation whereas
+           the latter state will put the associated pins to sleep
+           when the UART is unused
+- clocks:
+           When present, the first clock listed must correspond to
+           the clock named UARTCLK on the IP block, i.e. the clock
+           to the external serial line, whereas the second clock
+           must correspond to the PCLK clocking the internal logic
+           of the block. Just listing one clock (the first one) is
+           deprecated.
+- clocks-names:
+           When present, the first clock listed must be named
+           "uartclk" and the second clock listed must be named
            "apb_pclk"
-- dmas:    When present, may have one or two dma channels.
+- dmas: 
+           When present, may have one or two dma channels.
            The first one must be named "rx", the second one
            must be named "tx".
+- auto-poll:
+           Enables polling when using RX DMA.
+- poll-rate-ms:
+           Rate at which poll occurs when auto-poll is set,
+           default 100ms.
+- poll-timeout-ms:
+           Poll timeout when auto-poll is set, default
+           3000ms.
 
 See also bindings/arm/primecell.txt
+
+Example:
+
+uart@80120000 {
+        compatible = "arm,pl011", "arm,primecell";
+        reg = <0x80120000 0x1000>;
+        interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+        dmas = <&dma 13 0 0x2>, <&dma 13 0 0x0>;
+        dma-names = "rx", "tx";
+        clocks = <&foo_clk>, <&bar_clk>;
+        clock-names = "uartclk", "apb_pclk";
+};
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
index ffa5b784c66e..a2114c217376 100644
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
@@ -27,27 +27,52 @@ Optional properties:
 - dmas: Should contain dma specifiers for transmit and receive channels
 - dma-names: Should contain "tx" for transmit and "rx" for receive channels
 
+Note: Aliases may be defined to ensure the correct ordering of the UARTs.
+The alias serialN will result in the UART being assigned port N.  If any
+serialN alias exists, then an alias must exist for each enabled UART.  The
+serialN aliases should be in a .dts file instead of in a .dtsi file.
+
 Examples:
 
-A uartdm v1.4 device with dma capabilities.
-
-serial@f991e000 {
-        compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
-        reg = <0xf991e000 0x1000>;
-        interrupts = <0 108 0x0>;
-        clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
-        clock-names = "core", "iface";
-        dmas = <&dma0 0>, <&dma0 1>;
-        dma-names = "tx", "rx";
-};
-
-A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
-
-serial@19c40000 {
-        compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-        reg = <0x19c40000 0x1000>,
-              <0x19c00000 0x1000>;
-        interrupts = <0 195 0x0>;
-        clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
-        clock-names = "core", "iface";
-};
+- A uartdm v1.4 device with dma capabilities.
+
+        serial@f991e000 {
+                compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+                reg = <0xf991e000 0x1000>;
+                interrupts = <0 108 0x0>;
+                clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
+                clock-names = "core", "iface";
+                dmas = <&dma0 0>, <&dma0 1>;
+                dma-names = "tx", "rx";
+        };
+
+- A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
+
+        serial@19c40000 {
+                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                reg = <0x19c40000 0x1000>,
+                <0x19c00000 0x1000>;
+                interrupts = <0 195 0x0>;
+                clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
+                clock-names = "core", "iface";
+        };
+
+- serialN alias.
+
+        aliases {
+                serial0 = &uarta;
+                serial1 = &uartc;
+                serial2 = &uartb;
+        };
+
+        uarta: serial@12490000 {
+                status = "ok";
+        };
+
+        uartb: serial@16340000 {
+                status = "ok";
+        };
+
+        uartc: serial@1a240000 {
+                status = "ok";
+        };
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
index b3556609a06f..ae73bb0e9ad9 100644
--- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
+++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
@@ -4,8 +4,7 @@ Required properties:
 
   - compatible: Must contain one of the following:
 
-    - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
-    - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
+    - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
     - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
     - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
     - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
@@ -20,6 +19,12 @@ Required properties:
     - "renesas,scifa-r8a7791" for R8A7791 (R-Car M2) SCIFA compatible UART.
     - "renesas,scifb-r8a7791" for R8A7791 (R-Car M2) SCIFB compatible UART.
     - "renesas,hscif-r8a7791" for R8A7791 (R-Car M2) HSCIF compatible UART.
+    - "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
+    - "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
+    - "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
+    - "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
+    - "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
+    - "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
     - "renesas,scif" for generic SCIF compatible UART.
     - "renesas,scifa" for generic SCIFA compatible UART.
     - "renesas,scifb" for generic SCIFB compatible UART.
diff --git a/Documentation/devicetree/bindings/serial/sirf-uart.txt b/Documentation/devicetree/bindings/serial/sirf-uart.txt
index a2dfc6522a91..3acdd969edf1 100644
--- a/Documentation/devicetree/bindings/serial/sirf-uart.txt
+++ b/Documentation/devicetree/bindings/serial/sirf-uart.txt
@@ -1,7 +1,9 @@
 * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
 
 Required properties:
-- compatible : Should be "sirf,prima2-uart" or "sirf, prima2-usp-uart"
+- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
+                "sirf,marco-uart" or "sirf,marco-bt-uart" which means
+                uart located in BT module and used for BT.
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain uart interrupt
 - fifosize : Should define hardware rx/tx fifo size
@@ -31,3 +33,15 @@ usp@b0090000 {
         rts-gpios = <&gpio 15 0>;
         cts-gpios = <&gpio 46 0>;
 };
+
+for uart use in BT module,
+uart6: uart@11000000 {
+        cell-index = <6>;
+        compatible = "sirf,marco-bt-uart", "sirf,marco-uart";
+        reg = <0x11000000 0x1000>;
+        interrupts = <0 100 0>;
+        clocks = <&clks 138>, <&clks 140>, <&clks 141>;
+        clock-names = "uart", "general", "noc";
+        fifosize = <128>;
+        status = "disabled";
+}