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+* FSL MPIC Message Registers
+
+This binding specifies what properties must be available in the device tree
+representation of the message register blocks found in some FSL MPIC
+implementations.
+
+Required properties:
+
+    - compatible: Specifies the compatibility list for the message register
+      block.  The type shall be <string-list> and the value shall be of the form
+      "fsl,mpic-v<version>-msgr", where <version> is the version number of
+      the MPIC containing the message registers.
+
+    - reg: Specifies the base physical address(s) and size(s) of the
+      message register block's addressable register space.  The type shall be
+      <prop-encoded-array>.
+
+    - interrupts: Specifies a list of interrupt-specifiers which are available
+      for receiving interrupts. Interrupt-specifier consists of two cells: first
+      cell is interrupt-number and second cell is level-sense. The type shall be
+      <prop-encoded-array>.
+
+Optional properties:
+
+    - mpic-msgr-receive-mask: Specifies what registers in the containing block
+      are allowed to receive interrupts. The value is a bit mask where a set
+      bit at bit 'n' indicates that message register 'n' can receive interrupts.
+      Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall
+      be <u32>. If not present, then all of the message registers in the block
+      are available.
+
+Aliases:
+
+    An alias should be created for every message register block.  They are not
+    required, though.  However, a particular implementation of this binding
+    may require aliases to be present.  Aliases are of the form
+    'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
+    Numbers shall start at 0.
+
+Example:
+
+        aliases {
+                mpic-msgr-block0 = &mpic_msgr_block0;
+                mpic-msgr-block1 = &mpic_msgr_block1;
+        };
+
+        mpic_msgr_block0: mpic-msgr-block@41400 {
+                compatible = "fsl,mpic-v3.1-msgr";
+                reg = <0x41400 0x200>;
+                // Message registers 0 and 2 in this block can receive interrupts on
+                // sources 0xb0 and 0xb2, respectively.
+                interrupts = <0xb0 2 0xb2 2>;
+                mpic-msgr-receive-mask = <0x5>;
+        };
+
+        mpic_msgr_block1: mpic-msgr-block@42400 {
+                compatible = "fsl,mpic-v3.1-msgr";
+                reg = <0x42400 0x200>;
+                // Message registers 0 and 2 in this block can receive interrupts on
+                // sources 0xb4 and 0xb6, respectively.
+                interrupts = <0xb4 2 0xb6 2>;
+                mpic-msgr-receive-mask = <0x5>;
+        };