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1TI SoC Ethernet Switch Controller Device Tree Bindings
2------------------------------------------------------
3
4Required properties:
5- compatible : Should be "ti,cpsw"
6- reg : physical base address and size of the cpsw
7 registers map
8- interrupts : property with a value describing the interrupt
9 number
10- interrupt-parent : The parent interrupt controller
11- cpdma_channels : Specifies number of channels in CPDMA
12- host_port_no : Specifies host port shift
13- cpdma_reg_ofs : Specifies CPDMA submodule register offset
14- cpdma_sram_ofs : Specifies CPDMA SRAM offset
15- ale_reg_ofs : Specifies ALE submodule register offset
16- ale_entries : Specifies No of entries ALE can hold
17- host_port_reg_ofs : Specifies host port register offset
18- hw_stats_reg_ofs : Specifies hardware statistics register offset
19- bd_ram_ofs : Specifies internal desciptor RAM offset
20- bd_ram_size : Specifies internal descriptor RAM size
21- rx_descs : Specifies number of Rx descriptors
22- mac_control : Specifies Default MAC control register content
23 for the specific platform
24- slaves : Specifies number for slaves
25- slave_reg_ofs : Specifies slave register offset
26- sliver_reg_ofs : Specifies slave sliver register offset
27- phy_id : Specifies slave phy id
28- mac-address : Specifies slave MAC address
29
30Optional properties:
31- ti,hwmods : Must be "cpgmac0"
32- no_bd_ram : Must be 0 or 1
33
34Note: "ti,hwmods" field is used to fetch the base address and irq
35resources from TI, omap hwmod data base during device registration.
36Future plan is to migrate hwmod data base contents into device tree
37blob so that, all the required data will be used from device tree dts
38file.
39
40Examples:
41
42 mac: ethernet@4A100000 {
43 compatible = "ti,cpsw";
44 reg = <0x4A100000 0x1000>;
45 interrupts = <55 0x4>;
46 interrupt-parent = <&intc>;
47 cpdma_channels = <8>;
48 host_port_no = <0>;
49 cpdma_reg_ofs = <0x800>;
50 cpdma_sram_ofs = <0xa00>;
51 ale_reg_ofs = <0xd00>;
52 ale_entries = <1024>;
53 host_port_reg_ofs = <0x108>;
54 hw_stats_reg_ofs = <0x900>;
55 bd_ram_ofs = <0x2000>;
56 bd_ram_size = <0x2000>;
57 no_bd_ram = <0>;
58 rx_descs = <64>;
59 mac_control = <0x20>;
60 slaves = <2>;
61 cpsw_emac0: slave@0 {
62 slave_reg_ofs = <0x208>;
63 sliver_reg_ofs = <0xd80>;
64 phy_id = "davinci_mdio.16:00";
65 /* Filled in by U-Boot */
66 mac-address = [ 00 00 00 00 00 00 ];
67 };
68 cpsw_emac1: slave@1 {
69 slave_reg_ofs = <0x308>;
70 sliver_reg_ofs = <0xdc0>;
71 phy_id = "davinci_mdio.16:01";
72 /* Filled in by U-Boot */
73 mac-address = [ 00 00 00 00 00 00 ];
74 };
75 };
76
77(or)
78 mac: ethernet@4A100000 {
79 compatible = "ti,cpsw";
80 ti,hwmods = "cpgmac0";
81 cpdma_channels = <8>;
82 host_port_no = <0>;
83 cpdma_reg_ofs = <0x800>;
84 cpdma_sram_ofs = <0xa00>;
85 ale_reg_ofs = <0xd00>;
86 ale_entries = <1024>;
87 host_port_reg_ofs = <0x108>;
88 hw_stats_reg_ofs = <0x900>;
89 bd_ram_ofs = <0x2000>;
90 bd_ram_size = <0x2000>;
91 no_bd_ram = <0>;
92 rx_descs = <64>;
93 mac_control = <0x20>;
94 slaves = <2>;
95 cpsw_emac0: slave@0 {
96 slave_reg_ofs = <0x208>;
97 sliver_reg_ofs = <0xd80>;
98 phy_id = "davinci_mdio.16:00";
99 /* Filled in by U-Boot */
100 mac-address = [ 00 00 00 00 00 00 ];
101 };
102 cpsw_emac1: slave@1 {
103 slave_reg_ofs = <0x308>;
104 sliver_reg_ofs = <0xdc0>;
105 phy_id = "davinci_mdio.16:01";
106 /* Filled in by U-Boot */
107 mac-address = [ 00 00 00 00 00 00 ];
108 };
109 };