diff options
Diffstat (limited to 'Documentation/devicetree/bindings/mtd/fsmc-nand.txt')
-rw-r--r-- | Documentation/devicetree/bindings/mtd/fsmc-nand.txt | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt index 2240ac09f6ba..ec42935f3908 100644 --- a/Documentation/devicetree/bindings/mtd/fsmc-nand.txt +++ b/Documentation/devicetree/bindings/mtd/fsmc-nand.txt | |||
@@ -1,4 +1,5 @@ | |||
1 | * FSMC NAND | 1 | ST Microelectronics Flexible Static Memory Controller (FSMC) |
2 | NAND Interface | ||
2 | 3 | ||
3 | Required properties: | 4 | Required properties: |
4 | - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" | 5 | - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" |
@@ -9,6 +10,26 @@ Optional properties: | |||
9 | - bank-width : Width (in bytes) of the device. If not present, the width | 10 | - bank-width : Width (in bytes) of the device. If not present, the width |
10 | defaults to 1 byte | 11 | defaults to 1 byte |
11 | - nand-skip-bbtscan: Indicates the the BBT scanning should be skipped | 12 | - nand-skip-bbtscan: Indicates the the BBT scanning should be skipped |
13 | - timings: array of 6 bytes for NAND timings. The meanings of these bytes | ||
14 | are: | ||
15 | byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits | ||
16 | are valid. Zero means one clockcycle, 15 means 16 clock | ||
17 | cycles. | ||
18 | byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR. | ||
19 | byte 2 THIZ : number of HCLK clock cycles during which the data bus is | ||
20 | kept in Hi-Z (tristate) after the start of a write access. | ||
21 | Only valid for write transactions. Zero means zero cycles, | ||
22 | 255 means 255 cycles. | ||
23 | byte 3 THOLD : number of HCLK clock cycles to hold the address (and data | ||
24 | when writing) after the command deassertation. Zero means | ||
25 | one cycle, 255 means 256 cycles. | ||
26 | byte 4 TWAIT : number of HCLK clock cycles to assert the command to the | ||
27 | NAND flash in response to SMWAITn. Zero means 1 cycle, | ||
28 | 255 means 256 cycles. | ||
29 | byte 5 TSET : number of HCLK clock cycles to assert the address before the | ||
30 | command is asserted. Zero means one cycle, 255 means 256 | ||
31 | cycles. | ||
32 | - bank: default NAND bank to use (0-3 are valid, 0 is the default). | ||
12 | 33 | ||
13 | Example: | 34 | Example: |
14 | 35 | ||
@@ -24,6 +45,8 @@ Example: | |||
24 | 45 | ||
25 | bank-width = <1>; | 46 | bank-width = <1>; |
26 | nand-skip-bbtscan; | 47 | nand-skip-bbtscan; |
48 | timings = /bits/ 8 <0 0 0 2 3 0>; | ||
49 | bank = <1>; | ||
27 | 50 | ||
28 | partition@0 { | 51 | partition@0 { |
29 | ... | 52 | ... |