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Diffstat (limited to 'Documentation/devicetree/bindings/mmc/fsl-esdhc.txt')
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1 | * Freescale Enhanced Secure Digital Host Controller (eSDHC) | ||
2 | |||
3 | The Enhanced Secure Digital Host Controller provides an interface | ||
4 | for MMC, SD, and SDIO types of memory cards. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible : should be | ||
8 | "fsl,<chip>-esdhc", "fsl,esdhc" | ||
9 | - reg : should contain eSDHC registers location and length. | ||
10 | - interrupts : should contain eSDHC interrupt. | ||
11 | - interrupt-parent : interrupt source phandle. | ||
12 | - clock-frequency : specifies eSDHC base clock frequency. | ||
13 | - sdhci,wp-inverted : (optional) specifies that eSDHC controller | ||
14 | reports inverted write-protect state; | ||
15 | - sdhci,1-bit-only : (optional) specifies that a controller can | ||
16 | only handle 1-bit data transfers. | ||
17 | - sdhci,auto-cmd12: (optional) specifies that a controller can | ||
18 | only handle auto CMD12. | ||
19 | |||
20 | Example: | ||
21 | |||
22 | sdhci@2e000 { | ||
23 | compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; | ||
24 | reg = <0x2e000 0x1000>; | ||
25 | interrupts = <42 0x8>; | ||
26 | interrupt-parent = <&ipic>; | ||
27 | /* Filled in by U-Boot */ | ||
28 | clock-frequency = <0>; | ||
29 | }; | ||