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| 1 | ARM MHU Mailbox Driver | ||
| 2 | ====================== | ||
| 3 | |||
| 4 | The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has | ||
| 5 | 3 independent channels/links to communicate with remote processor(s). | ||
| 6 | MHU links are hardwired on a platform. A link raises interrupt for any | ||
| 7 | received data. However, there is no specified way of knowing if the sent | ||
| 8 | data has been read by the remote. This driver assumes the sender polls | ||
| 9 | STAT register and the remote clears it after having read the data. | ||
| 10 | The last channel is specified to be a 'Secure' resource, hence can't be | ||
| 11 | used by Linux running NS. | ||
| 12 | |||
| 13 | Mailbox Device Node: | ||
| 14 | ==================== | ||
| 15 | |||
| 16 | Required properties: | ||
| 17 | -------------------- | ||
| 18 | - compatible: Shall be "arm,mhu" & "arm,primecell" | ||
| 19 | - reg: Contains the mailbox register address range (base | ||
| 20 | address and length) | ||
| 21 | - #mbox-cells Shall be 1 - the index of the channel needed. | ||
| 22 | - interrupts: Contains the interrupt information corresponding to | ||
| 23 | each of the 3 links of MHU. | ||
| 24 | |||
| 25 | Example: | ||
| 26 | -------- | ||
| 27 | |||
| 28 | mhu: mailbox@2b1f0000 { | ||
| 29 | #mbox-cells = <1>; | ||
| 30 | compatible = "arm,mhu", "arm,primecell"; | ||
| 31 | reg = <0 0x2b1f0000 0x1000>; | ||
| 32 | interrupts = <0 36 4>, /* LP-NonSecure */ | ||
| 33 | <0 35 4>, /* HP-NonSecure */ | ||
| 34 | <0 37 4>; /* Secure */ | ||
| 35 | clocks = <&clock 0 2 1>; | ||
| 36 | clock-names = "apb_pclk"; | ||
| 37 | }; | ||
| 38 | |||
| 39 | mhu_client: scb@2e000000 { | ||
| 40 | compatible = "fujitsu,mb86s70-scb-1.0"; | ||
| 41 | reg = <0 0x2e000000 0x4000>; | ||
| 42 | mboxes = <&mhu 1>; /* HP-NonSecure */ | ||
| 43 | }; | ||
