diff options
Diffstat (limited to 'Documentation/devicetree/bindings/gpio')
11 files changed, 285 insertions, 17 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt b/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt new file mode 100644 index 000000000000..7bb1a9d60133 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-74xx-mmio.txt | |||
@@ -0,0 +1,30 @@ | |||
1 | * 74XX MMIO GPIO driver | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Should contain one of the following: | ||
5 | "ti,741g125": for 741G125 (1-bit Input), | ||
6 | "ti,741g174": for 741G74 (1-bit Output), | ||
7 | "ti,742g125": for 742G125 (2-bit Input), | ||
8 | "ti,7474" : for 7474 (2-bit Output), | ||
9 | "ti,74125" : for 74125 (4-bit Input), | ||
10 | "ti,74175" : for 74175 (4-bit Output), | ||
11 | "ti,74365" : for 74365 (6-bit Input), | ||
12 | "ti,74174" : for 74174 (6-bit Output), | ||
13 | "ti,74244" : for 74244 (8-bit Input), | ||
14 | "ti,74273" : for 74273 (8-bit Output), | ||
15 | "ti,741624" : for 741624 (16-bit Input), | ||
16 | "ti,7416374": for 7416374 (16-bit Output). | ||
17 | - reg: Physical base address and length where IC resides. | ||
18 | - gpio-controller: Marks the device node as a gpio controller. | ||
19 | - #gpio-cells: Should be two. The first cell is the pin number and | ||
20 | the second cell is used to specify the GPIO polarity: | ||
21 | 0 = Active High, | ||
22 | 1 = Active Low. | ||
23 | |||
24 | Example: | ||
25 | ctrl: gpio@30008004 { | ||
26 | compatible = "ti,74174"; | ||
27 | reg = <0x30008004 0x1>; | ||
28 | gpio-controller; | ||
29 | #gpio-cells = <2>; | ||
30 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt new file mode 100644 index 000000000000..6c7e6c7302f5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-dsp-keystone.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | Keystone 2 DSP GPIO controller bindings | ||
2 | |||
3 | HOST OS userland running on ARM can send interrupts to DSP cores using | ||
4 | the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core. | ||
5 | This is one of the component used by the IPC mechanism used on Keystone SOCs. | ||
6 | |||
7 | For example TCI6638K2K SoC has 8 DSP GPIO controllers: | ||
8 | - 8 for C66x CorePacx CPUs 0-7 | ||
9 | |||
10 | Keystone 2 DSP GPIO controller has specific features: | ||
11 | - each GPIO can be configured only as output pin; | ||
12 | - setting GPIO value to 1 causes IRQ generation on target DSP core; | ||
13 | - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still | ||
14 | pending. | ||
15 | |||
16 | Required Properties: | ||
17 | - compatible: should be "ti,keystone-dsp-gpio" | ||
18 | - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to | ||
19 | access device state control registers and the offset of device's specific | ||
20 | registers within device state control registers range. | ||
21 | - gpio-controller: Marks the device node as a gpio controller. | ||
22 | - #gpio-cells: Should be 2. | ||
23 | |||
24 | Please refer to gpio.txt in this directory for details of the common GPIO | ||
25 | bindings used by client devices. | ||
26 | |||
27 | Example: | ||
28 | dspgpio0: keystone_dsp_gpio@02620240 { | ||
29 | compatible = "ti,keystone-dsp-gpio"; | ||
30 | ti,syscon-dev = <&devctrl 0x240>; | ||
31 | gpio-controller; | ||
32 | #gpio-cells = <2>; | ||
33 | }; | ||
34 | |||
35 | dsp0: dsp0 { | ||
36 | compatible = "linux,rproc-user"; | ||
37 | ... | ||
38 | kick-gpio = <&dspgpio0 27>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt index c306a2d0f2b1..f3332b9a8ed4 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt | |||
@@ -57,6 +57,8 @@ Optional device specific properties: | |||
57 | occurred on. If it is not set, the interrupt are only generated for the | 57 | occurred on. If it is not set, the interrupt are only generated for the |
58 | bank they belong to. | 58 | bank they belong to. |
59 | On devices with only one interrupt output this property is useless. | 59 | On devices with only one interrupt output this property is useless. |
60 | - microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This | ||
61 | configures the IRQ output polarity as active high. | ||
60 | 62 | ||
61 | Example I2C (with interrupt): | 63 | Example I2C (with interrupt): |
62 | gpiom1: gpio@20 { | 64 | gpiom1: gpio@20 { |
diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt new file mode 100644 index 000000000000..b9a42f294dd0 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt | |||
@@ -0,0 +1,39 @@ | |||
1 | * NXP PCA953x I2C GPIO multiplexer | ||
2 | |||
3 | Required properties: | ||
4 | - compatible: Has to contain one of the following: | ||
5 | nxp,pca9505 | ||
6 | nxp,pca9534 | ||
7 | nxp,pca9535 | ||
8 | nxp,pca9536 | ||
9 | nxp,pca9537 | ||
10 | nxp,pca9538 | ||
11 | nxp,pca9539 | ||
12 | nxp,pca9554 | ||
13 | nxp,pca9555 | ||
14 | nxp,pca9556 | ||
15 | nxp,pca9557 | ||
16 | nxp,pca9574 | ||
17 | nxp,pca9575 | ||
18 | nxp,pca9698 | ||
19 | maxim,max7310 | ||
20 | maxim,max7312 | ||
21 | maxim,max7313 | ||
22 | maxim,max7315 | ||
23 | ti,pca6107 | ||
24 | ti,tca6408 | ||
25 | ti,tca6416 | ||
26 | ti,tca6424 | ||
27 | exar,xra1202 | ||
28 | |||
29 | Example: | ||
30 | |||
31 | |||
32 | gpio@20 { | ||
33 | compatible = "nxp,pca9505"; | ||
34 | reg = <0x20>; | ||
35 | pinctrl-names = "default"; | ||
36 | pinctrl-0 = <&pinctrl_pca9505>; | ||
37 | interrupt-parent = <&gpio3>; | ||
38 | interrupts = <23 IRQ_TYPE_LEVEL_LOW>; | ||
39 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-restart.txt b/Documentation/devicetree/bindings/gpio/gpio-restart.txt new file mode 100644 index 000000000000..af3701bc15c4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-restart.txt | |||
@@ -0,0 +1,54 @@ | |||
1 | Drive a GPIO line that can be used to restart the system from a restart | ||
2 | handler. | ||
3 | |||
4 | This binding supports level and edge triggered reset. At driver load | ||
5 | time, the driver will request the given gpio line and install a restart | ||
6 | handler. If the optional properties 'open-source' is not found, the GPIO line | ||
7 | will be driven in the inactive state. Otherwise its not driven until | ||
8 | the restart is initiated. | ||
9 | |||
10 | When the system is restarted, the restart handler will be invoked in | ||
11 | priority order. The gpio is configured as an output, and driven active, | ||
12 | triggering a level triggered reset condition. This will also cause an | ||
13 | inactive->active edge condition, triggering positive edge triggered | ||
14 | reset. After a delay specified by active-delay, the GPIO is set to | ||
15 | inactive, thus causing an active->inactive edge, triggering negative edge | ||
16 | triggered reset. After a delay specified by inactive-delay, the GPIO | ||
17 | is driven active again. After a delay specified by wait-delay, the | ||
18 | restart handler completes allowing other restart handlers to be attempted. | ||
19 | |||
20 | Required properties: | ||
21 | - compatible : should be "gpio-restart". | ||
22 | - gpios : The GPIO to set high/low, see "gpios property" in | ||
23 | Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be | ||
24 | low to reset the board set it to "Active Low", otherwise set | ||
25 | gpio to "Active High". | ||
26 | |||
27 | Optional properties: | ||
28 | - open-source : Treat the GPIO as being open source and defer driving | ||
29 | it to when the restart is initiated. If this optional property is not | ||
30 | specified, the GPIO is initialized as an output in its inactive state. | ||
31 | - priority : A priority ranging from 0 to 255 (default 128) according to | ||
32 | the following guidelines: | ||
33 | 0: Restart handler of last resort, with limited restart | ||
34 | capabilities | ||
35 | 128: Default restart handler; use if no other restart handler is | ||
36 | expected to be available, and/or if restart functionality is | ||
37 | sufficient to restart the entire system | ||
38 | 255: Highest priority restart handler, will preempt all other | ||
39 | restart handlers | ||
40 | - active-delay: Delay (default 100) to wait after driving gpio active [ms] | ||
41 | - inactive-delay: Delay (default 100) to wait after driving gpio inactive [ms] | ||
42 | - wait-delay: Delay (default 3000) to wait after completing restart | ||
43 | sequence [ms] | ||
44 | |||
45 | Examples: | ||
46 | |||
47 | gpio-restart { | ||
48 | compatible = "gpio-restart"; | ||
49 | gpios = <&gpio 4 0>; | ||
50 | priority = <128>; | ||
51 | active-delay = <100>; | ||
52 | inactive-delay = <100>; | ||
53 | wait-delay = <3000>; | ||
54 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt new file mode 100644 index 000000000000..436cc99c6598 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt | |||
@@ -0,0 +1,55 @@ | |||
1 | * Freescale VF610 PORT/GPIO module | ||
2 | |||
3 | The Freescale PORT/GPIO modules are two adjacent modules providing GPIO | ||
4 | functionality. Each pair serves 32 GPIOs. The VF610 has 5 instances of | ||
5 | each, and each PORT module has its own interrupt. | ||
6 | |||
7 | Required properties for GPIO node: | ||
8 | - compatible : Should be "fsl,<soc>-gpio", currently "fsl,vf610-gpio" | ||
9 | - reg : The first reg tuple represents the PORT module, the second tuple | ||
10 | the GPIO module. | ||
11 | - interrupts : Should be the port interrupt shared by all 32 pins. | ||
12 | - gpio-controller : Marks the device node as a gpio controller. | ||
13 | - #gpio-cells : Should be two. The first cell is the pin number and | ||
14 | the second cell is used to specify the gpio polarity: | ||
15 | 0 = active high | ||
16 | 1 = active low | ||
17 | - interrupt-controller: Marks the device node as an interrupt controller. | ||
18 | - #interrupt-cells : Should be 2. The first cell is the GPIO number. | ||
19 | The second cell bits[3:0] is used to specify trigger type and level flags: | ||
20 | 1 = low-to-high edge triggered. | ||
21 | 2 = high-to-low edge triggered. | ||
22 | 4 = active high level-sensitive. | ||
23 | 8 = active low level-sensitive. | ||
24 | |||
25 | Note: Each GPIO port should have an alias correctly numbered in "aliases" | ||
26 | node. | ||
27 | |||
28 | Examples: | ||
29 | |||
30 | aliases { | ||
31 | gpio0 = &gpio1; | ||
32 | gpio1 = &gpio2; | ||
33 | }; | ||
34 | |||
35 | gpio1: gpio@40049000 { | ||
36 | compatible = "fsl,vf610-gpio"; | ||
37 | reg = <0x40049000 0x1000 0x400ff000 0x40>; | ||
38 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | ||
39 | gpio-controller; | ||
40 | #gpio-cells = <2>; | ||
41 | interrupt-controller; | ||
42 | #interrupt-cells = <2>; | ||
43 | gpio-ranges = <&iomuxc 0 0 32>; | ||
44 | }; | ||
45 | |||
46 | gpio2: gpio@4004a000 { | ||
47 | compatible = "fsl,vf610-gpio"; | ||
48 | reg = <0x4004a000 0x1000 0x400ff040 0x40>; | ||
49 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | ||
50 | gpio-controller; | ||
51 | #gpio-cells = <2>; | ||
52 | interrupt-controller; | ||
53 | #interrupt-cells = <2>; | ||
54 | gpio-ranges = <&iomuxc 0 32 32>; | ||
55 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xgene.txt b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt new file mode 100644 index 000000000000..86dbb05e7758 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-xgene.txt | |||
@@ -0,0 +1,22 @@ | |||
1 | APM X-Gene SoC GPIO controller bindings | ||
2 | |||
3 | This is a gpio controller that is part of the flash controller. | ||
4 | This gpio controller controls a total of 48 gpios. | ||
5 | |||
6 | Required properties: | ||
7 | - compatible: "apm,xgene-gpio" for X-Gene GPIO controller | ||
8 | - reg: Physical base address and size of the controller's registers | ||
9 | - #gpio-cells: Should be two. | ||
10 | - first cell is the pin number | ||
11 | - second cell is used to specify the gpio polarity: | ||
12 | 0 = active high | ||
13 | 1 = active low | ||
14 | - gpio-controller: Marks the device node as a GPIO controller. | ||
15 | |||
16 | Example: | ||
17 | gpio0: gpio0@1701c000 { | ||
18 | compatible = "apm,xgene-gpio"; | ||
19 | reg = <0x0 0x1701c000 0x0 0x40>; | ||
20 | gpio-controller; | ||
21 | #gpio-cells = <2>; | ||
22 | }; | ||
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index 3fb8f53071b8..b9bd1d64cfa6 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt | |||
@@ -13,13 +13,22 @@ properties, each containing a 'gpio-list': | |||
13 | gpio-specifier : Array of #gpio-cells specifying specific gpio | 13 | gpio-specifier : Array of #gpio-cells specifying specific gpio |
14 | (controller specific) | 14 | (controller specific) |
15 | 15 | ||
16 | GPIO properties should be named "[<name>-]gpios". The exact | 16 | GPIO properties should be named "[<name>-]gpios", with <name> being the purpose |
17 | meaning of each gpios property must be documented in the device tree | 17 | of this GPIO for the device. While a non-existent <name> is considered valid |
18 | binding for each device. | 18 | for compatibility reasons (resolving to the "gpios" property), it is not allowed |
19 | for new bindings. | ||
19 | 20 | ||
20 | For example, the following could be used to describe GPIO pins used | 21 | GPIO properties can contain one or more GPIO phandles, but only in exceptional |
21 | as chip select lines; with chip selects 0, 1 and 3 populated, and chip | 22 | cases should they contain more than one. If your device uses several GPIOs with |
22 | select 2 left empty: | 23 | distinct functions, reference each of them under its own property, giving it a |
24 | meaningful name. The only case where an array of GPIOs is accepted is when | ||
25 | several GPIOs serve the same function (e.g. a parallel data line). | ||
26 | |||
27 | The exact purpose of each gpios property must be documented in the device tree | ||
28 | binding of the device. | ||
29 | |||
30 | The following example could be used to describe GPIO pins used as device enable | ||
31 | and bit-banged data signals: | ||
23 | 32 | ||
24 | gpio1: gpio1 { | 33 | gpio1: gpio1 { |
25 | gpio-controller | 34 | gpio-controller |
@@ -30,10 +39,12 @@ select 2 left empty: | |||
30 | #gpio-cells = <1>; | 39 | #gpio-cells = <1>; |
31 | }; | 40 | }; |
32 | [...] | 41 | [...] |
33 | chipsel-gpios = <&gpio1 12 0>, | 42 | |
34 | <&gpio1 13 0>, | 43 | enable-gpios = <&gpio2 2>; |
35 | <0>, /* holes are permitted, means no GPIO 2 */ | 44 | data-gpios = <&gpio1 12 0>, |
36 | <&gpio2 2>; | 45 | <&gpio1 13 0>, |
46 | <&gpio1 14 0>, | ||
47 | <&gpio1 15 0>; | ||
37 | 48 | ||
38 | Note that gpio-specifier length is controller dependent. In the | 49 | Note that gpio-specifier length is controller dependent. In the |
39 | above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 | 50 | above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 |
@@ -42,16 +53,17 @@ only uses one. | |||
42 | gpio-specifier may encode: bank, pin position inside the bank, | 53 | gpio-specifier may encode: bank, pin position inside the bank, |
43 | whether pin is open-drain and whether pin is logically inverted. | 54 | whether pin is open-drain and whether pin is logically inverted. |
44 | Exact meaning of each specifier cell is controller specific, and must | 55 | Exact meaning of each specifier cell is controller specific, and must |
45 | be documented in the device tree binding for the device. | 56 | be documented in the device tree binding for the device. Use the macros |
57 | defined in include/dt-bindings/gpio/gpio.h whenever possible: | ||
46 | 58 | ||
47 | Example of a node using GPIOs: | 59 | Example of a node using GPIOs: |
48 | 60 | ||
49 | node { | 61 | node { |
50 | gpios = <&qe_pio_e 18 0>; | 62 | enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; |
51 | }; | 63 | }; |
52 | 64 | ||
53 | In this example gpio-specifier is "18 0" and encodes GPIO pin number, | 65 | GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes |
54 | and GPIO flags as accepted by the "qe_pio_e" gpio-controller. | 66 | GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. |
55 | 67 | ||
56 | 1.1) GPIO specifier best practices | 68 | 1.1) GPIO specifier best practices |
57 | ---------------------------------- | 69 | ---------------------------------- |
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index 66416261e14d..b2afdb27adeb 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt | |||
@@ -19,7 +19,7 @@ Required properties: | |||
19 | - gpio-controller : Marks the device node as a gpio controller. | 19 | - gpio-controller : Marks the device node as a gpio controller. |
20 | - #gpio-cells : Should be one. It is the pin number. | 20 | - #gpio-cells : Should be one. It is the pin number. |
21 | 21 | ||
22 | Example: | 22 | Example for a MMP platform: |
23 | 23 | ||
24 | gpio: gpio@d4019000 { | 24 | gpio: gpio@d4019000 { |
25 | compatible = "marvell,mmp-gpio"; | 25 | compatible = "marvell,mmp-gpio"; |
@@ -32,6 +32,19 @@ Example: | |||
32 | #interrupt-cells = <1>; | 32 | #interrupt-cells = <1>; |
33 | }; | 33 | }; |
34 | 34 | ||
35 | Example for a PXA3xx platform: | ||
36 | |||
37 | gpio: gpio@40e00000 { | ||
38 | compatible = "intel,pxa3xx-gpio"; | ||
39 | reg = <0x40e00000 0x10000>; | ||
40 | interrupt-names = "gpio0", "gpio1", "gpio_mux"; | ||
41 | interrupts = <8 9 10>; | ||
42 | gpio-controller; | ||
43 | #gpio-cells = <0x2>; | ||
44 | interrupt-controller; | ||
45 | #interrupt-cells = <0x2>; | ||
46 | }; | ||
47 | |||
35 | * Marvell Orion GPIO Controller | 48 | * Marvell Orion GPIO Controller |
36 | 49 | ||
37 | Required properties: | 50 | Required properties: |
diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt index a2c416bcbccc..89058d375b7c 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.txt | |||
@@ -7,4 +7,4 @@ Required properties: | |||
7 | - bit 0 specifies polarity (0 for normal, 1 for inverted) | 7 | - bit 0 specifies polarity (0 for normal, 1 for inverted) |
8 | - gpio-controller : Marks the device node as a GPIO controller. | 8 | - gpio-controller : Marks the device node as a GPIO controller. |
9 | - interrupts : Interrupt mapping for GPIO IRQ. | 9 | - interrupts : Interrupt mapping for GPIO IRQ. |
10 | 10 | - gpio-ranges : Interaction with the PINCTRL subsystem. | |
diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt index 941a26aa4322..38fb86f28ba2 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt | |||
@@ -6,7 +6,9 @@ Required Properties: | |||
6 | - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. | 6 | - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO controller. |
7 | - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. | 7 | - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller. |
8 | - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. | 8 | - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller. |
9 | - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2) compatible GPIO controller. | 9 | - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller. |
10 | - "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller. | ||
11 | - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller. | ||
10 | - "renesas,gpio-rcar": for generic R-Car GPIO controller. | 12 | - "renesas,gpio-rcar": for generic R-Car GPIO controller. |
11 | 13 | ||
12 | - reg: Base address and length of each memory resource used by the GPIO | 14 | - reg: Base address and length of each memory resource used by the GPIO |