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-rw-r--r--Documentation/devicetree/bindings/clock/altr_socfpga.txt18
-rw-r--r--Documentation/devicetree/bindings/clock/axi-clkgen.txt22
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt288
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5250-clock.txt177
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5440-clock.txt61
-rw-r--r--Documentation/devicetree/bindings/clock/fixed-factor-clock.txt24
-rw-r--r--Documentation/devicetree/bindings/clock/imx27-clock.txt117
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt303
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/silabs,si5351.txt114
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi.txt151
11 files changed, 1277 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/altr_socfpga.txt b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
new file mode 100644
index 000000000000..bd0c8416a5c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/altr_socfpga.txt
@@ -0,0 +1,18 @@
1Device Tree Clock bindings for Altera's SoCFPGA platform
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
13- clocks : shall be the input parent clock phandle for the clock. This is
14 either an oscillator or a pll output.
15- #clock-cells : from common clock binding, shall be set to 0.
16
17Optional properties:
18- fixed-divider : If clocks have a fixed divider value, use this property.
diff --git a/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
new file mode 100644
index 000000000000..028b493e97ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/axi-clkgen.txt
@@ -0,0 +1,22 @@
1Binding for the axi-clkgen clock generator
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be "adi,axi-clkgen".
9- #clock-cells : from common clock binding; Should always be set to 0.
10- reg : Address and length of the axi-clkgen register set.
11- clocks : Phandle and clock specifier for the parent clock.
12
13Optional properties:
14- clock-output-names : From common clock binding.
15
16Example:
17 clock@0xff000000 {
18 compatible = "adi,axi-clkgen";
19 #clock-cells = <0>;
20 reg = <0xff000000 0x1000>;
21 clocks = <&osc 1>;
22 };
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
new file mode 100644
index 000000000000..ea5e26f16aec
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -0,0 +1,288 @@
1* Samsung Exynos4 Clock Controller
2
3The Exynos4 clock controller generates and supplies clock to various controllers
4within the Exynos4 SoC. The clock binding described here is applicable to all
5SoC's in the Exynos4 family.
6
7Required Properties:
8
9- comptible: should be one of the following.
10 - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
11 - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
12
13- reg: physical base address of the controller and length of memory mapped
14 region.
15
16- #clock-cells: should be 1.
17
18The following is the list of clocks generated by the controller. Each clock is
19assigned an identifier and client nodes use this identifier to specify the
20clock which they consume. Some of the clocks are available only on a particular
21Exynos4 SoC and this is specified where applicable.
22
23
24 [Core Clocks]
25
26 Clock ID SoC (if specific)
27 -----------------------------------------------
28
29 xxti 1
30 xusbxti 2
31 fin_pll 3
32 fout_apll 4
33 fout_mpll 5
34 fout_epll 6
35 fout_vpll 7
36 sclk_apll 8
37 sclk_mpll 9
38 sclk_epll 10
39 sclk_vpll 11
40 arm_clk 12
41 aclk200 13
42 aclk100 14
43 aclk160 15
44 aclk133 16
45 mout_mpll_user_t 17 Exynos4x12
46 mout_mpll_user_c 18 Exynos4x12
47 mout_core 19
48 mout_apll 20
49
50
51 [Clock Gate for Special Clocks]
52
53 Clock ID SoC (if specific)
54 -----------------------------------------------
55
56 sclk_fimc0 128
57 sclk_fimc1 129
58 sclk_fimc2 130
59 sclk_fimc3 131
60 sclk_cam0 132
61 sclk_cam1 133
62 sclk_csis0 134
63 sclk_csis1 135
64 sclk_hdmi 136
65 sclk_mixer 137
66 sclk_dac 138
67 sclk_pixel 139
68 sclk_fimd0 140
69 sclk_mdnie0 141 Exynos4412
70 sclk_mdnie_pwm0 12 142 Exynos4412
71 sclk_mipi0 143
72 sclk_audio0 144
73 sclk_mmc0 145
74 sclk_mmc1 146
75 sclk_mmc2 147
76 sclk_mmc3 148
77 sclk_mmc4 149
78 sclk_sata 150 Exynos4210
79 sclk_uart0 151
80 sclk_uart1 152
81 sclk_uart2 153
82 sclk_uart3 154
83 sclk_uart4 155
84 sclk_audio1 156
85 sclk_audio2 157
86 sclk_spdif 158
87 sclk_spi0 159
88 sclk_spi1 160
89 sclk_spi2 161
90 sclk_slimbus 162
91 sclk_fimd1 163 Exynos4210
92 sclk_mipi1 164 Exynos4210
93 sclk_pcm1 165
94 sclk_pcm2 166
95 sclk_i2s1 167
96 sclk_i2s2 168
97 sclk_mipihsi 169 Exynos4412
98 sclk_mfc 170
99 sclk_pcm0 171
100 sclk_g3d 172
101 sclk_pwm_isp 173 Exynos4x12
102 sclk_spi0_isp 174 Exynos4x12
103 sclk_spi1_isp 175 Exynos4x12
104 sclk_uart_isp 176 Exynos4x12
105
106 [Peripheral Clock Gates]
107
108 Clock ID SoC (if specific)
109 -----------------------------------------------
110
111 fimc0 256
112 fimc1 257
113 fimc2 258
114 fimc3 259
115 csis0 260
116 csis1 261
117 jpeg 262
118 smmu_fimc0 263
119 smmu_fimc1 264
120 smmu_fimc2 265
121 smmu_fimc3 266
122 smmu_jpeg 267
123 vp 268
124 mixer 269
125 tvenc 270 Exynos4210
126 hdmi 271
127 smmu_tv 272
128 mfc 273
129 smmu_mfcl 274
130 smmu_mfcr 275
131 g3d 276
132 g2d 277 Exynos4210
133 rotator 278 Exynos4210
134 mdma 279 Exynos4210
135 smmu_g2d 280 Exynos4210
136 smmu_rotator 281 Exynos4210
137 smmu_mdma 282 Exynos4210
138 fimd0 283
139 mie0 284
140 mdnie0 285 Exynos4412
141 dsim0 286
142 smmu_fimd0 287
143 fimd1 288 Exynos4210
144 mie1 289 Exynos4210
145 dsim1 290 Exynos4210
146 smmu_fimd1 291 Exynos4210
147 pdma0 292
148 pdma1 293
149 pcie_phy 294
150 sata_phy 295 Exynos4210
151 tsi 296
152 sdmmc0 297
153 sdmmc1 298
154 sdmmc2 299
155 sdmmc3 300
156 sdmmc4 301
157 sata 302 Exynos4210
158 sromc 303
159 usb_host 304
160 usb_device 305
161 pcie 306
162 onenand 307
163 nfcon 308
164 smmu_pcie 309
165 gps 310
166 smmu_gps 311
167 uart0 312
168 uart1 313
169 uart2 314
170 uart3 315
171 uart4 316
172 i2c0 317
173 i2c1 318
174 i2c2 319
175 i2c3 320
176 i2c4 321
177 i2c5 322
178 i2c6 323
179 i2c7 324
180 i2c_hdmi 325
181 tsadc 326
182 spi0 327
183 spi1 328
184 spi2 329
185 i2s1 330
186 i2s2 331
187 pcm0 332
188 i2s0 333
189 pcm1 334
190 pcm2 335
191 pwm 336
192 slimbus 337
193 spdif 338
194 ac97 339
195 modemif 340
196 chipid 341
197 sysreg 342
198 hdmi_cec 343
199 mct 344
200 wdt 345
201 rtc 346
202 keyif 347
203 audss 348
204 mipi_hsi 349 Exynos4210
205 mdma2 350 Exynos4210
206 pixelasyncm0 351
207 pixelasyncm1 352
208 fimc_lite0 353 Exynos4x12
209 fimc_lite1 354 Exynos4x12
210 ppmuispx 355 Exynos4x12
211 ppmuispmx 356 Exynos4x12
212 fimc_isp 357 Exynos4x12
213 fimc_drc 358 Exynos4x12
214 fimc_fd 359 Exynos4x12
215 mcuisp 360 Exynos4x12
216 gicisp 361 Exynos4x12
217 smmu_isp 362 Exynos4x12
218 smmu_drc 363 Exynos4x12
219 smmu_fd 364 Exynos4x12
220 smmu_lite0 365 Exynos4x12
221 smmu_lite1 366 Exynos4x12
222 mcuctl_isp 367 Exynos4x12
223 mpwm_isp 368 Exynos4x12
224 i2c0_isp 369 Exynos4x12
225 i2c1_isp 370 Exynos4x12
226 mtcadc_isp 371 Exynos4x12
227 pwm_isp 372 Exynos4x12
228 wdt_isp 373 Exynos4x12
229 uart_isp 374 Exynos4x12
230 asyncaxim 375 Exynos4x12
231 smmu_ispcx 376 Exynos4x12
232 spi0_isp 377 Exynos4x12
233 spi1_isp 378 Exynos4x12
234 pwm_isp_sclk 379 Exynos4x12
235 spi0_isp_sclk 380 Exynos4x12
236 spi1_isp_sclk 381 Exynos4x12
237 uart_isp_sclk 382 Exynos4x12
238
239 [Mux Clocks]
240
241 Clock ID SoC (if specific)
242 -----------------------------------------------
243
244 mout_fimc0 384
245 mout_fimc1 385
246 mout_fimc2 386
247 mout_fimc3 387
248 mout_cam0 388
249 mout_cam1 389
250 mout_csis0 390
251 mout_csis1 391
252 mout_g3d0 392
253 mout_g3d1 393
254 mout_g3d 394
255 aclk400_mcuisp 395 Exynos4x12
256
257 [Div Clocks]
258
259 Clock ID SoC (if specific)
260 -----------------------------------------------
261
262 div_isp0 450 Exynos4x12
263 div_isp1 451 Exynos4x12
264 div_mcuisp0 452 Exynos4x12
265 div_mcuisp1 453 Exynos4x12
266 div_aclk200 454 Exynos4x12
267 div_aclk400_mcuisp 455 Exynos4x12
268
269
270Example 1: An example of a clock controller node is listed below.
271
272 clock: clock-controller@0x10030000 {
273 compatible = "samsung,exynos4210-clock";
274 reg = <0x10030000 0x20000>;
275 #clock-cells = <1>;
276 };
277
278Example 2: UART controller node that consumes the clock generated by the clock
279 controller. Refer to the standard clock bindings for information
280 about 'clocks' and 'clock-names' property.
281
282 serial@13820000 {
283 compatible = "samsung,exynos4210-uart";
284 reg = <0x13820000 0x100>;
285 interrupts = <0 54 0>;
286 clocks = <&clock 314>, <&clock 153>;
287 clock-names = "uart", "clk_uart_baud0";
288 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
new file mode 100644
index 000000000000..781a6276adf7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -0,0 +1,177 @@
1* Samsung Exynos5250 Clock Controller
2
3The Exynos5250 clock controller generates and supplies clock to various
4controllers within the Exynos5250 SoC.
5
6Required Properties:
7
8- comptible: should be one of the following.
9 - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
10
11- reg: physical base address of the controller and length of memory mapped
12 region.
13
14- #clock-cells: should be 1.
15
16The following is the list of clocks generated by the controller. Each clock is
17assigned an identifier and client nodes use this identifier to specify the
18clock which they consume.
19
20
21 [Core Clocks]
22
23 Clock ID
24 ----------------------------
25
26 fin_pll 1
27
28 [Clock Gate for Special Clocks]
29
30 Clock ID
31 ----------------------------
32
33 sclk_cam_bayer 128
34 sclk_cam0 129
35 sclk_cam1 130
36 sclk_gscl_wa 131
37 sclk_gscl_wb 132
38 sclk_fimd1 133
39 sclk_mipi1 134
40 sclk_dp 135
41 sclk_hdmi 136
42 sclk_pixel 137
43 sclk_audio0 138
44 sclk_mmc0 139
45 sclk_mmc1 140
46 sclk_mmc2 141
47 sclk_mmc3 142
48 sclk_sata 143
49 sclk_usb3 144
50 sclk_jpeg 145
51 sclk_uart0 146
52 sclk_uart1 147
53 sclk_uart2 148
54 sclk_uart3 149
55 sclk_pwm 150
56 sclk_audio1 151
57 sclk_audio2 152
58 sclk_spdif 153
59 sclk_spi0 154
60 sclk_spi1 155
61 sclk_spi2 156
62
63
64 [Peripheral Clock Gates]
65
66 Clock ID
67 ----------------------------
68
69 gscl0 256
70 gscl1 257
71 gscl2 258
72 gscl3 259
73 gscl_wa 260
74 gscl_wb 261
75 smmu_gscl0 262
76 smmu_gscl1 263
77 smmu_gscl2 264
78 smmu_gscl3 265
79 mfc 266
80 smmu_mfcl 267
81 smmu_mfcr 268
82 rotator 269
83 jpeg 270
84 mdma1 271
85 smmu_rotator 272
86 smmu_jpeg 273
87 smmu_mdma1 274
88 pdma0 275
89 pdma1 276
90 sata 277
91 usbotg 278
92 mipi_hsi 279
93 sdmmc0 280
94 sdmmc1 281
95 sdmmc2 282
96 sdmmc3 283
97 sromc 284
98 usb2 285
99 usb3 286
100 sata_phyctrl 287
101 sata_phyi2c 288
102 uart0 289
103 uart1 290
104 uart2 291
105 uart3 292
106 uart4 293
107 i2c0 294
108 i2c1 295
109 i2c2 296
110 i2c3 297
111 i2c4 298
112 i2c5 299
113 i2c6 300
114 i2c7 301
115 i2c_hdmi 302
116 adc 303
117 spi0 304
118 spi1 305
119 spi2 306
120 i2s1 307
121 i2s2 308
122 pcm1 309
123 pcm2 310
124 pwm 311
125 spdif 312
126 ac97 313
127 hsi2c0 314
128 hsi2c1 315
129 hs12c2 316
130 hs12c3 317
131 chipid 318
132 sysreg 319
133 pmu 320
134 cmu_top 321
135 cmu_core 322
136 cmu_mem 323
137 tzpc0 324
138 tzpc1 325
139 tzpc2 326
140 tzpc3 327
141 tzpc4 328
142 tzpc5 329
143 tzpc6 330
144 tzpc7 331
145 tzpc8 332
146 tzpc9 333
147 hdmi_cec 334
148 mct 335
149 wdt 336
150 rtc 337
151 tmu 338
152 fimd1 339
153 mie1 340
154 dsim0 341
155 dp 342
156 mixer 343
157 hdmi 345
158
159Example 1: An example of a clock controller node is listed below.
160
161 clock: clock-controller@0x10010000 {
162 compatible = "samsung,exynos5250-clock";
163 reg = <0x10010000 0x30000>;
164 #clock-cells = <1>;
165 };
166
167Example 2: UART controller node that consumes the clock generated by the clock
168 controller. Refer to the standard clock bindings for information
169 about 'clocks' and 'clock-names' property.
170
171 serial@13820000 {
172 compatible = "samsung,exynos4210-uart";
173 reg = <0x13820000 0x100>;
174 interrupts = <0 54 0>;
175 clocks = <&clock 314>, <&clock 153>;
176 clock-names = "uart", "clk_uart_baud0";
177 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
new file mode 100644
index 000000000000..4499e9966bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
@@ -0,0 +1,61 @@
1* Samsung Exynos5440 Clock Controller
2
3The Exynos5440 clock controller generates and supplies clock to various
4controllers within the Exynos5440 SoC.
5
6Required Properties:
7
8- comptible: should be "samsung,exynos5440-clock".
9
10- reg: physical base address of the controller and length of memory mapped
11 region.
12
13- #clock-cells: should be 1.
14
15The following is the list of clocks generated by the controller. Each clock is
16assigned an identifier and client nodes use this identifier to specify the
17clock which they consume.
18
19
20 [Core Clocks]
21
22 Clock ID
23 ----------------------------
24
25 xtal 1
26 arm_clk 2
27
28 [Peripheral Clock Gates]
29
30 Clock ID
31 ----------------------------
32
33 spi_baud 16
34 pb0_250 17
35 pr0_250 18
36 pr1_250 19
37 b_250 20
38 b_125 21
39 b_200 22
40 sata 23
41 usb 24
42 gmac0 25
43 cs250 26
44 pb0_250_o 27
45 pr0_250_o 28
46 pr1_250_o 29
47 b_250_o 30
48 b_125_o 31
49 b_200_o 32
50 sata_o 33
51 usb_o 34
52 gmac0_o 35
53 cs250_o 36
54
55Example: An example of a clock controller node is listed below.
56
57 clock: clock-controller@0x10010000 {
58 compatible = "samsung,exynos5440-clock";
59 reg = <0x160000 0x10000>;
60 #clock-cells = <1>;
61 };
diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
new file mode 100644
index 000000000000..5757f9abfc26
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
@@ -0,0 +1,24 @@
1Binding for simple fixed factor rate clock sources.
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be "fixed-factor-clock".
9- #clock-cells : from common clock binding; shall be set to 0.
10- clock-div: fixed divider.
11- clock-mult: fixed multiplier.
12- clocks: parent clock.
13
14Optional properties:
15- clock-output-names : From common clock binding.
16
17Example:
18 clock {
19 compatible = "fixed-factor-clock";
20 clocks = <&parentclk>;
21 #clock-cells = <0>;
22 div = <2>;
23 mult = <1>;
24 };
diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt
new file mode 100644
index 000000000000..ab1a56e9de9d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx27-clock.txt
@@ -0,0 +1,117 @@
1* Clock bindings for Freescale i.MX27
2
3Required properties:
4- compatible: Should be "fsl,imx27-ccm"
5- reg: Address and length of the register set
6- interrupts: Should contain CCM interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of i.MX27
11clocks and IDs.
12
13 Clock ID
14 -----------------------
15 dummy 0
16 ckih 1
17 ckil 2
18 mpll 3
19 spll 4
20 mpll_main2 5
21 ahb 6
22 ipg 7
23 nfc_div 8
24 per1_div 9
25 per2_div 10
26 per3_div 11
27 per4_div 12
28 vpu_sel 13
29 vpu_div 14
30 usb_div 15
31 cpu_sel 16
32 clko_sel 17
33 cpu_div 18
34 clko_div 19
35 ssi1_sel 20
36 ssi2_sel 21
37 ssi1_div 22
38 ssi2_div 23
39 clko_en 24
40 ssi2_ipg_gate 25
41 ssi1_ipg_gate 26
42 slcdc_ipg_gate 27
43 sdhc3_ipg_gate 28
44 sdhc2_ipg_gate 29
45 sdhc1_ipg_gate 30
46 scc_ipg_gate 31
47 sahara_ipg_gate 32
48 rtc_ipg_gate 33
49 pwm_ipg_gate 34
50 owire_ipg_gate 35
51 lcdc_ipg_gate 36
52 kpp_ipg_gate 37
53 iim_ipg_gate 38
54 i2c2_ipg_gate 39
55 i2c1_ipg_gate 40
56 gpt6_ipg_gate 41
57 gpt5_ipg_gate 42
58 gpt4_ipg_gate 43
59 gpt3_ipg_gate 44
60 gpt2_ipg_gate 45
61 gpt1_ipg_gate 46
62 gpio_ipg_gate 47
63 fec_ipg_gate 48
64 emma_ipg_gate 49
65 dma_ipg_gate 50
66 cspi3_ipg_gate 51
67 cspi2_ipg_gate 52
68 cspi1_ipg_gate 53
69 nfc_baud_gate 54
70 ssi2_baud_gate 55
71 ssi1_baud_gate 56
72 vpu_baud_gate 57
73 per4_gate 58
74 per3_gate 59
75 per2_gate 60
76 per1_gate 61
77 usb_ahb_gate 62
78 slcdc_ahb_gate 63
79 sahara_ahb_gate 64
80 lcdc_ahb_gate 65
81 vpu_ahb_gate 66
82 fec_ahb_gate 67
83 emma_ahb_gate 68
84 emi_ahb_gate 69
85 dma_ahb_gate 70
86 csi_ahb_gate 71
87 brom_ahb_gate 72
88 ata_ahb_gate 73
89 wdog_ipg_gate 74
90 usb_ipg_gate 75
91 uart6_ipg_gate 76
92 uart5_ipg_gate 77
93 uart4_ipg_gate 78
94 uart3_ipg_gate 79
95 uart2_ipg_gate 80
96 uart1_ipg_gate 81
97 ckih_div1p5 82
98 fpm 83
99 mpll_osc_sel 84
100 mpll_sel 85
101
102Examples:
103
104clks: ccm@10027000{
105 compatible = "fsl,imx27-ccm";
106 reg = <0x10027000 0x1000>;
107 #clock-cells = <1>;
108};
109
110uart1: serial@1000a000 {
111 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
112 reg = <0x1000a000 0x1000>;
113 interrupts = <20>;
114 clocks = <&clks 81>, <&clks 61>;
115 clock-names = "ipg", "per";
116 status = "disabled";
117};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
new file mode 100644
index 000000000000..d6cb083b90a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
@@ -0,0 +1,303 @@
1NVIDIA Tegra114 Clock And Reset Controller
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
7for muxing and gating Tegra's clocks, and setting their rates.
8
9Required properties :
10- compatible : Should be "nvidia,tegra114-car"
11- reg : Should contain CAR registers location and length
12- clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14- #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the CAR.
16
17 The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
18 registers. These IDs often match those in the CAR's RST_DEVICES registers,
19 but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
20 this case, those clocks are assigned IDs above 160 in order to highlight
21 this issue. Implementations that interpret these clock IDs as bit values
22 within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
23 explicitly handle these special cases.
24
25 The balance of the clocks controlled by the CAR are assigned IDs of 160 and
26 above.
27
28 0 unassigned
29 1 unassigned
30 2 unassigned
31 3 unassigned
32 4 rtc
33 5 timer
34 6 uarta
35 7 unassigned (register bit affects uartb and vfir)
36 8 unassigned
37 9 sdmmc2
38 10 unassigned (register bit affects spdif_in and spdif_out)
39 11 i2s1
40 12 i2c1
41 13 ndflash
42 14 sdmmc1
43 15 sdmmc4
44 16 unassigned
45 17 pwm
46 18 i2s2
47 19 epp
48 20 unassigned (register bit affects vi and vi_sensor)
49 21 2d
50 22 usbd
51 23 isp
52 24 3d
53 25 unassigned
54 26 disp2
55 27 disp1
56 28 host1x
57 29 vcp
58 30 i2s0
59 31 unassigned
60
61 32 unassigned
62 33 unassigned
63 34 apbdma
64 35 unassigned
65 36 kbc
66 37 unassigned
67 38 unassigned
68 39 unassigned (register bit affects fuse and fuse_burn)
69 40 kfuse
70 41 sbc1
71 42 nor
72 43 unassigned
73 44 sbc2
74 45 unassigned
75 46 sbc3
76 47 i2c5
77 48 dsia
78 49 unassigned
79 50 mipi
80 51 hdmi
81 52 csi
82 53 unassigned
83 54 i2c2
84 55 uartc
85 56 mipi-cal
86 57 emc
87 58 usb2
88 59 usb3
89 60 msenc
90 61 vde
91 62 bsea
92 63 bsev
93
94 64 unassigned
95 65 uartd
96 66 unassigned
97 67 i2c3
98 68 sbc4
99 69 sdmmc3
100 70 unassigned
101 71 owr
102 72 afi
103 73 csite
104 74 unassigned
105 75 unassigned
106 76 la
107 77 trace
108 78 soc_therm
109 79 dtv
110 80 ndspeed
111 81 i2cslow
112 82 dsib
113 83 tsec
114 84 unassigned
115 85 unassigned
116 86 unassigned
117 87 unassigned
118 88 unassigned
119 89 xusb_host
120 90 unassigned
121 91 msenc
122 92 csus
123 93 unassigned
124 94 unassigned
125 95 unassigned (bit affects xusb_dev and xusb_dev_src)
126
127 96 unassigned
128 97 unassigned
129 98 unassigned
130 99 mselect
131 100 tsensor
132 101 i2s3
133 102 i2s4
134 103 i2c4
135 104 sbc5
136 105 sbc6
137 106 d_audio
138 107 apbif
139 108 dam0
140 109 dam1
141 110 dam2
142 111 hda2codec_2x
143 112 unassigned
144 113 audio0_2x
145 114 audio1_2x
146 115 audio2_2x
147 116 audio3_2x
148 117 audio4_2x
149 118 spdif_2x
150 119 actmon
151 120 extern1
152 121 extern2
153 122 extern3
154 123 unassigned
155 124 unassigned
156 125 hda
157 126 unassigned
158 127 se
159
160 128 hda2hdmi
161 129 unassigned
162 130 unassigned
163 131 unassigned
164 132 unassigned
165 133 unassigned
166 134 unassigned
167 135 unassigned
168 136 unassigned
169 137 unassigned
170 138 unassigned
171 139 unassigned
172 140 unassigned
173 141 unassigned
174 142 unassigned
175 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
176 xusb_host_src and xusb_ss_src)
177 144 cilab
178 145 cilcd
179 146 cile
180 147 dsialp
181 148 dsiblp
182 149 unassigned
183 150 dds
184 151 unassigned
185 152 dp2
186 153 amx
187 154 adx
188 155 unassigned (bit affects dfll_ref and dfll_soc)
189 156 xusb_ss
190
191 192 uartb
192 193 vfir
193 194 spdif_in
194 195 spdif_out
195 196 vi
196 197 vi_sensor
197 198 fuse
198 199 fuse_burn
199 200 clk_32k
200 201 clk_m
201 202 clk_m_div2
202 203 clk_m_div4
203 204 pll_ref
204 205 pll_c
205 206 pll_c_out1
206 207 pll_c2
207 208 pll_c3
208 209 pll_m
209 210 pll_m_out1
210 211 pll_p
211 212 pll_p_out1
212 213 pll_p_out2
213 214 pll_p_out3
214 215 pll_p_out4
215 216 pll_a
216 217 pll_a_out0
217 218 pll_d
218 219 pll_d_out0
219 220 pll_d2
220 221 pll_d2_out0
221 222 pll_u
222 223 pll_u_480M
223 224 pll_u_60M
224 225 pll_u_48M
225 226 pll_u_12M
226 227 pll_x
227 228 pll_x_out0
228 229 pll_re_vco
229 230 pll_re_out
230 231 pll_e_out0
231 232 spdif_in_sync
232 233 i2s0_sync
233 234 i2s1_sync
234 235 i2s2_sync
235 236 i2s3_sync
236 237 i2s4_sync
237 238 vimclk_sync
238 239 audio0
239 240 audio1
240 241 audio2
241 242 audio3
242 243 audio4
243 244 spdif
244 245 clk_out_1
245 246 clk_out_2
246 247 clk_out_3
247 248 blink
248 252 xusb_host_src
249 253 xusb_falcon_src
250 254 xusb_fs_src
251 255 xusb_ss_src
252 256 xusb_dev_src
253 257 xusb_dev
254 258 xusb_hs_src
255 259 sclk
256 260 hclk
257 261 pclk
258 262 cclk_g
259 263 cclk_lp
260 264 dfll_ref
261 265 dfll_soc
262
263Example SoC include file:
264
265/ {
266 tegra_car: clock {
267 compatible = "nvidia,tegra114-car";
268 reg = <0x60006000 0x1000>;
269 #clock-cells = <1>;
270 };
271
272 usb@c5004000 {
273 clocks = <&tegra_car 58>; /* usb2 */
274 };
275};
276
277Example board file:
278
279/ {
280 clocks {
281 compatible = "simple-bus";
282 #address-cells = <1>;
283 #size-cells = <0>;
284
285 osc: clock@0 {
286 compatible = "fixed-clock";
287 reg = <0>;
288 #clock-cells = <0>;
289 clock-frequency = <12000000>;
290 };
291
292 clk_32k: clock@1 {
293 compatible = "fixed-clock";
294 reg = <1>;
295 #clock-cells = <0>;
296 clock-frequency = <32768>;
297 };
298 };
299
300 &tegra_car {
301 clocks = <&clk_32k> <&osc>;
302 };
303};
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 0921fac73528..e885680f6b45 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
120 90 clk_d 120 90 clk_d
121 91 unassigned 121 91 unassigned
122 92 sus 122 92 sus
123 93 cdev1 123 93 cdev2
124 94 cdev2 124 94 cdev1
125 95 unassigned 125 95 unassigned
126 126
127 96 uart2 127 96 uart2
diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
new file mode 100644
index 000000000000..cc374651662c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/silabs,si5351.txt
@@ -0,0 +1,114 @@
1Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
2
3Reference
4[1] Si5351A/B/C Data Sheet
5 http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
6
7The Si5351a/b/c are programmable i2c clock generators with upto 8 output
8clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
93 output clocks are accessible. The internal structure of the clock
10generators can be found in [1].
11
12==I2C device node==
13
14Required properties:
15- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
16- reg: i2c device address, shall be 0x60 or 0x61.
17- #clock-cells: from common clock binding; shall be set to 1.
18- clocks: from common clock binding; list of parent clock
19 handles, shall be xtal reference clock or xtal and clkin for
20 si5351c only.
21- #address-cells: shall be set to 1.
22- #size-cells: shall be set to 0.
23
24Optional properties:
25- silabs,pll-source: pair of (number, source) for each pll. Allows
26 to overwrite clock source of pll A (number=0) or B (number=1).
27
28==Child nodes==
29
30Each of the clock outputs can be overwritten individually by
31using a child node to the I2C device node. If a child node for a clock
32output is not set, the eeprom configuration is not overwritten.
33
34Required child node properties:
35- reg: number of clock output.
36
37Optional child node properties:
38- silabs,clock-source: source clock of the output divider stage N, shall be
39 0 = multisynth N
40 1 = multisynth 0 for output clocks 0-3, else multisynth4
41 2 = xtal
42 3 = clkin (si5351c only)
43- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
44- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
45 divider.
46- silabs,pll-master: boolean, multisynth can change pll frequency.
47
48==Example==
49
50/* 25MHz reference crystal */
51ref25: ref25M {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <25000000>;
55};
56
57i2c-master-node {
58
59 /* Si5351a msop10 i2c clock generator */
60 si5351a: clock-generator@60 {
61 compatible = "silabs,si5351a-msop";
62 reg = <0x60>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 #clock-cells = <1>;
66
67 /* connect xtal input to 25MHz reference */
68 clocks = <&ref25>;
69
70 /* connect xtal input as source of pll0 and pll1 */
71 silabs,pll-source = <0 0>, <1 0>;
72
73 /*
74 * overwrite clkout0 configuration with:
75 * - 8mA output drive strength
76 * - pll0 as clock source of multisynth0
77 * - multisynth0 as clock source of output divider
78 * - multisynth0 can change pll0
79 * - set initial clock frequency of 74.25MHz
80 */
81 clkout0 {
82 reg = <0>;
83 silabs,drive-strength = <8>;
84 silabs,multisynth-source = <0>;
85 silabs,clock-source = <0>;
86 silabs,pll-master;
87 clock-frequency = <74250000>;
88 };
89
90 /*
91 * overwrite clkout1 configuration with:
92 * - 4mA output drive strength
93 * - pll1 as clock source of multisynth1
94 * - multisynth1 as clock source of output divider
95 * - multisynth1 can change pll1
96 */
97 clkout1 {
98 reg = <1>;
99 silabs,drive-strength = <4>;
100 silabs,multisynth-source = <1>;
101 silabs,clock-source = <0>;
102 pll-master;
103 };
104
105 /*
106 * overwrite clkout2 configuration with:
107 * - xtal as clock source of output divider
108 */
109 clkout2 {
110 reg = <2>;
111 silabs,clock-source = <2>;
112 };
113 };
114};
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
new file mode 100644
index 000000000000..729f52426fe1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -0,0 +1,151 @@
1Device Tree Clock bindings for arch-sunxi
2
3This binding uses the common clock binding[1].
4
5[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6
7Required properties:
8- compatible : shall be one of the following:
9 "allwinner,sun4i-osc-clk" - for a gatable oscillator
10 "allwinner,sun4i-pll1-clk" - for the main PLL clock
11 "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
12 "allwinner,sun4i-axi-clk" - for the AXI clock
13 "allwinner,sun4i-axi-gates-clk" - for the AXI gates
14 "allwinner,sun4i-ahb-clk" - for the AHB clock
15 "allwinner,sun4i-ahb-gates-clk" - for the AHB gates
16 "allwinner,sun4i-apb0-clk" - for the APB0 clock
17 "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
18 "allwinner,sun4i-apb1-clk" - for the APB1 clock
19 "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
20 "allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
21
22Required properties for all clocks:
23- reg : shall be the control register address for the clock.
24- clocks : shall be the input parent clock(s) phandle for the clock
25- #clock-cells : from common clock binding; shall be set to 0 except for
26 "allwinner,sun4i-*-gates-clk" where it shall be set to 1
27
28Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
29- clock-output-names : the corresponding gate names that the clock controls
30
31For example:
32
33osc24M: osc24M@01c20050 {
34 #clock-cells = <0>;
35 compatible = "allwinner,sun4i-osc-clk";
36 reg = <0x01c20050 0x4>;
37 clocks = <&osc24M_fixed>;
38};
39
40pll1: pll1@01c20000 {
41 #clock-cells = <0>;
42 compatible = "allwinner,sun4i-pll1-clk";
43 reg = <0x01c20000 0x4>;
44 clocks = <&osc24M>;
45};
46
47cpu: cpu@01c20054 {
48 #clock-cells = <0>;
49 compatible = "allwinner,sun4i-cpu-clk";
50 reg = <0x01c20054 0x4>;
51 clocks = <&osc32k>, <&osc24M>, <&pll1>;
52};
53
54
55
56Gate clock outputs
57
58The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
59their corresponding offsets as present on sun4i are listed below. Note that
60some of these gates are not present on sun5i.
61
62 * AXI gates ("allwinner,sun4i-axi-gates-clk")
63
64 DRAM 0
65
66 * AHB gates ("allwinner,sun4i-ahb-gates-clk")
67
68 USB0 0
69 EHCI0 1
70 OHCI0 2*
71 EHCI1 3
72 OHCI1 4*
73 SS 5
74 DMA 6
75 BIST 7
76 MMC0 8
77 MMC1 9
78 MMC2 10
79 MMC3 11
80 MS 12**
81 NAND 13
82 SDRAM 14
83
84 ACE 16
85 EMAC 17
86 TS 18
87
88 SPI0 20
89 SPI1 21
90 SPI2 22
91 SPI3 23
92 PATA 24
93 SATA 25**
94 GPS 26*
95
96 VE 32
97 TVD 33
98 TVE0 34
99 TVE1 35
100 LCD0 36
101 LCD1 37
102
103 CSI0 40
104 CSI1 41
105
106 HDMI 43
107 DE_BE0 44
108 DE_BE1 45
109 DE_FE0 46
110 DE_FE1 47
111
112 MP 50
113
114 MALI400 52
115
116 * APB0 gates ("allwinner,sun4i-apb0-gates-clk")
117
118 CODEC 0
119 SPDIF 1*
120 AC97 2
121 IIS 3
122
123 PIO 5
124 IR0 6
125 IR1 7
126
127 KEYPAD 10
128
129 * APB1 gates ("allwinner,sun4i-apb1-gates-clk")
130
131 I2C0 0
132 I2C1 1
133 I2C2 2
134
135 CAN 4
136 SCR 5
137 PS20 6
138 PS21 7
139
140 UART0 16
141 UART1 17
142 UART2 18
143 UART3 19
144 UART4 20
145 UART5 21
146 UART6 22
147 UART7 23
148
149Notation:
150 [*]: The datasheet didn't mention these, but they are present on AW code
151 [**]: The datasheet had this marked as "NC" but they are used on AW code
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 22:07:08 -0500