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-rw-r--r--Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt15
-rw-r--r--Documentation/devicetree/bindings/arm/amlogic.txt8
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-at91.txt45
-rw-r--r--Documentation/devicetree/bindings/arm/bcm/bcm63138.txt9
-rw-r--r--Documentation/devicetree/bindings/arm/cavium-thunder.txt10
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt9
-rw-r--r--Documentation/devicetree/bindings/arm/exynos/power_domain.txt13
-rw-r--r--Documentation/devicetree/bindings/arm/geniatech.txt5
-rw-r--r--Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt23
-rw-r--r--Documentation/devicetree/bindings/arm/idle-states.txt679
-rw-r--r--Documentation/devicetree/bindings/arm/l2cc.txt10
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek.txt6
-rw-r--r--Documentation/devicetree/bindings/arm/omap/mpu.txt3
-rw-r--r--Documentation/devicetree/bindings/arm/omap/omap.txt12
-rw-r--r--Documentation/devicetree/bindings/arm/psci.txt14
-rw-r--r--Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt18
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt71
-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt12
18 files changed, 944 insertions, 18 deletions
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
new file mode 100644
index 000000000000..d0ce01da5c59
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt
@@ -0,0 +1,15 @@
1Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2The EDAC accesses a range of registers in the SDRAM controller.
3
4Required properties:
5- compatible : should contain "altr,sdram-edac";
6- altr,sdr-syscon : phandle of the sdr module
7- interrupts : Should contain the SDRAM ECC IRQ in the
8 appropriate format for the IRQ controller.
9
10Example:
11 sdramedac {
12 compatible = "altr,sdram-edac";
13 altr,sdr-syscon = <&sdr>;
14 interrupts = <0 39 4>;
15 };
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
new file mode 100644
index 000000000000..7eece72b1a35
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -0,0 +1,8 @@
1Amlogic MesonX device tree bindings
2-------------------------------------------
3
4Boards with the Amlogic Meson6 SoC shall have the following properties:
5
6Required root node property:
7
8compatible = "amlogic,meson6";
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 16f60b41c147..562cda9d86d9 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -1,6 +1,43 @@
1Atmel AT91 device tree bindings. 1Atmel AT91 device tree bindings.
2================================ 2================================
3 3
4Boards with a SoC of the Atmel AT91 or SMART family shall have the following
5properties:
6
7Required root node properties:
8compatible: must be one of:
9 * "atmel,at91rm9200"
10
11 * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
12 the specific SoC family or compatible:
13 o "atmel,at91sam9260"
14 o "atmel,at91sam9261"
15 o "atmel,at91sam9263"
16 o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
17 SoC compatible:
18 - "atmel,at91sam9g15"
19 - "atmel,at91sam9g25"
20 - "atmel,at91sam9g35"
21 - "atmel,at91sam9x25"
22 - "atmel,at91sam9x35"
23 o "atmel,at91sam9g20"
24 o "atmel,at91sam9g45"
25 o "atmel,at91sam9n12"
26 o "atmel,at91sam9rl"
27 * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
28 SoC family:
29 o "atmel,sama5d3" shall be extended with the specific SoC compatible:
30 - "atmel,sama5d31"
31 - "atmel,sama5d33"
32 - "atmel,sama5d34"
33 - "atmel,sama5d35"
34 - "atmel,sama5d36"
35 o "atmel,sama5d4" shall be extended with the specific SoC compatible:
36 - "atmel,sama5d41"
37 - "atmel,sama5d42"
38 - "atmel,sama5d43"
39 - "atmel,sama5d44"
40
4PIT Timer required properties: 41PIT Timer required properties:
5- compatible: Should be "atmel,at91sam9260-pit" 42- compatible: Should be "atmel,at91sam9260-pit"
6- reg: Should contain registers location and length 43- reg: Should contain registers location and length
@@ -61,8 +98,8 @@ RAMC SDRAM/DDR Controller required properties:
61- compatible: Should be "atmel,at91rm9200-sdramc", 98- compatible: Should be "atmel,at91rm9200-sdramc",
62 "atmel,at91sam9260-sdramc", 99 "atmel,at91sam9260-sdramc",
63 "atmel,at91sam9g45-ddramc", 100 "atmel,at91sam9g45-ddramc",
101 "atmel,sama5d3-ddramc",
64- reg: Should contain registers location and length 102- reg: Should contain registers location and length
65 For at91sam9263 and at91sam9g45 you must specify 2 entries.
66 103
67Examples: 104Examples:
68 105
@@ -71,12 +108,6 @@ Examples:
71 reg = <0xffffe800 0x200>; 108 reg = <0xffffe800 0x200>;
72 }; 109 };
73 110
74 ramc0: ramc@ffffe400 {
75 compatible = "atmel,at91sam9g45-ddramc";
76 reg = <0xffffe400 0x200
77 0xffffe600 0x200>;
78 };
79
80SHDWC Shutdown Controller 111SHDWC Shutdown Controller
81 112
82required properties: 113required properties:
diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
new file mode 100644
index 000000000000..bd49987a8812
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/bcm63138.txt
@@ -0,0 +1,9 @@
1Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2-----------------------------------------------------------
3
4Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
5following properties:
6
7Required root node property:
8
9compatible: should be "brcm,bcm63138"
diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
new file mode 100644
index 000000000000..6f63a5866902
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cavium-thunder.txt
@@ -0,0 +1,10 @@
1Cavium Thunder platform device tree bindings
2--------------------------------------------
3
4Boards with Cavium's Thunder SoC shall have following properties.
5
6Root Node
7---------
8Required root node properties:
9
10 - compatible = "cavium,thunder-88xx";
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 298e2f6b33c6..fc446347ab6d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -166,6 +166,7 @@ nodes to be present and contain the properties described below.
166 "arm,cortex-r5" 166 "arm,cortex-r5"
167 "arm,cortex-r7" 167 "arm,cortex-r7"
168 "brcm,brahma-b15" 168 "brcm,brahma-b15"
169 "cavium,thunder"
169 "faraday,fa526" 170 "faraday,fa526"
170 "intel,sa110" 171 "intel,sa110"
171 "intel,sa1100" 172 "intel,sa1100"
@@ -219,6 +220,12 @@ nodes to be present and contain the properties described below.
219 Value type: <phandle> 220 Value type: <phandle>
220 Definition: Specifies the ACC[2] node associated with this CPU. 221 Definition: Specifies the ACC[2] node associated with this CPU.
221 222
223 - cpu-idle-states
224 Usage: Optional
225 Value type: <prop-encoded-array>
226 Definition:
227 # List of phandles to idle state nodes supported
228 by this cpu [3].
222 229
223Example 1 (dual-cluster big.LITTLE system 32-bit): 230Example 1 (dual-cluster big.LITTLE system 32-bit):
224 231
@@ -415,3 +422,5 @@ cpus {
415-- 422--
416[1] arm/msm/qcom,saw2.txt 423[1] arm/msm/qcom,saw2.txt
417[2] arm/msm/qcom,kpss-acc.txt 424[2] arm/msm/qcom,kpss-acc.txt
425[3] ARM Linux kernel documentation - idle states bindings
426 Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 8b4f7b7fe88b..abde1ea8a119 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -8,6 +8,8 @@ Required Properties:
8 * samsung,exynos4210-pd - for exynos4210 type power domain. 8 * samsung,exynos4210-pd - for exynos4210 type power domain.
9- reg: physical base address of the controller and length of memory mapped 9- reg: physical base address of the controller and length of memory mapped
10 region. 10 region.
11- #power-domain-cells: number of cells in power domain specifier;
12 must be 0.
11 13
12Optional Properties: 14Optional Properties:
13- clocks: List of clock handles. The parent clocks of the input clocks to the 15- clocks: List of clock handles. The parent clocks of the input clocks to the
@@ -29,6 +31,7 @@ Example:
29 lcd0: power-domain-lcd0 { 31 lcd0: power-domain-lcd0 {
30 compatible = "samsung,exynos4210-pd"; 32 compatible = "samsung,exynos4210-pd";
31 reg = <0x10023C00 0x10>; 33 reg = <0x10023C00 0x10>;
34 #power-domain-cells = <0>;
32 }; 35 };
33 36
34 mfc_pd: power-domain@10044060 { 37 mfc_pd: power-domain@10044060 {
@@ -37,12 +40,8 @@ Example:
37 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, 40 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
38 <&clock CLK_MOUT_USER_ACLK333>; 41 <&clock CLK_MOUT_USER_ACLK333>;
39 clock-names = "oscclk", "pclk0", "clk0"; 42 clock-names = "oscclk", "pclk0", "clk0";
43 #power-domain-cells = <0>;
40 }; 44 };
41 45
42Example of the node using power domain: 46See Documentation/devicetree/bindings/power/power_domain.txt for description
43 47of consumer-side bindings.
44 node {
45 /* ... */
46 samsung,power-domain = <&lcd0>;
47 /* ... */
48 };
diff --git a/Documentation/devicetree/bindings/arm/geniatech.txt b/Documentation/devicetree/bindings/arm/geniatech.txt
new file mode 100644
index 000000000000..74ccba40b73b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/geniatech.txt
@@ -0,0 +1,5 @@
1Geniatech platforms device tree bindings
2-------------------------------------------
3
4Geniatech ATV1200
5 - compatible = "geniatech,atv1200"
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
index 934f00025cc4..f717c7b48603 100644
--- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
@@ -5,6 +5,11 @@ Hi4511 Board
5Required root node properties: 5Required root node properties:
6 - compatible = "hisilicon,hi3620-hi4511"; 6 - compatible = "hisilicon,hi3620-hi4511";
7 7
8HiP04 D01 Board
9Required root node properties:
10 - compatible = "hisilicon,hip04-d01";
11
12
8Hisilicon system controller 13Hisilicon system controller
9 14
10Required properties: 15Required properties:
@@ -55,3 +60,21 @@ Example:
55 compatible = "hisilicon,pctrl"; 60 compatible = "hisilicon,pctrl";
56 reg = <0xfca09000 0x1000>; 61 reg = <0xfca09000 0x1000>;
57 }; 62 };
63
64-----------------------------------------------------------------------
65Fabric:
66
67Required Properties:
68- compatible: "hisilicon,hip04-fabric";
69- reg: Address and size of Fabric
70
71-----------------------------------------------------------------------
72Bootwrapper boot method (software protocol on SMP):
73
74Required Properties:
75- compatible: "hisilicon,hip04-bootwrapper";
76- boot-method: Address and size of boot method.
77 [0]: bootwrapper physical address
78 [1]: bootwrapper size
79 [2]: relocation physical address
80 [3]: relocation size
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
new file mode 100644
index 000000000000..37375c7f3ccc
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -0,0 +1,679 @@
1==========================================
2ARM idle states binding description
3==========================================
4
5==========================================
61 - Introduction
7==========================================
8
9ARM systems contain HW capable of managing power consumption dynamically,
10where cores can be put in different low-power states (ranging from simple
11wfi to power gating) according to OS PM policies. The CPU states representing
12the range of dynamic idle states that a processor can enter at run-time, can be
13specified through device tree bindings representing the parameters required
14to enter/exit specific idle states on a given processor.
15
16According to the Server Base System Architecture document (SBSA, [3]), the
17power states an ARM CPU can be put into are identified by the following list:
18
19- Running
20- Idle_standby
21- Idle_retention
22- Sleep
23- Off
24
25The power states described in the SBSA document define the basic CPU states on
26top of which ARM platforms implement power management schemes that allow an OS
27PM implementation to put the processor in different idle states (which include
28states listed above; "off" state is not an idle state since it does not have
29wake-up capabilities, hence it is not considered in this document).
30
31Idle state parameters (eg entry latency) are platform specific and need to be
32characterized with bindings that provide the required information to OS PM
33code so that it can build the required tables and use them at runtime.
34
35The device tree binding definition for ARM idle states is the subject of this
36document.
37
38===========================================
392 - idle-states definitions
40===========================================
41
42Idle states are characterized for a specific system through a set of
43timing and energy related properties, that underline the HW behaviour
44triggered upon idle states entry and exit.
45
46The following diagram depicts the CPU execution phases and related timing
47properties required to enter and exit an idle state:
48
49..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
50 | | | | |
51
52 |<------ entry ------->|
53 | latency |
54 |<- exit ->|
55 | latency |
56 |<-------- min-residency -------->|
57 |<------- wakeup-latency ------->|
58
59 Diagram 1: CPU idle state execution phases
60
61EXEC: Normal CPU execution.
62
63PREP: Preparation phase before committing the hardware to idle mode
64 like cache flushing. This is abortable on pending wake-up
65 event conditions. The abort latency is assumed to be negligible
66 (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
67 goes back to EXEC. This phase is optional. If not abortable,
68 this should be included in the ENTRY phase instead.
69
70ENTRY: The hardware is committed to idle mode. This period must run
71 to completion up to IDLE before anything else can happen.
72
73IDLE: This is the actual energy-saving idle period. This may last
74 between 0 and infinite time, until a wake-up event occurs.
75
76EXIT: Period during which the CPU is brought back to operational
77 mode (EXEC).
78
79entry-latency: Worst case latency required to enter the idle state. The
80exit-latency may be guaranteed only after entry-latency has passed.
81
82min-residency: Minimum period, including preparation and entry, for a given
83idle state to be worthwhile energywise.
84
85wakeup-latency: Maximum delay between the signaling of a wake-up event and the
86CPU being able to execute normal code again. If not specified, this is assumed
87to be entry-latency + exit-latency.
88
89These timing parameters can be used by an OS in different circumstances.
90
91An idle CPU requires the expected min-residency time to select the most
92appropriate idle state based on the expected expiry time of the next IRQ
93(ie wake-up) that causes the CPU to return to the EXEC phase.
94
95An operating system scheduler may need to compute the shortest wake-up delay
96for CPUs in the system by detecting how long will it take to get a CPU out
97of an idle state, eg:
98
99wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
100
101In other words, the scheduler can make its scheduling decision by selecting
102(eg waking-up) the CPU with the shortest wake-up latency.
103The wake-up latency must take into account the entry latency if that period
104has not expired. The abortable nature of the PREP period can be ignored
105if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
106the worst case since it depends on the CPU operating conditions, ie caches
107state).
108
109An OS has to reliably probe the wakeup-latency since some devices can enforce
110latency constraints guarantees to work properly, so the OS has to detect the
111worst case wake-up latency it can incur if a CPU is allowed to enter an
112idle state, and possibly to prevent that to guarantee reliable device
113functioning.
114
115The min-residency time parameter deserves further explanation since it is
116expressed in time units but must factor in energy consumption coefficients.
117
118The energy consumption of a cpu when it enters a power state can be roughly
119characterised by the following graph:
120
121 |
122 |
123 |
124 e |
125 n | /---
126 e | /------
127 r | /------
128 g | /-----
129 y | /------
130 | ----
131 | /|
132 | / |
133 | / |
134 | / |
135 | / |
136 | / |
137 |/ |
138 -----|-------+----------------------------------
139 0| 1 time(ms)
140
141 Graph 1: Energy vs time example
142
143The graph is split in two parts delimited by time 1ms on the X-axis.
144The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
145and denotes the energy costs incurred whilst entering and leaving the idle
146state.
147The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
148shallower slope and essentially represents the energy consumption of the idle
149state.
150
151min-residency is defined for a given idle state as the minimum expected
152residency time for a state (inclusive of preparation and entry) after
153which choosing that state become the most energy efficient option. A good
154way to visualise this, is by taking the same graph above and comparing some
155states energy consumptions plots.
156
157For sake of simplicity, let's consider a system with two idle states IDLE1,
158and IDLE2:
159
160 |
161 |
162 |
163 | /-- IDLE1
164 e | /---
165 n | /----
166 e | /---
167 r | /-----/--------- IDLE2
168 g | /-------/---------
169 y | ------------ /---|
170 | / /---- |
171 | / /--- |
172 | / /---- |
173 | / /--- |
174 | --- |
175 | / |
176 | / |
177 |/ | time
178 ---/----------------------------+------------------------
179 |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
180 |
181 IDLE2-min-residency
182
183 Graph 2: idle states min-residency example
184
185In graph 2 above, that takes into account idle states entry/exit energy
186costs, it is clear that if the idle state residency time (ie time till next
187wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
188choice energywise.
189
190This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
191than IDLE2.
192
193However, the lower power consumption (ie shallower energy curve slope) of idle
194state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
195efficient.
196
197The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
198shallower states in a system with multiple idle states) is defined
199IDLE2-min-residency and corresponds to the time when energy consumption of
200IDLE1 and IDLE2 states breaks even.
201
202The definitions provided in this section underpin the idle states
203properties specification that is the subject of the following sections.
204
205===========================================
2063 - idle-states node
207===========================================
208
209ARM processor idle states are defined within the idle-states node, which is
210a direct child of the cpus node [1] and provides a container where the
211processor idle states, defined as device tree nodes, are listed.
212
213- idle-states node
214
215 Usage: Optional - On ARM systems, it is a container of processor idle
216 states nodes. If the system does not provide CPU
217 power management capabilities or the processor just
218 supports idle_standby an idle-states node is not
219 required.
220
221 Description: idle-states node is a container node, where its
222 subnodes describe the CPU idle states.
223
224 Node name must be "idle-states".
225
226 The idle-states node's parent node must be the cpus node.
227
228 The idle-states node's child nodes can be:
229
230 - one or more state nodes
231
232 Any other configuration is considered invalid.
233
234 An idle-states node defines the following properties:
235
236 - entry-method
237 Value type: <stringlist>
238 Usage and definition depend on ARM architecture version.
239 # On ARM v8 64-bit this property is required and must
240 be one of:
241 - "psci" (see bindings in [2])
242 # On ARM 32-bit systems this property is optional
243
244The nodes describing the idle states (state) can only be defined within the
245idle-states node, any other configuration is considered invalid and therefore
246must be ignored.
247
248===========================================
2494 - state node
250===========================================
251
252A state node represents an idle state description and must be defined as
253follows:
254
255- state node
256
257 Description: must be child of the idle-states node
258
259 The state node name shall follow standard device tree naming
260 rules ([5], 2.2.1 "Node names"), in particular state nodes which
261 are siblings within a single common parent must be given a unique name.
262
263 The idle state entered by executing the wfi instruction (idle_standby
264 SBSA,[3][4]) is considered standard on all ARM platforms and therefore
265 must not be listed.
266
267 With the definitions provided above, the following list represents
268 the valid properties for a state node:
269
270 - compatible
271 Usage: Required
272 Value type: <stringlist>
273 Definition: Must be "arm,idle-state".
274
275 - local-timer-stop
276 Usage: See definition
277 Value type: <none>
278 Definition: if present the CPU local timer control logic is
279 lost on state entry, otherwise it is retained.
280
281 - entry-latency-us
282 Usage: Required
283 Value type: <prop-encoded-array>
284 Definition: u32 value representing worst case latency in
285 microseconds required to enter the idle state.
286 The exit-latency-us duration may be guaranteed
287 only after entry-latency-us has passed.
288
289 - exit-latency-us
290 Usage: Required
291 Value type: <prop-encoded-array>
292 Definition: u32 value representing worst case latency
293 in microseconds required to exit the idle state.
294
295 - min-residency-us
296 Usage: Required
297 Value type: <prop-encoded-array>
298 Definition: u32 value representing minimum residency duration
299 in microseconds, inclusive of preparation and
300 entry, for this idle state to be considered
301 worthwhile energy wise (refer to section 2 of
302 this document for a complete description).
303
304 - wakeup-latency-us:
305 Usage: Optional
306 Value type: <prop-encoded-array>
307 Definition: u32 value representing maximum delay between the
308 signaling of a wake-up event and the CPU being
309 able to execute normal code again. If omitted,
310 this is assumed to be equal to:
311
312 entry-latency-us + exit-latency-us
313
314 It is important to supply this value on systems
315 where the duration of PREP phase (see diagram 1,
316 section 2) is non-neglibigle.
317 In such systems entry-latency-us + exit-latency-us
318 will exceed wakeup-latency-us by this duration.
319
320 In addition to the properties listed above, a state node may require
321 additional properties specifics to the entry-method defined in the
322 idle-states node, please refer to the entry-method bindings
323 documentation for properties definitions.
324
325===========================================
3264 - Examples
327===========================================
328
329Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
330
331cpus {
332 #size-cells = <0>;
333 #address-cells = <2>;
334
335 CPU0: cpu@0 {
336 device_type = "cpu";
337 compatible = "arm,cortex-a57";
338 reg = <0x0 0x0>;
339 enable-method = "psci";
340 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
341 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
342 };
343
344 CPU1: cpu@1 {
345 device_type = "cpu";
346 compatible = "arm,cortex-a57";
347 reg = <0x0 0x1>;
348 enable-method = "psci";
349 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
350 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
351 };
352
353 CPU2: cpu@100 {
354 device_type = "cpu";
355 compatible = "arm,cortex-a57";
356 reg = <0x0 0x100>;
357 enable-method = "psci";
358 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
359 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
360 };
361
362 CPU3: cpu@101 {
363 device_type = "cpu";
364 compatible = "arm,cortex-a57";
365 reg = <0x0 0x101>;
366 enable-method = "psci";
367 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
368 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
369 };
370
371 CPU4: cpu@10000 {
372 device_type = "cpu";
373 compatible = "arm,cortex-a57";
374 reg = <0x0 0x10000>;
375 enable-method = "psci";
376 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
377 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
378 };
379
380 CPU5: cpu@10001 {
381 device_type = "cpu";
382 compatible = "arm,cortex-a57";
383 reg = <0x0 0x10001>;
384 enable-method = "psci";
385 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
386 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
387 };
388
389 CPU6: cpu@10100 {
390 device_type = "cpu";
391 compatible = "arm,cortex-a57";
392 reg = <0x0 0x10100>;
393 enable-method = "psci";
394 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
395 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
396 };
397
398 CPU7: cpu@10101 {
399 device_type = "cpu";
400 compatible = "arm,cortex-a57";
401 reg = <0x0 0x10101>;
402 enable-method = "psci";
403 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
404 &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
405 };
406
407 CPU8: cpu@100000000 {
408 device_type = "cpu";
409 compatible = "arm,cortex-a53";
410 reg = <0x1 0x0>;
411 enable-method = "psci";
412 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
413 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
414 };
415
416 CPU9: cpu@100000001 {
417 device_type = "cpu";
418 compatible = "arm,cortex-a53";
419 reg = <0x1 0x1>;
420 enable-method = "psci";
421 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
422 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
423 };
424
425 CPU10: cpu@100000100 {
426 device_type = "cpu";
427 compatible = "arm,cortex-a53";
428 reg = <0x1 0x100>;
429 enable-method = "psci";
430 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
431 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
432 };
433
434 CPU11: cpu@100000101 {
435 device_type = "cpu";
436 compatible = "arm,cortex-a53";
437 reg = <0x1 0x101>;
438 enable-method = "psci";
439 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
440 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
441 };
442
443 CPU12: cpu@100010000 {
444 device_type = "cpu";
445 compatible = "arm,cortex-a53";
446 reg = <0x1 0x10000>;
447 enable-method = "psci";
448 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
449 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
450 };
451
452 CPU13: cpu@100010001 {
453 device_type = "cpu";
454 compatible = "arm,cortex-a53";
455 reg = <0x1 0x10001>;
456 enable-method = "psci";
457 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
458 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
459 };
460
461 CPU14: cpu@100010100 {
462 device_type = "cpu";
463 compatible = "arm,cortex-a53";
464 reg = <0x1 0x10100>;
465 enable-method = "psci";
466 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
467 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
468 };
469
470 CPU15: cpu@100010101 {
471 device_type = "cpu";
472 compatible = "arm,cortex-a53";
473 reg = <0x1 0x10101>;
474 enable-method = "psci";
475 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
476 &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
477 };
478
479 idle-states {
480 entry-method = "arm,psci";
481
482 CPU_RETENTION_0_0: cpu-retention-0-0 {
483 compatible = "arm,idle-state";
484 arm,psci-suspend-param = <0x0010000>;
485 entry-latency-us = <20>;
486 exit-latency-us = <40>;
487 min-residency-us = <80>;
488 };
489
490 CLUSTER_RETENTION_0: cluster-retention-0 {
491 compatible = "arm,idle-state";
492 local-timer-stop;
493 arm,psci-suspend-param = <0x1010000>;
494 entry-latency-us = <50>;
495 exit-latency-us = <100>;
496 min-residency-us = <250>;
497 wakeup-latency-us = <130>;
498 };
499
500 CPU_SLEEP_0_0: cpu-sleep-0-0 {
501 compatible = "arm,idle-state";
502 local-timer-stop;
503 arm,psci-suspend-param = <0x0010000>;
504 entry-latency-us = <250>;
505 exit-latency-us = <500>;
506 min-residency-us = <950>;
507 };
508
509 CLUSTER_SLEEP_0: cluster-sleep-0 {
510 compatible = "arm,idle-state";
511 local-timer-stop;
512 arm,psci-suspend-param = <0x1010000>;
513 entry-latency-us = <600>;
514 exit-latency-us = <1100>;
515 min-residency-us = <2700>;
516 wakeup-latency-us = <1500>;
517 };
518
519 CPU_RETENTION_1_0: cpu-retention-1-0 {
520 compatible = "arm,idle-state";
521 arm,psci-suspend-param = <0x0010000>;
522 entry-latency-us = <20>;
523 exit-latency-us = <40>;
524 min-residency-us = <90>;
525 };
526
527 CLUSTER_RETENTION_1: cluster-retention-1 {
528 compatible = "arm,idle-state";
529 local-timer-stop;
530 arm,psci-suspend-param = <0x1010000>;
531 entry-latency-us = <50>;
532 exit-latency-us = <100>;
533 min-residency-us = <270>;
534 wakeup-latency-us = <100>;
535 };
536
537 CPU_SLEEP_1_0: cpu-sleep-1-0 {
538 compatible = "arm,idle-state";
539 local-timer-stop;
540 arm,psci-suspend-param = <0x0010000>;
541 entry-latency-us = <70>;
542 exit-latency-us = <100>;
543 min-residency-us = <300>;
544 wakeup-latency-us = <150>;
545 };
546
547 CLUSTER_SLEEP_1: cluster-sleep-1 {
548 compatible = "arm,idle-state";
549 local-timer-stop;
550 arm,psci-suspend-param = <0x1010000>;
551 entry-latency-us = <500>;
552 exit-latency-us = <1200>;
553 min-residency-us = <3500>;
554 wakeup-latency-us = <1300>;
555 };
556 };
557
558};
559
560Example 2 (ARM 32-bit, 8-cpu system, two clusters):
561
562cpus {
563 #size-cells = <0>;
564 #address-cells = <1>;
565
566 CPU0: cpu@0 {
567 device_type = "cpu";
568 compatible = "arm,cortex-a15";
569 reg = <0x0>;
570 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
571 };
572
573 CPU1: cpu@1 {
574 device_type = "cpu";
575 compatible = "arm,cortex-a15";
576 reg = <0x1>;
577 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
578 };
579
580 CPU2: cpu@2 {
581 device_type = "cpu";
582 compatible = "arm,cortex-a15";
583 reg = <0x2>;
584 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
585 };
586
587 CPU3: cpu@3 {
588 device_type = "cpu";
589 compatible = "arm,cortex-a15";
590 reg = <0x3>;
591 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
592 };
593
594 CPU4: cpu@100 {
595 device_type = "cpu";
596 compatible = "arm,cortex-a7";
597 reg = <0x100>;
598 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
599 };
600
601 CPU5: cpu@101 {
602 device_type = "cpu";
603 compatible = "arm,cortex-a7";
604 reg = <0x101>;
605 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
606 };
607
608 CPU6: cpu@102 {
609 device_type = "cpu";
610 compatible = "arm,cortex-a7";
611 reg = <0x102>;
612 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
613 };
614
615 CPU7: cpu@103 {
616 device_type = "cpu";
617 compatible = "arm,cortex-a7";
618 reg = <0x103>;
619 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
620 };
621
622 idle-states {
623 CPU_SLEEP_0_0: cpu-sleep-0-0 {
624 compatible = "arm,idle-state";
625 local-timer-stop;
626 entry-latency-us = <200>;
627 exit-latency-us = <100>;
628 min-residency-us = <400>;
629 wakeup-latency-us = <250>;
630 };
631
632 CLUSTER_SLEEP_0: cluster-sleep-0 {
633 compatible = "arm,idle-state";
634 local-timer-stop;
635 entry-latency-us = <500>;
636 exit-latency-us = <1500>;
637 min-residency-us = <2500>;
638 wakeup-latency-us = <1700>;
639 };
640
641 CPU_SLEEP_1_0: cpu-sleep-1-0 {
642 compatible = "arm,idle-state";
643 local-timer-stop;
644 entry-latency-us = <300>;
645 exit-latency-us = <500>;
646 min-residency-us = <900>;
647 wakeup-latency-us = <600>;
648 };
649
650 CLUSTER_SLEEP_1: cluster-sleep-1 {
651 compatible = "arm,idle-state";
652 local-timer-stop;
653 entry-latency-us = <800>;
654 exit-latency-us = <2000>;
655 min-residency-us = <6500>;
656 wakeup-latency-us = <2300>;
657 };
658 };
659
660};
661
662===========================================
6635 - References
664===========================================
665
666[1] ARM Linux Kernel documentation - CPUs bindings
667 Documentation/devicetree/bindings/arm/cpus.txt
668
669[2] ARM Linux Kernel documentation - PSCI bindings
670 Documentation/devicetree/bindings/arm/psci.txt
671
672[3] ARM Server Base System Architecture (SBSA)
673 http://infocenter.arm.com/help/index.jsp
674
675[4] ARM Architecture Reference Manuals
676 http://infocenter.arm.com/help/index.jsp
677
678[5] ePAPR standard
679 https://www.power.org/documentation/epapr-version-1-1/
diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index af527ee111c2..292ef7ca3058 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -2,6 +2,10 @@
2 2
3ARM cores often have a separate level 2 cache controller. There are various 3ARM cores often have a separate level 2 cache controller. There are various
4implementations of the L2 cache controller with compatible programming models. 4implementations of the L2 cache controller with compatible programming models.
5Some of the properties that are just prefixed "cache-*" are taken from section
63.7.3 of the ePAPR v1.1 specification which can be found at:
7https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf
8
5The ARM L2 cache representation in the device tree should be done as follows: 9The ARM L2 cache representation in the device tree should be done as follows:
6 10
7Required properties: 11Required properties:
@@ -44,6 +48,12 @@ Optional properties:
44 I/O coherent mode. Valid only when the arm,pl310-cache compatible 48 I/O coherent mode. Valid only when the arm,pl310-cache compatible
45 string is used. 49 string is used.
46- interrupts : 1 combined interrupt. 50- interrupts : 1 combined interrupt.
51- cache-size : specifies the size in bytes of the cache
52- cache-sets : specifies the number of associativity sets of the cache
53- cache-block-size : specifies the size in bytes of a cache block
54- cache-line-size : specifies the size in bytes of a line in the cache,
55 if this is not specified, the line size is assumed to be equal to the
56 cache block size
47- cache-id-part: cache id part number to be used if it is not present 57- cache-id-part: cache id part number to be used if it is not present
48 on hardware 58 on hardware
49- wt-override: If present then L2 is forced to Write through mode 59- wt-override: If present then L2 is forced to Write through mode
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt
index d6ac71f37314..fa252261dfaf 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -6,3 +6,9 @@ Required root node property:
6 6
7compatible: must contain "mediatek,mt6589" 7compatible: must contain "mediatek,mt6589"
8 8
9
10Supported boards:
11
12- bq Aquaris5 smart phone:
13 Required root node properties:
14 - compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
diff --git a/Documentation/devicetree/bindings/arm/omap/mpu.txt b/Documentation/devicetree/bindings/arm/omap/mpu.txt
index 83f405bde138..763695db2bd9 100644
--- a/Documentation/devicetree/bindings/arm/omap/mpu.txt
+++ b/Documentation/devicetree/bindings/arm/omap/mpu.txt
@@ -10,6 +10,9 @@ Required properties:
10 Should be "ti,omap5-mpu" for OMAP5 10 Should be "ti,omap5-mpu" for OMAP5
11- ti,hwmods: "mpu" 11- ti,hwmods: "mpu"
12 12
13Optional properties:
14- sram: Phandle to the ocmcram node
15
13Examples: 16Examples:
14 17
15- For an OMAP5 SMP system: 18- For an OMAP5 SMP system:
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index 0edc90305dfe..ddd9bcdf889c 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -85,6 +85,18 @@ SoCs:
85- DRA722 85- DRA722
86 compatible = "ti,dra722", "ti,dra72", "ti,dra7" 86 compatible = "ti,dra722", "ti,dra72", "ti,dra7"
87 87
88- AM5728
89 compatible = "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
90
91- AM5726
92 compatible = "ti,am5726", "ti,dra742", "ti,dra74", "ti,dra7"
93
94- AM5718
95 compatible = "ti,am5718", "ti,dra722", "ti,dra72", "ti,dra7"
96
97- AM5716
98 compatible = "ti,am5716", "ti,dra722", "ti,dra72", "ti,dra7"
99
88- AM4372 100- AM4372
89 compatible = "ti,am4372", "ti,am43" 101 compatible = "ti,am4372", "ti,am43"
90 102
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
index b4a58f39223c..5aa40ede0e99 100644
--- a/Documentation/devicetree/bindings/arm/psci.txt
+++ b/Documentation/devicetree/bindings/arm/psci.txt
@@ -50,6 +50,16 @@ Main node optional properties:
50 50
51 - migrate : Function ID for MIGRATE operation 51 - migrate : Function ID for MIGRATE operation
52 52
53Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
54state nodes, as per bindings in [1]) must specify the following properties:
55
56- arm,psci-suspend-param
57 Usage: Required for state nodes[1] if the corresponding
58 idle-states node entry-method property is set
59 to "psci".
60 Value type: <u32>
61 Definition: power_state parameter to pass to the PSCI
62 suspend call.
53 63
54Example: 64Example:
55 65
@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
64 migrate = <0x95c10003>; 74 migrate = <0x95c10003>;
65 }; 75 };
66 76
67
68Case 2: PSCI v0.2 only 77Case 2: PSCI v0.2 only
69 78
70 psci { 79 psci {
@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
88 97
89 ... 98 ...
90 }; 99 };
100
101[1] Kernel documentation - ARM idle states bindings
102 Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index adc61b095bd1..709efaa30841 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -11,13 +11,25 @@ New driver handles the following
11 11
12Required properties: 12Required properties:
13- compatible: Must be "samsung,exynos-adc-v1" 13- compatible: Must be "samsung,exynos-adc-v1"
14 for exynos4412/5250 controllers. 14 for exynos4412/5250 and s5pv210 controllers.
15 Must be "samsung,exynos-adc-v2" for 15 Must be "samsung,exynos-adc-v2" for
16 future controllers. 16 future controllers.
17 Must be "samsung,exynos3250-adc" for 17 Must be "samsung,exynos3250-adc" for
18 controllers compatible with ADC of Exynos3250. 18 controllers compatible with ADC of Exynos3250.
19- reg: Contains ADC register address range (base address and 19 Must be "samsung,s3c2410-adc" for
20 length) and the address of the phy enable register. 20 the ADC in s3c2410 and compatibles
21 Must be "samsung,s3c2416-adc" for
22 the ADC in s3c2416 and compatibles
23 Must be "samsung,s3c2440-adc" for
24 the ADC in s3c2440 and compatibles
25 Must be "samsung,s3c2443-adc" for
26 the ADC in s3c2443 and compatibles
27 Must be "samsung,s3c6410-adc" for
28 the ADC in s3c6410 and compatibles
29- reg: List of ADC register address range
30 - The base address and range of ADC register
31 - The base address and range of ADC_PHY register (every
32 SoC except for s3c24xx/s3c64xx ADC)
21- interrupts: Contains the interrupt information for the timer. The 33- interrupts: Contains the interrupt information for the timer. The
22 format is being dependent on which interrupt controller 34 format is being dependent on which interrupt controller
23 the Samsung device uses. 35 the Samsung device uses.
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
new file mode 100644
index 000000000000..51147cb5c036
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -0,0 +1,71 @@
1Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
2--------------------------------------------------------------------
3
4SoCs:
5
6 - Emma Mobile EV2
7 compatible = "renesas,emev2"
8 - RZ/A1H (R7S72100)
9 compatible = "renesas,r7s72100"
10 - SH-Mobile AP4 (R8A73720/SH7372)
11 compatible = "renesas,sh7372"
12 - SH-Mobile AG5 (R8A73A00/SH73A0)
13 compatible = "renesas,sh73a0"
14 - R-Mobile APE6 (R8A73A40)
15 compatible = "renesas,r8a73a4"
16 - R-Mobile A1 (R8A77400)
17 compatible = "renesas,r8a7740"
18 - R-Car M1A (R8A77781)
19 compatible = "renesas,r8a7778"
20 - R-Car H1 (R8A77790)
21 compatible = "renesas,r8a7779"
22 - R-Car H2 (R8A77900)
23 compatible = "renesas,r8a7790"
24 - R-Car M2-W (R8A77910)
25 compatible = "renesas,r8a7791"
26 - R-Car V2H (R8A77920)
27 compatible = "renesas,r8a7792"
28 - R-Car M2-N (R8A77930)
29 compatible = "renesas,r8a7793"
30 - R-Car E2 (R8A77940)
31 compatible = "renesas,r8a7794"
32
33
34Boards:
35
36 - Alt
37 compatible = "renesas,alt", "renesas,r8a7794"
38 - APE6-EVM
39 compatible = "renesas,ape6evm", "renesas,r8a73a4"
40 - APE6-EVM - Reference Device Tree Implementation
41 compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"
42 - Atmark Techno Armadillo-800 EVA
43 compatible = "renesas,armadillo800eva"
44 - BOCK-W
45 compatible = "renesas,bockw", "renesas,r8a7778"
46 - BOCK-W - Reference Device Tree Implementation
47 compatible = "renesas,bockw-reference", "renesas,r8a7778"
48 - Genmai (RTK772100BC00000BR)
49 compatible = "renesas,genmai", "renesas,r7s72100"
50 - Gose
51 compatible = "renesas,gose", "renesas,r8a7793"
52 - Henninger
53 compatible = "renesas,henninger", "renesas,r8a7791"
54 - Koelsch (RTP0RC7791SEB00010S)
55 compatible = "renesas,koelsch", "renesas,r8a7791"
56 - Kyoto Microcomputer Co. KZM-A9-Dual
57 compatible = "renesas,kzm9d", "renesas,emev2"
58 - Kyoto Microcomputer Co. KZM-A9-GT
59 compatible = "renesas,kzm9g", "renesas,sh73a0"
60 - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
61 compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
62 - Lager (RTP0RC7790SEB00010S)
63 compatible = "renesas,lager", "renesas,r8a7790"
64 - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
65 compatible = "renesas,mackerel"
66 - Marzen
67 compatible = "renesas,marzen", "renesas,r8a7779"
68
69Note: Reference Device Tree Implementations are temporary implementations
70 to ease the migration from platform devices to Device Tree, and are
71 intended to be removed in the future.
diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
new file mode 100644
index 000000000000..ccf0adddc820
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -0,0 +1,12 @@
1NVIDIA Tegra Flow Controller
2
3Required properties:
4- compatible: Should be "nvidia,tegra<chip>-flowctrl"
5- reg: Should contain one register range (address and length)
6
7Example:
8
9 flow-controller@60007000 {
10 compatible = "nvidia,tegra20-flowctrl";
11 reg = <0x60007000 0x1000>;
12 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 03:29:52 -0400