8 files changed, 156 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt b/Documentation/devicetree/bindings/arm/armada-375.txt
new file mode 100644
index 000000000000..867d0b80cb8f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-375.txt
@@ -0,0 +1,9 @@
+Marvell Armada 375 Platforms Device Tree Bindings
+-------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 375 family shall have the
+following property:
+
+Required root node property:
+
+compatible: must contain "marvell,armada375"
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt b/Documentation/devicetree/bindings/arm/armada-38x.txt
new file mode 100644
index 000000000000..11f2330a6554
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-38x.txt
@@ -0,0 +1,10 @@
+Marvell Armada 38x Platforms Device Tree Bindings
+-------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 38x family shall have the
+following property:
+
+Required root node property:
+
+ - compatible: must contain either "marvell,armada380" or
+   "marvell,armada385" depending on the variant of the SoC being used.
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 91304353eea4..333f4aea3029 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -180,7 +180,11 @@ nodes to be present and contain the properties described below.
                           be one of:
                              "spin-table"
                              "psci"
-                        # On ARM 32-bit systems this property is optional.
+                        # On ARM 32-bit systems this property is optional and
+                          can be one of:
+                            "qcom,gcc-msm8660"
+                            "qcom,kpss-acc-v1"
+                            "qcom,kpss-acc-v2"
 
         - cpu-release-addr
                 Usage: required for systems that have an "enable-method"
@@ -191,6 +195,21 @@ nodes to be present and contain the properties described below.
                           property identifying a 64-bit zero-initialised
                           memory location.
 
+        - qcom,saw
+                Usage: required for systems that have an "enable-method"
+                       property value of "qcom,kpss-acc-v1" or
+                       "qcom,kpss-acc-v2"
+                Value type: <phandle>
+                Definition: Specifies the SAW[1] node associated with this CPU.
+
+        - qcom,acc
+                Usage: required for systems that have an "enable-method"
+                       property value of "qcom,kpss-acc-v1" or
+                       "qcom,kpss-acc-v2"
+                Value type: <phandle>
+                Definition: Specifies the ACC[2] node associated with this CPU.
+
+
 Example 1 (dual-cluster big.LITTLE system 32-bit):
 
         cpus {
@@ -382,3 +401,7 @@ cpus {
                 cpu-release-addr = <0 0x20000000>;
         };
 };
+
+--
+[1] arm/msm/qcom,saw2.txt
+[2] arm/msm/qcom,kpss-acc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
new file mode 100644
index 000000000000..1333db9acfee
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,kpss-acc.txt
@@ -0,0 +1,30 @@
+Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
+
+The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+There is one ACC register region per CPU within the KPSS remapped region as
+well as an alias register region that remaps accesses to the ACC associated
+with the CPU accessing the region.
+
+PROPERTIES
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: should be one of:
+                        "qcom,kpss-acc-v1"
+                        "qcom,kpss-acc-v2"
+
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the first element specifies the base address and size of
+                    the register region. An optional second element specifies
+                    the base address and size of the alias register region.
+
+Example:
+
+        clock-controller@2088000 {
+                compatible = "qcom,kpss-acc-v2";
+                reg = <0x02088000 0x1000>,
+                      <0x02008000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
new file mode 100644
index 000000000000..1505fb8e131a
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -0,0 +1,35 @@
+SPM AVS Wrapper 2 (SAW2)
+
+The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+micro-controller that transitions a piece of hardware (like a processor or
+subsystem) into and out of low power modes via a direct connection to
+the PMIC. It can also be wired up to interact with other processors in the
+system, notifying them when a low power state is entered or exited.
+
+PROPERTIES
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: shall contain "qcom,saw2". A more specific value should be
+                    one of:
+                         "qcom,saw2-v1"
+                         "qcom,saw2-v1.1"
+                         "qcom,saw2-v2"
+                         "qcom,saw2-v2.1"
+
+- reg:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: the first element specifies the base address and size of
+                    the register region. An optional second element specifies
+                    the base address and size of the alias register region.
+
+
+Example:
+
+        regulator@2099000 {
+                compatible = "qcom,saw2";
+                reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
index 081c6a786c8a..d24ab2ebf8a7 100644
--- a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt
@@ -1,12 +1,13 @@
 MVEBU System Controller
 -----------------------
-MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x)
+MVEBU (Marvell SOCs: Armada 370/375/XP, Dove, mv78xx0, Kirkwood, Orion5x)
 
 Required properties:
 
 - compatible: one of:
         - "marvell,orion-system-controller"
         - "marvell,armada-370-xp-system-controller"
+        - "marvell,armada-375-system-controller"
 - reg: Should contain system controller registers location and length.
 
 Example:
diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.txt b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt
new file mode 100644
index 000000000000..3ee9b428b2f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.txt
@@ -0,0 +1,16 @@
+Rockchip power-management-unit:
+-------------------------------
+
+The pmu is used to turn off and on different power domains of the SoCs
+This includes the power to the CPU cores.
+
+Required node properties:
+- compatible value : = "rockchip,rk3066-pmu";
+- reg : physical base address and the size of the registers window
+
+Example:
+
+        pmu@20004000 {
+                compatible = "rockchip,rk3066-pmu";
+                reg = <0x20004000 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
new file mode 100644
index 000000000000..d9416fb8db6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/rockchip/smp-sram.txt
@@ -0,0 +1,30 @@
+Rockchip SRAM for smp bringup:
+------------------------------
+
+Rockchip's smp-capable SoCs use the first part of the sram for the bringup
+of the cores. Once the core gets powered up it executes the code that is
+residing at the very beginning of the sram.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Required sub-node properties:
+- compatible : should be "rockchip,rk3066-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+        sram: sram@10080000 {
+                compatible = "mmio-sram";
+                reg = <0x10080000 0x10000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                smp-sram@10080000 {
+                        compatible = "rockchip,rk3066-smp-sram";
+                        reg = <0x10080000 0x50>;
+                };
+        };